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Data Structures | |
| struct | armv7a_arch_cache |
| struct | armv7a_cache_common |
| struct | armv7a_cachesize |
| struct | armv7a_common |
| struct | armv7a_l2x_cache |
| struct | armv7a_mmu_common |
Macros | |
| #define | ARMV7_COMMON_MAGIC 0x0A450999U |
| #define | CPUDBG_AUTHSTATUS 0xFB8 |
| #define | CPUDBG_BCR_BASE 0x140 |
| #define | CPUDBG_BVR_BASE 0x100 |
| #define | CPUDBG_DIDR 0x000 |
| #define | CPUDBG_DRCR 0x090 |
| #define | CPUDBG_DSCCR 0x028 |
| #define | CPUDBG_DSCR 0x088 |
| #define | CPUDBG_DSMCR 0x02C |
| #define | CPUDBG_DTRRX 0x080 |
| #define | CPUDBG_DTRTX 0x08c |
| #define | CPUDBG_ECR 0x024 |
| #define | CPUDBG_ID_PFR1 0xD24 |
| #define | CPUDBG_ITR 0x084 |
| #define | CPUDBG_OSLAR 0x300 |
| #define | CPUDBG_OSLSR 0x304 |
| #define | CPUDBG_OSSRR 0x308 |
| #define | CPUDBG_PRCR 0x310 |
| #define | CPUDBG_PRSR 0x314 |
| #define | CPUDBG_VCR 0x01C |
| #define | CPUDBG_WCR_BASE 0x1C0 |
| #define | CPUDBG_WFAR 0x018 |
| #define | CPUDBG_WVR_BASE 0x180 |
| #define | DBG_VCR_DATA_ABORT_MASK ((1 << 28) | (1 << 4)) |
| #define | DBG_VCR_FIQ_MASK ((1 << 31) | (1 << 7)) |
| #define | DBG_VCR_IRQ_MASK ((1 << 30) | (1 << 6)) |
| #define | DBG_VCR_PREF_ABORT_MASK ((1 << 27) | (1 << 3)) |
| #define | DBG_VCR_SVC_MASK ((1 << 26) | (1 << 2)) |
| #define | MPIDR_MP_EXT (1UL << 31) |
| #define | V2PCWPR 0 |
| #define | V2PCWPW 1 |
| #define | V2PCWUR 2 |
| #define | V2PCWUW 3 |
| #define | V2POWPR 4 |
| #define | V2POWPW 5 |
| #define | V2POWUR 6 |
| #define | V2POWUW 7 |
Enumerations | |
| enum | { ARM_PC = 15 , ARM_CPSR = 16 } |
Functions | |
| int | armv7a_arch_state (struct target *target) |
| int | armv7a_handle_cache_info_command (struct command_invocation *cmd, struct armv7a_cache_common *armv7a_cache) |
| int | armv7a_identify_cache (struct target *target) |
| int | armv7a_init_arch_info (struct target *target, struct armv7a_common *armv7a) |
| int | armv7a_read_ttbcr (struct target *target) |
| static bool | is_armv7a (struct armv7a_common *armv7a) |
| static struct armv7a_common * | target_to_armv7a (struct target *target) |
Variables | |
| const struct command_registration | armv7a_command_handlers [] |
Macro Definition Documentation
◆ ARMV7_COMMON_MAGIC
◆ CPUDBG_AUTHSTATUS
◆ CPUDBG_BCR_BASE
◆ CPUDBG_BVR_BASE
◆ CPUDBG_DIDR
◆ CPUDBG_DRCR
◆ CPUDBG_DSCCR
◆ CPUDBG_DSCR
◆ CPUDBG_DSMCR
◆ CPUDBG_DTRRX
◆ CPUDBG_DTRTX
◆ CPUDBG_ECR
◆ CPUDBG_ID_PFR1
◆ CPUDBG_ITR
◆ CPUDBG_OSLAR
◆ CPUDBG_OSLSR
◆ CPUDBG_OSSRR
◆ CPUDBG_PRCR
◆ CPUDBG_PRSR
◆ CPUDBG_VCR
◆ CPUDBG_WCR_BASE
◆ CPUDBG_WFAR
◆ CPUDBG_WVR_BASE
◆ DBG_VCR_DATA_ABORT_MASK
◆ DBG_VCR_FIQ_MASK
◆ DBG_VCR_IRQ_MASK
◆ DBG_VCR_PREF_ABORT_MASK
◆ DBG_VCR_SVC_MASK
◆ MPIDR_MP_EXT
◆ V2PCWPR
◆ V2PCWPW
◆ V2PCWUR
◆ V2PCWUW
◆ V2POWPR
◆ V2POWPW
◆ V2POWUR
◆ V2POWUW
Enumeration Type Documentation
◆ anonymous enum
Function Documentation
◆ armv7a_arch_state()
| int armv7a_arch_state | ( | struct target * | target | ) |
Definition at line 531 of file armv7a.c.
References armv7a_common::arm, arm_arch_state(), ARM_MODE_ABT, ARMV7_COMMON_MAGIC, armv7a_mmu_common::armv7a_cache, armv7a_common::armv7a_mmu, armv7a_show_fault_registers(), armv7a_common::common_magic, arm::core_mode, armv7a_cache_common::d_u_cache_enabled, ERROR_COMMAND_SYNTAX_ERROR, ERROR_OK, armv7a_cache_common::i_cache_enabled, armv7a_common::is_armv7r, LOG_ERROR, LOG_USER, armv7a_mmu_common::mmu_enabled, state, and target_to_armv7a().
◆ armv7a_handle_cache_info_command()
| int armv7a_handle_cache_info_command | ( | struct command_invocation * | cmd, |
| struct armv7a_cache_common * | armv7a_cache | ||
| ) |
Definition at line 230 of file armv7a.c.
References armv7a_cache_common::arch, armv7a_cachesize::associativity, armv7a_l2x_cache::base, armv7a_cachesize::cachesize, cmd, command_print(), armv7a_arch_cache::ctype, armv7a_arch_cache::d_u_size, ERROR_OK, armv7a_arch_cache::i_size, armv7a_cache_common::info, armv7a_cachesize::linelen, armv7a_cache_common::loc, armv7a_cachesize::nsets, armv7a_cache_common::outer_cache, and armv7a_l2x_cache::way.
Referenced by COMMAND_HANDLER().
◆ armv7a_identify_cache()
| int armv7a_identify_cache | ( | struct target * | target | ) |
Definition at line 364 of file armv7a.c.
References armv7a_cache_common::arch, armv7a_common::arm, ARMV4_5_MRC, armv7a_mmu_common::armv7a_cache, armv7a_cache_flush_all_data(), armv7a_common::armv7a_mmu, armv7a_read_mpidr(), armv7a_cachesize::associativity, CACHE_LEVEL_HAS_D_CACHE, CACHE_LEVEL_HAS_I_CACHE, CACHE_LEVEL_HAS_UNIFIED_CACHE, armv7a_cachesize::cachesize, armv7a_arch_cache::ctype, armv7a_arch_cache::d_u_size, decode_cache_reg(), armv7a_cache_common::dminline, arm::dpm, ERROR_FAIL, ERROR_OK, arm_dpm::finish, armv7a_cache_common::flush_all_data_cache, get_cache_info(), armv7a_arch_cache::i_size, armv7a_cache_common::iminline, armv7a_cachesize::index, armv7a_cachesize::index_shift, armv7a_cache_common::info, arm_dpm::instr_read_data_r0, arm_dpm::instr_write_data_r0, armv7a_cachesize::linelen, armv7a_cache_common::loc, LOG_DEBUG, arm_dpm::prepare, target_to_armv7a(), armv7a_cachesize::way, and armv7a_cachesize::way_shift.
Referenced by cortex_a_post_debug_entry().
◆ armv7a_init_arch_info()
| int armv7a_init_arch_info | ( | struct target * | target, |
| struct armv7a_common * | armv7a | ||
| ) |
Definition at line 515 of file armv7a.c.
References arm::arch_info, target::arch_info, armv7a_common::arm, ARM_COMMON_MAGIC, ARMV7_COMMON_MAGIC, armv7a_mmu_common::armv7a_cache, armv7a_common::armv7a_mmu, armv7a_setup_semihosting(), arm::common_magic, armv7a_common::common_magic, ERROR_OK, armv7a_cache_common::flush_all_data_cache, armv7a_cache_common::info, NULL, armv7a_cache_common::outer_cache, arm::setup_semihosting, target, and arm::target.
Referenced by cortex_a_init_arch_info().
◆ armv7a_read_ttbcr()
| int armv7a_read_ttbcr | ( | struct target * | target | ) |
Definition at line 118 of file armv7a.c.
References armv7a_common::arm, ARMV4_5_MRC, armv7a_common::armv7a_mmu, armv7a_read_midr(), armv7a_mmu_common::cached, arm::dpm, ERROR_OK, arm_dpm::finish, arm_dpm::instr_read_data_r0, LOG_DEBUG, armv7a_common::partnum, arm_dpm::prepare, target_to_armv7a(), armv7a_mmu_common::ttbcr, armv7a_mmu_common::ttbr, armv7a_mmu_common::ttbr_mask, and armv7a_mmu_common::ttbr_range.
Referenced by cortex_a_post_debug_entry().
◆ is_armv7a()
|
inlinestatic |
Definition at line 125 of file armv7a.h.
References ARMV7_COMMON_MAGIC, and armv7a_common::common_magic.
Referenced by arm_semihosting(), and post_result().
◆ target_to_armv7a()
|
inlinestatic |
Definition at line 120 of file armv7a.h.
References target::arch_info, and container_of.
Referenced by arm7a_l2x_flush_all_data(), arm7a_l2x_sanity_check(), arm_semihosting(), armv7a_arch_state(), armv7a_identify_cache(), armv7a_l1_d_cache_clean_inval_all(), armv7a_l1_d_cache_clean_virt(), armv7a_l1_d_cache_flush_virt(), armv7a_l1_d_cache_inval_virt(), armv7a_l1_d_cache_sanity_check(), armv7a_l1_i_cache_inval_all(), armv7a_l1_i_cache_inval_virt(), armv7a_l1_i_cache_sanity_check(), armv7a_l2x_cache_clean_virt(), armv7a_l2x_cache_flush_virt(), armv7a_l2x_cache_init(), armv7a_l2x_cache_inval_virt(), armv7a_mmu_translate_va_pa(), armv7a_read_midr(), armv7a_read_mpidr(), armv7a_read_ttbcr(), armv7a_setup_semihosting(), armv7a_show_fault_registers(), COMMAND_HANDLER(), cortex_a_assert_reset(), cortex_a_deassert_reset(), cortex_a_debug_entry(), cortex_a_exec_opcode(), cortex_a_halt(), cortex_a_handle_target_request(), cortex_a_init_debug_access(), cortex_a_internal_restart(), cortex_a_internal_restore(), cortex_a_mmu(), cortex_a_mmu_modify(), cortex_a_post_memaccess(), cortex_a_prep_memaccess(), cortex_a_read_copro(), cortex_a_read_cpu_memory(), cortex_a_read_cpu_memory_fast(), cortex_a_read_cpu_memory_slow(), cortex_a_restore_context(), cortex_a_restore_cp15_control_reg(), cortex_a_set_dcc_mode(), cortex_a_set_dscr_bits(), cortex_a_step(), cortex_a_wait_dscr_bits(), cortex_a_wait_instrcmpl(), cortex_a_write_copro(), cortex_a_write_cpu_memory(), cortex_a_write_cpu_memory_fast(), cortex_a_write_cpu_memory_slow(), and post_result().
Variable Documentation
◆ armv7a_command_handlers
|
extern |
