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Data Structures | |
struct | cortex_m_common |
struct | cortex_m_dwt_comparator |
struct | cortex_m_fp_comparator |
struct | cortex_m_part_info |
Macros | |
#define | AIRCR_SYSRESETREQ BIT(2) |
#define | AIRCR_VECTCLRACTIVE BIT(1) |
#define | AIRCR_VECTKEY (0x5FAul << 16) |
#define | AIRCR_VECTRESET BIT(0) |
#define | ARM_CPUID_PARTNO_MASK (0xFFF << ARM_CPUID_PARTNO_POS) |
#define | ARM_CPUID_PARTNO_POS 4 |
#define | C_DEBUGEN BIT(0) |
#define | C_HALT BIT(1) |
#define | C_MASKINTS BIT(3) |
#define | C_STEP BIT(2) |
#define | CORTEX_M_COMMON_MAGIC 0x1A451A45U |
#define | CORTEX_M_F_HAS_FPV4 BIT(0) |
#define | CORTEX_M_F_HAS_FPV5 BIT(1) |
#define | CORTEX_M_F_TAR_AUTOINCR_BLOCK_4K BIT(2) |
#define | CPUID 0xE000ED00 |
#define | DAUTHSTATUS 0xE000EFB8 |
#define | DAUTHSTATUS_SID_MASK 0x00000030 |
#define | DBGKEY (0xA05Ful << 16) |
#define | DCB_DCRDR 0xE000EDF8 |
#define | DCB_DCRSR 0xE000EDF4 |
#define | DCB_DEMCR 0xE000EDFC |
#define | DCB_DHCSR 0xE000EDF0 |
#define | DCB_DSCSR 0xE000EE08 |
#define | DCRSR_WNR BIT(16) |
#define | DFSR_BKPT 2 |
#define | DFSR_DWTTRAP 4 |
#define | DFSR_EXTERNAL 16 |
#define | DFSR_HALTED 1 |
#define | DFSR_VCATCH 8 |
#define | DSCSR_CDS BIT(16) |
#define | DWT_COMP0 0xE0001020 |
#define | DWT_CTRL 0xE0001000 |
#define | DWT_CYCCNT 0xE0001004 |
#define | DWT_DEVARCH 0xE0001FBC |
#define | DWT_DEVARCH_ARMV8M 0x101A02 |
#define | DWT_FUNCTION0 0xE0001028 |
#define | DWT_MASK0 0xE0001024 |
#define | DWT_PCSR 0xE000101C |
#define | FP_COMP0 0xE0002008 |
#define | FP_COMP1 0xE000200C |
#define | FP_COMP2 0xE0002010 |
#define | FP_COMP3 0xE0002014 |
#define | FP_COMP4 0xE0002018 |
#define | FP_COMP5 0xE000201C |
#define | FP_COMP6 0xE0002020 |
#define | FP_COMP7 0xE0002024 |
#define | FP_CTRL 0xE0002000 |
#define | FP_REMAP 0xE0002004 |
#define | FPCR_CODE 0 |
#define | FPCR_LITERAL 1 |
#define | FPCR_REPLACE_BKPT_BOTH (3ul << 30) |
#define | FPCR_REPLACE_BKPT_HIGH (2ul << 30) |
#define | FPCR_REPLACE_BKPT_LOW (1ul << 30) |
#define | FPCR_REPLACE_REMAP (0ul << 30) |
#define | FPU_CPACR 0xE000ED88 |
#define | FPU_FPCAR 0xE000EF38 |
#define | FPU_FPCCR 0xE000EF34 |
#define | FPU_FPDSCR 0xE000EF3C |
#define | ITM_LAR 0xE0000FB0 |
#define | ITM_LAR_KEY 0xC5ACCE55 |
#define | ITM_TCR 0xE0000E80 |
#define | ITM_TCR_BUSY_BIT BIT(23) |
#define | ITM_TCR_ITMENA_BIT BIT(0) |
#define | ITM_TER0 0xE0000E00 |
#define | ITM_TPR 0xE0000E40 |
#define | NVIC_AIRCR 0xE000ED0C |
#define | NVIC_BFAR 0xE000ED38 |
#define | NVIC_BFSRB 0xE000ED29 |
#define | NVIC_CFSR 0xE000ED28 |
#define | NVIC_DFSR 0xE000ED30 |
#define | NVIC_HFSR 0xE000ED2C |
#define | NVIC_ICSR 0xE000ED04 |
#define | NVIC_ICTR 0xE000E004 |
#define | NVIC_ISE0 0xE000E100 |
#define | NVIC_MMFAR 0xE000ED34 |
#define | NVIC_MMFSRB 0xE000ED28 |
#define | NVIC_SFAR 0xE000EDE8 |
#define | NVIC_SFSR 0xE000EDE4 |
#define | NVIC_SHCSR 0xE000ED24 |
#define | NVIC_USFSRH 0xE000ED2A |
#define | S_HALT BIT(17) |
#define | S_LOCKUP BIT(19) |
#define | S_REGRDY BIT(16) |
#define | S_RESET_ST BIT(25) |
#define | S_RETIRE_ST BIT(24) |
#define | S_SLEEP BIT(18) |
#define | SHCSR_BUSFAULTENA BIT(17) |
#define | SYSTEM_CONTROL_BASE 0x400FE000 |
#define | TPIU_ACPR 0xE0040010 |
#define | TPIU_ACPR_MAX_SWOSCALER 0x1fff |
#define | TPIU_CSPSR 0xE0040004 |
#define | TPIU_FFCR 0xE0040304 |
#define | TPIU_FFSR 0xE0040300 |
#define | TPIU_FSCR 0xE0040308 |
#define | TPIU_SPPR 0xE00400F0 |
#define | TPIU_SSPSR 0xE0040000 |
#define | TRCENA BIT(24) |
#define | VC_BUSERR BIT(8) |
#define | VC_CHKERR BIT(6) |
#define | VC_CORERESET BIT(0) |
#define | VC_HARDERR BIT(10) |
#define | VC_INTERR BIT(9) |
#define | VC_MMERR BIT(4) |
#define | VC_NOCPERR BIT(5) |
#define | VC_STATERR BIT(7) |
Enumerations | |
enum | cortex_m_isrmasking_mode { CORTEX_M_ISRMASK_AUTO , CORTEX_M_ISRMASK_OFF , CORTEX_M_ISRMASK_ON , CORTEX_M_ISRMASK_STEPONLY } |
enum | cortex_m_partno { CORTEX_M_PARTNO_INVALID , STAR_MC1_PARTNO = 0x132 , CORTEX_M0_PARTNO = 0xC20 , CORTEX_M1_PARTNO = 0xC21 , CORTEX_M3_PARTNO = 0xC23 , CORTEX_M4_PARTNO = 0xC24 , CORTEX_M7_PARTNO = 0xC27 , CORTEX_M0P_PARTNO = 0xC60 , CORTEX_M23_PARTNO = 0xD20 , CORTEX_M33_PARTNO = 0xD21 , CORTEX_M35P_PARTNO = 0xD31 , CORTEX_M55_PARTNO = 0xD22 } |
enum | cortex_m_soft_reset_config { CORTEX_M_RESET_SYSRESETREQ , CORTEX_M_RESET_VECTRESET } |
#define AIRCR_SYSRESETREQ BIT(2) |
Definition at line 159 of file cortex_m.h.
#define AIRCR_VECTCLRACTIVE BIT(1) |
Definition at line 160 of file cortex_m.h.
#define AIRCR_VECTKEY (0x5FAul << 16) |
Definition at line 158 of file cortex_m.h.
#define AIRCR_VECTRESET BIT(0) |
Definition at line 161 of file cortex_m.h.
#define ARM_CPUID_PARTNO_MASK (0xFFF << ARM_CPUID_PARTNO_POS) |
Definition at line 35 of file cortex_m.h.
#define ARM_CPUID_PARTNO_POS 4 |
Definition at line 34 of file cortex_m.h.
#define C_DEBUGEN BIT(0) |
Definition at line 115 of file cortex_m.h.
#define C_HALT BIT(1) |
Definition at line 116 of file cortex_m.h.
#define C_MASKINTS BIT(3) |
Definition at line 118 of file cortex_m.h.
#define C_STEP BIT(2) |
Definition at line 117 of file cortex_m.h.
#define CORTEX_M_COMMON_MAGIC 0x1A451A45U |
Definition at line 20 of file cortex_m.h.
#define CORTEX_M_F_HAS_FPV4 BIT(0) |
Definition at line 53 of file cortex_m.h.
#define CORTEX_M_F_HAS_FPV5 BIT(1) |
Definition at line 54 of file cortex_m.h.
#define CORTEX_M_F_TAR_AUTOINCR_BLOCK_4K BIT(2) |
Definition at line 55 of file cortex_m.h.
#define CPUID 0xE000ED00 |
Definition at line 32 of file cortex_m.h.
#define DAUTHSTATUS 0xE000EFB8 |
Definition at line 71 of file cortex_m.h.
#define DAUTHSTATUS_SID_MASK 0x00000030 |
Definition at line 72 of file cortex_m.h.
#define DBGKEY (0xA05Ful << 16) |
Definition at line 114 of file cortex_m.h.
#define DCB_DCRDR 0xE000EDF8 |
Definition at line 67 of file cortex_m.h.
#define DCB_DCRSR 0xE000EDF4 |
Definition at line 66 of file cortex_m.h.
#define DCB_DEMCR 0xE000EDFC |
Definition at line 68 of file cortex_m.h.
#define DCB_DHCSR 0xE000EDF0 |
Definition at line 65 of file cortex_m.h.
#define DCB_DSCSR 0xE000EE08 |
Definition at line 69 of file cortex_m.h.
#define DCRSR_WNR BIT(16) |
Definition at line 74 of file cortex_m.h.
#define DFSR_BKPT 2 |
Definition at line 166 of file cortex_m.h.
#define DFSR_DWTTRAP 4 |
Definition at line 167 of file cortex_m.h.
#define DFSR_EXTERNAL 16 |
Definition at line 169 of file cortex_m.h.
#define DFSR_HALTED 1 |
Definition at line 165 of file cortex_m.h.
#define DFSR_VCATCH 8 |
Definition at line 168 of file cortex_m.h.
#define DSCSR_CDS BIT(16) |
Definition at line 138 of file cortex_m.h.
#define DWT_COMP0 0xE0001020 |
Definition at line 79 of file cortex_m.h.
#define DWT_CTRL 0xE0001000 |
Definition at line 76 of file cortex_m.h.
#define DWT_CYCCNT 0xE0001004 |
Definition at line 77 of file cortex_m.h.
#define DWT_DEVARCH 0xE0001FBC |
Definition at line 82 of file cortex_m.h.
#define DWT_DEVARCH_ARMV8M 0x101A02 |
Definition at line 84 of file cortex_m.h.
#define DWT_FUNCTION0 0xE0001028 |
Definition at line 81 of file cortex_m.h.
#define DWT_MASK0 0xE0001024 |
Definition at line 80 of file cortex_m.h.
#define DWT_PCSR 0xE000101C |
Definition at line 78 of file cortex_m.h.
#define FP_COMP0 0xE0002008 |
Definition at line 88 of file cortex_m.h.
#define FP_COMP1 0xE000200C |
Definition at line 89 of file cortex_m.h.
#define FP_COMP2 0xE0002010 |
Definition at line 90 of file cortex_m.h.
#define FP_COMP3 0xE0002014 |
Definition at line 91 of file cortex_m.h.
#define FP_COMP4 0xE0002018 |
Definition at line 92 of file cortex_m.h.
#define FP_COMP5 0xE000201C |
Definition at line 93 of file cortex_m.h.
#define FP_COMP6 0xE0002020 |
Definition at line 94 of file cortex_m.h.
#define FP_COMP7 0xE0002024 |
Definition at line 95 of file cortex_m.h.
#define FP_CTRL 0xE0002000 |
Definition at line 86 of file cortex_m.h.
#define FP_REMAP 0xE0002004 |
Definition at line 87 of file cortex_m.h.
#define FPCR_CODE 0 |
Definition at line 171 of file cortex_m.h.
#define FPCR_LITERAL 1 |
Definition at line 172 of file cortex_m.h.
#define FPCR_REPLACE_BKPT_BOTH (3ul << 30) |
Definition at line 176 of file cortex_m.h.
#define FPCR_REPLACE_BKPT_HIGH (2ul << 30) |
Definition at line 175 of file cortex_m.h.
#define FPCR_REPLACE_BKPT_LOW (1ul << 30) |
Definition at line 174 of file cortex_m.h.
#define FPCR_REPLACE_REMAP (0ul << 30) |
Definition at line 173 of file cortex_m.h.
#define FPU_CPACR 0xE000ED88 |
Definition at line 97 of file cortex_m.h.
#define FPU_FPCAR 0xE000EF38 |
Definition at line 99 of file cortex_m.h.
#define FPU_FPCCR 0xE000EF34 |
Definition at line 98 of file cortex_m.h.
#define FPU_FPDSCR 0xE000EF3C |
Definition at line 100 of file cortex_m.h.
#define ITM_LAR 0xE0000FB0 |
Definition at line 29 of file cortex_m.h.
#define ITM_LAR_KEY 0xC5ACCE55 |
Definition at line 30 of file cortex_m.h.
#define ITM_TCR 0xE0000E80 |
Definition at line 26 of file cortex_m.h.
#define ITM_TCR_BUSY_BIT BIT(23) |
Definition at line 28 of file cortex_m.h.
#define ITM_TCR_ITMENA_BIT BIT(0) |
Definition at line 27 of file cortex_m.h.
#define ITM_TER0 0xE0000E00 |
Definition at line 24 of file cortex_m.h.
#define ITM_TPR 0xE0000E40 |
Definition at line 25 of file cortex_m.h.
#define NVIC_AIRCR 0xE000ED0C |
Definition at line 144 of file cortex_m.h.
#define NVIC_BFAR 0xE000ED38 |
Definition at line 153 of file cortex_m.h.
#define NVIC_BFSRB 0xE000ED29 |
Definition at line 148 of file cortex_m.h.
#define NVIC_CFSR 0xE000ED28 |
Definition at line 146 of file cortex_m.h.
#define NVIC_DFSR 0xE000ED30 |
Definition at line 151 of file cortex_m.h.
#define NVIC_HFSR 0xE000ED2C |
Definition at line 150 of file cortex_m.h.
#define NVIC_ICSR 0xE000ED04 |
Definition at line 143 of file cortex_m.h.
#define NVIC_ICTR 0xE000E004 |
Definition at line 141 of file cortex_m.h.
#define NVIC_ISE0 0xE000E100 |
Definition at line 142 of file cortex_m.h.
#define NVIC_MMFAR 0xE000ED34 |
Definition at line 152 of file cortex_m.h.
#define NVIC_MMFSRB 0xE000ED28 |
Definition at line 147 of file cortex_m.h.
#define NVIC_SFAR 0xE000EDE8 |
Definition at line 155 of file cortex_m.h.
#define NVIC_SFSR 0xE000EDE4 |
Definition at line 154 of file cortex_m.h.
#define NVIC_SHCSR 0xE000ED24 |
Definition at line 145 of file cortex_m.h.
#define NVIC_USFSRH 0xE000ED2A |
Definition at line 149 of file cortex_m.h.
#define S_HALT BIT(17) |
Definition at line 120 of file cortex_m.h.
#define S_LOCKUP BIT(19) |
Definition at line 122 of file cortex_m.h.
#define S_REGRDY BIT(16) |
Definition at line 119 of file cortex_m.h.
#define S_RESET_ST BIT(25) |
Definition at line 124 of file cortex_m.h.
#define S_RETIRE_ST BIT(24) |
Definition at line 123 of file cortex_m.h.
#define S_SLEEP BIT(18) |
Definition at line 121 of file cortex_m.h.
#define SHCSR_BUSFAULTENA BIT(17) |
Definition at line 163 of file cortex_m.h.
#define SYSTEM_CONTROL_BASE 0x400FE000 |
Definition at line 22 of file cortex_m.h.
#define TPIU_ACPR 0xE0040010 |
Definition at line 104 of file cortex_m.h.
#define TPIU_ACPR_MAX_SWOSCALER 0x1fff |
Definition at line 111 of file cortex_m.h.
#define TPIU_CSPSR 0xE0040004 |
Definition at line 103 of file cortex_m.h.
#define TPIU_FFCR 0xE0040304 |
Definition at line 107 of file cortex_m.h.
#define TPIU_FFSR 0xE0040300 |
Definition at line 106 of file cortex_m.h.
#define TPIU_FSCR 0xE0040308 |
Definition at line 108 of file cortex_m.h.
#define TPIU_SPPR 0xE00400F0 |
Definition at line 105 of file cortex_m.h.
#define TPIU_SSPSR 0xE0040000 |
Definition at line 102 of file cortex_m.h.
#define TRCENA BIT(24) |
Definition at line 127 of file cortex_m.h.
#define VC_BUSERR BIT(8) |
Definition at line 130 of file cortex_m.h.
#define VC_CHKERR BIT(6) |
Definition at line 132 of file cortex_m.h.
#define VC_CORERESET BIT(0) |
Definition at line 135 of file cortex_m.h.
#define VC_HARDERR BIT(10) |
Definition at line 128 of file cortex_m.h.
#define VC_INTERR BIT(9) |
Definition at line 129 of file cortex_m.h.
#define VC_MMERR BIT(4) |
Definition at line 134 of file cortex_m.h.
#define VC_NOCPERR BIT(5) |
Definition at line 133 of file cortex_m.h.
#define VC_STATERR BIT(7) |
Definition at line 131 of file cortex_m.h.
Enumerator | |
---|---|
CORTEX_M_ISRMASK_AUTO | |
CORTEX_M_ISRMASK_OFF | |
CORTEX_M_ISRMASK_ON | |
CORTEX_M_ISRMASK_STEPONLY |
Definition at line 198 of file cortex_m.h.
enum cortex_m_partno |
Definition at line 37 of file cortex_m.h.
Enumerator | |
---|---|
CORTEX_M_RESET_SYSRESETREQ | |
CORTEX_M_RESET_VECTRESET |
Definition at line 193 of file cortex_m.h.
int cortex_m_add_breakpoint | ( | struct target * | target, |
struct breakpoint * | breakpoint | ||
) |
Definition at line 1718 of file cortex_m.c.
References cortex_m_set_breakpoint(), ERROR_TARGET_RESOURCE_NOT_AVAILABLE, breakpoint::length, LOG_TARGET_DEBUG, and LOG_TARGET_INFO.
int cortex_m_add_watchpoint | ( | struct target * | target, |
struct watchpoint * | watchpoint | ||
) |
Definition at line 1857 of file cortex_m.c.
References watchpoint::address, cortex_m_common::dwt_comp_available, ERROR_OK, ERROR_TARGET_RESOURCE_NOT_AVAILABLE, watchpoint::length, LOG_TARGET_DEBUG, watchpoint::mask, mask, target_to_cm(), and watchpoint::value.
void cortex_m_deinit_target | ( | struct target * | target | ) |
Definition at line 2002 of file cortex_m.c.
References armv7m_free_reg_cache(), cortex_m_dwt_free(), dap_put_ap(), armv7m_common::debug_ap, cortex_m_common::fp_comparator_list, armv7m_common::is_hla_target, target::private_config, target_to_armv7m(), and target_to_cm().
void cortex_m_enable_breakpoints | ( | struct target * | target | ) |
Definition at line 1087 of file cortex_m.c.
References target::breakpoints, cortex_m_set_breakpoint(), breakpoint::is_set, and breakpoint::next.
Referenced by adapter_resume(), and cortex_m_resume().
void cortex_m_enable_watchpoints | ( | struct target * | target | ) |
Definition at line 1954 of file cortex_m.c.
References cortex_m_set_watchpoint(), watchpoint::is_set, watchpoint::next, and target::watchpoints.
Referenced by adapter_resume(), and cortex_m_resume().
int cortex_m_examine | ( | struct target * | target | ) |
Definition at line 2309 of file cortex_m.c.
References cortex_m_common::apsel, arm::arch, cortex_m_part_info::arch, armv7m_common::arm, ARM_ARCH_V7M, ARM_CPUID_PARTNO_MASK, ARM_CPUID_PARTNO_POS, cortex_m_common::armv7m, ARMV7M_FPU_FIRST_REG, ARMV7M_FPU_LAST_REG, armv7m_trace_itm_config(), ARMV8M_FIRST_REG, ARMV8M_LAST_REG, ARRAY_SIZE, C_DEBUGEN, C_HALT, C_MASKINTS, C_STEP, arm::core_cache, cortex_m_common::core_info, CORTEX_M7_PARTNO, cortex_m_cumulate_dhcsr_sticky(), cortex_m_dwt_free(), cortex_m_dwt_setup(), CORTEX_M_F_HAS_FPV4, CORTEX_M_F_HAS_FPV5, CORTEX_M_F_TAR_AUTOINCR_BLOCK_4K, cortex_m_find_mem_ap(), cortex_m_has_tz(), cortex_m_parts, CPUID, arm::dap, dap_get_ap(), DBGKEY, DCB_DEMCR, DCB_DHCSR, cortex_m_common::dcb_dhcsr, cortex_m_common::dcb_dhcsr_sticky_is_recent, armv7m_common::debug_ap, armv7m_common::demcr, DP_APSEL_INVALID, cortex_m_common::dwt_num_comp, ERROR_FAIL, ERROR_OK, reg::exist, cortex_m_part_info::flags, FP_COMP0, cortex_m_common::fp_comparator_list, FP_CTRL, armv7m_common::fp_feature, FP_NONE, cortex_m_common::fp_num_code, cortex_m_common::fp_num_lit, cortex_m_common::fp_rev, cortex_m_common::fpb_enabled, cortex_m_fp_comparator::fpcr_address, FPCR_CODE, FPCR_LITERAL, FPV4_SP, FPV5_DP, FPV5_SP, armv7m_common::is_hla_target, armv7m_trace_config::itm_deferred_config, LOG_ERROR, LOG_TARGET_DEBUG, LOG_TARGET_ERROR, LOG_TARGET_INFO, LOG_TARGET_WARNING, cortex_m_common::maskints_erratum, mem_ap_init(), adiv5_ap::memaccess_tck, MVFR0, MVFR0_DEFAULT_M4, MVFR0_DEFAULT_M7_DP, MVFR0_DEFAULT_M7_SP, MVFR1, MVFR1_DEFAULT_M4, MVFR1_DEFAULT_M7_DP, MVFR1_DEFAULT_M7_SP, cortex_m_part_info::name, partno, reg_cache::reg_list, S_RESET_ST, adiv5_ap::tar_autoincr_block, target_read_u32(), target_set_examined(), target_to_armv7m(), target_to_cm(), target_was_examined(), target_write_u32(), armv7m_common::trace_config, TRCENA, cortex_m_fp_comparator::type, and cortex_m_common::vectreset_supported.
|
inlinestatic |
Definition at line 280 of file cortex_m.h.
References is_cortex_m_or_hla(), NULL, target_to_armv7m_safe(), and target_to_cm().
Referenced by stm32l4_read_idcode(), stm32x_get_device_id(), stm32x_get_property_addr(), and stm32x_probe().
int cortex_m_profiling | ( | struct target * | target, |
uint32_t * | samples, | ||
uint32_t | max_num_samples, | ||
uint32_t * | num_samples, | ||
uint32_t | seconds | ||
) |
Definition at line 2019 of file cortex_m.c.
References armv7m_common::debug_ap, DWT_PCSR, ERROR_OK, gettimeofday(), LOG_TARGET_ERROR, LOG_TARGET_INFO, mem_ap_read_buf_noincr(), NULL, target::state, TARGET_HALTED, target_poll(), target_profiling_default(), target_read_u32(), target_resume(), target_to_armv7m(), timeval_add_time(), and timeval_compare().
int cortex_m_remove_breakpoint | ( | struct target * | target, |
struct breakpoint * | breakpoint | ||
) |
Definition at line 1733 of file cortex_m.c.
References cortex_m_unset_breakpoint(), ERROR_OK, and breakpoint::is_set.
int cortex_m_remove_watchpoint | ( | struct target * | target, |
struct watchpoint * | watchpoint | ||
) |
Definition at line 1906 of file cortex_m.c.
References cortex_m_unset_watchpoint(), cortex_m_common::dwt_comp_available, ERROR_OK, ERROR_TARGET_NOT_HALTED, watchpoint::is_set, LOG_TARGET_DEBUG, LOG_TARGET_WARNING, target::state, TARGET_HALTED, and target_to_cm().
int cortex_m_set_breakpoint | ( | struct target * | target, |
struct breakpoint * | breakpoint | ||
) |
Definition at line 1592 of file cortex_m.c.
References breakpoint::address, ARMV5_T_BKPT, BKPT_HARD, BKPT_SOFT, breakpoint_hw_set(), buf_set_u32(), cortex_m_enable_fpb(), ERROR_FAIL, ERROR_OK, ERROR_TARGET_RESOURCE_NOT_AVAILABLE, cortex_m_common::fp_comparator_list, cortex_m_common::fp_num_code, cortex_m_common::fp_rev, cortex_m_common::fpb_enabled, cortex_m_fp_comparator::fpcr_address, FPCR_REPLACE_BKPT_HIGH, FPCR_REPLACE_BKPT_LOW, cortex_m_fp_comparator::fpcr_value, breakpoint::is_set, breakpoint::length, LOG_TARGET_DEBUG, LOG_TARGET_ERROR, LOG_TARGET_WARNING, breakpoint::number, breakpoint::orig_instr, TARGET_ADDR_FMT, target_read_memory(), target_to_cm(), target_write_memory(), target_write_u32(), breakpoint::type, breakpoint::unique_id, and cortex_m_fp_comparator::used.
Referenced by adapter_resume(), adapter_step(), cortex_m_add_breakpoint(), cortex_m_enable_breakpoints(), cortex_m_resume(), and cortex_m_step().
int cortex_m_unset_breakpoint | ( | struct target * | target, |
struct breakpoint * | breakpoint | ||
) |
Definition at line 1677 of file cortex_m.c.
References breakpoint::address, BKPT_HARD, BKPT_SOFT, ERROR_OK, cortex_m_common::fp_comparator_list, cortex_m_common::fp_num_code, cortex_m_fp_comparator::fpcr_address, cortex_m_fp_comparator::fpcr_value, breakpoint::is_set, breakpoint::length, LOG_TARGET_DEBUG, LOG_TARGET_WARNING, breakpoint::number, breakpoint::orig_instr, TARGET_ADDR_FMT, target_to_cm(), target_write_memory(), target_write_u32(), breakpoint::type, breakpoint::unique_id, and cortex_m_fp_comparator::used.
Referenced by adapter_resume(), adapter_step(), cortex_m_remove_breakpoint(), cortex_m_resume(), and cortex_m_step().
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inlinestatic |
Definition at line 247 of file cortex_m.h.
References cortex_m_common::common_magic, and CORTEX_M_COMMON_MAGIC.
Referenced by cortex_m_get_partno_safe(), and is_cortex_m_with_dap_access().
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inlinestatic |
Definition at line 252 of file cortex_m.h.
References cortex_m_common::armv7m, is_cortex_m_or_hla(), and armv7m_common::is_hla_target.
Referenced by cortex_m_verify_pointer().
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inlinestatic |
Definition at line 267 of file cortex_m.h.
References target::arch_info, armv7m_common::arm, cortex_m_common::armv7m, and container_of.
Referenced by COMMAND_HANDLER(), cortex_m_add_watchpoint(), cortex_m_assert_reset(), cortex_m_clear_halt(), cortex_m_deassert_reset(), cortex_m_debug_entry(), cortex_m_deinit_target(), cortex_m_dwt_free(), cortex_m_endreset_event(), cortex_m_examine(), cortex_m_examine_debug_reason(), cortex_m_fast_read_all_regs(), cortex_m_get_partno_safe(), cortex_m_hit_watchpoint(), cortex_m_load_core_reg_u32(), cortex_m_poll(), cortex_m_read_dhcsr_atomic_sticky(), cortex_m_remove_watchpoint(), cortex_m_set_breakpoint(), cortex_m_set_maskints(), cortex_m_set_maskints_for_halt(), cortex_m_set_maskints_for_run(), cortex_m_set_maskints_for_step(), cortex_m_set_watchpoint(), cortex_m_single_step_core(), cortex_m_slow_read_all_regs(), cortex_m_soft_reset_halt(), cortex_m_step(), cortex_m_store_core_reg_u32(), cortex_m_unset_breakpoint(), cortex_m_unset_watchpoint(), cortex_m_write_debug_halt_mask(), efm32x_read_info(), and jim_arm_tpiu_swo_enable().
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Definition at line 280 of file cortex_m.h.