116 #define FLASH_ERASE_TIMEOUT 250
117 #define FLASH_WRITE_TIMEOUT 50
123 #define F_HAS_DUAL_BANK BIT(0)
126 #define F_USE_ALL_WRPXX BIT(1)
128 #define F_HAS_TZ BIT(2)
130 #define F_HAS_L5_FLASH_REGS BIT(3)
133 #define F_QUAD_WORD_PROG BIT(4)
269 { 0x1000,
"1" }, { 0x1001,
"2" }, { 0x1003,
"3" }, { 0x1007,
"4" }
273 { 0x1000,
"A" }, { 0x1001,
"Z" }, { 0x2001,
"Y" },
281 { 0x1000,
"A/Z" } , { 0x2000,
"B" },
285 { 0x1000,
"A" }, { 0x2000,
"B" },
289 { 0x1000,
"A" }, { 0x1001,
"Z" }, { 0x2001,
"Y" },
293 { 0x1000,
"A" }, { 0x1001,
"Z" }, { 0x2001,
"Y" },
297 { 0x1000,
"A" }, { 0x1001,
"Z" }, { 0x2000,
"B" },
305 { 0x1000,
"A" }, { 0x2000,
"B" }, { 0x2001,
"Z" },
309 { 0x1000,
"A" }, { 0x2000,
"B" }, { 0x2001,
"Z" },
313 { 0x1000,
"A" }, { 0x1001,
"Z" }, { 0x1003,
"Y" }, { 0x100F,
"W" },
321 { 0x1000,
"A" }, { 0x2000,
"B" },
329 { 0x1000,
"A" }, { 0x1001,
"Z" }, { 0x1003,
"Y" }, { 0x2000,
"B" },
333 { 0x1000,
"A" }, { 0x2000,
"B" },
353 .device_str =
"STM32L47/L48xx",
354 .max_flash_size_kb = 1024,
356 .flash_regs_base = 0x40022000,
357 .fsize_addr = 0x1FFF75E0,
358 .otp_base = 0x1FFF7000,
365 .device_str =
"STM32L43/L44xx",
366 .max_flash_size_kb = 256,
368 .flash_regs_base = 0x40022000,
369 .fsize_addr = 0x1FFF75E0,
370 .otp_base = 0x1FFF7000,
377 .device_str =
"STM32G05/G06xx",
378 .max_flash_size_kb = 64,
380 .flash_regs_base = 0x40022000,
381 .fsize_addr = 0x1FFF75E0,
382 .otp_base = 0x1FFF7000,
389 .device_str =
"STM32G07/G08xx",
390 .max_flash_size_kb = 128,
392 .flash_regs_base = 0x40022000,
393 .fsize_addr = 0x1FFF75E0,
394 .otp_base = 0x1FFF7000,
401 .device_str =
"STM32L49/L4Axx",
402 .max_flash_size_kb = 1024,
404 .flash_regs_base = 0x40022000,
405 .fsize_addr = 0x1FFF75E0,
406 .otp_base = 0x1FFF7000,
413 .device_str =
"STM32L45/L46xx",
414 .max_flash_size_kb = 512,
416 .flash_regs_base = 0x40022000,
417 .fsize_addr = 0x1FFF75E0,
418 .otp_base = 0x1FFF7000,
425 .device_str =
"STM32L41/L42xx",
426 .max_flash_size_kb = 128,
428 .flash_regs_base = 0x40022000,
429 .fsize_addr = 0x1FFF75E0,
430 .otp_base = 0x1FFF7000,
437 .device_str =
"STM32G03x/G04xx",
438 .max_flash_size_kb = 64,
440 .flash_regs_base = 0x40022000,
441 .fsize_addr = 0x1FFF75E0,
442 .otp_base = 0x1FFF7000,
449 .device_str =
"STM32G0B/G0Cx",
450 .max_flash_size_kb = 512,
452 .flash_regs_base = 0x40022000,
453 .fsize_addr = 0x1FFF75E0,
454 .otp_base = 0x1FFF7000,
461 .device_str =
"STM32G43/G44xx",
462 .max_flash_size_kb = 128,
464 .flash_regs_base = 0x40022000,
465 .fsize_addr = 0x1FFF75E0,
466 .otp_base = 0x1FFF7000,
473 .device_str =
"STM32G47/G48xx",
474 .max_flash_size_kb = 512,
476 .flash_regs_base = 0x40022000,
477 .fsize_addr = 0x1FFF75E0,
478 .otp_base = 0x1FFF7000,
485 .device_str =
"STM32L4R/L4Sxx",
486 .max_flash_size_kb = 2048,
488 .flash_regs_base = 0x40022000,
489 .fsize_addr = 0x1FFF75E0,
490 .otp_base = 0x1FFF7000,
497 .device_str =
"STM32L4P/L4Qxx",
498 .max_flash_size_kb = 1024,
500 .flash_regs_base = 0x40022000,
501 .fsize_addr = 0x1FFF75E0,
502 .otp_base = 0x1FFF7000,
509 .device_str =
"STM32L55/L56xx",
510 .max_flash_size_kb = 512,
512 .flash_regs_base = 0x40022000,
513 .fsize_addr = 0x0BFA05E0,
514 .otp_base = 0x0BFA0000,
521 .device_str =
"STM32G49/G4Axx",
522 .max_flash_size_kb = 512,
524 .flash_regs_base = 0x40022000,
525 .fsize_addr = 0x1FFF75E0,
526 .otp_base = 0x1FFF7000,
533 .device_str =
"STM32U57/U58xx",
534 .max_flash_size_kb = 2048,
536 .flash_regs_base = 0x40022000,
537 .fsize_addr = 0x0BFA07A0,
538 .otp_base = 0x0BFA0000,
545 .device_str =
"STM32WB1x",
546 .max_flash_size_kb = 320,
548 .flash_regs_base = 0x58004000,
549 .fsize_addr = 0x1FFF75E0,
550 .otp_base = 0x1FFF7000,
557 .device_str =
"STM32WB5x",
558 .max_flash_size_kb = 1024,
560 .flash_regs_base = 0x58004000,
561 .fsize_addr = 0x1FFF75E0,
562 .otp_base = 0x1FFF7000,
569 .device_str =
"STM32WB3x",
570 .max_flash_size_kb = 512,
572 .flash_regs_base = 0x58004000,
573 .fsize_addr = 0x1FFF75E0,
574 .otp_base = 0x1FFF7000,
581 .device_str =
"STM32WLE/WL5x",
582 .max_flash_size_kb = 256,
584 .flash_regs_base = 0x58004000,
585 .fsize_addr = 0x1FFF75E0,
586 .otp_base = 0x1FFF7000,
606 bank->driver_priv = stm32l4_info;
608 stm32l4_info->
probed =
false;
622 struct range *ranges,
unsigned int *ranges_count) {
624 bool last_bit = 0, cur_bit;
625 for (
unsigned int i = 0; i < nbits; i++) {
628 if (cur_bit && !last_bit) {
630 ranges[*ranges_count - 1].
start = i;
631 ranges[*ranges_count - 1].
end = i;
632 }
else if (cur_bit && last_bit) {
634 ranges[*ranges_count - 1].
end = i;
657 char *str = calloc(1, ranges_count * (24 *
sizeof(
char)) + 1);
660 for (
unsigned int i = 0; i < ranges_count; i++) {
663 if (i < ranges_count - 1)
685 char *op_str = enable ?
"enabled" :
"disabled";
687 LOG_INFO(
"OTP memory (bank #%d) is %s%s for write commands",
689 stm32l4_info->
otp_enabled == enable ?
"already " :
"",
784 LOG_ERROR(
"timed out waiting for flash");
826 LOG_DEBUG(
"setting secure block-based areas registers (SECBBxRy) to 0x%08x", value);
828 const uint8_t secbb_regs[] = {
834 unsigned int num_secbb_regs =
ARRAY_SIZE(secbb_regs);
842 for (
unsigned int i = 0; i < num_secbb_regs; i++) {
887 LOG_ERROR(
"flash not unlocked STM32_FLASH_CR: %" PRIx32,
ctrl);
920 LOG_ERROR(
"options not unlocked STM32_FLASH_CR: %" PRIx32,
ctrl);
952 stm32l4_info->
probed =
false;
965 uint32_t value, uint32_t
mask)
977 const uint32_t *saved_flash_regs = stm32l4_info->
flash_regs;
989 optiondata = (optiondata & ~
mask) | (value &
mask);
1047 int wrp2y_sectors_offset = -1;
1063 wrp2y_sectors_offset = 0;
1070 if (wrp2y_sectors_offset >= 0) {
1092 uint32_t wrp_value = (wrp_start & stm32l4_info->
wrpxxr_mask) | ((wrp_end & stm32l4_info->
wrpxxr_mask) << 16);
1101 for (
unsigned int i = 0; i < n_wrp; i++) {
1120 for (
unsigned int i = 0; i <
bank->num_sectors; i++)
1121 bank->sectors[i].is_protected = 0;
1124 for (
unsigned int i = 0; i < n_wrp; i++) {
1125 if (wrpxy[i].
used) {
1126 for (
int s = wrpxy[i].
first; s <= wrpxy[i].
last; s++)
1127 bank->sectors[s].is_protected = 1;
1138 int retval, retval2;
1140 assert((first <= last) && (last < bank->num_sectors));
1177 for (
unsigned int i = first; i <= last; i++) {
1178 uint32_t erase_flags;
1213 unsigned int first,
unsigned int last)
1218 for (i = first; i <= last; i++) {
1219 if (
bank->sectors[i].is_protected != set)
1221 else if (i == last) {
1222 LOG_INFO(
"The specified sectors are already %s", set ?
"protected" :
"unprotected");
1240 for (i = 0; i < n_wrp; i++) {
1241 if (wrpxy[i].
used) {
1242 for (
int p = wrpxy[i].
first; p <= wrpxy[i].
last; p++)
1249 struct range ranges[n_wrp + 1];
1250 unsigned int ranges_count = 0;
1255 if (ranges_count > 0) {
1257 LOG_DEBUG(
"current protected areas: %s", ranges_str);
1260 LOG_DEBUG(
"current protected areas: none");
1263 for (i = first; i <= last; i++)
1266 for (i = first; i <= last; i++)
1274 if (ranges_count > 0) {
1276 LOG_DEBUG(
"requested areas for protection: %s", ranges_str);
1279 LOG_DEBUG(
"requested areas for protection: none");
1281 if (ranges_count > n_wrp) {
1282 LOG_ERROR(
"cannot set the requested protection "
1283 "(only %u write protection areas are available)" , n_wrp);
1288 for (i = 0; i < n_wrp; i++) {
1294 for (i = 0; i < ranges_count; i++) {
1296 wrpxy[i].
last = ranges[i].
end;
1309 LOG_ERROR(
"cannot protect/unprotect OTP memory");
1350 static const uint8_t stm32l4_flash_write_code[] = {
1351 #include "../../../contrib/loaders/flash/stm32/stm32l4x.inc"
1356 LOG_WARNING(
"no working area available, can't do block memory writes");
1361 sizeof(stm32l4_flash_write_code),
1362 stm32l4_flash_write_code);
1373 buffer_size &= ~(stm32l4_info->
data_width - 1);
1375 if (buffer_size < 256) {
1376 LOG_WARNING(
"large enough working area not available, can't do block memory writes");
1379 }
else if (buffer_size > 16384) {
1381 buffer_size = 16384;
1385 LOG_ERROR(
"allocating working area failed");
1408 struct stm32l4_loader_params loader_extra_params;
1420 (uint8_t *) &loader_extra_params);
1433 LOG_ERROR(
"error executing stm32l4 flash write algorithm");
1440 LOG_ERROR(
"flash memory write protected");
1443 LOG_ERROR(
"flash write failed = %08" PRIx32, error);
1483 const uint8_t *src =
buffer;
1484 const uint32_t data_width_in_words = stm32l4_info->
data_width / 4;
1514 LOG_ERROR(
"OTP memory is disabled for write commands");
1539 while ((head < tail) && (
offset >= (head + 1)->
offset)) {
1549 LOG_DEBUG(
"data: 0x%08" PRIx32
" - 0x%08" PRIx32
", sectors: 0x%08" PRIx32
" - 0x%08" PRIx32,
1555 while (head < tail) {
1556 if (head->
offset + head->
size != (head + 1)->offset) {
1559 bank->base + (head + 1)->offset - 1);
1588 LOG_WARNING(
"RDP = 0x55, the work-area should be in non-secure RAM (check SAU partitioning)");
1596 LOG_WARNING(
"falling back to programming without a flash loader (slower)");
1626 for (
unsigned int i = 0; i <
ARRAY_SIZE(dbgmcu_idcode); i++) {
1628 if ((retval ==
ERROR_OK) && ((*
id & 0xfff) != 0) && ((*
id & 0xfff) != 0xfff))
1638 LOG_ERROR(
"Flash requires Cortex-M target");
1673 const uint16_t rev_id = stm32l4_info->
idcode >> 16;
1674 for (
unsigned int i = 0; i < part_info->
num_revs; i++) {
1675 if (rev_id == part_info->
revs[i].
rev)
1676 return part_info->
revs[i].
str;
1695 uint16_t flash_size_kb = 0xffff;
1704 LOG_ERROR(
"Flash requires Cortex-M target");
1708 stm32l4_info->
probed =
false;
1715 const uint32_t device_id = stm32l4_info->
idcode & 0xFFF;
1731 const uint16_t rev_id = stm32l4_info->
idcode >> 16;
1733 LOG_INFO(
"device idcode = 0x%08" PRIx32
" (%s - Rev %s : 0x%04x)",
1764 LOG_ERROR(
"BUG: device supported incomplete");
1770 LOG_INFO(
"TZEN = %d : TrustZone %s by option bytes",
1772 stm32l4_info->
tzen ?
"enabled" :
"disabled");
1784 free(
bank->sectors);
1785 bank->num_sectors = 1;
1788 if (!
bank->sectors) {
1789 LOG_ERROR(
"failed to allocate bank sectors");
1793 stm32l4_info->
probed =
true;
1805 if (retval !=
ERROR_OK || flash_size_kb == 0xffff || flash_size_kb == 0
1807 LOG_WARNING(
"STM32 flash size failed, probe inaccurate - assuming %dk flash",
1815 LOG_WARNING(
"overriding size register by configured bank size - MAY CAUSE TROUBLE");
1819 LOG_INFO(
"flash size = %d KiB", flash_size_kb);
1822 assert((flash_size_kb != 0xffff) && flash_size_kb);
1830 int page_size_kb = 0;
1834 switch (device_id) {
1846 num_pages = flash_size_kb / page_size_kb;
1866 num_pages = flash_size_kb / page_size_kb;
1872 num_pages = flash_size_kb / page_size_kb;
1889 num_pages = flash_size_kb / page_size_kb;
1894 num_pages = flash_size_kb / page_size_kb;
1912 num_pages = flash_size_kb / page_size_kb;
1918 num_pages = flash_size_kb / page_size_kb;
1931 num_pages = flash_size_kb / page_size_kb;
1945 num_pages = flash_size_kb / page_size_kb;
1956 num_pages = flash_size_kb / page_size_kb;
1962 num_pages = flash_size_kb / page_size_kb;
1976 if (num_pages == 0) {
1978 LOG_ERROR(
"The specified flash size is less than page size");
1980 LOG_ERROR(
"Flash pages count cannot be zero");
1986 const int gap_size_kb = stm32l4_info->
hole_sectors * page_size_kb;
1988 if (gap_size_kb != 0) {
1989 LOG_INFO(
"gap detected from 0x%08x to 0x%08x",
1991 * page_size_kb * 1024,
1993 * page_size_kb + gap_size_kb) * 1024 - 1);
2009 assert((stm32l4_info->
wrpxxr_mask & 0xFFFF0000) == 0);
2012 free(
bank->sectors);
2014 bank->size = (flash_size_kb + gap_size_kb) * 1024;
2015 bank->num_sectors = num_pages;
2017 if (!
bank->sectors) {
2018 LOG_ERROR(
"failed to allocate bank sectors");
2022 for (
unsigned int i = 0; i <
bank->num_sectors; i++) {
2023 bank->sectors[i].offset = i * page_size_kb * 1024;
2027 bank->sectors[i].offset += gap_size_kb * 1024;
2028 bank->sectors[i].size = page_size_kb * 1024;
2029 bank->sectors[i].is_erased = -1;
2030 bank->sectors[i].is_protected = 1;
2033 stm32l4_info->
probed =
true;
2040 if (stm32l4_info->
probed) {
2059 if (stm32l4_info->
optr == optr_cur)
2072 const uint16_t rev_id = stm32l4_info->
idcode >> 16;
2075 if (stm32l4_info->
probed)
2086 int retval, retval2;
2174 command_print(
CMD,
"stm32l4x option_read <STM32L4 bank> <option_reg offset>");
2183 uint32_t reg_offset, reg_addr;
2193 command_print(
CMD,
"Option Register: <0x%" PRIx32
"> = 0x%" PRIx32
"", reg_addr, value);
2201 command_print(
CMD,
"stm32l4x option_write <STM32L4 bank> <option_reg offset> <value> [mask]");
2210 uint32_t reg_offset;
2212 uint32_t
mask = 0xFFFFFFFF;
2221 "INFO: a reset or power cycle is required "
2222 "for the new settings to take effect.",
bank->driver->name);
2230 if (CMD_ARGC < 1 || CMD_ARGC > 2)
2240 LOG_ERROR(
"This device does not have a TrustZone");
2252 LOG_INFO(
"Global TrustZone Security is %s", stm32l4_info->
tzen ?
"enabled" :
"disabled");
2259 if (new_tzen == stm32l4_info->
tzen) {
2260 LOG_INFO(
"The requested TZEN is already programmed");
2266 LOG_ERROR(
"TZEN can be set only when RDP level is 0");
2275 LOG_ERROR(
"Deactivation of TZEN is only possible when the RDP is changing to level 0");
2306 command_print(
CMD,
"stm32l4x option load completed. Power-on reset might be required");
2324 LOG_ERROR(
"cannot lock/unlock OTP memory");
2359 LOG_ERROR(
"cannot lock/unlock OTP memory");
2382 if (CMD_ARGC < 1 || CMD_ARGC > 2)
2391 LOG_ERROR(
"OTP memory does not have write protection areas");
2398 if (strcmp(
CMD_ARGV[1],
"bank1") == 0)
2400 else if (strcmp(
CMD_ARGV[1],
"bank2") == 0)
2408 LOG_ERROR(
"this device has no second bank");
2411 LOG_ERROR(
"this device is configured in single bank mode");
2417 unsigned int n_wrp, i;
2428 for (i = 0; i < n_wrp; i++) {
2429 if (wrpxy[i].
used) {
2430 for (
int p = wrpxy[i].
first; p <= wrpxy[i].
last; p++)
2436 struct range ranges[n_wrp];
2437 unsigned int ranges_count = 0;
2441 if (ranges_count > 0) {
2466 if (strcmp(
CMD_ARGV[1],
"enable") == 0)
2468 else if (strcmp(
CMD_ARGV[1],
"disable") == 0)
2470 else if (strcmp(
CMD_ARGV[1],
"show") == 0)
2482 .handler = stm32l4_handle_lock_command,
2485 .help =
"Lock entire flash device.",
2489 .handler = stm32l4_handle_unlock_command,
2492 .help =
"Unlock entire protected flash device.",
2495 .name =
"mass_erase",
2496 .handler = stm32l4_handle_mass_erase_command,
2499 .help =
"Erase entire flash device.",
2502 .name =
"option_read",
2503 .handler = stm32l4_handle_option_read_command,
2505 .usage =
"bank_id reg_offset",
2506 .help =
"Read & Display device option bytes.",
2509 .name =
"option_write",
2510 .handler = stm32l4_handle_option_write_command,
2512 .usage =
"bank_id reg_offset value mask",
2513 .help =
"Write device option bit fields with provided value.",
2516 .name =
"trustzone",
2517 .handler = stm32l4_handle_trustzone_command,
2519 .usage =
"<bank_id> [enable|disable]",
2520 .help =
"Configure TrustZone security",
2524 .handler = stm32l4_handle_wrp_info_command,
2526 .usage =
"bank_id [bank1|bank2]",
2527 .help =
"list the protected areas using WRP",
2530 .name =
"option_load",
2531 .handler = stm32l4_handle_option_load_command,
2534 .help =
"Force re-load of device options (will cause device reset).",
2538 .handler = stm32l4_handle_otp_command,
2540 .usage =
"<bank_id> <enable|disable|show>",
2541 .help =
"OTP (One Time Programmable) memory write enable/disable",
2550 .help =
"stm32l4x flash command group",
2560 .flash_bank_command = stm32l4_flash_bank_command,
void init_reg_param(struct reg_param *param, char *reg_name, uint32_t size, enum param_direction direction)
void destroy_reg_param(struct reg_param *param)
This defines formats and data structures used to talk to ADIv5 entities.
static struct armv7m_common * target_to_armv7m_safe(struct target *target)
#define ARMV7M_COMMON_MAGIC
Support functions to access arbitrary bits in a byte array.
static void buf_set_u32(uint8_t *_buffer, unsigned first, unsigned num, uint32_t value)
Sets num bits in _buffer, starting at the first bit, using the bits in value.
static int test_bit(unsigned int nr, const volatile unsigned long *addr)
test_bit - Determine whether a bit is set
static void bitmap_zero(unsigned long *dst, unsigned int nbits)
bitmap_zero - Clears all the bits in memory
static void set_bit(unsigned int nr, volatile unsigned long *addr)
set_bit - Set a bit in memory
static void clear_bit(unsigned int nr, volatile unsigned long *addr)
clear_bit - Clear a bit in memory
#define DECLARE_BITMAP(name, bits)
void command_print_sameline(struct command_invocation *cmd, const char *format,...)
void command_print(struct command_invocation *cmd, const char *format,...)
#define CMD
Use this macro to access the command being handled, rather than accessing the variable directly.
#define CALL_COMMAND_HANDLER(name, extra ...)
Use this to macro to call a command helper (or a nested handler).
#define CMD_ARGV
Use this macro to access the arguments for the command being handled, rather than accessing the varia...
#define ERROR_COMMAND_SYNTAX_ERROR
#define CMD_ARGC
Use this macro to access the number of arguments for the command being handled, rather than accessing...
#define COMMAND_PARSE_ENABLE(in, out)
parses an enable/disable command argument
#define COMMAND_PARSE_NUMBER(type, in, out)
parses the string in into out as a type, or prints a command error and passes the error code to the c...
#define COMMAND_REGISTRATION_DONE
Use this as the last entry in an array of command_registration records.
#define ERROR_COMMAND_ARGUMENT_INVALID
static enum cortex_m_partno cortex_m_get_partno_safe(struct target *target)
#define ERROR_FLASH_OPER_UNSUPPORTED
#define ERROR_FLASH_OPERATION_FAILED
#define ERROR_FLASH_DST_OUT_OF_BANK
struct flash_sector * alloc_block_array(uint32_t offset, uint32_t size, unsigned int num_blocks)
Allocate and fill an array of sectors or protection blocks.
int default_flash_blank_check(struct flash_bank *bank)
Provides default erased-bank check handling.
int default_flash_read(struct flash_bank *bank, uint8_t *buffer, uint32_t offset, uint32_t count)
Provides default read implementation for flash memory.
void default_flash_free_driver_priv(struct flash_bank *bank)
Deallocates bank->driver_priv.
void alive_sleep(uint64_t ms)
#define ERROR_NOT_IMPLEMENTED
#define LOG_WARNING(expr ...)
#define LOG_ERROR(expr ...)
#define LOG_INFO(expr ...)
#define LOG_DEBUG(expr ...)
struct rtt_control ctrl
Control block.
size_t size
Size of the control block search area.
static const struct stm32l4_rev stm32g05_g06xx_revs[]
static int stm32l4_get_all_wrpxy(struct flash_bank *bank, enum stm32_bank_id dev_bank_id, struct stm32l4_wrp *wrpxy, unsigned int *n_wrp)
static int stm32l4_protect_check(struct flash_bank *bank)
#define FLASH_ERASE_TIMEOUT
static int stm32l4_get_one_wrpxy(struct flash_bank *bank, struct stm32l4_wrp *wrpxy, enum stm32l4_flash_reg_index reg_idx, int offset)
static const struct stm32l4_rev stm32l43_l44xx_revs[]
static const struct command_registration stm32l4_exec_command_handlers[]
static int stm32l4_write_flash_reg(struct flash_bank *bank, uint32_t reg_offset, uint32_t value)
static const uint32_t stm32l4_flash_regs[STM32_FLASH_REG_INDEX_NUM]
@ STM32_FLASH_CR_WLK_INDEX
@ STM32_FLASH_WRP1AR_INDEX
@ STM32_FLASH_WRP2BR_INDEX
@ STM32_FLASH_OPTKEYR_INDEX
@ STM32_FLASH_WRP1BR_INDEX
@ STM32_FLASH_WRP2AR_INDEX
@ STM32_FLASH_REG_INDEX_NUM
static int stm32l4_perform_obl_launch(struct flash_bank *bank)
static const struct stm32l4_part_info stm32l4_parts[]
static char * range_print_alloc(struct range *ranges, unsigned int ranges_count)
static int stm32l4_read_idcode(struct flash_bank *bank, uint32_t *id)
static const struct stm32l4_rev stm32g47_g48xx_revs[]
static int stm32l4_read_flash_reg(struct flash_bank *bank, uint32_t reg_offset, uint32_t *value)
static bool stm32l4_otp_is_enabled(struct flash_bank *bank)
#define F_HAS_L5_FLASH_REGS
static const char * get_stm32l4_bank_type_str(struct flash_bank *bank)
static bool stm32l4_is_otp(struct flash_bank *bank)
static int stm32l4_get_flash_cr_with_lock_index(struct flash_bank *bank)
static int range_print_one(struct range *range, char *str)
static const struct stm32l4_rev stm32g03_g04xx_revs[]
static const char * device_families
static const struct stm32l4_rev stm32u57_u58xx_revs[]
static const struct command_registration stm32l4_command_handlers[]
static const struct stm32l4_rev stm32l45_l46xx_revs[]
static int stm32l4_erase(struct flash_bank *bank, unsigned int first, unsigned int last)
static const struct stm32l4_rev stm32l4p_l4qxx_revs[]
static const struct stm32l4_rev stm32l41_l42xx_revs[]
static int stm32l4_otp_enable(struct flash_bank *bank, bool enable)
static const struct stm32l4_rev stm32l47_l48xx_revs[]
static const struct stm32l4_rev stm32l4r_l4sxx_revs[]
static int stm32l4_write_option(struct flash_bank *bank, uint32_t reg_offset, uint32_t value, uint32_t mask)
static const struct stm32l4_rev stm32l55_l56xx_revs[]
static const struct stm32l4_rev stm32wb1xx_revs[]
static int stm32l4_wait_status_busy(struct flash_bank *bank, int timeout)
static int stm32l4_mass_erase(struct flash_bank *bank)
static const char * get_stm32l4_rev_str(struct flash_bank *bank)
static int get_stm32l4_info(struct flash_bank *bank, struct command_invocation *cmd)
COMMAND_HANDLER(stm32l4_handle_mass_erase_command)
static const struct stm32l4_rev stm32_g07_g08xx_revs[]
static const struct stm32l4_rev stm32g43_g44xx_revs[]
static uint32_t stm32l4_get_flash_reg(struct flash_bank *bank, uint32_t reg_offset)
static const struct stm32l4_rev stm32wle_wl5xx_revs[]
static int stm32l4_protect_same_bank(struct flash_bank *bank, enum stm32_bank_id bank_id, int set, unsigned int first, unsigned int last)
FLASH_BANK_COMMAND_HANDLER(stm32l4_flash_bank_command)
static int stm32l4_set_secbb(struct flash_bank *bank, uint32_t value)
set all FLASH_SECBB registers to the same value
static int stm32l4_write(struct flash_bank *bank, const uint8_t *buffer, uint32_t offset, uint32_t count)
static const struct stm32l4_rev stm32g49_g4axx_revs[]
const struct flash_driver stm32l4x_flash
static int stm32l4_probe(struct flash_bank *bank)
static const uint32_t stm32l5_s_flash_regs[STM32_FLASH_REG_INDEX_NUM]
static int stm32l4_write_block_without_loader(struct flash_bank *bank, const uint8_t *buffer, uint32_t offset, uint32_t count)
static int stm32l4_read_flash_reg_by_index(struct flash_bank *bank, enum stm32l4_flash_reg_index reg_index, uint32_t *value)
static int stm32l4_unlock_option_reg(struct flash_bank *bank)
static const uint32_t stm32wl_cpu2_flash_regs[STM32_FLASH_REG_INDEX_NUM]
static int stm32l4_unlock_reg(struct flash_bank *bank)
static int stm32l4_write_all_wrpxy(struct flash_bank *bank, struct stm32l4_wrp *wrpxy, unsigned int n_wrp)
static void stm32l4_sync_rdp_tzen(struct flash_bank *bank)
static const struct stm32l4_rev stm32wb3xx_revs[]
#define FLASH_WRITE_TIMEOUT
static const struct stm32l4_rev stm32wb5xx_revs[]
static void bitmap_to_ranges(unsigned long *bitmap, unsigned int nbits, struct range *ranges, unsigned int *ranges_count)
static const uint32_t stm32l5_ns_flash_regs[STM32_FLASH_REG_INDEX_NUM]
static int stm32l4_write_block(struct flash_bank *bank, const uint8_t *buffer, uint32_t offset, uint32_t count)
static int stm32l4_write_flash_reg_by_index(struct flash_bank *bank, enum stm32l4_flash_reg_index reg_index, uint32_t value)
static int stm32l4_protect(struct flash_bank *bank, int set, unsigned int first, unsigned int last)
static uint32_t stm32l4_get_flash_reg_by_index(struct flash_bank *bank, enum stm32l4_flash_reg_index reg_index)
static int stm32l4_write_one_wrpxy(struct flash_bank *bank, struct stm32l4_wrp *wrpxy)
static const struct stm32l4_rev stm32l49_l4axx_revs[]
static int stm32l4_auto_probe(struct flash_bank *bank)
static const struct stm32l4_rev stm32g0b_g0cxx_revs[]
#define DEVID_STM32G03_G04XX
#define DEVID_STM32L55_L56XX
#define DEVID_STM32G0B_G0CXX
#define FLASH_SECBB_SECURE
#define FLASH_G0_DUAL_BANK
#define STM32_FLASH_S_BANK_BASE
#define DEVID_STM32G49_G4AXX
#define DEVID_STM32L4R_L4SXX
#define FLASH_L4_DUAL_BANK
#define DEVID_STM32G47_G48XX
#define FLASH_U5_DUALBANK
#define STM32_FLASH_BANK_BASE
#define FLASH_G4_DUAL_BANK
#define DEVID_STM32L47_L48XX
#define DEVID_STM32G07_G08XX
#define DEVID_STM32L49_L4AXX
#define DEVID_STM32L43_L44XX
#define DEVID_STM32L41_L42XX
#define DEVID_STM32WLE_WL5XX
#define DEVID_STM32G05_G06XX
#define DEVID_STM32G43_G44XX
#define UID64_IDS_STM32WL
#define FLASH_SECBB_NON_SECURE
#define STM32L5_REGS_SEC_OFFSET
#define DEVID_STM32U57_U58XX
#define DBGMCU_IDCODE_L4_G4
#define DEVID_STM32L4P_L4QXX
#define DEVID_STM32L45_L46XX
uint64_t ap_num
ADIv5: Number of this AP (0~255) ADIv6: Base address of this AP (4k aligned) TODO: to be more coheren...
unsigned int common_magic
struct adiv5_ap * debug_ap
When run_command is called, a new instance will be created on the stack, filled with the proper value...
Provides details of a flash bank, available either on-chip or through a major interface.
Provides the implementation-independent structure that defines all of the callbacks required by OpenO...
const char * name
Gives a human-readable name of this flash driver, This field is used to select and initialize the dri...
Describes the geometry and status of a single flash sector within a flash bank.
uint32_t offset
Bus offset from start of the flash chip (in bytes).
uint32_t size
Number of bytes in this flash sector.
unsigned int bank1_sectors
const uint32_t * flash_regs
const struct stm32l4_part_info * part_info
const struct stm32l4_rev * revs
const uint32_t fsize_addr
const uint32_t flash_regs_base
const uint16_t max_flash_size_kb
uint8_t stack[LDR_STACK_SIZE]
enum stm32l4_flash_reg_index reg_idx
void target_buffer_set_u32(struct target *target, uint8_t *buffer, uint32_t value)
int target_write_buffer(struct target *target, target_addr_t address, uint32_t size, const uint8_t *buffer)
int target_write_memory(struct target *target, target_addr_t address, uint32_t size, uint32_t count, const uint8_t *buffer)
Write count items of size bytes to the memory of target at the address given.
uint32_t target_get_working_area_avail(struct target *target)
int target_alloc_working_area(struct target *target, uint32_t size, struct working_area **area)
int target_write_u32(struct target *target, target_addr_t address, uint32_t value)
int target_free_working_area(struct target *target, struct working_area *area)
Free a working area.
int target_alloc_working_area_try(struct target *target, uint32_t size, struct working_area **area)
int target_read_u16(struct target *target, target_addr_t address, uint16_t *value)
int target_run_flash_async_algorithm(struct target *target, const uint8_t *buffer, uint32_t count, int block_size, int num_mem_params, struct mem_param *mem_params, int num_reg_params, struct reg_param *reg_params, uint32_t buffer_start, uint32_t buffer_size, uint32_t entry_point, uint32_t exit_point, void *arch_info)
Streams data to a circular buffer on target intended for consumption by code running asynchronously o...
int target_read_u32(struct target *target, target_addr_t address, uint32_t *value)
#define ERROR_TARGET_NOT_HALTED
#define ERROR_TARGET_INVALID
#define ERROR_TARGET_NOT_EXAMINED
#define ERROR_TARGET_RESOURCE_NOT_AVAILABLE
static bool target_was_examined(struct target *target)
#define ERROR_TARGET_FAILURE
#define ARRAY_SIZE(x)
Compute the number of elements of a variable length array.