27 #define FLASH_REG_BASE_B0 0x40022000
28 #define FLASH_REG_BASE_B1 0x40022040
30 #define STM32_FLASH_ACR 0x00
31 #define STM32_FLASH_KEYR 0x04
32 #define STM32_FLASH_OPTKEYR 0x08
33 #define STM32_FLASH_SR 0x0C
34 #define STM32_FLASH_CR 0x10
35 #define STM32_FLASH_AR 0x14
36 #define STM32_FLASH_OBR 0x1C
37 #define STM32_FLASH_WRPR 0x20
42 #define STM32_FLASH_ACR_B0 0x40022000
43 #define STM32_FLASH_KEYR_B0 0x40022004
44 #define STM32_FLASH_OPTKEYR_B0 0x40022008
45 #define STM32_FLASH_SR_B0 0x4002200C
46 #define STM32_FLASH_CR_B0 0x40022010
47 #define STM32_FLASH_AR_B0 0x40022014
48 #define STM32_FLASH_OBR_B0 0x4002201C
49 #define STM32_FLASH_WRPR_B0 0x40022020
53 #define STM32_OB_RDP 0x1FFFF800
54 #define STM32_OB_USER 0x1FFFF802
55 #define STM32_OB_DATA0 0x1FFFF804
56 #define STM32_OB_DATA1 0x1FFFF806
57 #define STM32_OB_WRP0 0x1FFFF808
58 #define STM32_OB_WRP1 0x1FFFF80A
59 #define STM32_OB_WRP2 0x1FFFF80C
60 #define STM32_OB_WRP3 0x1FFFF80E
64 #define FLASH_PG (1 << 0)
65 #define FLASH_PER (1 << 1)
66 #define FLASH_MER (1 << 2)
67 #define FLASH_OPTPG (1 << 4)
68 #define FLASH_OPTER (1 << 5)
69 #define FLASH_STRT (1 << 6)
70 #define FLASH_LOCK (1 << 7)
71 #define FLASH_OPTWRE (1 << 9)
72 #define FLASH_OBL_LAUNCH (1 << 13)
76 #define FLASH_BSY (1 << 0)
77 #define FLASH_PGERR (1 << 2)
78 #define FLASH_WRPRTERR (1 << 4)
79 #define FLASH_EOP (1 << 5)
86 #define OPT_RDRSTSTOP 3
87 #define OPT_RDRSTSTDBY 4
92 #define KEY1 0x45670123
93 #define KEY2 0xCDEF89AB
97 #define FLASH_WRITE_TIMEOUT 10
98 #define FLASH_ERASE_TIMEOUT 100
124 uint32_t address, uint32_t hwords_count);
137 bank->driver_priv = stm32x_info;
138 stm32x_info->
probed =
false;
145 bank->write_start_alignment =
bank->write_end_alignment = 2;
177 LOG_ERROR(
"timed out waiting for flash");
189 LOG_ERROR(
"stm32x device programming failed / flash not erased");
211 LOG_ERROR(
"Option byte operations must use bank 0");
222 uint32_t option_bytes;
294 stm32x_info =
bank->driver_priv;
317 uint8_t opt_bytes[16];
360 for (
unsigned int i = 0; i <
bank->num_prot_blocks; i++)
361 bank->prot_blocks[i].is_protected = (protection & (1 << i)) ? 0 : 1;
376 if ((first == 0) && (last == (
bank->num_sectors - 1)))
387 for (
unsigned int i = first; i <= last; i++) {
392 bank->base +
bank->sectors[i].offset);
431 LOG_ERROR(
"stm32x failed to erase options");
435 for (
unsigned int i = first; i <= last; i++) {
446 uint32_t address, uint32_t hwords_count)
450 uint32_t buffer_size;
456 static const uint8_t stm32x_flash_write_code[] = {
457 #include "../../../contrib/loaders/flash/stm32/stm32f1x.inc"
463 LOG_WARNING(
"no working area available, can't do block memory writes");
468 sizeof(stm32x_flash_write_code), stm32x_flash_write_code);
476 buffer_size =
MIN(hwords_count * 2 + 8,
MAX(buffer_size, 256));
488 LOG_WARNING(
"no large enough working area available, can't do block memory writes");
530 LOG_ERROR(
"flash write failed just before address 0x%"PRIx32,
534 for (
unsigned int i = 0; i <
ARRAY_SIZE(reg_params); i++)
544 uint32_t address, uint32_t hwords_count)
547 uint32_t buffer_size;
550 static const uint8_t gd32vf103_flash_write_code[] = {
551 #include "../../../contrib/loaders/flash/gd32vf103/gd32vf103.inc"
557 LOG_WARNING(
"no working area available, can't do block memory writes");
562 sizeof(gd32vf103_flash_write_code), gd32vf103_flash_write_code);
570 buffer_size =
MIN(hwords_count * 2,
MAX(buffer_size, 256));
576 LOG_WARNING(
"no large enough working area available, can't do block memory writes");
590 while (hwords_count > 0) {
591 uint32_t thisrun_hwords =
source->size / 2;
594 if (thisrun_hwords > hwords_count)
595 thisrun_hwords = hwords_count;
599 thisrun_hwords * 2,
buffer);
612 write_algorithm->
address +
sizeof(gd32vf103_flash_write_code) - 4,
617 write_algorithm->
address, retval);
626 LOG_ERROR(
"flash write failed at address 0x%"PRIx32,
632 buffer += thisrun_hwords * 2;
633 address += thisrun_hwords * 2;
634 hwords_count -= thisrun_hwords;
637 for (
unsigned int i = 0; i <
ARRAY_SIZE(reg_params); i++)
651 const uint8_t *
buffer, uint32_t address, uint32_t hwords_count)
658 assert(address % 2 == 0);
673 LOG_WARNING(
"couldn't use block writes, falling back to single memory accesses");
675 while (hwords_count > 0) {
706 assert(
count % 2 == 0);
716 goto reset_pg_and_lock;
721 goto reset_pg_and_lock;
748 addr->device_id = 0x40015800;
749 addr->flash_size = 0x1FFFF7CC;
752 addr->device_id = 0xE0042000;
753 addr->flash_size = 0x1FFFF7E0;
756 addr->device_id = 0xE0042000;
757 addr->flash_size = 0x1FFFF7CC;
760 addr->device_id = 0x40015800;
761 addr->flash_size = 0x1FFFF7E0;
770 addr->device_id = 0xE0042000;
771 addr->flash_size = 0x1FFFF7E0;
776 LOG_ERROR(
"Cannot identify target as a stm32x");
808 uint16_t flash_size_in_kb;
809 uint16_t max_flash_size_in_kb;
810 uint32_t dbgmcu_idcode;
812 uint32_t base_address = 0x08000000;
814 stm32x_info->
probed =
false;
827 LOG_INFO(
"device id = 0x%08" PRIx32
"", dbgmcu_idcode);
829 uint16_t device_id = dbgmcu_idcode & 0xfff;
830 uint16_t rev_id = dbgmcu_idcode >> 16;
837 max_flash_size_in_kb = 64;
847 max_flash_size_in_kb = 32;
856 max_flash_size_in_kb = 128;
865 max_flash_size_in_kb = 256;
874 max_flash_size_in_kb = 128;
887 max_flash_size_in_kb = 64;
900 max_flash_size_in_kb = 64;
908 max_flash_size_in_kb = 32;
913 max_flash_size_in_kb = 512;
918 max_flash_size_in_kb = 256;
923 max_flash_size_in_kb = 1024;
929 max_flash_size_in_kb = 128;
934 max_flash_size_in_kb = 512;
939 max_flash_size_in_kb = 256;
948 max_flash_size_in_kb = 512;
957 max_flash_size_in_kb = 256;
967 max_flash_size_in_kb = 64;
974 LOG_WARNING(
"Cannot identify target as a STM32 family.");
983 if (retval !=
ERROR_OK || flash_size_in_kb == 0xffff || flash_size_in_kb == 0) {
984 LOG_WARNING(
"STM32 flash size failed, probe inaccurate - assuming %dk flash",
985 max_flash_size_in_kb);
986 flash_size_in_kb = max_flash_size_in_kb;
991 if (
bank->base != 0x08080000) {
993 flash_size_in_kb = 512;
995 flash_size_in_kb -= 512;
998 base_address = 0x08080000;
1005 LOG_INFO(
"ignoring flash probed value, using configured bank size");
1009 LOG_INFO(
"flash size = %d KiB", flash_size_in_kb);
1012 assert(flash_size_in_kb != 0xffff);
1015 int num_pages = flash_size_in_kb * 1024 / page_size;
1018 assert(num_pages > 0);
1020 free(
bank->sectors);
1023 free(
bank->prot_blocks);
1026 bank->base = base_address;
1027 bank->size = (num_pages * page_size);
1029 bank->num_sectors = num_pages;
1035 int num_prot_blocks = num_pages / stm32x_info->
ppage_size;
1036 if (num_prot_blocks > 32)
1037 num_prot_blocks = 32;
1039 bank->num_prot_blocks = num_prot_blocks;
1041 if (!
bank->prot_blocks)
1044 if (num_prot_blocks == 32)
1045 bank->prot_blocks[31].size = (num_pages - (31 * stm32x_info->
ppage_size)) * page_size;
1047 stm32x_info->
probed =
true;
1069 const char *rev_str =
NULL;
1084 uint32_t dbgmcu_idcode;
1091 uint16_t device_id = dbgmcu_idcode & 0xfff;
1092 uint16_t rev_id = dbgmcu_idcode >> 16;
1093 const char *device_str;
1094 const char *rev_str =
NULL;
1096 switch (device_id) {
1098 device_str =
"STM32F10x (Medium Density)";
1106 device_str =
"GD32F1x0";
1110 device_str =
"GD32F3x0";
1114 device_str =
"GD32VF103";
1118 device_str =
"GD32E23x";
1136 device_str =
"STM32F10x (Low Density)";
1146 device_str =
"STM32F10x (High Density)";
1164 device_str =
"STM32F10x (Connectivity)";
1178 device_str =
"STM32F100 (Low/Medium Density)";
1192 device_str =
"STM32F302xB/C";
1214 device_str =
"STM32F100 (High Density)";
1228 device_str =
"STM32F10x (XL Density)";
1238 device_str =
"STM32F37x";
1252 device_str =
"STM32F33x";
1262 device_str =
"STM32F302x6/8";
1276 device_str =
"STM32F03x";
1281 device_str =
"STM32F05x";
1286 device_str =
"STM32F04x";
1291 device_str =
"STM32F303xD/E";
1300 device_str =
"STM32F07x";
1305 device_str =
"STM32F09x";
1335 stm32x_info =
bank->driver_priv;
1400 "INFO: a reset or power cycle is required "
1401 "for the new settings to take effect.");
1408 uint32_t optionbyte, protection;
1420 stm32x_info =
bank->driver_priv;
1447 command_print(
CMD,
"write protection register = 0x%" PRIx32
"", protection);
1450 (optionbyte & (1 <<
OPT_READOUT)) ?
"on" :
"off");
1456 (optionbyte & (1 <<
OPT_RDWDGSW)) ?
"soft" :
"hard");
1487 stm32x_info =
bank->driver_priv;
1513 if (strcmp(
"SWWDG",
CMD_ARGV[0]) == 0)
1514 optionbyte |= (1 << 0);
1515 else if (strcmp(
"HWWDG",
CMD_ARGV[0]) == 0)
1516 optionbyte &= ~(1 << 0);
1517 else if (strcmp(
"NORSTSTOP",
CMD_ARGV[0]) == 0)
1518 optionbyte |= (1 << 1);
1519 else if (strcmp(
"RSTSTOP",
CMD_ARGV[0]) == 0)
1520 optionbyte &= ~(1 << 1);
1521 else if (strcmp(
"NORSTSTNDBY",
CMD_ARGV[0]) == 0)
1522 optionbyte |= (1 << 2);
1523 else if (strcmp(
"RSTSTNDBY",
CMD_ARGV[0]) == 0)
1524 optionbyte &= ~(1 << 2);
1525 else if (strcmp(
"USEROPT",
CMD_ARGV[0]) == 0) {
1532 if (strcmp(
"BOOT0",
CMD_ARGV[0]) == 0)
1533 optionbyte |= (1 << 3);
1534 else if (strcmp(
"BOOT1",
CMD_ARGV[0]) == 0)
1535 optionbyte &= ~(1 << 3);
1558 "INFO: %spower cycle is required "
1559 "for the new settings to take effect.",
1561 ?
"'stm32f1x options_load' command or " :
"");
1579 LOG_ERROR(
"Command not applicable to stm32f1x devices - power cycle is "
1580 "required instead.");
1672 .handler = stm32x_handle_lock_command,
1675 .help =
"Lock entire flash device.",
1679 .handler = stm32x_handle_unlock_command,
1682 .help =
"Unlock entire protected flash device.",
1685 .name =
"mass_erase",
1686 .handler = stm32x_handle_mass_erase_command,
1689 .help =
"Erase entire flash device.",
1692 .name =
"options_read",
1693 .handler = stm32x_handle_options_read_command,
1696 .help =
"Read and display device option bytes.",
1699 .name =
"options_write",
1700 .handler = stm32x_handle_options_write_command,
1702 .usage =
"bank_id ('SWWDG'|'HWWDG') "
1703 "('RSTSTNDBY'|'NORSTSTNDBY') "
1704 "('RSTSTOP'|'NORSTSTOP') ('USEROPT' user_data)",
1705 .help =
"Replace bits in device option bytes.",
1708 .name =
"options_load",
1709 .handler = stm32x_handle_options_load_command,
1712 .help =
"Force re-load of device option bytes.",
1721 .help =
"stm32f1x flash command group",
1731 .flash_bank_command = stm32x_flash_bank_command,
void init_reg_param(struct reg_param *param, char *reg_name, uint32_t size, enum param_direction direction)
void destroy_reg_param(struct reg_param *param)
static bool is_arm(struct arm *arm)
static struct arm * target_to_arm(struct target *target)
Convert target handle to generic ARM target state handle.
#define ARMV7M_COMMON_MAGIC
Support functions to access arbitrary bits in a byte array.
static uint32_t buf_get_u32(const uint8_t *_buffer, unsigned first, unsigned num)
Retrieves num bits from _buffer, starting at the first bit, returning the bits in a 32-bit word.
static void buf_set_u32(uint8_t *_buffer, unsigned first, unsigned num, uint32_t value)
Sets num bits in _buffer, starting at the first bit, using the bits in value.
void command_print_sameline(struct command_invocation *cmd, const char *format,...)
void command_print(struct command_invocation *cmd, const char *format,...)
#define CMD
Use this macro to access the command being handled, rather than accessing the variable directly.
#define CALL_COMMAND_HANDLER(name, extra ...)
Use this to macro to call a command helper (or a nested handler).
#define CMD_ARGV
Use this macro to access the arguments for the command being handled, rather than accessing the varia...
#define ERROR_COMMAND_SYNTAX_ERROR
#define CMD_ARGC
Use this macro to access the number of arguments for the command being handled, rather than accessing...
#define COMMAND_PARSE_NUMBER(type, in, out)
parses the string in into out as a type, or prints a command error and passes the error code to the c...
#define COMMAND_REGISTRATION_DONE
Use this as the last entry in an array of command_registration records.
@ CORTEX_M_PARTNO_INVALID
static enum cortex_m_partno cortex_m_get_partno_safe(struct target *target)
#define ERROR_FLASH_PROTECTED
#define ERROR_FLASH_OPERATION_FAILED
struct flash_sector * alloc_block_array(uint32_t offset, uint32_t size, unsigned int num_blocks)
Allocate and fill an array of sectors or protection blocks.
int default_flash_blank_check(struct flash_bank *bank)
Provides default erased-bank check handling.
int default_flash_read(struct flash_bank *bank, uint8_t *buffer, uint32_t offset, uint32_t count)
Provides default read implementation for flash memory.
void default_flash_free_driver_priv(struct flash_bank *bank)
Deallocates bank->driver_priv.
void alive_sleep(uint64_t ms)
#define LOG_WARNING(expr ...)
#define LOG_ERROR(expr ...)
#define LOG_INFO(expr ...)
#define LOG_DEBUG(expr ...)
static int stm32x_get_property_addr(struct target *target, struct stm32x_property_addr *addr)
static int stm32x_auto_probe(struct flash_bank *bank)
static const struct command_registration stm32f1x_exec_command_handlers[]
static int stm32x_probe(struct flash_bank *bank)
#define FLASH_ERASE_TIMEOUT
static const struct command_registration stm32f1x_command_handlers[]
static int get_stm32x_info(struct flash_bank *bank, struct command_invocation *cmd)
#define STM32_FLASH_OBR_B0
static int stm32x_get_flash_status(struct flash_bank *bank, uint32_t *status)
static int stm32x_get_flash_reg(struct flash_bank *bank, uint32_t reg)
static int stm32x_check_operation_supported(struct flash_bank *bank)
static int stm32x_get_flash_size(struct flash_bank *bank, uint16_t *flash_size_in_kb)
static int stm32x_erase_options(struct flash_bank *bank)
FLASH_BANK_COMMAND_HANDLER(stm32x_flash_bank_command)
static int stm32x_read_options(struct flash_bank *bank)
#define STM32_FLASH_WRPR_B0
#define STM32_FLASH_OPTKEYR_B0
static int stm32x_write(struct flash_bank *bank, const uint8_t *buffer, uint32_t offset, uint32_t count)
static int stm32x_get_device_id(struct flash_bank *bank, uint32_t *device_id)
#define FLASH_REG_BASE_B0
#define STM32_FLASH_KEYR_B0
static int stm32x_write_options(struct flash_bank *bank)
COMMAND_HANDLER(stm32x_handle_lock_command)
static int stm32x_write_block_riscv(struct flash_bank *bank, const uint8_t *buffer, uint32_t address, uint32_t hwords_count)
static int stm32x_write_block(struct flash_bank *bank, const uint8_t *buffer, uint32_t address, uint32_t hwords_count)
Writes a block to flash either using target algorithm or use fallback, host controlled halfword-by-ha...
static int stm32x_wait_status_busy(struct flash_bank *bank, int timeout)
static int stm32x_mass_erase(struct flash_bank *bank)
static int stm32x_write_block_async(struct flash_bank *bank, const uint8_t *buffer, uint32_t address, uint32_t hwords_count)
static int stm32x_erase(struct flash_bank *bank, unsigned int first, unsigned int last)
static const char * get_stm32f0_revision(uint16_t rev_id)
static int stm32x_protect_check(struct flash_bank *bank)
const struct flash_driver stm32f1x_flash
#define FLASH_REG_BASE_B1
static int stm32x_protect(struct flash_bank *bank, int set, unsigned int first, unsigned int last)
#define STM32_FLASH_CR_B0
Represents a generic ARM core, with standard application registers.
unsigned int common_magic
When run_command is called, a new instance will be created on the stack, filled with the proper value...
Provides details of a flash bank, available either on-chip or through a major interface.
Provides the implementation-independent structure that defines all of the callbacks required by OpenO...
const char * name
Gives a human-readable name of this flash driver, This field is used to select and initialize the dri...
struct stm32x_options option_bytes
void target_buffer_set_u16(struct target *target, uint8_t *buffer, uint16_t value)
int target_write_buffer(struct target *target, target_addr_t address, uint32_t size, const uint8_t *buffer)
int target_write_memory(struct target *target, target_addr_t address, uint32_t size, uint32_t count, const uint8_t *buffer)
Write count items of size bytes to the memory of target at the address given.
unsigned target_address_bits(struct target *target)
Return the number of address bits this target supports.
uint32_t target_get_working_area_avail(struct target *target)
int target_alloc_working_area(struct target *target, uint32_t size, struct working_area **area)
int target_write_u32(struct target *target, target_addr_t address, uint32_t value)
int target_free_working_area(struct target *target, struct working_area *area)
Free a working area.
int target_run_algorithm(struct target *target, int num_mem_params, struct mem_param *mem_params, int num_reg_params, struct reg_param *reg_param, target_addr_t entry_point, target_addr_t exit_point, int timeout_ms, void *arch_info)
Downloads a target-specific native code algorithm to the target, and executes it.
int target_read_u16(struct target *target, target_addr_t address, uint16_t *value)
int target_run_flash_async_algorithm(struct target *target, const uint8_t *buffer, uint32_t count, int block_size, int num_mem_params, struct mem_param *mem_params, int num_reg_params, struct reg_param *reg_params, uint32_t buffer_start, uint32_t buffer_size, uint32_t entry_point, uint32_t exit_point, void *arch_info)
Streams data to a circular buffer on target intended for consumption by code running asynchronously o...
int target_read_u32(struct target *target, target_addr_t address, uint32_t *value)
const char * target_type_name(struct target *target)
Get the target type name.
#define ERROR_TARGET_NOT_HALTED
#define ERROR_TARGET_NOT_EXAMINED
#define ERROR_TARGET_RESOURCE_NOT_AVAILABLE
static bool target_was_examined(struct target *target)
#define ARRAY_SIZE(x)
Compute the number of elements of a variable length array.