109 #define FLASH_ERASE_TIMEOUT 10000
110 #define FLASH_WRITE_TIMEOUT 5
113 #define FLASH_MASS_ERASE_TIMEOUT 33000
115 #define FLASH_BANK_BASE 0x80000000
117 #define STM32F2_OTP_SIZE 512
118 #define STM32F2_OTP_SECTOR_SIZE 32
119 #define STM32F2_OTP_BANK_BASE 0x1fff7800
120 #define STM32F2_OTP_LOCK_BASE ((STM32F2_OTP_BANK_BASE) + (STM32F2_OTP_SIZE))
123 #define STM32F7_OTP_SECTOR_SIZE 64
124 #define STM32F7_OTP_SIZE 1024
125 #define STM32F7_OTP_BANK_BASE 0x1ff0f000
126 #define STM32F7_OTP_LOCK_BASE ((STM32F7_OTP_BANK_BASE) + (STM32F7_OTP_SIZE))
128 #define STM32_FLASH_BASE 0x40023c00
129 #define STM32_FLASH_ACR 0x40023c00
130 #define STM32_FLASH_KEYR 0x40023c04
131 #define STM32_FLASH_OPTKEYR 0x40023c08
132 #define STM32_FLASH_SR 0x40023c0C
133 #define STM32_FLASH_CR 0x40023c10
134 #define STM32_FLASH_OPTCR 0x40023c14
135 #define STM32_FLASH_OPTCR1 0x40023c18
136 #define STM32_FLASH_OPTCR2 0x40023c1c
139 #define FLASH_PG (1 << 0)
140 #define FLASH_SER (1 << 1)
141 #define FLASH_MER (1 << 2)
142 #define FLASH_MER1 (1 << 15)
143 #define FLASH_STRT (1 << 16)
144 #define FLASH_PSIZE_8 (0 << 8)
145 #define FLASH_PSIZE_16 (1 << 8)
146 #define FLASH_PSIZE_32 (2 << 8)
147 #define FLASH_PSIZE_64 (3 << 8)
149 #define FLASH_SNB(a) ((a) << 3)
150 #define FLASH_LOCK (1 << 31)
153 #define FLASH_BSY (1 << 16)
154 #define FLASH_PGSERR (1 << 7)
155 #define FLASH_PGPERR (1 << 6)
156 #define FLASH_PGAERR (1 << 5)
157 #define FLASH_WRPERR (1 << 4)
158 #define FLASH_OPERR (1 << 1)
160 #define FLASH_ERROR (FLASH_PGSERR | FLASH_PGPERR | FLASH_PGAERR | FLASH_WRPERR | FLASH_OPERR)
163 #define OPTCR_LOCK (1 << 0)
164 #define OPTCR_START (1 << 1)
165 #define OPTCR_NDBANK (1 << 29)
166 #define OPTCR_DB1M (1 << 30)
167 #define OPTCR_SPRMOD (1 << 31)
170 #define OPTCR2_PCROP_RDP (1 << 31)
173 #define KEY1 0x45670123
174 #define KEY2 0xCDEF89AB
177 #define OPTKEY1 0x08192A3B
178 #define OPTKEY2 0x4C5D6E7F
222 LOG_INFO(
"OTP memory bank #%u is disabled for write commands.",
233 LOG_INFO(
"OTP memory bank #%u is is enabled for write commands.",
237 LOG_WARNING(
"OTP memory bank #%u is is already enabled for write commands.",
253 bank->driver_priv = stm32x_info;
255 stm32x_info->
probed =
false;
288 LOG_ERROR(
"timed out waiting for flash");
341 LOG_ERROR(
"flash not unlocked STM32_FLASH_CR: 0x%" PRIx32,
ctrl);
373 LOG_ERROR(
"options not unlocked STM32_FLASH_OPTCR: 0x%" PRIx32,
ctrl);
386 stm32x_info =
bank->driver_priv;
398 (optiondata >> 16) & (~(0xffff << stm32x_info->
protection_bits) & 0xffff);
436 LOG_INFO(
"Device Security Bit Set");
445 uint32_t optiondata, optiondata2;
447 stm32x_info =
bank->driver_priv;
520 for (
unsigned int i = 0; i <
bank->num_sectors; i++) {
524 bank->sectors[i].is_protected = !lock;
538 assert((first <= last) && (last < bank->num_sectors));
543 for (i = first; first <= last; i++) {
563 unsigned int num_prot_blocks;
573 LOG_DEBUG(
"unable to read option bytes");
577 if (
bank->prot_blocks) {
578 num_prot_blocks =
bank->num_prot_blocks;
579 prot_blocks =
bank->prot_blocks;
581 num_prot_blocks =
bank->num_sectors;
582 prot_blocks =
bank->sectors;
585 for (
unsigned int i = 0; i < num_prot_blocks; i++)
603 assert((first <= last) && (last < bank->num_sectors));
626 for (
unsigned int i = first; i <= last; i++) {
629 snb = (i - (
bank->num_sectors / 2)) | 0x10;
671 LOG_DEBUG(
"unable to read option bytes");
675 for (
unsigned int i = first; i <= last; i++) {
693 uint32_t buffer_size = 16384;
701 static const uint8_t stm32x_flash_write_code[] = {
702 #include "../../../contrib/loaders/flash/stm32/stm32f2x.inc"
706 LOG_ERROR(
"OTP memory bank is disabled for write commands.");
712 LOG_WARNING(
"no working area available, can't do block memory writes");
717 sizeof(stm32x_flash_write_code),
718 stm32x_flash_write_code);
727 if (buffer_size <= 256) {
732 LOG_WARNING(
"no large enough working area available, can't do block memory writes");
760 LOG_ERROR(
"error executing stm32x flash write algorithm");
765 LOG_ERROR(
"flash memory write protected");
768 LOG_ERROR(
"flash write failed = 0x%08" PRIx32, error);
791 uint32_t words_remaining = (
count / 2);
792 uint32_t bytes_remaining = (
count & 0x00000001);
794 uint32_t bytes_written = 0;
812 if (words_remaining > 0) {
819 LOG_WARNING(
"couldn't use block writes, falling back to single memory accesses");
822 buffer += words_remaining * 2;
823 address += words_remaining * 2;
847 while (words_remaining > 0) {
866 if (bytes_remaining) {
886 assert(i < bank->num_sectors);
887 bank->sectors[i].offset =
bank->size;
889 bank->size +=
bank->sectors[i].size;
896 return max_sector_size_in_kb / 8;
898 return max_sector_size_in_kb / 2;
899 return max_sector_size_in_kb;
903 uint16_t flash_size_in_kb,
904 uint16_t max_sector_size_in_kb)
907 uint16_t remaining_flash_size_in_kb = flash_size_in_kb;
908 unsigned int nr_sectors;
912 remaining_flash_size_in_kb /= 2;
914 for (nr_sectors = 0; remaining_flash_size_in_kb > 0; nr_sectors++) {
916 if (size_in_kb > remaining_flash_size_in_kb) {
917 LOG_INFO(
"%s Bank %" PRIu16
" kiB final sector clipped to %" PRIu16
" kiB",
919 flash_size_in_kb, remaining_flash_size_in_kb);
920 remaining_flash_size_in_kb = 0;
922 remaining_flash_size_in_kb -= size_in_kb;
926 return stm32x_info->
has_large_mem ? nr_sectors*2 : nr_sectors;
930 uint16_t flash_size_in_kb, uint16_t max_sector_size_in_kb)
932 uint16_t remaining_flash_size_in_kb = flash_size_in_kb;
933 unsigned int sector_index = 0;
934 while (remaining_flash_size_in_kb > 0) {
936 if (size_in_kb > remaining_flash_size_in_kb) {
939 size_in_kb = remaining_flash_size_in_kb;
942 remaining_flash_size_in_kb -= size_in_kb;
961 if ((*device_id & 0xfff) == 0x411
963 *device_id &= ~((0xFFFF << 16) | 0xfff);
964 *device_id |= (0x1000 << 16) | 0x413;
965 LOG_INFO(
"stm32f4x errata detected - fixing incorrect MCU_IDCODE");
974 unsigned int num_prot_blocks, num_sectors;
975 uint16_t flash_size_in_kb;
976 uint16_t otp_size_in_b;
977 uint16_t otp_sector_size;
978 uint32_t flash_size_reg = 0x1FFF7A22;
979 uint16_t max_sector_size_in_kb = 128;
980 uint16_t max_flash_size_in_kb;
982 uint32_t base_address = 0x08000000;
984 stm32x_info->
probed =
false;
993 bank->num_sectors = 0;
996 free(
bank->prot_blocks);
997 bank->num_prot_blocks = 0;
1015 num_sectors = otp_size_in_b / otp_sector_size;
1016 LOG_INFO(
"flash size = %" PRIu16
" bytes", otp_size_in_b);
1018 assert(num_sectors > 0);
1020 bank->num_sectors = num_sectors;
1028 for (
unsigned int i = 0; i < num_sectors; i++) {
1029 bank->sectors[i].offset = i * otp_sector_size;
1030 bank->sectors[i].size = otp_sector_size;
1031 bank->sectors[i].is_erased = 1;
1032 bank->sectors[i].is_protected = 0;
1035 stm32x_info->
probed =
true;
1043 LOG_INFO(
"device id = 0x%08" PRIx32, device_id);
1047 switch (device_id) {
1050 max_flash_size_in_kb = 1024;
1056 max_flash_size_in_kb = 2048;
1060 max_flash_size_in_kb = 256;
1067 max_flash_size_in_kb = 512;
1071 max_flash_size_in_kb = 128;
1075 max_flash_size_in_kb = 1024;
1076 max_sector_size_in_kb = 256;
1077 flash_size_reg = 0x1FF0F442;
1083 max_flash_size_in_kb = 2048;
1084 max_sector_size_in_kb = 256;
1085 flash_size_reg = 0x1FF0F442;
1091 max_flash_size_in_kb = 512;
1092 flash_size_reg = 0x1FF07A22;
1099 max_flash_size_in_kb = 1536;
1102 num_prot_blocks = 15;
1106 LOG_WARNING(
"Cannot identify target as a STM32 family.");
1115 if (retval !=
ERROR_OK || flash_size_in_kb == 0xffff || flash_size_in_kb == 0) {
1116 LOG_WARNING(
"STM32 flash size failed, probe inaccurate - assuming %" PRIu16
"k flash",
1117 max_flash_size_in_kb);
1118 flash_size_in_kb = max_flash_size_in_kb;
1124 LOG_INFO(
"ignoring flash probed value, using configured bank size");
1128 LOG_INFO(
"flash size = %" PRIu16
" KiB", flash_size_in_kb);
1131 assert(flash_size_in_kb != 0xffff);
1134 if ((device_id == 0x419) || (device_id == 0x434)) {
1135 uint32_t optiondata;
1138 LOG_DEBUG(
"unable to read option bytes");
1141 if ((flash_size_in_kb > 1024) || (optiondata &
OPTCR_DB1M)) {
1143 LOG_INFO(
"Dual Bank %" PRIu16
" kiB STM32F42x/43x/469/479 found", flash_size_in_kb);
1146 LOG_INFO(
"Single Bank %" PRIu16
" kiB STM32F42x/43x/469/479 found", flash_size_in_kb);
1151 if (device_id == 0x451) {
1152 uint32_t optiondata;
1155 LOG_DEBUG(
"unable to read option bytes");
1160 LOG_INFO(
"Single Bank %" PRIu16
" kiB STM32F76x/77x found", flash_size_in_kb);
1163 max_sector_size_in_kb >>= 1;
1164 LOG_INFO(
"Dual Bank %" PRIu16
" kiB STM32F76x/77x found", flash_size_in_kb);
1170 bank, flash_size_in_kb, max_sector_size_in_kb);
1172 bank->base = base_address;
1173 bank->num_sectors = num_pages;
1175 for (
unsigned int i = 0; i < num_pages; i++) {
1176 bank->sectors[i].is_erased = -1;
1177 bank->sectors[i].is_protected = 0;
1180 LOG_DEBUG(
"allocated %u sectors", num_pages);
1184 num_prot_blocks = num_pages >> 1;
1186 if (num_prot_blocks) {
1188 for (
unsigned int i = 0; i < num_prot_blocks; i++)
1189 bank->prot_blocks[i].is_protected = 0;
1190 LOG_DEBUG(
"allocated %u prot blocks", num_prot_blocks);
1195 setup_bank(
bank, 0, flash_size_in_kb >> 1, max_sector_size_in_kb);
1197 max_sector_size_in_kb);
1200 if (device_id == 0x451) {
1201 for (
unsigned int i = 0; i < num_prot_blocks; i++) {
1202 bank->prot_blocks[i].offset =
bank->sectors[i << 1].offset;
1203 bank->prot_blocks[i].size =
bank->sectors[i << 1].size
1204 +
bank->sectors[(i << 1) + 1].
size;
1212 if (device_id == 0x463) {
1213 for (
unsigned int i = 0; i < num_prot_blocks; i++) {
1214 bank->prot_blocks[i].offset =
bank->sectors[i].offset;
1215 bank->prot_blocks[i].size =
bank->sectors[i].size;
1217 bank->prot_blocks[num_prot_blocks - 1].size <<= 1;
1220 bank->num_prot_blocks = num_prot_blocks;
1221 assert((
bank->size >> 10) == flash_size_in_kb);
1223 stm32x_info->
probed =
true;
1237 uint32_t dbgmcu_idcode;
1244 uint16_t device_id = dbgmcu_idcode & 0xfff;
1245 uint16_t rev_id = dbgmcu_idcode >> 16;
1246 const char *device_str;
1247 const char *rev_str =
NULL;
1249 switch (device_id) {
1251 device_str =
"STM32F2xx";
1291 device_str =
"STM32F4xx";
1317 device_str =
"STM32F446";
1331 device_str =
"STM32F4xx (Low Power)";
1353 device_str =
"STM32F7[4|5]x";
1367 device_str =
"STM32F7[6|7]x";
1380 device_str =
"STM32F7[2|3]x";
1390 device_str =
"STM32F4[1|2]3";
1425 stm32x_info =
bank->driver_priv;
1464 stm32x_info =
bank->driver_priv;
1490 "INFO: a reset or power cycle is required "
1491 "for the new settings to take effect.",
bank->driver->name);
1508 stm32x_info =
bank->driver_priv;
1580 stm32x_info =
bank->driver_priv;
1586 " boot_add0 0x%04" PRIX32
", boot_add1 0x%04" PRIX32,
1588 boot_addr & 0xffff, (boot_addr & 0xffff0000) >> 16);
1611 uint16_t user_options, boot_addr0, boot_addr1, options_mask;
1626 stm32x_info =
bank->driver_priv;
1630 " <boot_addr0> <boot_addr1>");
1646 if (user_options & options_mask) {
1660 stm32x_info->
probed =
false;
1663 "INFO: a reset or power cycle is required "
1664 "for the new settings to take effect.");
1673 uint32_t optcr2_pcrop;
1684 stm32x_info =
bank->driver_priv;
1691 " with PCROPi bits STILL SET, then\nlock device and"
1692 " finally unlock it. Clears PCROP and mass erases flash.");
1722 if (strcmp(
CMD_ARGV[1],
"enable") == 0) {
1724 }
else if (strcmp(
CMD_ARGV[1],
"disable") == 0) {
1726 }
else if (strcmp(
CMD_ARGV[1],
"show") == 0) {
1728 "OTP memory bank #%u is %s for write commands.",
1744 .handler = stm32x_handle_lock_command,
1747 .help =
"Lock entire flash device.",
1751 .handler = stm32x_handle_unlock_command,
1754 .help =
"Unlock entire protected flash device.",
1757 .name =
"mass_erase",
1758 .handler = stm32x_handle_mass_erase_command,
1761 .help =
"Erase entire flash device.",
1764 .name =
"options_read",
1765 .handler = stm32f2x_handle_options_read_command,
1768 .help =
"Read and display device option bytes.",
1771 .name =
"options_write",
1772 .handler = stm32f2x_handle_options_write_command,
1774 .usage =
"bank_id user_options [ boot_add0 boot_add1 ]",
1775 .help =
"Write option bytes",
1778 .name =
"optcr2_write",
1779 .handler = stm32f2x_handle_optcr2_write_command,
1781 .usage =
"bank_id optcr2",
1782 .help =
"Write optcr2 word",
1786 .handler = stm32x_handle_otp_command,
1789 .help =
"OTP (One Time Programmable) memory write enable/disable.",
1798 .help =
"stm32f2x flash command group",
1808 .flash_bank_command = stm32x_flash_bank_command,
void init_reg_param(struct reg_param *param, char *reg_name, uint32_t size, enum param_direction direction)
void destroy_reg_param(struct reg_param *param)
#define ARMV7M_COMMON_MAGIC
Support functions to access arbitrary bits in a byte array.
static uint32_t buf_get_u32(const uint8_t *_buffer, unsigned first, unsigned num)
Retrieves num bits from _buffer, starting at the first bit, returning the bits in a 32-bit word.
static void buf_set_u32(uint8_t *_buffer, unsigned first, unsigned num, uint32_t value)
Sets num bits in _buffer, starting at the first bit, using the bits in value.
void command_print_sameline(struct command_invocation *cmd, const char *format,...)
void command_print(struct command_invocation *cmd, const char *format,...)
#define CMD
Use this macro to access the command being handled, rather than accessing the variable directly.
#define CALL_COMMAND_HANDLER(name, extra ...)
Use this to macro to call a command helper (or a nested handler).
#define CMD_ARGV
Use this macro to access the arguments for the command being handled, rather than accessing the varia...
#define ERROR_COMMAND_SYNTAX_ERROR
#define CMD_ARGC
Use this macro to access the number of arguments for the command being handled, rather than accessing...
#define COMMAND_PARSE_NUMBER(type, in, out)
parses the string in into out as a type, or prints a command error and passes the error code to the c...
#define COMMAND_REGISTRATION_DONE
Use this as the last entry in an array of command_registration records.
#define ERROR_COMMAND_ARGUMENT_INVALID
static enum cortex_m_partno cortex_m_get_partno_safe(struct target *target)
#define ERROR_FLASH_OPERATION_FAILED
#define ERROR_FLASH_DST_BREAKS_ALIGNMENT
int default_flash_blank_check(struct flash_bank *bank)
Provides default erased-bank check handling.
int default_flash_read(struct flash_bank *bank, uint8_t *buffer, uint32_t offset, uint32_t count)
Provides default read implementation for flash memory.
void default_flash_free_driver_priv(struct flash_bank *bank)
Deallocates bank->driver_priv.
void alive_sleep(uint64_t ms)
#define LOG_WARNING(expr ...)
#define LOG_ERROR(expr ...)
#define LOG_INFO(expr ...)
#define LOG_DEBUG(expr ...)
struct rtt_control ctrl
Control block.
size_t size
Size of the control block search area.
static int stm32x_auto_probe(struct flash_bank *bank)
#define STM32F7_OTP_SECTOR_SIZE
const struct flash_driver stm32f2x_flash
static int stm32x_probe(struct flash_bank *bank)
#define FLASH_ERASE_TIMEOUT
static int get_stm32x_info(struct flash_bank *bank, struct command_invocation *cmd)
static int stm32x_write_block(struct flash_bank *bank, const uint8_t *buffer, uint32_t offset, uint32_t count)
static int stm32x_otp_enable(struct flash_bank *bank)
static int stm32x_get_flash_status(struct flash_bank *bank, uint32_t *status)
static uint16_t sector_size_in_kb(unsigned int i, uint16_t max_sector_size_in_kb)
static unsigned int calculate_number_of_sectors(struct flash_bank *bank, uint16_t flash_size_in_kb, uint16_t max_sector_size_in_kb)
static int stm32x_get_flash_reg(struct flash_bank *bank, uint32_t reg)
static bool stm32x_is_otp(struct flash_bank *bank)
#define STM32_FLASH_OPTKEYR
static const struct command_registration stm32f2x_exec_command_handlers[]
FLASH_BANK_COMMAND_HANDLER(stm32x_flash_bank_command)
static int stm32x_is_otp_unlocked(struct flash_bank *bank)
static void setup_bank(struct flash_bank *bank, unsigned int start, uint16_t flash_size_in_kb, uint16_t max_sector_size_in_kb)
#define STM32F2_OTP_LOCK_BASE
static int stm32x_read_options(struct flash_bank *bank)
#define STM32_FLASH_OPTCR
#define STM32F7_OTP_BANK_BASE
static int stm32x_write(struct flash_bank *bank, const uint8_t *buffer, uint32_t offset, uint32_t count)
static int stm32x_get_device_id(struct flash_bank *bank, uint32_t *device_id)
static int stm32x_write_options(struct flash_bank *bank)
COMMAND_HANDLER(stm32x_handle_lock_command)
#define STM32F7_OTP_LOCK_BASE
static int stm32x_unlock_reg(struct target *target)
#define STM32F2_OTP_BANK_BASE
static int stm32x_wait_status_busy(struct flash_bank *bank, int timeout)
static int stm32x_otp_read_protect(struct flash_bank *bank)
#define STM32F2_OTP_SECTOR_SIZE
#define STM32_FLASH_OPTCR1
static int stm32x_unlock_option_reg(struct target *target)
static int stm32x_mass_erase(struct flash_bank *bank)
static bool stm32x_otp_is_f7(struct flash_bank *bank)
static int stm32x_otp_disable(struct flash_bank *bank)
static int stm32x_erase(struct flash_bank *bank, unsigned int first, unsigned int last)
#define STM32_FLASH_OPTCR2
static int stm32x_protect_check(struct flash_bank *bank)
static const struct command_registration stm32f2x_command_handlers[]
static void setup_sector(struct flash_bank *bank, unsigned int i, unsigned int size)
#define FLASH_WRITE_TIMEOUT
#define FLASH_MASS_ERASE_TIMEOUT
static int stm32x_protect(struct flash_bank *bank, int set, unsigned int first, unsigned int last)
static int stm32x_otp_protect(struct flash_bank *bank, unsigned int first, unsigned int last)
unsigned int common_magic
When run_command is called, a new instance will be created on the stack, filled with the proper value...
Provides details of a flash bank, available either on-chip or through a major interface.
Provides the implementation-independent structure that defines all of the callbacks required by OpenO...
const char * name
Gives a human-readable name of this flash driver, This field is used to select and initialize the dri...
Describes the geometry and status of a single flash sector within a flash bank.
int is_protected
Indication of protection status: 0 = unprotected/unlocked, 1 = protected/locked, other = unknown.
struct stm32x_options option_bytes
unsigned int protection_bits
int target_write_buffer(struct target *target, target_addr_t address, uint32_t size, const uint8_t *buffer)
int target_write_u8(struct target *target, target_addr_t address, uint8_t value)
int target_read_u8(struct target *target, target_addr_t address, uint8_t *value)
int target_write_memory(struct target *target, target_addr_t address, uint32_t size, uint32_t count, const uint8_t *buffer)
Write count items of size bytes to the memory of target at the address given.
int target_alloc_working_area(struct target *target, uint32_t size, struct working_area **area)
int target_write_u32(struct target *target, target_addr_t address, uint32_t value)
int target_free_working_area(struct target *target, struct working_area *area)
Free a working area.
int target_alloc_working_area_try(struct target *target, uint32_t size, struct working_area **area)
int target_read_u16(struct target *target, target_addr_t address, uint16_t *value)
int target_run_flash_async_algorithm(struct target *target, const uint8_t *buffer, uint32_t count, int block_size, int num_mem_params, struct mem_param *mem_params, int num_reg_params, struct reg_param *reg_params, uint32_t buffer_start, uint32_t buffer_size, uint32_t entry_point, uint32_t exit_point, void *arch_info)
Streams data to a circular buffer on target intended for consumption by code running asynchronously o...
int target_read_u32(struct target *target, target_addr_t address, uint32_t *value)
#define ERROR_TARGET_NOT_HALTED
#define ERROR_TARGET_NOT_EXAMINED
#define ERROR_TARGET_RESOURCE_NOT_AVAILABLE
static bool target_was_examined(struct target *target)
#define ERROR_TARGET_FAILURE