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mips32.c
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1 // SPDX-License-Identifier: GPL-2.0-or-later
2 
3 /***************************************************************************
4  * Copyright (C) 2008 by Spencer Oliver *
5  * spen@spen-soft.co.uk *
6  * *
7  * Copyright (C) 2008 by David T.L. Wong *
8  * *
9  * Copyright (C) 2007,2008 Øyvind Harboe *
10  * oyvind.harboe@zylin.com *
11  * *
12  * Copyright (C) 2011 by Drasko DRASKOVIC *
13  * drasko.draskovic@gmail.com *
14  ***************************************************************************/
15 
16 #ifdef HAVE_CONFIG_H
17 #include "config.h"
18 #endif
19 
20 #include "mips32.h"
21 #include "mips_cpu.h"
22 #include "breakpoints.h"
23 #include "algorithm.h"
24 #include "register.h"
25 
26 static const char *mips_isa_strings[] = {
27  "MIPS32", "MIPS16", "", "MICRO MIPS32",
28 };
29 
30 #define MIPS32_GDB_FP_REG 1
31 
32 /*
33  * GDB registers
34  * based on gdb-7.6.2/gdb/features/mips-{fpu,cp0,cpu,dsp}.xml
35  */
36 static const struct {
37  unsigned int id;
38  const char *name;
39  enum reg_type type;
40  const char *group;
41  const char *feature;
42  int size;
43 } mips32_regs[] = {
44  { 0, "r0", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 },
45  { 1, "r1", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 },
46  { 2, "r2", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 },
47  { 3, "r3", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 },
48  { 4, "r4", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 },
49  { 5, "r5", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 },
50  { 6, "r6", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 },
51  { 7, "r7", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 },
52  { 8, "r8", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 },
53  { 9, "r9", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 },
54  { 10, "r10", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 },
55  { 11, "r11", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 },
56  { 12, "r12", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 },
57  { 13, "r13", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 },
58  { 14, "r14", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 },
59  { 15, "r15", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 },
60  { 16, "r16", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 },
61  { 17, "r17", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 },
62  { 18, "r18", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 },
63  { 19, "r19", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 },
64  { 20, "r20", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 },
65  { 21, "r21", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 },
66  { 22, "r22", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 },
67  { 23, "r23", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 },
68  { 24, "r24", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 },
69  { 25, "r25", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 },
70  { 26, "r26", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 },
71  { 27, "r27", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 },
72  { 28, "r28", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 },
73  { 29, "r29", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 },
74  { 30, "r30", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 },
75  { 31, "r31", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 },
76  { 32, "lo", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 },
77  { 33, "hi", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 },
78 
79  { MIPS32_REGLIST_FP_INDEX + 0, "f0", REG_TYPE_IEEE_DOUBLE, NULL,
80  "org.gnu.gdb.mips.fpu", MIPS32_GDB_FP_REG },
81  { MIPS32_REGLIST_FP_INDEX + 1, "f1", REG_TYPE_IEEE_DOUBLE, NULL,
82  "org.gnu.gdb.mips.fpu", MIPS32_GDB_FP_REG },
83  { MIPS32_REGLIST_FP_INDEX + 2, "f2", REG_TYPE_IEEE_DOUBLE, NULL,
84  "org.gnu.gdb.mips.fpu", MIPS32_GDB_FP_REG },
85  { MIPS32_REGLIST_FP_INDEX + 3, "f3", REG_TYPE_IEEE_DOUBLE, NULL,
86  "org.gnu.gdb.mips.fpu", MIPS32_GDB_FP_REG },
87  { MIPS32_REGLIST_FP_INDEX + 4, "f4", REG_TYPE_IEEE_DOUBLE, NULL,
88  "org.gnu.gdb.mips.fpu", MIPS32_GDB_FP_REG },
89  { MIPS32_REGLIST_FP_INDEX + 5, "f5", REG_TYPE_IEEE_DOUBLE, NULL,
90  "org.gnu.gdb.mips.fpu", MIPS32_GDB_FP_REG },
91  { MIPS32_REGLIST_FP_INDEX + 6, "f6", REG_TYPE_IEEE_DOUBLE, NULL,
92  "org.gnu.gdb.mips.fpu", MIPS32_GDB_FP_REG },
93  { MIPS32_REGLIST_FP_INDEX + 7, "f7", REG_TYPE_IEEE_DOUBLE, NULL,
94  "org.gnu.gdb.mips.fpu", MIPS32_GDB_FP_REG },
95  { MIPS32_REGLIST_FP_INDEX + 8, "f8", REG_TYPE_IEEE_DOUBLE, NULL,
96  "org.gnu.gdb.mips.fpu", MIPS32_GDB_FP_REG },
97  { MIPS32_REGLIST_FP_INDEX + 9, "f9", REG_TYPE_IEEE_DOUBLE, NULL,
98  "org.gnu.gdb.mips.fpu", MIPS32_GDB_FP_REG },
99  { MIPS32_REGLIST_FP_INDEX + 10, "f10", REG_TYPE_IEEE_DOUBLE, NULL,
100  "org.gnu.gdb.mips.fpu", MIPS32_GDB_FP_REG },
101  { MIPS32_REGLIST_FP_INDEX + 11, "f11", REG_TYPE_IEEE_DOUBLE, NULL,
102  "org.gnu.gdb.mips.fpu", MIPS32_GDB_FP_REG },
103  { MIPS32_REGLIST_FP_INDEX + 12, "f12", REG_TYPE_IEEE_DOUBLE, NULL,
104  "org.gnu.gdb.mips.fpu", MIPS32_GDB_FP_REG },
105  { MIPS32_REGLIST_FP_INDEX + 13, "f13", REG_TYPE_IEEE_DOUBLE, NULL,
106  "org.gnu.gdb.mips.fpu", MIPS32_GDB_FP_REG },
107  { MIPS32_REGLIST_FP_INDEX + 14, "f14", REG_TYPE_IEEE_DOUBLE, NULL,
108  "org.gnu.gdb.mips.fpu", MIPS32_GDB_FP_REG },
109  { MIPS32_REGLIST_FP_INDEX + 15, "f15", REG_TYPE_IEEE_DOUBLE, NULL,
110  "org.gnu.gdb.mips.fpu", MIPS32_GDB_FP_REG },
111  { MIPS32_REGLIST_FP_INDEX + 16, "f16", REG_TYPE_IEEE_DOUBLE, NULL,
112  "org.gnu.gdb.mips.fpu", MIPS32_GDB_FP_REG },
113  { MIPS32_REGLIST_FP_INDEX + 17, "f17", REG_TYPE_IEEE_DOUBLE, NULL,
114  "org.gnu.gdb.mips.fpu", MIPS32_GDB_FP_REG },
115  { MIPS32_REGLIST_FP_INDEX + 18, "f18", REG_TYPE_IEEE_DOUBLE, NULL,
116  "org.gnu.gdb.mips.fpu", MIPS32_GDB_FP_REG },
117  { MIPS32_REGLIST_FP_INDEX + 19, "f19", REG_TYPE_IEEE_DOUBLE, NULL,
118  "org.gnu.gdb.mips.fpu", MIPS32_GDB_FP_REG },
119  { MIPS32_REGLIST_FP_INDEX + 20, "f20", REG_TYPE_IEEE_DOUBLE, NULL,
120  "org.gnu.gdb.mips.fpu", MIPS32_GDB_FP_REG },
121  { MIPS32_REGLIST_FP_INDEX + 21, "f21", REG_TYPE_IEEE_DOUBLE, NULL,
122  "org.gnu.gdb.mips.fpu", MIPS32_GDB_FP_REG },
123  { MIPS32_REGLIST_FP_INDEX + 22, "f22", REG_TYPE_IEEE_DOUBLE, NULL,
124  "org.gnu.gdb.mips.fpu", MIPS32_GDB_FP_REG },
125  { MIPS32_REGLIST_FP_INDEX + 23, "f23", REG_TYPE_IEEE_DOUBLE, NULL,
126  "org.gnu.gdb.mips.fpu", MIPS32_GDB_FP_REG },
127  { MIPS32_REGLIST_FP_INDEX + 24, "f24", REG_TYPE_IEEE_DOUBLE, NULL,
128  "org.gnu.gdb.mips.fpu", MIPS32_GDB_FP_REG },
129  { MIPS32_REGLIST_FP_INDEX + 25, "f25", REG_TYPE_IEEE_DOUBLE, NULL,
130  "org.gnu.gdb.mips.fpu", MIPS32_GDB_FP_REG },
131  { MIPS32_REGLIST_FP_INDEX + 26, "f26", REG_TYPE_IEEE_DOUBLE, NULL,
132  "org.gnu.gdb.mips.fpu", MIPS32_GDB_FP_REG },
133  { MIPS32_REGLIST_FP_INDEX + 27, "f27", REG_TYPE_IEEE_DOUBLE, NULL,
134  "org.gnu.gdb.mips.fpu", MIPS32_GDB_FP_REG },
135  { MIPS32_REGLIST_FP_INDEX + 28, "f28", REG_TYPE_IEEE_DOUBLE, NULL,
136  "org.gnu.gdb.mips.fpu", MIPS32_GDB_FP_REG },
137  { MIPS32_REGLIST_FP_INDEX + 29, "f29", REG_TYPE_IEEE_DOUBLE, NULL,
138  "org.gnu.gdb.mips.fpu", MIPS32_GDB_FP_REG },
139  { MIPS32_REGLIST_FP_INDEX + 30, "f30", REG_TYPE_IEEE_DOUBLE, NULL,
140  "org.gnu.gdb.mips.fpu", MIPS32_GDB_FP_REG },
141  { MIPS32_REGLIST_FP_INDEX + 31, "f31", REG_TYPE_IEEE_DOUBLE, NULL,
142  "org.gnu.gdb.mips.fpu", MIPS32_GDB_FP_REG },
143 
144  { MIPS32_REGLIST_FPC_INDEX + 0, "fcsr", REG_TYPE_INT, "float",
145  "org.gnu.gdb.mips.fpu", 0 },
146  { MIPS32_REGLIST_FPC_INDEX + 1, "fir", REG_TYPE_INT, "float",
147  "org.gnu.gdb.mips.fpu", 0 },
148 
149  { MIPS32_REGLIST_C0_STATUS_INDEX, "status", REG_TYPE_INT, NULL,
150  "org.gnu.gdb.mips.cp0", 0 },
151  { MIPS32_REGLIST_C0_BADVADDR_INDEX, "badvaddr", REG_TYPE_INT, NULL,
152  "org.gnu.gdb.mips.cp0", 0 },
153  { MIPS32_REGLIST_C0_CAUSE_INDEX, "cause", REG_TYPE_INT, NULL,
154  "org.gnu.gdb.mips.cp0", 0 },
155  { MIPS32_REGLIST_C0_PC_INDEX, "pc", REG_TYPE_INT, NULL,
156  "org.gnu.gdb.mips.cpu", 0 },
157  { MIPS32_REGLIST_C0_GUESTCTL1_INDEX, "guestCtl1", REG_TYPE_INT, NULL,
158  "org.gnu.gdb.mips.cp0", 0 },
159 
160  { MIPS32_REGLIST_DSP_INDEX + 0, "hi1", REG_TYPE_INT, NULL,
161  "org.gnu.gdb.mips.dsp", 0 },
162  { MIPS32_REGLIST_DSP_INDEX + 1, "lo1", REG_TYPE_INT, NULL,
163  "org.gnu.gdb.mips.dsp", 0 },
164  { MIPS32_REGLIST_DSP_INDEX + 2, "hi2", REG_TYPE_INT, NULL,
165  "org.gnu.gdb.mips.dsp", 0 },
166  { MIPS32_REGLIST_DSP_INDEX + 3, "lo2", REG_TYPE_INT, NULL,
167  "org.gnu.gdb.mips.dsp", 0 },
168  { MIPS32_REGLIST_DSP_INDEX + 4, "hi3", REG_TYPE_INT, NULL,
169  "org.gnu.gdb.mips.dsp", 0 },
170  { MIPS32_REGLIST_DSP_INDEX + 5, "lo3", REG_TYPE_INT, NULL,
171  "org.gnu.gdb.mips.dsp", 0 },
172 
173  { MIPS32_REGLIST_DSP_DSPCTL_INDEX, "dspctl", REG_TYPE_INT, NULL,
174  "org.gnu.gdb.mips.dsp", 0 },
175 };
176 
177 #define MIPS32_NUM_REGS ARRAY_SIZE(mips32_regs)
178 
179 
180 
181 #define zero 0
182 
183 #define AT 1
184 
185 #define v0 2
186 #define v1 3
187 
188 #define a0 4
189 #define a1 5
190 #define a2 6
191 #define a3 7
192 #define t0 8
193 #define t1 9
194 #define t2 10
195 #define t3 11
196 #define t4 12
197 #define t5 13
198 #define t6 14
199 #define t7 15
200 #define ta0 12 /* alias for $t4 */
201 #define ta1 13 /* alias for $t5 */
202 #define ta2 14 /* alias for $t6 */
203 #define ta3 15 /* alias for $t7 */
204 
205 #define s0 16
206 #define s1 17
207 #define s2 18
208 #define s3 19
209 #define s4 20
210 #define s5 21
211 #define s6 22
212 #define s7 23
213 #define s8 30 /* == fp */
214 
215 #define t8 24
216 #define t9 25
217 #define k0 26
218 #define k1 27
219 
220 #define gp 28
221 
222 #define sp 29
223 #define fp 30
224 #define ra 31
225 
226 
227 static const struct {
228  const char *name;
229 } mips32_dsp_regs[MIPS32NUMDSPREGS] = {
230  { "hi1"},
231  { "lo1"},
232  { "hi2"},
233  { "lo2"},
234  { "hi3"},
235  { "lo3"},
236  { "control"},
237 };
238 
239 static int mips32_get_core_reg(struct reg *reg)
240 {
241  int retval;
242  struct mips32_core_reg *mips32_reg = reg->arch_info;
243  struct target *target = mips32_reg->target;
244  struct mips32_common *mips32_target = target_to_mips32(target);
245 
246  if (target->state != TARGET_HALTED)
247  return ERROR_TARGET_NOT_HALTED;
248 
249  retval = mips32_target->read_core_reg(target, mips32_reg->num);
250 
251  return retval;
252 }
253 
254 static int mips32_set_core_reg(struct reg *reg, uint8_t *buf)
255 {
256  struct mips32_core_reg *mips32_reg = reg->arch_info;
257  struct target *target = mips32_reg->target;
258  uint64_t value;
259 
260  if (reg->size == 64)
261  value = buf_get_u64(buf, 0, 64);
262  else
263  value = buf_get_u32(buf, 0, 32);
264 
265  if (target->state != TARGET_HALTED)
266  return ERROR_TARGET_NOT_HALTED;
267 
268  if (reg->size == 64)
269  buf_set_u64(reg->value, 0, 64, value);
270  else
271  buf_set_u32(reg->value, 0, 32, value);
272 
273  reg->dirty = true;
274  reg->valid = true;
275 
276  return ERROR_OK;
277 }
278 
286 static void mips32_set_all_fpr_width(struct mips32_common *mips32, bool fp64)
287 {
288  struct reg_cache *cache = mips32->core_cache;
289  struct reg *reg_list = cache->reg_list;
290  int i;
291 
292  for (i = MIPS32_REGLIST_FP_INDEX; i < (MIPS32_REGLIST_FP_INDEX + MIPS32_REG_FP_COUNT); i++) {
293  reg_list[i].size = fp64 ? 64 : 32;
294  reg_list[i].reg_data_type->type = fp64 ? REG_TYPE_IEEE_DOUBLE : REG_TYPE_IEEE_SINGLE;
295  }
296 }
297 
307 static void mips32_detect_fpr_mode_change(struct mips32_common *mips32, uint32_t cp0_status)
308 {
309  if (!mips32->fp_imp)
310  return;
311 
312  /* CP0.Status.FR indicates the working mode of floating-point register.
313  * When FP = 0, fpr can contain any 32bit data type,
314  * 64bit data types are stored in even-odd register pairs.
315  * When FP = 1, fpr can contain any data types.*/
316  bool fpu_in_64bit = ((cp0_status & BIT(MIPS32_CP0_STATUS_FR_SHIFT)) != 0);
317 
318  /* CP0.Status.CU1 indicated whether CoProcessor1(which is FPU) is present. */
319  bool fp_enabled = ((cp0_status & BIT(MIPS32_CP0_STATUS_CU1_SHIFT)) != 0);
320 
321  if (mips32->fpu_in_64bit != fpu_in_64bit) {
322  mips32->fpu_in_64bit = fpu_in_64bit;
323  mips32_set_all_fpr_width(mips32, fpu_in_64bit);
324  LOG_WARNING("** FP mode changed to %sbit, you must reconnect GDB **", fpu_in_64bit ? "64" : "32");
325  }
326 
327  if (mips32->fpu_enabled != fp_enabled) {
328  mips32->fpu_enabled = fp_enabled;
329  const char *s = fp_enabled ? "enabled" : "disabled";
330  LOG_WARNING("** FP is %s, register update %s **", s, s);
331  }
332 }
333 
334 static int mips32_read_core_reg(struct target *target, unsigned int num)
335 {
336  unsigned int cnum;
337  uint64_t reg_value = 0;
338 
339  /* get pointers to arch-specific information */
340  struct mips32_common *mips32 = target_to_mips32(target);
341 
342  if (num >= MIPS32_NUM_REGS)
343  return ERROR_COMMAND_SYNTAX_ERROR;
344 
345  if (num >= MIPS32_REGLIST_DSP_INDEX) {
346  /* DSP */
347  cnum = num - MIPS32_REGLIST_DSP_INDEX;
348  reg_value = mips32->core_regs.dsp[cnum];
349  buf_set_u32(mips32->core_cache->reg_list[num].value, 0, 32, reg_value);
350  } else if (num >= MIPS32_REGLIST_C0_INDEX) {
351  /* CP0 */
352  cnum = num - MIPS32_REGLIST_C0_INDEX;
353  reg_value = mips32->core_regs.cp0[cnum];
354  buf_set_u32(mips32->core_cache->reg_list[num].value, 0, 32, reg_value);
355  if (cnum == MIPS32_REG_C0_STATUS_INDEX)
356  mips32_detect_fpr_mode_change(mips32, reg_value);
357  } else if (num >= MIPS32_REGLIST_FPC_INDEX) {
358  /* FPCR */
359  cnum = num - MIPS32_REGLIST_FPC_INDEX;
360  reg_value = mips32->core_regs.fpcr[cnum];
361  buf_set_u32(mips32->core_cache->reg_list[num].value, 0, 32, reg_value);
362  } else if (num >= MIPS32_REGLIST_FP_INDEX) {
363  /* FPR */
364  cnum = num - MIPS32_REGLIST_FP_INDEX;
365  reg_value = mips32->core_regs.fpr[cnum];
366  buf_set_u64(mips32->core_cache->reg_list[num].value, 0, 64, reg_value);
367  } else {
368  /* GPR */
369  cnum = num - MIPS32_REGLIST_GP_INDEX;
370  reg_value = mips32->core_regs.gpr[cnum];
371  buf_set_u32(mips32->core_cache->reg_list[num].value, 0, 32, reg_value);
372  }
373 
374  mips32->core_cache->reg_list[num].valid = true;
375  mips32->core_cache->reg_list[num].dirty = false;
376 
377  LOG_DEBUG("read core reg %i value 0x%" PRIx64 "", num, reg_value);
378 
379  return ERROR_OK;
380 }
381 
382 static int mips32_write_core_reg(struct target *target, unsigned int num)
383 {
384  unsigned int cnum;
385  uint64_t reg_value;
386 
387  /* get pointers to arch-specific information */
388  struct mips32_common *mips32 = target_to_mips32(target);
389 
390  if (num >= MIPS32_NUM_REGS)
391  return ERROR_COMMAND_SYNTAX_ERROR;
392 
393  if (num >= MIPS32_REGLIST_DSP_INDEX) {
394  /* DSP */
395  cnum = num - MIPS32_REGLIST_DSP_INDEX;
396  reg_value = buf_get_u32(mips32->core_cache->reg_list[num].value, 0, 32);
397  mips32->core_regs.dsp[cnum] = (uint32_t)reg_value;
398  } else if (num >= MIPS32_REGLIST_C0_INDEX) {
399  /* CP0 */
400  cnum = num - MIPS32_REGLIST_C0_INDEX;
401  reg_value = buf_get_u32(mips32->core_cache->reg_list[num].value, 0, 32);
402  mips32->core_regs.cp0[cnum] = (uint32_t)reg_value;
403  if (cnum == MIPS32_REG_C0_STATUS_INDEX)
404  mips32_detect_fpr_mode_change(mips32, reg_value);
405  } else if (num >= MIPS32_REGLIST_FPC_INDEX) {
406  /* FPCR */
407  cnum = num - MIPS32_REGLIST_FPC_INDEX;
408  reg_value = buf_get_u32(mips32->core_cache->reg_list[num].value, 0, 32);
409  mips32->core_regs.fpcr[cnum] = (uint32_t)reg_value;
410  } else if (num >= MIPS32_REGLIST_FP_INDEX) {
411  /* FPR */
412  cnum = num - MIPS32_REGLIST_FP_INDEX;
413  reg_value = buf_get_u64(mips32->core_cache->reg_list[num].value, 0, 64);
414  mips32->core_regs.fpr[cnum] = reg_value;
415  } else {
416  /* GPR */
417  cnum = num - MIPS32_REGLIST_GP_INDEX;
418  reg_value = buf_get_u32(mips32->core_cache->reg_list[num].value, 0, 32);
419  mips32->core_regs.gpr[cnum] = (uint32_t)reg_value;
420  }
421 
422  LOG_DEBUG("write core reg %i value 0x%" PRIx64 "", num, reg_value);
423  mips32->core_cache->reg_list[num].valid = true;
424  mips32->core_cache->reg_list[num].dirty = false;
425 
426  return ERROR_OK;
427 }
428 
429 int mips32_get_gdb_reg_list(struct target *target, struct reg **reg_list[],
430  int *reg_list_size, enum target_register_class reg_class)
431 {
432  /* get pointers to arch-specific information */
433  struct mips32_common *mips32 = target_to_mips32(target);
434  unsigned int i;
435 
436  /* include floating point registers */
437  *reg_list_size = MIPS32_NUM_REGS;
438  *reg_list = malloc(sizeof(struct reg *) * (*reg_list_size));
439 
440  for (i = 0; i < MIPS32_NUM_REGS; i++)
441  (*reg_list)[i] = &mips32->core_cache->reg_list[i];
442 
443  return ERROR_OK;
444 }
445 
446 int mips32_save_context(struct target *target)
447 {
448  unsigned int i;
449 
450  /* get pointers to arch-specific information */
451  struct mips32_common *mips32 = target_to_mips32(target);
452 
453  /* read core registers */
454  int retval = mips32_pracc_read_regs(mips32);
455  if (retval != ERROR_OK) {
456  LOG_ERROR("Could not read core registers from target");
457  return retval;
458  }
459 
460  for (i = 0; i < MIPS32_NUM_REGS; i++) {
461  if (!mips32->core_cache->reg_list[i].valid)
462  mips32->read_core_reg(target, i);
463  }
464 
465  return ERROR_OK;
466 }
467 
468 int mips32_restore_context(struct target *target)
469 {
470  unsigned int i;
471 
472  /* get pointers to arch-specific information */
473  struct mips32_common *mips32 = target_to_mips32(target);
474 
475  for (i = 0; i < MIPS32_NUM_REGS; i++) {
476  if (mips32->core_cache->reg_list[i].dirty)
477  mips32->write_core_reg(target, i);
478  }
479 
480  /* write core regs */
481  return mips32_pracc_write_regs(mips32);
482 }
483 
484 int mips32_arch_state(struct target *target)
485 {
486  struct mips32_common *mips32 = target_to_mips32(target);
487 
488  LOG_USER("target halted in %s mode due to %s, pc: 0x%8.8" PRIx32 "",
489  mips_isa_strings[mips32->isa_mode],
490  debug_reason_name(target),
491  buf_get_u32(mips32->core_cache->reg_list[MIPS32_REGLIST_C0_PC_INDEX].value, 0, 32));
492 
493  return ERROR_OK;
494 }
495 
496 static const struct reg_arch_type mips32_reg_type = {
497  .get = mips32_get_core_reg,
498  .set = mips32_set_core_reg,
499 };
500 
501 struct reg_cache *mips32_build_reg_cache(struct target *target)
502 {
503  /* get pointers to arch-specific information */
504  struct mips32_common *mips32 = target_to_mips32(target);
505 
506  int num_regs = MIPS32_NUM_REGS;
507  struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
508  struct reg_cache *cache = malloc(sizeof(struct reg_cache));
509  struct reg *reg_list = calloc(num_regs, sizeof(struct reg));
510  struct mips32_core_reg *arch_info = malloc(sizeof(struct mips32_core_reg) * num_regs);
511  struct reg_feature *feature;
512  int i;
513 
514  /* Build the process context cache */
515  cache->name = "mips32 registers";
516  cache->next = NULL;
517  cache->reg_list = reg_list;
518  cache->num_regs = num_regs;
519  (*cache_p) = cache;
520  mips32->core_cache = cache;
521 
522  for (i = 0; i < num_regs; i++) {
523  arch_info[i].num = mips32_regs[i].id;
524  arch_info[i].target = target;
525  arch_info[i].mips32_common = mips32;
526 
527  reg_list[i].name = mips32_regs[i].name;
528  reg_list[i].size = mips32_regs[i].size ? 64 : 32;
529 
530  reg_list[i].value = mips32_regs[i].size ? calloc(1, 8) : calloc(1, 4);
531  reg_list[i].valid = false;
532  reg_list[i].type = &mips32_reg_type;
533  reg_list[i].arch_info = &arch_info[i];
534 
535  reg_list[i].reg_data_type = calloc(1, sizeof(struct reg_data_type));
536  if (reg_list[i].reg_data_type)
537  reg_list[i].reg_data_type->type = mips32_regs[i].type;
538  else
539  LOG_ERROR("unable to allocate reg type list");
540 
541 
542  reg_list[i].dirty = false;
543 
544  reg_list[i].group = mips32_regs[i].group;
545  reg_list[i].number = i;
546  reg_list[i].exist = true;
547  reg_list[i].caller_save = true; /* gdb defaults to true */
548 
549  feature = calloc(1, sizeof(struct reg_feature));
550  if (feature) {
551  feature->name = mips32_regs[i].feature;
552  reg_list[i].feature = feature;
553  } else
554  LOG_ERROR("unable to allocate feature list");
555  }
556 
557  return cache;
558 }
559 
560 int mips32_init_arch_info(struct target *target, struct mips32_common *mips32, struct jtag_tap *tap)
561 {
562  target->arch_info = mips32;
563  mips32->common_magic = MIPS32_COMMON_MAGIC;
564  mips32->fast_data_area = NULL;
565  mips32->isa_imp = MIPS32_ONLY; /* default */
566 
567  /* has breakpoint/watchpoint unit been scanned */
568  mips32->bp_scanned = 0;
569  mips32->data_break_list = NULL;
570 
571  mips32->ejtag_info.tap = tap;
572  mips32->read_core_reg = mips32_read_core_reg;
573  mips32->write_core_reg = mips32_write_core_reg;
574  /* if unknown endianness defaults to little endian, 1 */
575  mips32->ejtag_info.endianness = target->endianness == TARGET_BIG_ENDIAN ? 0 : 1;
576  mips32->ejtag_info.scan_delay = MIPS32_SCAN_DELAY_LEGACY_MODE;
577  mips32->ejtag_info.mode = 0; /* Initial default value */
578  mips32->ejtag_info.isa = 0; /* isa on debug mips32, updated by poll function */
579  mips32->ejtag_info.config_regs = 0; /* no config register read */
580  return ERROR_OK;
581 }
582 
583 /* run to exit point. return error if exit point was not reached. */
584 static int mips32_run_and_wait(struct target *target, target_addr_t entry_point,
585  unsigned int timeout_ms, target_addr_t exit_point, struct mips32_common *mips32)
586 {
587  uint32_t pc;
588  int retval;
589  /* This code relies on the target specific resume() and poll()->debug_entry()
590  * sequence to write register values to the processor and the read them back */
591  retval = target_resume(target, 0, entry_point, 0, 1);
592  if (retval != ERROR_OK)
593  return retval;
594 
595  retval = target_wait_state(target, TARGET_HALTED, timeout_ms);
596  /* If the target fails to halt due to the breakpoint, force a halt */
597  if (retval != ERROR_OK || target->state != TARGET_HALTED) {
598  retval = target_halt(target);
599  if (retval != ERROR_OK)
600  return retval;
601  retval = target_wait_state(target, TARGET_HALTED, 500);
602  if (retval != ERROR_OK)
603  return retval;
604  return ERROR_TARGET_TIMEOUT;
605  }
606 
607  pc = buf_get_u32(mips32->core_cache->reg_list[MIPS32_REGLIST_C0_PC_INDEX].value, 0, 32);
608  if (exit_point && (pc != exit_point)) {
609  LOG_DEBUG("failed algorithm halted at 0x%" PRIx32 " ", pc);
610  return ERROR_TARGET_TIMEOUT;
611  }
612 
613  return ERROR_OK;
614 }
615 
616 int mips32_run_algorithm(struct target *target, int num_mem_params,
617  struct mem_param *mem_params, int num_reg_params,
618  struct reg_param *reg_params, target_addr_t entry_point,
619  target_addr_t exit_point, unsigned int timeout_ms, void *arch_info)
620 {
621  struct mips32_common *mips32 = target_to_mips32(target);
622  struct mips32_algorithm *mips32_algorithm_info = arch_info;
623  enum mips32_isa_mode isa_mode = mips32->isa_mode;
624 
625  uint32_t context[MIPS32_NUM_REGS];
626  int retval = ERROR_OK;
627 
628  LOG_DEBUG("Running algorithm");
629 
630  /* NOTE: mips32_run_algorithm requires that each algorithm uses a software breakpoint
631  * at the exit point */
632 
633  if (mips32->common_magic != MIPS32_COMMON_MAGIC) {
634  LOG_ERROR("current target isn't a MIPS32 target");
635  return ERROR_TARGET_INVALID;
636  }
637 
638  if (target->state != TARGET_HALTED) {
639  LOG_TARGET_ERROR(target, "not halted (run target algo)");
640  return ERROR_TARGET_NOT_HALTED;
641  }
642 
643  /* refresh core register cache */
644  for (unsigned int i = 0; i < MIPS32_NUM_REGS; i++) {
645  if (!mips32->core_cache->reg_list[i].valid)
646  mips32->read_core_reg(target, i);
647  context[i] = buf_get_u32(mips32->core_cache->reg_list[i].value, 0, 32);
648  }
649 
650  for (int i = 0; i < num_mem_params; i++) {
651  if (mem_params[i].direction == PARAM_IN)
652  continue;
653  retval = target_write_buffer(target, mem_params[i].address,
654  mem_params[i].size, mem_params[i].value);
655  if (retval != ERROR_OK)
656  return retval;
657  }
658 
659  for (int i = 0; i < num_reg_params; i++) {
660  if (reg_params[i].direction == PARAM_IN)
661  continue;
662 
663  struct reg *reg = register_get_by_name(mips32->core_cache, reg_params[i].reg_name, false);
664 
665  if (!reg) {
666  LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
667  return ERROR_COMMAND_SYNTAX_ERROR;
668  }
669 
670  if (reg->size != reg_params[i].size) {
671  LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size",
672  reg_params[i].reg_name);
673  return ERROR_COMMAND_SYNTAX_ERROR;
674  }
675 
676  mips32_set_core_reg(reg, reg_params[i].value);
677  }
678 
679  mips32->isa_mode = mips32_algorithm_info->isa_mode;
680 
681  retval = mips32_run_and_wait(target, entry_point, timeout_ms, exit_point, mips32);
682 
683  if (retval != ERROR_OK)
684  return retval;
685 
686  for (int i = 0; i < num_mem_params; i++) {
687  if (mem_params[i].direction != PARAM_OUT) {
688  retval = target_read_buffer(target, mem_params[i].address, mem_params[i].size,
689  mem_params[i].value);
690  if (retval != ERROR_OK)
691  return retval;
692  }
693  }
694 
695  for (int i = 0; i < num_reg_params; i++) {
696  if (reg_params[i].direction != PARAM_OUT) {
697  struct reg *reg = register_get_by_name(mips32->core_cache, reg_params[i].reg_name, false);
698  if (!reg) {
699  LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
700  return ERROR_COMMAND_SYNTAX_ERROR;
701  }
702 
703  if (reg->size != reg_params[i].size) {
704  LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size",
705  reg_params[i].reg_name);
706  return ERROR_COMMAND_SYNTAX_ERROR;
707  }
708 
709  buf_set_u32(reg_params[i].value, 0, 32, buf_get_u32(reg->value, 0, 32));
710  }
711  }
712 
713  /* restore everything we saved before */
714  for (unsigned int i = 0; i < MIPS32_NUM_REGS; i++) {
715  uint32_t regvalue;
716  regvalue = buf_get_u32(mips32->core_cache->reg_list[i].value, 0, 32);
717  if (regvalue != context[i]) {
718  LOG_DEBUG("restoring register %s with value 0x%8.8" PRIx32,
719  mips32->core_cache->reg_list[i].name, context[i]);
720  buf_set_u32(mips32->core_cache->reg_list[i].value,
721  0, 32, context[i]);
722  mips32->core_cache->reg_list[i].valid = true;
723  mips32->core_cache->reg_list[i].dirty = true;
724  }
725  }
726 
727  mips32->isa_mode = isa_mode;
728 
729  return ERROR_OK;
730 }
731 
732 int mips32_examine(struct target *target)
733 {
734  struct mips32_common *mips32 = target_to_mips32(target);
735 
736  if (!target_was_examined(target)) {
737  target_set_examined(target);
738 
739  /* we will configure later */
740  mips32->bp_scanned = 0;
741  mips32->num_inst_bpoints = 0;
742  mips32->num_data_bpoints = 0;
743  mips32->num_inst_bpoints_avail = 0;
744  mips32->num_data_bpoints_avail = 0;
745  }
746 
747  return ERROR_OK;
748 }
749 
750 static int mips32_configure_ibs(struct target *target)
751 {
752  struct mips32_common *mips32 = target_to_mips32(target);
753  struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
754  int retval, i;
755  uint32_t bpinfo;
756 
757  /* get number of inst breakpoints */
758  retval = target_read_u32(target, ejtag_info->ejtag_ibs_addr, &bpinfo);
759  if (retval != ERROR_OK)
760  return retval;
761 
762  mips32->num_inst_bpoints = (bpinfo >> 24) & 0x0F;
763  mips32->num_inst_bpoints_avail = mips32->num_inst_bpoints;
764  mips32->inst_break_list = calloc(mips32->num_inst_bpoints,
765  sizeof(struct mips32_comparator));
766 
767  for (i = 0; i < mips32->num_inst_bpoints; i++)
768  mips32->inst_break_list[i].reg_address =
769  ejtag_info->ejtag_iba0_addr +
770  (ejtag_info->ejtag_iba_step_size * i);
771 
772  /* clear IBIS reg */
773  retval = target_write_u32(target, ejtag_info->ejtag_ibs_addr, 0);
774  return retval;
775 }
776 
777 static int mips32_configure_dbs(struct target *target)
778 {
779  struct mips32_common *mips32 = target_to_mips32(target);
780  struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
781  int retval, i;
782  uint32_t bpinfo;
783 
784  /* get number of data breakpoints */
785  retval = target_read_u32(target, ejtag_info->ejtag_dbs_addr, &bpinfo);
786  if (retval != ERROR_OK)
787  return retval;
788 
789  mips32->num_data_bpoints = (bpinfo >> 24) & 0x0F;
790  mips32->num_data_bpoints_avail = mips32->num_data_bpoints;
791  mips32->data_break_list = calloc(mips32->num_data_bpoints,
792  sizeof(struct mips32_comparator));
793 
794  for (i = 0; i < mips32->num_data_bpoints; i++)
795  mips32->data_break_list[i].reg_address =
796  ejtag_info->ejtag_dba0_addr +
797  (ejtag_info->ejtag_dba_step_size * i);
798 
799  /* clear DBIS reg */
800  retval = target_write_u32(target, ejtag_info->ejtag_dbs_addr, 0);
801  return retval;
802 }
803 
804 int mips32_configure_break_unit(struct target *target)
805 {
806  /* get pointers to arch-specific information */
807  struct mips32_common *mips32 = target_to_mips32(target);
808  struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
809  int retval;
810  uint32_t dcr;
811 
812  if (mips32->bp_scanned)
813  return ERROR_OK;
814 
815  /* get info about breakpoint support */
816  retval = target_read_u32(target, EJTAG_DCR, &dcr);
817  if (retval != ERROR_OK)
818  return retval;
819 
820  /* EJTAG 2.0 defines IB and DB bits in IMP instead of DCR. */
821  if (ejtag_info->ejtag_version == EJTAG_VERSION_20) {
822  ejtag_info->debug_caps = dcr & EJTAG_DCR_ENM;
823  if (!(ejtag_info->impcode & EJTAG_V20_IMP_NOIB))
824  ejtag_info->debug_caps |= EJTAG_DCR_IB;
825  if (!(ejtag_info->impcode & EJTAG_V20_IMP_NODB))
826  ejtag_info->debug_caps |= EJTAG_DCR_DB;
827  } else
828  /* keep debug caps for later use */
829  ejtag_info->debug_caps = dcr & (EJTAG_DCR_ENM
830  | EJTAG_DCR_IB | EJTAG_DCR_DB);
831 
832 
833  if (ejtag_info->debug_caps & EJTAG_DCR_IB) {
834  retval = mips32_configure_ibs(target);
835  if (retval != ERROR_OK)
836  return retval;
837  }
838 
839  if (ejtag_info->debug_caps & EJTAG_DCR_DB) {
840  retval = mips32_configure_dbs(target);
841  if (retval != ERROR_OK)
842  return retval;
843  }
844 
845  /* check if target endianness settings matches debug control register */
846  if (((ejtag_info->debug_caps & EJTAG_DCR_ENM)
847  && (target->endianness == TARGET_LITTLE_ENDIAN)) ||
848  (!(ejtag_info->debug_caps & EJTAG_DCR_ENM)
849  && (target->endianness == TARGET_BIG_ENDIAN)))
850  LOG_WARNING("DCR endianness settings does not match target settings");
851 
852  LOG_DEBUG("DCR 0x%" PRIx32 " numinst %i numdata %i", dcr, mips32->num_inst_bpoints,
853  mips32->num_data_bpoints);
854 
855  mips32->bp_scanned = 1;
856 
857  return ERROR_OK;
858 }
859 
860 int mips32_enable_interrupts(struct target *target, int enable)
861 {
862  int retval;
863  int update = 0;
864  uint32_t dcr;
865 
866  /* read debug control register */
867  retval = target_read_u32(target, EJTAG_DCR, &dcr);
868  if (retval != ERROR_OK)
869  return retval;
870 
871  if (enable) {
872  if (!(dcr & EJTAG_DCR_INTE)) {
873  /* enable interrupts */
874  dcr |= EJTAG_DCR_INTE;
875  update = 1;
876  }
877  } else {
878  if (dcr & EJTAG_DCR_INTE) {
879  /* disable interrupts */
880  dcr &= ~EJTAG_DCR_INTE;
881  update = 1;
882  }
883  }
884 
885  if (update) {
886  retval = target_write_u32(target, EJTAG_DCR, dcr);
887  if (retval != ERROR_OK)
888  return retval;
889  }
890 
891  return ERROR_OK;
892 }
893 
894 /* read processor identification cp0 register */
895 static int mips32_read_c0_prid(struct target *target)
896 {
897  struct mips32_common *mips32 = target_to_mips32(target);
898  struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
899  int retval;
900 
901  retval = mips32_cp0_read(ejtag_info, &mips32->prid, 15, 0);
902  if (retval != ERROR_OK) {
903  LOG_ERROR("processor id not available, failed to read cp0 PRId register");
904  mips32->prid = 0;
905  }
906 
907  return retval;
908 }
909 
920 static const struct cpu_entry *mips32_find_cpu_by_prid(uint32_t prid)
921 {
922  /* AMD/Alchemy CPU uses Company Options instead of Processor ID.
923  * Therefore an extra transform step for prid to map it to an assigned ID,
924  */
925  if ((prid & PRID_COMP_MASK) == PRID_COMP_ALCHEMY) {
926  /* Clears Processor ID field, then put Company Option field to its place */
927  prid = (prid & 0xFFFF00FF) | ((prid & 0xFF000000) >> 16);
928  }
929 
930  /* Mask out Company Option */
931  prid &= 0x00FFFFFF;
932 
933  for (unsigned int i = 0; i < MIPS32_NUM_CPU_ENTRIES; i++) {
934  const struct cpu_entry *entry = &mips32_cpu_entry[i];
935  if ((entry->prid & MIPS32_CORE_MASK) <= prid && prid <= entry->prid)
936  return entry;
937  }
938 
939  /* If nothing matched, then return unknown entry */
940  return &mips32_cpu_entry[MIPS32_NUM_CPU_ENTRIES - 1];
941 }
942 
943 static bool mips32_cpu_is_lexra(struct mips_ejtag *ejtag_info)
944 {
945  return (ejtag_info->prid & PRID_COMP_MASK) == PRID_COMP_LEXRA;
946 }
947 
948 static int mips32_cpu_get_release(struct mips_ejtag *ejtag_info)
949 {
950  return (ejtag_info->config[0] & MIPS32_CONFIG0_AR_MASK) >> MIPS32_CONFIG0_AR_SHIFT;
951 }
952 
963 bool mips32_cpu_support_sync(struct mips_ejtag *ejtag_info)
964 {
965  return !mips32_cpu_is_lexra(ejtag_info);
966 }
967 
976 bool mips32_cpu_support_hazard_barrier(struct mips_ejtag *ejtag_info)
977 {
978  return mips32_cpu_get_release(ejtag_info) > MIPS32_RELEASE_1;
979 }
980 
995 int mips32_cpu_probe(struct target *target)
996 {
997  struct mips32_common *mips32 = target_to_mips32(target);
998  int retval;
999 
1000  if (mips32->prid)
1001  return ERROR_OK; /* Already probed once, return early. */
1002 
1003  retval = mips32_read_c0_prid(target);
1004  if (retval != ERROR_OK)
1005  return retval;
1006 
1007  const struct cpu_entry *entry = mips32_find_cpu_by_prid(mips32->prid);
1008 
1009  switch (mips32->prid & PRID_COMP_MASK) {
1010  case PRID_COMP_INGENIC_E1:
1011  switch (mips32->prid & PRID_IMP_MASK) {
1012  case PRID_IMP_XBURST_REV1:
1013  mips32->cpu_quirks |= EJTAG_QUIRK_PAD_DRET;
1014  break;
1015  default:
1016  break;
1017  }
1018  break;
1019 
1020  /* Determine which CP0 registers are available in the current processor core */
1021  case PRID_COMP_MTI:
1022  switch (entry->prid & PRID_IMP_MASK) {
1023  case PRID_IMP_MAPTIV_UC:
1024  mips32->cp0_mask = MIPS_CP0_MAPTIV_UC;
1025  break;
1026  case PRID_IMP_MAPTIV_UP:
1027  case PRID_IMP_M5150:
1028  mips32->cp0_mask = MIPS_CP0_MAPTIV_UP;
1029  break;
1030  case PRID_IMP_IAPTIV:
1031  case PRID_IMP_IAPTIV_CM:
1032  mips32->cp0_mask = MIPS_CP0_IAPTIV;
1033  break;
1034  default:
1035  /* CP0 mask should be the same as MK4 by default */
1036  mips32->cp0_mask = MIPS_CP0_MK4;
1037  break;
1038  }
1039 
1040  default:
1041  break;
1042  }
1043 
1044  mips32->cpu_info = entry;
1045  LOG_DEBUG("CPU: %s (PRId %08x)", entry->cpu_name, mips32->prid);
1046 
1047  return ERROR_OK;
1048 }
1049 
1050 /* reads dsp implementation info from CP0 Config3 register {DSPP, DSPREV}*/
1051 static void mips32_read_config_dsp(struct mips32_common *mips32, struct mips_ejtag *ejtag_info)
1052 {
1053  uint32_t retval, status_value, dsp_present;
1054  bool dsp_enabled;
1055 
1056  retval = mips32_cp0_read(ejtag_info, &status_value, MIPS32_C0_STATUS, 0);
1057  if (retval != ERROR_OK) {
1058  LOG_ERROR("Failed to read cp0 status register");
1059  return;
1060  }
1061 
1062  dsp_present = ((ejtag_info->config[3] & MIPS32_CONFIG3_DSPP_MASK) >> MIPS32_CONFIG3_DSPP_SHIFT);
1063  dsp_enabled = (status_value & BIT(MIPS32_CP0_STATUS_MX_SHIFT)) != 0;
1064  if (dsp_present) {
1065  mips32->dsp_imp = ((ejtag_info->config[3] & MIPS32_CONFIG3_DSPREV_MASK) >> MIPS32_CONFIG3_DSPREV_SHIFT) + 1;
1066  LOG_USER("DSP implemented: rev %d, %s", mips32->dsp_imp, dsp_enabled ? "enabled" : "disabled");
1067  } else {
1068  LOG_USER("DSP implemented: %s", "no");
1069  }
1070 }
1071 
1072 /* read fpu implementation info from CP0 Config1 register {CU1, FP}*/
1073 static int mips32_read_config_fpu(struct mips32_common *mips32, struct mips_ejtag *ejtag_info)
1074 {
1075  int retval;
1076  uint32_t fp_imp = (ejtag_info->config[1] & MIPS32_CONFIG1_FP_MASK) >> MIPS32_CONFIG1_FP_SHIFT;
1077  char buf[60] = {0};
1078  if (!fp_imp) {
1079  LOG_USER("FPU implemented: %s", "no");
1080  mips32->fp_imp = MIPS32_FP_IMP_NONE;
1081  return ERROR_OK;
1082  }
1083  uint32_t fir_value, status_value;
1084  bool fpu_in_64bit, fp_enabled;
1085 
1086  retval = mips32_cp0_read(ejtag_info, &status_value, MIPS32_C0_STATUS, 0);
1087  if (retval != ERROR_OK) {
1088  LOG_ERROR("Failed to read cp0 status register");
1089  return retval;
1090  }
1091 
1092  fpu_in_64bit = (status_value & BIT(MIPS32_CP0_STATUS_FR_SHIFT)) != 0;
1093  fp_enabled = (status_value & BIT(MIPS32_CP0_STATUS_CU1_SHIFT)) != 0;
1094  if (fp_enabled) {
1095  retval = mips32_cp1_control_read(ejtag_info, &fir_value, 0);
1096  if (retval != ERROR_OK) {
1097  LOG_ERROR("Failed to read cp1 FIR register");
1098  return retval;
1099  }
1100 
1101  if ((fir_value >> MIPS32_CP1_FIR_F64_SHIFT) & 0x1)
1102  fp_imp++;
1103  } else {
1104  /* This is the only condition that writes to buf */
1105  snprintf(buf, sizeof(buf), "yes, disabled");
1106  fp_imp = MIPS32_FP_IMP_UNKNOWN;
1107  }
1108 
1109  mips32->fpu_in_64bit = fpu_in_64bit;
1110  mips32->fpu_enabled = fp_enabled;
1111 
1112  mips32_set_all_fpr_width(mips32, fpu_in_64bit);
1113 
1114  /* If fpu is not disabled, print out more information */
1115  if (!buf[0])
1116  snprintf(buf, sizeof(buf), "yes, %sbit (%s, working in %sbit)",
1117  fp_imp == MIPS32_FP_IMP_64 ? "64" : "32",
1118  fp_enabled ? "enabled" : "disabled",
1119  fpu_in_64bit ? "64" : "32");
1120 
1121  LOG_USER("FPU implemented: %s", buf);
1122  mips32->fp_imp = fp_imp;
1123 
1124  return ERROR_OK;
1125 }
1126 
1143 static void mips32_read_config_fdc(struct mips32_common *mips32, struct mips_ejtag *ejtag_info, uint32_t dcr)
1144 {
1145  if (((ejtag_info->config[3] & MIPS32_CONFIG3_CDMM_MASK) != 0) && ((dcr & EJTAG_DCR_FDC) != 0)) {
1146  mips32->fdc = 1;
1147  mips32->semihosting = 1;
1148  } else {
1149  mips32->fdc = 0;
1150  mips32->semihosting = 0;
1151  }
1152 }
1153 
1154 /* read config to config3 cp0 registers and log isa implementation */
1155 int mips32_read_config_regs(struct target *target)
1156 {
1157  struct mips32_common *mips32 = target_to_mips32(target);
1158  struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
1159  char buf[60] = {0};
1160  int retval;
1161 
1162  if (ejtag_info->config_regs == 0)
1163  for (int i = 0; i != 4; i++) {
1164  retval = mips32_cp0_read(ejtag_info, &ejtag_info->config[i], 16, i);
1165  if (retval != ERROR_OK) {
1166  LOG_ERROR("isa info not available, failed to read cp0 config register: %" PRId32, i);
1167  ejtag_info->config_regs = 0;
1168  return retval;
1169  }
1170  ejtag_info->config_regs = i + 1;
1171  if ((ejtag_info->config[i] & (1 << 31)) == 0)
1172  break; /* no more config registers implemented */
1173  }
1174  else
1175  return ERROR_OK; /* already successfully read */
1176 
1177  LOG_DEBUG("read %"PRIu32" config registers", ejtag_info->config_regs);
1178 
1179  mips32->isa_rel = (ejtag_info->config[0] & MIPS32_CONFIG0_AR_MASK) >> MIPS32_CONFIG0_AR_SHIFT;
1180  snprintf(buf, sizeof(buf), ", release %s(AR=%d)",
1181  mips32->isa_rel == MIPS32_RELEASE_1 ? "1"
1182  : mips32->isa_rel == MIPS32_RELEASE_2 ? "2"
1183  : mips32->isa_rel == MIPS32_RELEASE_6 ? "6"
1184  : "unknown", mips32->isa_rel);
1185 
1186  if (ejtag_info->impcode & EJTAG_IMP_MIPS16) {
1187  mips32->isa_imp = MIPS32_MIPS16;
1188  LOG_USER("ISA implemented: %s%s", "MIPS32, MIPS16", buf);
1189  } else if (ejtag_info->config_regs >= 4) { /* config3 implemented */
1190  unsigned int isa_imp = (ejtag_info->config[3] & MIPS32_CONFIG3_ISA_MASK) >> MIPS32_CONFIG3_ISA_SHIFT;
1191  if (isa_imp == 1) {
1192  mips32->isa_imp = MMIPS32_ONLY;
1193  LOG_USER("ISA implemented: %s%s", "microMIPS32", buf);
1194 
1195  } else if (isa_imp != 0) {
1196  mips32->isa_imp = MIPS32_MMIPS32;
1197  LOG_USER("ISA implemented: %s%s", "MIPS32, microMIPS32", buf);
1198  }
1199  } else if (mips32->isa_imp == MIPS32_ONLY) {
1200  /* initial default value */
1201  LOG_USER("ISA implemented: %s%s", "MIPS32", buf);
1202  }
1203 
1204  /* Retrieve DSP info */
1205  mips32_read_config_dsp(mips32, ejtag_info);
1206 
1207  /* Retrieve if Float Point CoProcessor Implemented */
1208  retval = mips32_read_config_fpu(mips32, ejtag_info);
1209  if (retval != ERROR_OK) {
1210  LOG_ERROR("fpu info is not available, error while reading cp0 status");
1211  mips32->fp_imp = MIPS32_FP_IMP_NONE;
1212  return retval;
1213  }
1214 
1215  uint32_t dcr;
1216 
1217  retval = target_read_u32(target, EJTAG_DCR, &dcr);
1218  if (retval != ERROR_OK) {
1219  LOG_ERROR("failed to read EJTAG_DCR register");
1220  return retval;
1221  }
1222 
1223  /* Determine if FDC and CDMM are implemented for this core */
1224  mips32_read_config_fdc(mips32, ejtag_info, dcr);
1225 
1226  return ERROR_OK;
1227 }
1228 
1229 int mips32_checksum_memory(struct target *target, target_addr_t address,
1230  uint32_t count, uint32_t *checksum)
1231 {
1232  struct working_area *crc_algorithm;
1233  struct reg_param reg_params[2];
1234  struct mips32_algorithm mips32_info;
1235 
1236  struct mips32_common *mips32 = target_to_mips32(target);
1237  struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
1238 
1239  /* see contrib/loaders/checksum/mips32.s for src */
1240  uint32_t isa = ejtag_info->isa ? 1 : 0;
1241 
1242  uint32_t mips_crc_code[] = {
1243  MIPS32_ADDIU(isa, 12, 4, 0), /* addiu $t4, $a0, 0 */
1244  MIPS32_ADDIU(isa, 10, 5, 0), /* addiu $t2, $a1, 0 */
1245  MIPS32_ADDIU(isa, 4, 0, 0xFFFF), /* addiu $a0, $zero, 0xffff */
1246  MIPS32_BEQ(isa, 0, 0, 0x10 << isa), /* beq $zero, $zero, ncomp */
1247  MIPS32_ADDIU(isa, 11, 0, 0), /* addiu $t3, $zero, 0 */
1248  /* nbyte: */
1249  MIPS32_LB(isa, 5, 0, 12), /* lb $a1, ($t4) */
1250  MIPS32_ADDI(isa, 12, 12, 1), /* addi $t4, $t4, 1 */
1251  MIPS32_SLL(isa, 5, 5, 24), /* sll $a1, $a1, 24 */
1252  MIPS32_LUI(isa, 2, 0x04c1), /* lui $v0, 0x04c1 */
1253  MIPS32_XOR(isa, 4, 4, 5), /* xor $a0, $a0, $a1 */
1254  MIPS32_ORI(isa, 7, 2, 0x1db7), /* ori $a3, $v0, 0x1db7 */
1255  MIPS32_ADDU(isa, 6, 0, 0), /* addu $a2, $zero, $zero */
1256  /* loop */
1257  MIPS32_SLL(isa, 8, 4, 1), /* sll $t0, $a0, 1 */
1258  MIPS32_ADDIU(isa, 6, 6, 1), /* addiu $a2, $a2, 1 */
1259  MIPS32_SLTI(isa, 4, 4, 0), /* slti $a0, $a0, 0 */
1260  MIPS32_XOR(isa, 9, 8, 7), /* xor $t1, $t0, $a3 */
1261  MIPS32_MOVN(isa, 8, 9, 4), /* movn $t0, $t1, $a0 */
1262  MIPS32_SLTI(isa, 3, 6, 8), /* slti $v1, $a2, 8 */
1263  MIPS32_BNE(isa, 3, 0, NEG16(7 << isa)), /* bne $v1, $zero, loop */
1264  MIPS32_ADDU(isa, 4, 8, 0), /* addu $a0, $t0, $zero */
1265  /* ncomp */
1266  MIPS32_BNE(isa, 10, 11, NEG16(16 << isa)), /* bne $t2, $t3, nbyte */
1267  MIPS32_ADDIU(isa, 11, 11, 1), /* addiu $t3, $t3, 1 */
1268  MIPS32_SDBBP(isa),
1269  };
1270 
1271  /* make sure we have a working area */
1272  if (target_alloc_working_area(target, sizeof(mips_crc_code), &crc_algorithm) != ERROR_OK)
1273  return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1274 
1275  pracc_swap16_array(ejtag_info, mips_crc_code, ARRAY_SIZE(mips_crc_code));
1276 
1277  /* convert mips crc code into a buffer in target endianness */
1278  uint8_t mips_crc_code_8[sizeof(mips_crc_code)];
1279  target_buffer_set_u32_array(target, mips_crc_code_8,
1280  ARRAY_SIZE(mips_crc_code), mips_crc_code);
1281 
1282  int retval = target_write_buffer(target, crc_algorithm->address, sizeof(mips_crc_code), mips_crc_code_8);
1283  if (retval != ERROR_OK)
1284  return retval;
1285 
1286  mips32_info.common_magic = MIPS32_COMMON_MAGIC;
1287  mips32_info.isa_mode = isa ? MIPS32_ISA_MMIPS32 : MIPS32_ISA_MIPS32; /* run isa as in debug mode */
1288 
1289  init_reg_param(&reg_params[0], "r4", 32, PARAM_IN_OUT);
1290  buf_set_u32(reg_params[0].value, 0, 32, address);
1291 
1292  init_reg_param(&reg_params[1], "r5", 32, PARAM_OUT);
1293  buf_set_u32(reg_params[1].value, 0, 32, count);
1294 
1295  unsigned int timeout = 20000 * (1 + (count / (1024 * 1024)));
1296 
1297  retval = target_run_algorithm(target, 0, NULL, 2, reg_params, crc_algorithm->address,
1298  crc_algorithm->address + (sizeof(mips_crc_code) - 4), timeout, &mips32_info);
1299 
1300  if (retval == ERROR_OK)
1301  *checksum = buf_get_u32(reg_params[0].value, 0, 32);
1302 
1303  destroy_reg_param(&reg_params[0]);
1304  destroy_reg_param(&reg_params[1]);
1305 
1306  target_free_working_area(target, crc_algorithm);
1307 
1308  return retval;
1309 }
1310 
1312 int mips32_blank_check_memory(struct target *target,
1313  struct target_memory_check_block *blocks, int num_blocks,
1314  uint8_t erased_value)
1315 {
1316  struct working_area *erase_check_algorithm;
1317  struct reg_param reg_params[3];
1318  struct mips32_algorithm mips32_info;
1319 
1320  struct mips32_common *mips32 = target_to_mips32(target);
1321  struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
1322 
1323  if (erased_value != 0xff) {
1324  LOG_ERROR("Erase value 0x%02" PRIx8 " not yet supported for MIPS32",
1325  erased_value);
1326  return ERROR_FAIL;
1327  }
1328  uint32_t isa = ejtag_info->isa ? 1 : 0;
1329  uint32_t erase_check_code[] = {
1330  /* nbyte: */
1331  MIPS32_LB(isa, 8, 0, 4), /* lb $t0, ($a0) */
1332  MIPS32_AND(isa, 6, 6, 8), /* and $a2, $a2, $t0 */
1333  MIPS32_ADDIU(isa, 5, 5, NEG16(1)), /* addiu $a1, $a1, -1 */
1334  MIPS32_BNE(isa, 5, 0, NEG16(4 << isa)), /* bne $a1, $zero, nbyte */
1335  MIPS32_ADDIU(isa, 4, 4, 1), /* addiu $a0, $a0, 1 */
1336  MIPS32_SDBBP(isa) /* sdbbp */
1337  };
1338 
1339  /* make sure we have a working area */
1340  if (target_alloc_working_area(target, sizeof(erase_check_code), &erase_check_algorithm) != ERROR_OK)
1341  return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1342 
1343  pracc_swap16_array(ejtag_info, erase_check_code, ARRAY_SIZE(erase_check_code));
1344 
1345  /* convert erase check code into a buffer in target endianness */
1346  uint8_t erase_check_code_8[sizeof(erase_check_code)];
1347  target_buffer_set_u32_array(target, erase_check_code_8,
1348  ARRAY_SIZE(erase_check_code), erase_check_code);
1349 
1350  int retval = target_write_buffer(target, erase_check_algorithm->address,
1351  sizeof(erase_check_code), erase_check_code_8);
1352  if (retval != ERROR_OK)
1353  goto cleanup;
1354 
1355  mips32_info.common_magic = MIPS32_COMMON_MAGIC;
1356  mips32_info.isa_mode = isa ? MIPS32_ISA_MMIPS32 : MIPS32_ISA_MIPS32;
1357 
1358  init_reg_param(&reg_params[0], "r4", 32, PARAM_OUT);
1359  buf_set_u32(reg_params[0].value, 0, 32, blocks[0].address);
1360 
1361  init_reg_param(&reg_params[1], "r5", 32, PARAM_OUT);
1362  buf_set_u32(reg_params[1].value, 0, 32, blocks[0].size);
1363 
1364  init_reg_param(&reg_params[2], "r6", 32, PARAM_IN_OUT);
1365  buf_set_u32(reg_params[2].value, 0, 32, erased_value);
1366 
1367  retval = target_run_algorithm(target, 0, NULL, 3, reg_params, erase_check_algorithm->address,
1368  erase_check_algorithm->address + (sizeof(erase_check_code) - 4), 10000, &mips32_info);
1369 
1370  if (retval == ERROR_OK)
1371  blocks[0].result = buf_get_u32(reg_params[2].value, 0, 32);
1372 
1373  destroy_reg_param(&reg_params[0]);
1374  destroy_reg_param(&reg_params[1]);
1375  destroy_reg_param(&reg_params[2]);
1376 
1377 cleanup:
1378  target_free_working_area(target, erase_check_algorithm);
1379 
1380  if (retval != ERROR_OK)
1381  return retval;
1382 
1383  return 1; /* only one block has been checked */
1384 }
1385 
1386 static int mips32_verify_pointer(struct command_invocation *cmd,
1387  struct mips32_common *mips32)
1388 {
1389  if (mips32->common_magic != MIPS32_COMMON_MAGIC) {
1390  command_print(cmd, "target is not an MIPS32");
1391  return ERROR_TARGET_INVALID;
1392  }
1393  return ERROR_OK;
1394 }
1395 
1405 static int mips32_read_config_mmu(struct mips_ejtag *ejtag_info)
1406 {
1407  uint32_t config4, tlb_entries = 0, ways = 0, sets = 0;
1408  uint32_t config0 = ejtag_info->config[0];
1409  uint32_t config1 = ejtag_info->config[1];
1410  uint32_t config3 = ejtag_info->config[3];
1411  uint32_t mmu_type = (config0 >> 7) & 7;
1412  uint32_t vz_present = (config3 & BIT(23));
1413 
1414  int retval = mips32_cp0_read(ejtag_info, &config4, 16, 4);
1415  if (retval != ERROR_OK)
1416  return retval;
1417 
1418  /* mmu type = 1: VTLB only (Note: Does not account for Config4.ExtVTLB)
1419  * mmu type = 3: root RPU/Fixed (Note: Only valid with VZ ASE)
1420  * mmu type = 4: VTLB and FTLB
1421  */
1422  if ((mmu_type == 1 || mmu_type == 4) || (mmu_type == 3 && vz_present)) {
1423  tlb_entries = (uint32_t)(((config1 >> 25) & 0x3f) + 1);
1424  if (mmu_type == 4) {
1425  /* Release 6 definition for Config4[0:15] (MD01251, page 243) */
1426  /* The FTLB ways field is defined as [2, 3, 4, 5, 6, 7, 8, ...0 (reserved)] */
1427  int index = ((config4 >> 4) & 0xf);
1428  ways = index > 6 ? 0 : index + 2;
1429 
1430  /* The FTLB sets field is defined as [1, 2, 4, 8, ..., 16384, 32768] (powers of 2) */
1431  index = (config4 & 0xf);
1432  sets = 1 << index;
1433  tlb_entries = tlb_entries + (ways * sets);
1434  }
1435  }
1436  LOG_USER("TLB Entries: %d (%d ways, %d sets per way)", tlb_entries, ways, sets);
1437 
1438  return ERROR_OK;
1439 }
1440 
1452 static const struct mips32_cp0 *mips32_cp0_find_register_by_name(uint32_t cp0_mask, const char *reg_name)
1453 {
1454  if (reg_name)
1455  for (unsigned int i = 0; i < MIPS32NUMCP0REGS; i++) {
1456  if ((mips32_cp0_regs[i].core & cp0_mask) == 0)
1457  continue;
1458 
1459  if (strcmp(mips32_cp0_regs[i].name, reg_name) == 0)
1460  return &mips32_cp0_regs[i];
1461  }
1462  return NULL;
1463 }
1464 
1476 static int mips32_cp0_get_all_regs(struct command_invocation *cmd, struct mips_ejtag *ejtag_info, uint32_t cp0_mask)
1477 {
1478  uint32_t value;
1479 
1480  for (unsigned int i = 0; i < MIPS32NUMCP0REGS; i++) {
1481  /* Register name not valid for this core */
1482  if ((mips32_cp0_regs[i].core & cp0_mask) == 0)
1483  continue;
1484 
1485  int retval = mips32_cp0_read(ejtag_info, &value, mips32_cp0_regs[i].reg, mips32_cp0_regs[i].sel);
1486  if (retval != ERROR_OK) {
1487  command_print(CMD, "Error: couldn't access reg %s", mips32_cp0_regs[i].name);
1488  return retval;
1489  }
1490 
1491  command_print(CMD, "%*s: 0x%8.8" PRIx32, 14, mips32_cp0_regs[i].name, value);
1492  }
1493  return ERROR_OK;
1494 }
1495 
1507 static int mips32_cp0_get_reg_by_name(struct command_invocation *cmd, struct mips_ejtag *ejtag_info, uint32_t cp0_mask)
1508 {
1509  const struct mips32_cp0 *cp0_regs = mips32_cp0_find_register_by_name(cp0_mask, CMD_ARGV[0]);
1510  if (!cp0_regs) {
1511  command_print(CMD, "Error: Register '%s' not found", CMD_ARGV[0]);
1512  return ERROR_COMMAND_ARGUMENT_INVALID;
1513  }
1514 
1515  uint32_t value;
1516  int retval = mips32_cp0_read(ejtag_info, &value, cp0_regs->reg, cp0_regs->sel);
1517  if (retval != ERROR_OK) {
1518  command_print(CMD, "Error: Encounter an Error while reading cp0 reg %d sel %d",
1519  cp0_regs->reg, cp0_regs->sel);
1520  return retval;
1521  }
1522 
1523  command_print(CMD, "0x%8.8" PRIx32, value);
1524  return ERROR_OK;
1525 }
1526 
1537 static int mips32_cp0_get_reg_by_number(struct command_invocation *cmd, struct mips_ejtag *ejtag_info)
1538 {
1539  uint32_t cp0_reg, cp0_sel, value;
1540  COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], cp0_reg);
1541  COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], cp0_sel);
1542 
1543  int retval = mips32_cp0_read(ejtag_info, &value, cp0_reg, cp0_sel);
1544  if (retval != ERROR_OK) {
1545  command_print(CMD,
1546  "Error: couldn't access reg %" PRIu32,
1547  cp0_reg);
1548  return retval;
1549  }
1550 
1551  command_print(CMD, "cp0 reg %" PRIu32 ", select %" PRIu32 ": %8.8" PRIx32,
1552  cp0_reg, cp0_sel, value);
1553  return ERROR_OK;
1554 }
1555 
1567 static int mips32_cp0_set_reg_by_name(struct command_invocation *cmd,
1568  struct mips32_common *mips32, struct mips_ejtag *ejtag_info)
1569 {
1570  const struct mips32_cp0 *cp0_regs = mips32_cp0_find_register_by_name(mips32->cp0_mask, CMD_ARGV[0]);
1571  if (!cp0_regs) {
1572  command_print(CMD, "Error: Register '%s' not found", CMD_ARGV[0]);
1573  return ERROR_COMMAND_ARGUMENT_INVALID;
1574  }
1575 
1576 
1577  uint32_t value;
1578  COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], value);
1579 
1580  if (cp0_regs->reg == MIPS32_C0_STATUS && cp0_regs->sel == 0) {
1581  /* Update cached Status register if user is writing to Status */
1582  mips32->core_regs.cp0[MIPS32_REG_C0_STATUS_INDEX] = value;
1583  mips32->core_cache->reg_list[MIPS32_REGLIST_C0_STATUS_INDEX].dirty = 1;
1584  } else if (cp0_regs->reg == MIPS32_C0_CAUSE && cp0_regs->sel == 0) {
1585  /* Update register cache with new value if its Cause */
1586  mips32->core_regs.cp0[MIPS32_REG_C0_CAUSE_INDEX] = value;
1587  mips32->core_cache->reg_list[MIPS32_REGLIST_C0_CAUSE_INDEX].dirty = 1;
1588  } else if (cp0_regs->reg == MIPS32_C0_DEPC && cp0_regs->sel == 0) {
1589  /* Update cached PC if its DEPC */
1590  mips32->core_regs.cp0[MIPS32_REG_C0_PC_INDEX] = value;
1591  mips32->core_cache->reg_list[MIPS32_REGLIST_C0_PC_INDEX].dirty = 1;
1592  } else if (cp0_regs->reg == MIPS32_C0_GUESTCTL1 && cp0_regs->sel == 4) {
1593  /* Update cached guestCtl1 */
1594  mips32->core_regs.cp0[MIPS32_REG_C0_GUESTCTL1_INDEX] = value;
1595  mips32->core_cache->reg_list[MIPS32_REGLIST_C0_GUESTCTL1_INDEX].dirty = 1;
1596  }
1597 
1598  int retval = mips32_cp0_write(ejtag_info, value,
1599  cp0_regs->reg,
1600  cp0_regs->sel);
1601  if (retval != ERROR_OK) {
1602  command_print(CMD, "Error: Encounter an Error while writing to cp0 reg %d, sel %d",
1603  cp0_regs->reg, cp0_regs->sel);
1604  return retval;
1605  }
1606 
1607  command_print(CMD, "cp0 reg %s (%u, select %u: %8.8" PRIx32 ")",
1608  CMD_ARGV[0], cp0_regs->reg, cp0_regs->sel, value);
1609  return ERROR_OK;
1610 }
1611 
1623 static int mips32_cp0_set_reg_by_number(struct command_invocation *cmd,
1624  struct mips32_common *mips32, struct mips_ejtag *ejtag_info)
1625 {
1626  uint32_t cp0_reg, cp0_sel, value;
1627  COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], cp0_reg);
1628  COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], cp0_sel);
1629  COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], value);
1630 
1631  if (cp0_reg == MIPS32_C0_STATUS && cp0_sel == 0) {
1632  /* Update cached status register if user is writing to Status register */
1633  mips32->core_regs.cp0[MIPS32_REG_C0_STATUS_INDEX] = value;
1634  mips32->core_cache->reg_list[MIPS32_REGLIST_C0_STATUS_INDEX].dirty = 1;
1635  } else if (cp0_reg == MIPS32_C0_CAUSE && cp0_sel == 0) {
1636  /* Update register cache with new value if its Cause register */
1637  mips32->core_regs.cp0[MIPS32_REG_C0_CAUSE_INDEX] = value;
1638  mips32->core_cache->reg_list[MIPS32_REGLIST_C0_CAUSE_INDEX].dirty = 1;
1639  } else if (cp0_reg == MIPS32_C0_DEPC && cp0_sel == 0) {
1640  /* Update cached PC if its DEPC */
1641  mips32->core_regs.cp0[MIPS32_REG_C0_PC_INDEX] = value;
1642  mips32->core_cache->reg_list[MIPS32_REGLIST_C0_PC_INDEX].dirty = 1;
1643  } else if (cp0_reg == MIPS32_C0_GUESTCTL1 && cp0_sel == 4) {
1644  /* Update cached guestCtl1, too */
1645  mips32->core_regs.cp0[MIPS32_REG_C0_GUESTCTL1_INDEX] = value;
1646  mips32->core_cache->reg_list[MIPS32_REGLIST_C0_GUESTCTL1_INDEX].dirty = 1;
1647  }
1648 
1649  int retval = mips32_cp0_write(ejtag_info, value, cp0_reg, cp0_sel);
1650  if (retval != ERROR_OK) {
1651  command_print(CMD,
1652  "Error: couldn't access cp0 reg %" PRIu32 ", select %" PRIu32,
1653  cp0_reg, cp0_sel);
1654  return retval;
1655  }
1656 
1657  command_print(CMD, "cp0 reg %" PRIu32 ", select %" PRIu32 ": %8.8" PRIx32,
1658  cp0_reg, cp0_sel, value);
1659  return ERROR_OK;
1660 }
1661 
1672 COMMAND_HANDLER(mips32_handle_cp0_command)
1673 {
1674  int retval, tmp;
1675  struct target *target = get_current_target(CMD_CTX);
1676  struct mips32_common *mips32 = target_to_mips32(target);
1677  struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
1678 
1679 
1680  retval = mips32_verify_pointer(CMD, mips32);
1681  if (retval != ERROR_OK)
1682  return retval;
1683 
1684  if (target->state != TARGET_HALTED) {
1685  command_print(CMD, "Error: target must be stopped for \"%s\" command", CMD_NAME);
1686  return ERROR_TARGET_NOT_HALTED;
1687  }
1688 
1689  switch (CMD_ARGC) {
1690  case 0: /* No arg => print out all cp0 regs */
1691  retval = mips32_cp0_get_all_regs(CMD, ejtag_info, mips32->cp0_mask);
1692  break;
1693  case 1: /* 1 arg => get cp0 #reg/#sel value by name */
1694  retval = mips32_cp0_get_reg_by_name(CMD, ejtag_info, mips32->cp0_mask);
1695  break;
1696  case 2: /* 2 args => get cp0 reg/sel value or set value by name */
1697  tmp = *CMD_ARGV[0];
1698  if (isdigit(tmp)) /* starts from number then args are #reg and #sel */
1699  retval = mips32_cp0_get_reg_by_number(CMD, ejtag_info);
1700  else /* or set value by register name */
1701  retval = mips32_cp0_set_reg_by_name(CMD, mips32, ejtag_info);
1702 
1703  break;
1704  case 3: /* 3 args => set cp0 reg/sel value*/
1705  retval = mips32_cp0_set_reg_by_number(CMD, mips32, ejtag_info);
1706  break;
1707  default: /* Other argc => err */
1708  retval = ERROR_COMMAND_SYNTAX_ERROR;
1709  break;
1710  }
1711 
1712  return retval;
1713 }
1714 
1725 static void mips32_dsp_enable(struct pracc_queue_info *ctx, int isa)
1726 {
1727  /* Save Status Register */
1728  /* move status to $9 (t1) 2*/
1729  pracc_add(ctx, 0, MIPS32_MFC0(isa, 9, 12, 0));
1730 
1731  /* Read it again in order to modify it */
1732  /* move status to $0 (t0) 3*/
1733  pracc_add(ctx, 0, MIPS32_MFC0(isa, 8, 12, 0));
1734 
1735  /* Enable access to DSP registers by setting MX bit in status register */
1736  /* $15 = MIPS32_PRACC_STACK 4/5/6*/
1737  pracc_add(ctx, 0, MIPS32_LUI(isa, 15, UPPER16(MIPS32_DSP_ENABLE)));
1738  pracc_add(ctx, 0, MIPS32_ORI(isa, 15, 15, LOWER16(MIPS32_DSP_ENABLE)));
1739  pracc_add(ctx, 0, MIPS32_ISA_OR(8, 8, 15));
1740  /* Enable DSP - update status registers 7*/
1741  pracc_add(ctx, 0, MIPS32_MTC0(isa, 8, 12, 0));
1742 }
1743 
1754 static void mips32_dsp_restore(struct pracc_queue_info *ctx, int isa)
1755 {
1756  pracc_add(ctx, 0, MIPS32_MTC0(isa, 9, 12, 0)); /* Restore status registers to previous setting */
1757  pracc_add(ctx, 0, MIPS32_NOP); /* nop */
1758 }
1759 
1774 static int mips32_pracc_read_dsp_reg(struct mips_ejtag *ejtag_info, uint32_t *val, uint32_t reg)
1775 {
1776  int isa = 0;
1777 
1778  struct pracc_queue_info ctx = {
1779  .max_code = 48,
1780  .ejtag_info = ejtag_info
1781  };
1782 
1783  uint32_t dsp_read_code[] = {
1784  MIPS32_DSP_MFHI(t0, 1), /* mfhi t0,$ac1 - OPCODE - 0x00204010 */
1785  MIPS32_DSP_MFLO(t0, 1), /* mflo t0,$ac1 - OPCODE - 0x00204012 */
1786  MIPS32_DSP_MFHI(t0, 2), /* mfhi t0,$ac2 - OPCODE - 0x00404010 */
1787  MIPS32_DSP_MFLO(t0, 2), /* mflo t0,$ac2 - OPCODE - 0x00404012 */
1788  MIPS32_DSP_MFHI(t0, 3), /* mfhi t0,$ac3 - OPCODE - 0x00604010*/
1789  MIPS32_DSP_MFLO(t0, 3), /* mflo t0,$ac3 - OPCODE - 0x00604012 */
1790  MIPS32_DSP_RDDSP(t0, 0x3F), /* rddsp t0, 0x3f (DSPCtl) - OPCODE - 0x7c3f44b8 */
1791  };
1792 
1793  /* Check status register to determine if dsp register access is enabled */
1794  /* Get status register so it can be restored later */
1795 
1796  ctx.pracc_list = NULL;
1797 
1798  /* Init context queue */
1799  pracc_queue_init(&ctx);
1800 
1801  if (ctx.retval != ERROR_OK)
1802  goto exit;
1803 
1804  /* Enables DSP whether its already enabled or not */
1805  mips32_dsp_enable(&ctx, isa);
1806 
1807  /* move AC or Control to $8 (t0) 8*/
1808  pracc_add(&ctx, 0, dsp_read_code[reg]);
1809  /* Restore status registers to previous setting */
1810  mips32_dsp_restore(&ctx, isa);
1811 
1812  /* $15 = MIPS32_PRACC_BASE_ADDR 1*/
1813  pracc_add(&ctx, 0, MIPS32_LUI(isa, 15, PRACC_UPPER_BASE_ADDR));
1814  /* store $8 to pracc_out 10*/
1815  pracc_add(&ctx, MIPS32_PRACC_PARAM_OUT, MIPS32_SW(isa, 8, PRACC_OUT_OFFSET, 15));
1816  /* move COP0 DeSave to $15 11*/
1817  pracc_add(&ctx, 0, MIPS32_MFC0(isa, 15, 31, 0));
1818  /* restore upper 16 of $8 12*/
1819  pracc_add(&ctx, 0, MIPS32_LUI(isa, 8, UPPER16(ejtag_info->reg8)));
1820  /* restore lower 16 of $8 13*/
1821  pracc_add(&ctx, 0, MIPS32_ORI(isa, 8, 8, LOWER16(ejtag_info->reg8)));
1822  /* restore upper 16 of $9 14*/
1823  pracc_add(&ctx, 0, MIPS32_LUI(isa, 9, UPPER16(ejtag_info->reg9)));
1824  pracc_add(&ctx, 0, MIPS32_SYNC(isa));
1825  /* jump to start 18*/
1826  pracc_add(&ctx, 0, MIPS32_B(isa, NEG16(ctx.code_count + 1)));
1827  /* restore lower 16 of $9 15*/
1828  pracc_add(&ctx, 0, MIPS32_ORI(isa, 9, 9, LOWER16(ejtag_info->reg9)));
1829 
1830  ctx.retval = mips32_pracc_queue_exec(ejtag_info, &ctx, val, 1);
1831 exit:
1832  pracc_queue_free(&ctx);
1833  return ctx.retval;
1834 }
1835 
1849 static int mips32_pracc_write_dsp_reg(struct mips_ejtag *ejtag_info, uint32_t val, uint32_t reg)
1850 {
1851  int isa = 0;
1852 
1853  struct pracc_queue_info ctx = {
1854  .max_code = 48,
1855  .ejtag_info = ejtag_info
1856  };
1857 
1858  uint32_t dsp_write_code[] = {
1859  MIPS32_DSP_MTHI(t0, 1), /* mthi t0, $ac1 - OPCODE - 0x01000811 */
1860  MIPS32_DSP_MTLO(t0, 1), /* mtlo t0, $ac1 - OPCODE - 0x01000813 */
1861  MIPS32_DSP_MTHI(t0, 2), /* mthi t0, $ac2 - OPCODE - 0x01001011 */
1862  MIPS32_DSP_MTLO(t0, 2), /* mtlo t0, $ac2 - OPCODE - 0x01001013 */
1863  MIPS32_DSP_MTHI(t0, 3), /* mthi t0, $ac3 - OPCODE - 0x01001811 */
1864  MIPS32_DSP_MTLO(t0, 3), /* mtlo t0, $ac3 - OPCODE - 0x01001813 */
1865  MIPS32_DSP_WRDSP(t0, 0x1F), /* wrdsp t0, 0x1f (DSPCtl) - OPCODE - 0x7d00fcf8*/
1866  };
1867 
1868  /* Init context queue */
1869  pracc_queue_init(&ctx);
1870  if (ctx.retval != ERROR_OK)
1871  goto exit;
1872 
1873  /* Enables DSP whether its already enabled or not */
1874  mips32_dsp_enable(&ctx, isa);
1875 
1876  /* Load val to $8 (t0) */
1877  pracc_add(&ctx, 0, MIPS32_LUI(isa, 8, UPPER16(val)));
1878  pracc_add(&ctx, 0, MIPS32_ORI(isa, 8, 8, LOWER16(val)));
1879 
1880  /* move AC or Control to $8 (t0) */
1881  pracc_add(&ctx, 0, dsp_write_code[reg]);
1882 
1883  /* nop, delay in order to ensure write */
1884  pracc_add(&ctx, 0, MIPS32_NOP);
1885  /* Restore status registers to previous setting */
1886  mips32_dsp_restore(&ctx, isa);
1887 
1888  /* move COP0 DeSave to $15 */
1889  pracc_add(&ctx, 0, MIPS32_MFC0(isa, 15, 31, 0));
1890 
1891  /* restore $8 */
1892  pracc_add(&ctx, 0, MIPS32_LUI(isa, 8, UPPER16(ejtag_info->reg8)));
1893  pracc_add(&ctx, 0, MIPS32_ORI(isa, 8, 8, LOWER16(ejtag_info->reg8)));
1894 
1895  /* restore upper 16 of $9 */
1896  pracc_add(&ctx, 0, MIPS32_LUI(isa, 9, UPPER16(ejtag_info->reg9)));
1897 
1898  /* jump to start */
1899  pracc_add(&ctx, 0, MIPS32_B(isa, NEG16(ctx.code_count + 1)));
1900  /* restore lower 16 of $9 */
1901  pracc_add(&ctx, 0, MIPS32_ORI(isa, 9, 9, LOWER16(ejtag_info->reg9)));
1902 
1903  ctx.retval = mips32_pracc_queue_exec(ejtag_info, &ctx, NULL, 1);
1904 exit:
1905  pracc_queue_free(&ctx);
1906  return ctx.retval;
1907 }
1908 
1918 COMMAND_HANDLER(mips32_handle_cpuinfo_command)
1919 {
1920  int retval;
1921  struct target *target = get_current_target(CMD_CTX);
1922  struct mips32_common *mips32 = target_to_mips32(target);
1923  struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
1924 
1925  uint32_t prid = mips32->prid; /* cp0 PRID - 15, 0 */
1926  uint32_t config0 = ejtag_info->config[0]; /* cp0 config - 16, 0 */
1927  uint32_t config1 = ejtag_info->config[1]; /* cp0 config - 16, 1 */
1928  uint32_t config3 = ejtag_info->config[3]; /* cp0 config - 16, 3 */
1929 
1930  /* Following configs are not read during probe */
1931  uint32_t config5; /* cp0 config - 16, 5 */
1932 
1933  /* No args for now */
1934  if (CMD_ARGC != 0)
1935  return ERROR_COMMAND_SYNTAX_ERROR;
1936 
1937  if (target->state != TARGET_HALTED) {
1938  command_print(CMD, "target must be stopped for \"%s\" command", CMD_NAME);
1939  return ERROR_TARGET_NOT_HALTED;
1940  }
1941 
1942  retval = mips32_cp0_read(ejtag_info, &config5, 16, 5);
1943  if (retval != ERROR_OK)
1944  return retval;
1945 
1946  /* Determine Core info */
1947  const struct cpu_entry *entry = mips32->cpu_info;
1948  /* Display Core Type info */
1949  command_print(CMD, "CPU Core: %s", entry->cpu_name);
1950 
1951  /* Display Core Vendor ID if it's unknown */
1952  if (entry == &mips32_cpu_entry[MIPS32_NUM_CPU_ENTRIES - 1])
1953  command_print(CMD, "Vendor: Unknown CPU vendor code %x.", ((prid & 0x00ffff00) >> 16));
1954  else
1955  command_print(CMD, "Vendor: %s", entry->vendor);
1956 
1957  /* If MIPS release 2 or above, then get exception base info */
1958  enum mips32_isa_rel ar = mips32->isa_rel;
1959  if (ar > MIPS32_RELEASE_1) { /* release 2 and above */
1960  uint32_t ebase;
1961  retval = mips32_cp0_read(ejtag_info, &ebase, 15, 1);
1962  if (retval != ERROR_OK)
1963  return retval;
1964 
1965  command_print(CMD, "Current CPU ID: %d", (ebase & 0x1ff));
1966  } else {
1967  command_print(CMD, "Current CPU ID: 0");
1968  }
1969 
1970  char *instr;
1971  switch ((config3 & MIPS32_CONFIG3_ISA_MASK) >> MIPS32_CONFIG3_ISA_SHIFT) {
1972  case 0:
1973  instr = "MIPS32";
1974  break;
1975  case 1:
1976  instr = "microMIPS";
1977  break;
1978  case 2:
1979  instr = "MIPS32 (at reset) and microMIPS";
1980  break;
1981  case 3:
1982  default:
1983  instr = "microMIPS (at reset) and MIPS32";
1984  break;
1985  }
1986 
1987  /* Display Instruction Set Info */
1988  command_print(CMD, "Instr set: %s", instr);
1989  command_print(CMD, "Instr rel: %s",
1990  ar == MIPS32_RELEASE_1 ? "1"
1991  : ar == MIPS32_RELEASE_2 ? "2"
1992  : ar == MIPS32_RELEASE_6 ? "6"
1993  : "unknown");
1994  command_print(CMD, "PRId: %x", prid);
1995  /* Some of MIPS CPU Revisions(for M74K) can be seen on MD00541, page 26 */
1996  uint32_t rev = prid & 0x000000ff;
1997  command_print(CMD, "RTL Rev: %d.%d.%d", (rev & 0xE0), (rev & 0x1C), (rev & 0x3));
1998 
1999  command_print(CMD, "Max Number of Instr Breakpoints: %d", mips32->num_inst_bpoints);
2000  command_print(CMD, "Max Number of Data Breakpoints: %d", mips32->num_data_bpoints);
2001 
2002  /* MMU Support */
2003  uint32_t mmu_type = (config0 >> 7) & 7; /* MMU Type Info */
2004  char *mmu;
2005  switch (mmu_type) {
2006  case MIPS32_MMU_TLB:
2007  mmu = "TLB";
2008  break;
2009  case MIPS32_MMU_BAT:
2010  mmu = "BAT";
2011  break;
2012  case MIPS32_MMU_FIXED:
2013  mmu = "FIXED";
2014  break;
2015  case MIPS32_MMU_DUAL_VTLB_FTLB:
2016  mmu = "DUAL VAR/FIXED";
2017  break;
2018  default:
2019  mmu = "Unknown";
2020  }
2021  command_print(CMD, "MMU Type: %s", mmu);
2022 
2023  retval = mips32_read_config_mmu(ejtag_info);
2024  if (retval != ERROR_OK)
2025  return retval;
2026 
2027  /* Definitions of I/D Cache Sizes are available on MD01251, page 224~226 */
2028  int index;
2029  uint32_t ways, sets, bpl;
2030 
2031  /* Determine Instr Cache Size */
2032  /* Ways mapping = [1, 2, 3, 4, 5, 6, 7, 8] */
2033  ways = ((config1 >> MIPS32_CFG1_IASHIFT) & 7);
2034 
2035  /* Sets per way = [64, 128, 256, 512, 1024, 2048, 4096, 32] */
2036  index = ((config1 >> MIPS32_CFG1_ISSHIFT) & 7);
2037  sets = index == 7 ? 32 : 32 << (index + 1);
2038 
2039  /* Bytes per line = [0, 4, 8, 16, 32, 64, 128, Reserved] */
2040  index = ((config1 >> MIPS32_CFG1_ILSHIFT) & 7);
2041  bpl = index == 0 ? 0 : 4 << (index - 1);
2042  command_print(CMD, "Instr Cache: %d (%d ways, %d lines, %d byte per line)", ways * sets * bpl, ways, sets, bpl);
2043 
2044  /* Determine data cache size, same as above */
2045  ways = ((config1 >> MIPS32_CFG1_DASHIFT) & 7);
2046 
2047  index = ((config1 >> MIPS32_CFG1_DSSHIFT) & 7);
2048  sets = index == 7 ? 32 : 32 << (index + 1);
2049 
2050  index = ((config1 >> MIPS32_CFG1_DLSHIFT) & 7);
2051  bpl = index == 0 ? 0 : 4 << (index - 1);
2052  command_print(CMD, " Data Cache: %d (%d ways, %d lines, %d byte per line)", ways * sets * bpl, ways, sets, bpl);
2053 
2054  /* does the core hava FPU*/
2055  mips32_read_config_fpu(mips32, ejtag_info);
2056 
2057  /* does the core support a DSP */
2058  mips32_read_config_dsp(mips32, ejtag_info);
2059 
2060  /* VZ module */
2061  uint32_t vzase = (config3 & BIT(23));
2062  if (vzase)
2063  command_print(CMD, "VZ implemented: yes");
2064  else
2065  command_print(CMD, "VZ implemented: no");
2066 
2067  /* multithreading */
2068  uint32_t mtase = (config3 & BIT(2));
2069  if (mtase) {
2070  command_print(CMD, "MT implemented: yes");
2071 
2072  /* Get VPE and Thread info */
2073  uint32_t tcbind;
2074  uint32_t mvpconf0;
2075 
2076  /* Read tcbind register */
2077  retval = mips32_cp0_read(ejtag_info, &tcbind, 2, 2);
2078  if (retval != ERROR_OK)
2079  return retval;
2080 
2081  command_print(CMD, " | Current VPE: %d", (tcbind & 0xf));
2082  command_print(CMD, " | Current TC: %d", ((tcbind >> 21) & 0xff));
2083 
2084  /* Read mvpconf0 register */
2085  retval = mips32_cp0_read(ejtag_info, &mvpconf0, 0, 2);
2086  if (retval != ERROR_OK)
2087  return retval;
2088 
2089  command_print(CMD, " | Total TC: %d", (mvpconf0 & 0xf) + 1);
2090  command_print(CMD, " | Total VPE: %d", ((mvpconf0 >> 10) & 0xf) + 1);
2091  } else {
2092  command_print(CMD, "MT implemented: no");
2093  }
2094 
2095  /* MIPS SIMD Architecture (MSA) */
2096  uint32_t msa = (config3 & BIT(28));
2097  command_print(CMD, "MSA implemented: %s", msa ? "yes" : "no");
2098 
2099  /* Move To/From High COP0 (MTHC0/MFHC0) instructions are implemented.
2100  * Implicates current ISA release >= 5.*/
2101  uint32_t mvh = (config5 & BIT(5));
2102  command_print(CMD, "MVH implemented: %s", mvh ? "yes" : "no");
2103 
2104  /* Common Device Memory Map implemented? */
2105  uint32_t cdmm = (config3 & BIT(3));
2106  command_print(CMD, "CDMM implemented: %s", cdmm ? "yes" : "no");
2107 
2108  return ERROR_OK;
2109 }
2110 
2120 static int mips32_dsp_find_register_by_name(const char *reg_name)
2121 {
2122  if (reg_name)
2123  for (int i = 0; i < MIPS32NUMDSPREGS; i++) {
2124  if (strcmp(mips32_dsp_regs[i].name, reg_name) == 0)
2125  return i;
2126  }
2127  return MIPS32NUMDSPREGS;
2128 }
2129 
2140 static int mips32_dsp_get_all_regs(struct command_invocation *cmd, struct mips32_common *mips32)
2141 {
2142  uint32_t value = 0;
2143  struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
2144  for (int i = 0; i < MIPS32NUMDSPREGS; i++) {
2145  int retval = mips32_pracc_read_dsp_reg(ejtag_info, &value, i);
2146  if (retval != ERROR_OK) {
2147  command_print(CMD, "couldn't access reg %s", mips32_dsp_regs[i].name);
2148  return retval;
2149  }
2150  mips32->core_regs.dsp[i] = value;
2151  mips32->core_cache->reg_list[MIPS32_REGLIST_DSP_INDEX + i].dirty = 1;
2152  command_print(CMD, "%*s: 0x%8.8x", 7, mips32_dsp_regs[i].name, value);
2153  }
2154  return ERROR_OK;
2155 }
2156 
2168 static int mips32_dsp_get_register(struct command_invocation *cmd, struct mips32_common *mips32)
2169 {
2170  uint32_t value = 0;
2171  int index = mips32_dsp_find_register_by_name(CMD_ARGV[0]);
2172  struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
2173  if (index == MIPS32NUMDSPREGS) {
2174  command_print(CMD, "ERROR: register '%s' not found", CMD_ARGV[0]);
2175  return ERROR_COMMAND_SYNTAX_ERROR;
2176  }
2177 
2178  int retval = mips32_pracc_read_dsp_reg(ejtag_info, &value, index);
2179  if (retval != ERROR_OK) {
2180  command_print(CMD, "ERROR: Could not access dsp register %s", CMD_ARGV[0]);
2181  return retval;
2182  }
2183 
2184  command_print(CMD, "0x%8.8x", value);
2185 
2186  if (mips32->core_regs.dsp[index] != value) {
2187  mips32->core_regs.dsp[index] = value;
2188  mips32->core_cache->reg_list[MIPS32_REGLIST_DSP_INDEX + index].dirty = 1;
2189  }
2190 
2191  return retval;
2192 }
2193 
2206 static int mips32_dsp_set_register(struct command_invocation *cmd, struct mips32_common *mips32)
2207 {
2208  uint32_t value;
2209  struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
2210  int index = mips32_dsp_find_register_by_name(CMD_ARGV[0]);
2211  if (index == MIPS32NUMDSPREGS) {
2212  command_print(CMD, "ERROR: register '%s' not found", CMD_ARGV[0]);
2213  return ERROR_COMMAND_SYNTAX_ERROR;
2214  }
2215 
2216  COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], value);
2217 
2218  int retval = mips32_pracc_write_dsp_reg(ejtag_info, value, index);
2219  if (retval != ERROR_OK) {
2220  command_print(CMD, "Error: could not write to dsp register %s", CMD_ARGV[0]);
2221  return retval;
2222  }
2223 
2224  mips32->core_regs.dsp[index] = value;
2225  mips32->core_cache->reg_list[MIPS32_REGLIST_DSP_INDEX + index].dirty = 1;
2226 
2227  return retval;
2228 }
2229 
2238 COMMAND_HANDLER(mips32_handle_dsp_command)
2239 {
2240  int retval, tmp;
2241  struct target *target = get_current_target(CMD_CTX);
2242  struct mips32_common *mips32 = target_to_mips32(target);
2243 
2244  retval = mips32_verify_pointer(CMD, mips32);
2245  if (retval != ERROR_OK)
2246  return retval;
2247 
2248  if (target->state != TARGET_HALTED) {
2249  command_print(CMD, "target must be stopped for \"%s\" command", CMD_NAME);
2250  return ERROR_OK;
2251  }
2252 
2253  /* Check for too many command args */
2254  if (CMD_ARGC >= 3)
2255  return ERROR_COMMAND_SYNTAX_ERROR;
2256 
2257  /* Check if DSP access supported or not */
2258  if (!mips32->dsp_imp) {
2259  /* Issue Error Message */
2260  command_print(CMD, "DSP not implemented by this processor");
2261  return ERROR_OK;
2262  }
2263 
2264  switch (CMD_ARGC) {
2265  case 0:
2266  retval = mips32_dsp_get_all_regs(CMD, mips32);
2267  break;
2268  case 1:
2269  retval = mips32_dsp_get_register(CMD, mips32);
2270  break;
2271  case 2:
2272  tmp = *CMD_ARGV[0];
2273  if (isdigit(tmp)) {
2274  command_print(CMD, "Error: invalid dsp command format");
2275  retval = ERROR_COMMAND_ARGUMENT_INVALID;
2276  } else {
2277  retval = mips32_dsp_set_register(CMD, mips32);
2278  }
2279  break;
2280  default:
2281  command_print(CMD, "Error: invalid argument format, required 0-2, given %d", CMD_ARGC);
2282  retval = ERROR_COMMAND_ARGUMENT_INVALID;
2283  break;
2284  }
2285  return retval;
2286 }
2287 
2296 COMMAND_HANDLER(mips32_handle_ejtag_reg_command)
2297 {
2298  struct target *target = get_current_target(CMD_CTX);
2299  struct mips32_common *mips32 = target_to_mips32(target);
2300  struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
2301 
2302  uint32_t ejtag_ctrl;
2303  uint32_t dcr;
2304  int retval;
2305 
2306  retval = mips_ejtag_get_idcode(ejtag_info);
2307  if (retval != ERROR_OK)
2308  command_print(CMD, "Error: Encounter an Error while getting idcode");
2309  else
2310  command_print(CMD, " idcode: 0x%8.8" PRIx32, ejtag_info->idcode);
2311 
2312  retval = mips_ejtag_get_impcode(ejtag_info);
2313  if (retval != ERROR_OK)
2314  command_print(CMD, "Error: Encounter an Error while getting impcode");
2315  else
2316  command_print(CMD, " impcode: 0x%8.8" PRIx32, ejtag_info->impcode);
2317 
2318  mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
2319  ejtag_ctrl = ejtag_info->ejtag_ctrl;
2320  retval = mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
2321  if (retval != ERROR_OK)
2322  command_print(CMD, "Error: Encounter an Error while executing drscan reading EJTAG Control register");
2323  else
2324  command_print(CMD, "ejtag control: 0x%8.8" PRIx32, ejtag_ctrl);
2325 
2326  ejtag_main_print_imp(ejtag_info);
2327 
2328  /* Display current DCR */
2329  retval = target_read_u32(target, EJTAG_DCR, &dcr);
2330  if (retval != ERROR_OK)
2331  command_print(CMD, "Error: Encounter an Error while reading Debug Control Register");
2332  else
2333  command_print(CMD, " DCR: 0x%8.8" PRIx32, dcr);
2334 
2335  for (unsigned int i = 0; i < EJTAG_DCR_ENTRIES; i++) {
2336  if (dcr & BIT(dcr_features[i].bit))
2337  command_print(CMD, "%s supported", dcr_features[i].name);
2338  }
2339 
2340  return ERROR_OK;
2341 }
2342 
2351 COMMAND_HANDLER(mips32_handle_scan_delay_command)
2352 {
2353  struct target *target = get_current_target(CMD_CTX);
2354  struct mips32_common *mips32 = target_to_mips32(target);
2355  struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
2356 
2357  if (CMD_ARGC == 1)
2358  COMMAND_PARSE_NUMBER(uint, CMD_ARGV[0], ejtag_info->scan_delay);
2359  else if (CMD_ARGC > 1)
2360  return ERROR_COMMAND_SYNTAX_ERROR;
2361 
2362  command_print(CMD, "scan delay: %d nsec", ejtag_info->scan_delay);
2363  if (ejtag_info->scan_delay >= MIPS32_SCAN_DELAY_LEGACY_MODE) {
2364  ejtag_info->mode = 0;
2365  command_print(CMD, "running in legacy mode");
2366  } else {
2367  ejtag_info->mode = 1;
2368  command_print(CMD, "running in fast queued mode");
2369  }
2370 
2371  return ERROR_OK;
2372 }
2373 
2374 static const struct command_registration mips32_exec_command_handlers[] = {
2375  {
2376  .name = "cp0",
2377  .handler = mips32_handle_cp0_command,
2378  .mode = COMMAND_EXEC,
2379  .usage = "[[reg_name|regnum select] [value]]",
2380  .help = "display/modify cp0 register",
2381  },
2382  {
2383  .name = "cpuinfo",
2384  .handler = mips32_handle_cpuinfo_command,
2385  .mode = COMMAND_EXEC,
2386  .help = "display CPU information",
2387  .usage = "",
2388  },
2389  {
2390  .name = "dsp",
2391  .handler = mips32_handle_dsp_command,
2392  .mode = COMMAND_EXEC,
2393  .help = "display or set DSP register; "
2394  "with no arguments, displays all registers and their values",
2395  .usage = "[[register_name] [value]]",
2396  },
2397  {
2398  .name = "scan_delay",
2399  .handler = mips32_handle_scan_delay_command,
2400  .mode = COMMAND_ANY,
2401  .help = "display/set scan delay in nano seconds",
2402  .usage = "[value]",
2403  },
2404  {
2405  .name = "ejtag_reg",
2406  .handler = mips32_handle_ejtag_reg_command,
2407  .mode = COMMAND_ANY,
2408  .help = "read ejtag registers",
2409  .usage = "",
2410  },
2411  COMMAND_REGISTRATION_DONE
2412 };
2413 
2414 const struct command_registration mips32_command_handlers[] = {
2415  {
2416  .name = "mips32",
2417  .mode = COMMAND_ANY,
2418  .help = "mips32 command group",
2419  .usage = "",
2420  .chain = mips32_exec_command_handlers,
2421  },
2422  COMMAND_REGISTRATION_DONE
2423 };
init_reg_param
void init_reg_param(struct reg_param *param, char *reg_name, uint32_t size, enum param_direction direction)
Definition: algorithm.c:29
destroy_reg_param
void destroy_reg_param(struct reg_param *param)
Definition: algorithm.c:37
PARAM_OUT
@ PARAM_OUT
Definition: algorithm.h:16
PARAM_IN
@ PARAM_IN
Definition: algorithm.h:15
PARAM_IN_OUT
@ PARAM_IN_OUT
Definition: algorithm.h:17
buf_get_u32
static uint32_t buf_get_u32(const uint8_t *_buffer, unsigned int first, unsigned int num)
Retrieves num bits from _buffer, starting at the first bit, returning the bits in a 32-bit word.
Definition: binarybuffer.h:104
buf_set_u32
static void buf_set_u32(uint8_t *_buffer, unsigned int first, unsigned int num, uint32_t value)
Sets num bits in _buffer, starting at the first bit, using the bits in value.
Definition: binarybuffer.h:34
buf_get_u64
static uint64_t buf_get_u64(const uint8_t *_buffer, unsigned int first, unsigned int num)
Retrieves num bits from _buffer, starting at the first bit, returning the bits in a 64-bit word.
Definition: binarybuffer.h:134
buf_set_u64
static void buf_set_u64(uint8_t *_buffer, unsigned int first, unsigned int num, uint64_t value)
Sets num bits in _buffer, starting at the first bit, using the bits in value.
Definition: binarybuffer.h:65
command_print
void command_print(struct command_invocation *cmd, const char *format,...)
Definition: command.c:443
CMD
#define CMD
Use this macro to access the command being handled, rather than accessing the variable directly.
Definition: command.h:141
CMD_NAME
#define CMD_NAME
Use this macro to access the name of the command being handled, rather than accessing the variable di...
Definition: command.h:166
CMD_ARGV
#define CMD_ARGV
Use this macro to access the arguments for the command being handled, rather than accessing the varia...
Definition: command.h:156
ERROR_COMMAND_SYNTAX_ERROR
#define ERROR_COMMAND_SYNTAX_ERROR
Definition: command.h:402
CMD_ARGC
#define CMD_ARGC
Use this macro to access the number of arguments for the command being handled, rather than accessing...
Definition: command.h:151
COMMAND_PARSE_NUMBER
#define COMMAND_PARSE_NUMBER(type, in, out)
parses the string in into out as a type, or prints a command error and passes the error code to the c...
Definition: command.h:442
CMD_CTX
#define CMD_CTX
Use this macro to access the context of the command being handled, rather than accessing the variable...
Definition: command.h:146
COMMAND_REGISTRATION_DONE
#define COMMAND_REGISTRATION_DONE
Use this as the last entry in an array of command_registration records.
Definition: command.h:253
ERROR_COMMAND_ARGUMENT_INVALID
#define ERROR_COMMAND_ARGUMENT_INVALID
Definition: command.h:404
COMMAND_ANY
@ COMMAND_ANY
Definition: command.h:42
COMMAND_EXEC
@ COMMAND_EXEC
Definition: command.h:40
direction
static uint16_t direction
Definition: ftdi.c:120
LOG_USER
#define LOG_USER(expr ...)
Definition: log.h:135
LOG_WARNING
#define LOG_WARNING(expr ...)
Definition: log.h:129
ERROR_FAIL
#define ERROR_FAIL
Definition: log.h:170
LOG_TARGET_ERROR
#define LOG_TARGET_ERROR(target, fmt_str,...)
Definition: log.h:158
LOG_ERROR
#define LOG_ERROR(expr ...)
Definition: log.h:132
LOG_DEBUG
#define LOG_DEBUG(expr ...)
Definition: log.h:109
ERROR_OK
#define ERROR_OK
Definition: log.h:164
mips32_build_reg_cache
struct reg_cache * mips32_build_reg_cache(struct target *target)
Definition: mips32.c:501
mips32_cpu_support_sync
bool mips32_cpu_support_sync(struct mips_ejtag *ejtag_info)
mips32_cpu_support_sync - Checks CPU supports ordering
Definition: mips32.c:963
mips32_read_config_mmu
static int mips32_read_config_mmu(struct mips_ejtag *ejtag_info)
mips32_read_config_mmu - Reads MMU configuration and logs relevant information.
Definition: mips32.c:1405
mips32_command_handlers
const struct command_registration mips32_command_handlers[]
Definition: mips32.c:2414
mips32_read_config_regs
int mips32_read_config_regs(struct target *target)
Definition: mips32.c:1155
mips32_checksum_memory
int mips32_checksum_memory(struct target *target, target_addr_t address, uint32_t count, uint32_t *checksum)
Definition: mips32.c:1229
mips32_set_core_reg
static int mips32_set_core_reg(struct reg *reg, uint8_t *buf)
Definition: mips32.c:254
mips32_read_config_dsp
static void mips32_read_config_dsp(struct mips32_common *mips32, struct mips_ejtag *ejtag_info)
Definition: mips32.c:1051
mips32_pracc_read_dsp_reg
static int mips32_pracc_read_dsp_reg(struct mips_ejtag *ejtag_info, uint32_t *val, uint32_t reg)
mips32_pracc_read_dsp_reg - Read a value from a MIPS32 DSP register
Definition: mips32.c:1774
t0
#define t0
Definition: mips32.c:192
mips32_dsp_regs
static const struct @112 mips32_dsp_regs[MIPS32NUMDSPREGS]
mips32_regs
static const struct @111 mips32_regs[]
mips32_dsp_restore
static void mips32_dsp_restore(struct pracc_queue_info *ctx, int isa)
mips32_dsp_restore - Restore DSP status registers to the previous setting
Definition: mips32.c:1754
mips32_cp0_get_reg_by_number
static int mips32_cp0_get_reg_by_number(struct command_invocation *cmd, struct mips_ejtag *ejtag_info)
mips32_cp0_get_reg_by_number - Read and print a CP0 register's value by number.
Definition: mips32.c:1537
size
int size
Definition: mips32.c:42
mips32_cp0_get_all_regs
static int mips32_cp0_get_all_regs(struct command_invocation *cmd, struct mips_ejtag *ejtag_info, uint32_t cp0_mask)
mips32_cp0_get_all_regs - Print all CP0 registers and their values.
Definition: mips32.c:1476
mips32_dsp_get_register
static int mips32_dsp_get_register(struct command_invocation *cmd, struct mips32_common *mips32)
mips32_dsp_get_register - Get the value of a MIPS32 DSP register
Definition: mips32.c:2168
mips32_configure_break_unit
int mips32_configure_break_unit(struct target *target)
Definition: mips32.c:804
mips32_get_core_reg
static int mips32_get_core_reg(struct reg *reg)
Definition: mips32.c:239
mips32_arch_state
int mips32_arch_state(struct target *target)
Definition: mips32.c:484
COMMAND_HANDLER
COMMAND_HANDLER(mips32_handle_cp0_command)
mips32_handle_cp0_command - Handle commands related to CP0 registers.
Definition: mips32.c:1672
group
const char * group
Definition: mips32.c:40
mips32_cp0_set_reg_by_number
static int mips32_cp0_set_reg_by_number(struct command_invocation *cmd, struct mips32_common *mips32, struct mips_ejtag *ejtag_info)
mips32_cp0_set_reg_by_number - Write to a CP0 register identified by number.
Definition: mips32.c:1623
mips32_cpu_probe
int mips32_cpu_probe(struct target *target)
mips32_cpu_probe - Detects processor type and applies necessary quirks.
Definition: mips32.c:995
mips32_run_algorithm
int mips32_run_algorithm(struct target *target, int num_mem_params, struct mem_param *mem_params, int num_reg_params, struct reg_param *reg_params, target_addr_t entry_point, target_addr_t exit_point, unsigned int timeout_ms, void *arch_info)
Definition: mips32.c:616
MIPS32_NUM_REGS
#define MIPS32_NUM_REGS
Definition: mips32.c:177
mips32_read_config_fpu
static int mips32_read_config_fpu(struct mips32_common *mips32, struct mips_ejtag *ejtag_info)
Definition: mips32.c:1073
MIPS32_GDB_FP_REG
#define MIPS32_GDB_FP_REG
Definition: mips32.c:30
mips32_dsp_get_all_regs
static int mips32_dsp_get_all_regs(struct command_invocation *cmd, struct mips32_common *mips32)
mips32_dsp_get_all_regs - Get values of all MIPS32 DSP registers
Definition: mips32.c:2140
mips32_configure_ibs
static int mips32_configure_ibs(struct target *target)
Definition: mips32.c:750
mips32_examine
int mips32_examine(struct target *target)
Definition: mips32.c:732
mips32_read_config_fdc
static void mips32_read_config_fdc(struct mips32_common *mips32, struct mips_ejtag *ejtag_info, uint32_t dcr)
mips32_read_config_fdc - Read Fast Debug Channel configuration
Definition: mips32.c:1143
mips32_init_arch_info
int mips32_init_arch_info(struct target *target, struct mips32_common *mips32, struct jtag_tap *tap)
Definition: mips32.c:560
mips32_reg_type
static const struct reg_arch_type mips32_reg_type
Definition: mips32.c:496
mips32_configure_dbs
static int mips32_configure_dbs(struct target *target)
Definition: mips32.c:777
name
const char * name
Definition: mips32.c:38
mips32_cpu_support_hazard_barrier
bool mips32_cpu_support_hazard_barrier(struct mips_ejtag *ejtag_info)
mips32_cpu_support_hazard_barrier - Checks CPU supports hazard barrier
Definition: mips32.c:976
mips32_pracc_write_dsp_reg
static int mips32_pracc_write_dsp_reg(struct mips_ejtag *ejtag_info, uint32_t val, uint32_t reg)
mips32_pracc_write_dsp_reg - Write a value to a MIPS32 DSP register
Definition: mips32.c:1849
mips32_read_c0_prid
static int mips32_read_c0_prid(struct target *target)
Definition: mips32.c:895
mips32_dsp_enable
static void mips32_dsp_enable(struct pracc_queue_info *ctx, int isa)
mips32_dsp_enable - Enable access to DSP registers
Definition: mips32.c:1725
mips32_cp0_find_register_by_name
static const struct mips32_cp0 * mips32_cp0_find_register_by_name(uint32_t cp0_mask, const char *reg_name)
mips32_cp0_find_register_by_name - Find CP0 register by its name.
Definition: mips32.c:1452
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static int mips32_write_core_reg(struct target *target, unsigned int num)
Definition: mips32.c:382
mips32_set_all_fpr_width
static void mips32_set_all_fpr_width(struct mips32_common *mips32, bool fp64)
mips32_set_all_fpr_width - Set the width of all floating-point registers
Definition: mips32.c:286
type
enum reg_type type
Definition: mips32.c:39
mips32_read_core_reg
static int mips32_read_core_reg(struct target *target, unsigned int num)
Definition: mips32.c:334
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static int mips32_run_and_wait(struct target *target, target_addr_t entry_point, unsigned int timeout_ms, target_addr_t exit_point, struct mips32_common *mips32)
Definition: mips32.c:584
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int mips32_save_context(struct target *target)
Definition: mips32.c:446
id
unsigned int id
Definition: mips32.c:37
mips32_dsp_set_register
static int mips32_dsp_set_register(struct command_invocation *cmd, struct mips32_common *mips32)
mips32_dsp_set_register - Set the value of a MIPS32 DSP register
Definition: mips32.c:2206
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int mips32_enable_interrupts(struct target *target, int enable)
Definition: mips32.c:860
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static const char * mips_isa_strings[]
Definition: mips32.c:26
mips32_find_cpu_by_prid
static const struct cpu_entry * mips32_find_cpu_by_prid(uint32_t prid)
mips32_find_cpu_by_prid - Find CPU information by processor ID.
Definition: mips32.c:920
mips32_detect_fpr_mode_change
static void mips32_detect_fpr_mode_change(struct mips32_common *mips32, uint32_t cp0_status)
mips32_detect_fpr_mode_change - Detect changes in floating-point register mode
Definition: mips32.c:307
mips32_blank_check_memory
int mips32_blank_check_memory(struct target *target, struct target_memory_check_block *blocks, int num_blocks, uint8_t erased_value)
Checks whether a memory region is erased.
Definition: mips32.c:1312
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static int mips32_cp0_set_reg_by_name(struct command_invocation *cmd, struct mips32_common *mips32, struct mips_ejtag *ejtag_info)
mips32_cp0_set_reg_by_name - Write to a CP0 register identified by name.
Definition: mips32.c:1567
mips32_dsp_find_register_by_name
static int mips32_dsp_find_register_by_name(const char *reg_name)
mips32_dsp_find_register_by_name - Find DSP register index by name
Definition: mips32.c:2120
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static bool mips32_cpu_is_lexra(struct mips_ejtag *ejtag_info)
Definition: mips32.c:943
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int mips32_restore_context(struct target *target)
Definition: mips32.c:468
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static int mips32_verify_pointer(struct command_invocation *cmd, struct mips32_common *mips32)
Definition: mips32.c:1386
mips32_cp0_get_reg_by_name
static int mips32_cp0_get_reg_by_name(struct command_invocation *cmd, struct mips_ejtag *ejtag_info, uint32_t cp0_mask)
mips32_cp0_get_reg_by_name - Read and print a CP0 register's value by name.
Definition: mips32.c:1507
mips32_get_gdb_reg_list
int mips32_get_gdb_reg_list(struct target *target, struct reg **reg_list[], int *reg_list_size, enum target_register_class reg_class)
Definition: mips32.c:429
feature
const char * feature
Definition: mips32.c:41
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static int mips32_cpu_get_release(struct mips_ejtag *ejtag_info)
Definition: mips32.c:948
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static const struct command_registration mips32_exec_command_handlers[]
Definition: mips32.c:2374
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#define MIPS32_CONFIG3_DSPP_MASK
Definition: mips32.h:59
MIPS32_CONFIG3_DSPREV_SHIFT
#define MIPS32_CONFIG3_DSPREV_SHIFT
Definition: mips32.h:61
MIPS32_CONFIG3_DSPP_SHIFT
#define MIPS32_CONFIG3_DSPP_SHIFT
Definition: mips32.h:58
MIPS32_NOP
#define MIPS32_NOP
Definition: mips32.h:719
MIPS32_C0_CAUSE
#define MIPS32_C0_CAUSE
Definition: mips32.h:860
MIPS32_SCAN_DELAY_LEGACY_MODE
#define MIPS32_SCAN_DELAY_LEGACY_MODE
Definition: mips32.h:70
MIPS32_REGLIST_DSP_DSPCTL_INDEX
#define MIPS32_REGLIST_DSP_DSPCTL_INDEX
Definition: mips32.h:245
MIPS32_CORE_MASK
#define MIPS32_CORE_MASK
Definition: mips32.h:282
MIPS32_ISA_OR
#define MIPS32_ISA_OR(dst, src, val)
Definition: mips32.h:561
MIPS32_CONFIG3_DSPREV_MASK
#define MIPS32_CONFIG3_DSPREV_MASK
Definition: mips32.h:62
MIPS32_REGLIST_FP_INDEX
#define MIPS32_REGLIST_FP_INDEX
Definition: mips32.h:228
MIPS32_CONFIG3_CDMM_MASK
#define MIPS32_CONFIG3_CDMM_MASK
Definition: mips32.h:56
MIPS32_ADDI
#define MIPS32_ADDI(isa, tar, src, val)
Definition: mips32.h:720
MIPS32_SYNC
#define MIPS32_SYNC(isa)
Definition: mips32.h:772
MIPS32_REG_C0_PC_INDEX
#define MIPS32_REG_C0_PC_INDEX
Definition: mips32.h:242
MIPS32_CONFIG3_ISA_MASK
#define MIPS32_CONFIG3_ISA_MASK
Definition: mips32.h:65
MIPS32_REGLIST_C0_STATUS_INDEX
#define MIPS32_REGLIST_C0_STATUS_INDEX
Definition: mips32.h:233
MIPS32_DSP_MTLO
#define MIPS32_DSP_MTLO(reg, ac)
Definition: mips32.h:799
target_to_mips32
static struct mips32_common * target_to_mips32(struct target *target)
Definition: mips32.h:444
MIPS32_XOR
#define MIPS32_XOR(isa, reg, val1, val2)
Definition: mips32.h:773
EJTAG_QUIRK_PAD_DRET
#define EJTAG_QUIRK_PAD_DRET
Definition: mips32.h:209
MIPS32_DSP_ENABLE
#define MIPS32_DSP_ENABLE
Definition: mips32.h:787
MIPS32_COMMON_MAGIC
#define MIPS32_COMMON_MAGIC
Definition: mips32.h:21
MIPS32_NUM_CPU_ENTRIES
#define MIPS32_NUM_CPU_ENTRIES
Definition: mips32.h:362
MIPS32_CFG1_ILSHIFT
#define MIPS32_CFG1_ILSHIFT
Definition: mips32.h:814
MIPS32_SDBBP
#define MIPS32_SDBBP(isa)
Definition: mips32.h:780
MIPS_CP0_MK4
#define MIPS_CP0_MK4
Definition: mips32.h:75
MIPS32_FP_IMP_64
@ MIPS32_FP_IMP_64
Definition: mips32.h:367
MIPS32_FP_IMP_NONE
@ MIPS32_FP_IMP_NONE
Definition: mips32.h:365
MIPS32_FP_IMP_UNKNOWN
@ MIPS32_FP_IMP_UNKNOWN
Definition: mips32.h:368
MIPS32_CFG1_DASHIFT
#define MIPS32_CFG1_DASHIFT
Definition: mips32.h:822
MIPS32_LB
#define MIPS32_LB(isa, reg, off, base)
Definition: mips32.h:736
MIPS32_CP0_STATUS_CU1_SHIFT
#define MIPS32_CP0_STATUS_CU1_SHIFT
Definition: mips32.h:83
MIPS32_REG_C0_GUESTCTL1_INDEX
#define MIPS32_REG_C0_GUESTCTL1_INDEX
Definition: mips32.h:243
MIPS32_REGLIST_C0_CAUSE_INDEX
#define MIPS32_REGLIST_C0_CAUSE_INDEX
Definition: mips32.h:235
MIPS32_CONFIG0_AR_SHIFT
#define MIPS32_CONFIG0_AR_SHIFT
Definition: mips32.h:46
MIPS32_CONFIG1_FP_SHIFT
#define MIPS32_CONFIG1_FP_SHIFT
Definition: mips32.h:49
MIPS32_BNE
#define MIPS32_BNE(isa, src, tar, off)
Definition: mips32.h:729
MIPS32_REG_C0_CAUSE_INDEX
#define MIPS32_REG_C0_CAUSE_INDEX
Definition: mips32.h:241
MIPS32_REG_FP_COUNT
#define MIPS32_REG_FP_COUNT
Definition: mips32.h:222
MIPS_CP0_IAPTIV
#define MIPS_CP0_IAPTIV
Definition: mips32.h:78
MIPS32_BEQ
#define MIPS32_BEQ(isa, src, tar, off)
Definition: mips32.h:727
MIPS32_CP1_FIR_F64_SHIFT
#define MIPS32_CP1_FIR_F64_SHIFT
Definition: mips32.h:86
MIPS32_C0_DEPC
#define MIPS32_C0_DEPC
Definition: mips32.h:874
MIPS_CP0_MAPTIV_UP
#define MIPS_CP0_MAPTIV_UP
Definition: mips32.h:77
MIPS32_REGLIST_DSP_INDEX
#define MIPS32_REGLIST_DSP_INDEX
Definition: mips32.h:231
MIPS32_REGLIST_C0_GUESTCTL1_INDEX
#define MIPS32_REGLIST_C0_GUESTCTL1_INDEX
Definition: mips32.h:237
MIPS32_CONFIG3_ISA_SHIFT
#define MIPS32_CONFIG3_ISA_SHIFT
Definition: mips32.h:64
MIPS32_SW
#define MIPS32_SW(isa, reg, off, base)
Definition: mips32.h:760
MIPS32_MOVN
#define MIPS32_MOVN(isa, dst, src, tar)
Definition: mips32.h:755
MIPS32_REGLIST_C0_PC_INDEX
#define MIPS32_REGLIST_C0_PC_INDEX
Definition: mips32.h:236
MIPS32_C0_STATUS
#define MIPS32_C0_STATUS
Definition: mips32.h:855
MIPS32_REGLIST_FPC_INDEX
#define MIPS32_REGLIST_FPC_INDEX
Definition: mips32.h:229
MIPS32NUMDSPREGS
#define MIPS32NUMDSPREGS
Definition: mips32.h:72
MIPS32_MMU_TLB
#define MIPS32_MMU_TLB
Definition: mips32.h:895
MIPS32_CFG1_ISSHIFT
#define MIPS32_CFG1_ISSHIFT
Definition: mips32.h:812
MIPS32_REGLIST_GP_INDEX
#define MIPS32_REGLIST_GP_INDEX
Definition: mips32.h:227
MIPS32_ADDU
#define MIPS32_ADDU(isa, dst, src, tar)
Definition: mips32.h:722
MMIPS32_ONLY
@ MMIPS32_ONLY
Definition: mips32.h:257
MIPS32_MMIPS32
@ MIPS32_MMIPS32
Definition: mips32.h:259
MIPS32_MIPS16
@ MIPS32_MIPS16
Definition: mips32.h:258
MIPS32_ONLY
@ MIPS32_ONLY
Definition: mips32.h:256
MIPS32_CFG1_DSSHIFT
#define MIPS32_CFG1_DSSHIFT
Definition: mips32.h:818
MIPS32_REG_C0_STATUS_INDEX
#define MIPS32_REG_C0_STATUS_INDEX
Definition: mips32.h:239
MIPS32_MTC0
#define MIPS32_MTC0(isa, gpr, cpr, sel)
Definition: mips32.h:744
MIPS32_ADDIU
#define MIPS32_ADDIU(isa, tar, src, val)
Definition: mips32.h:721
MIPS32_LUI
#define MIPS32_LUI(isa, reg, val)
Definition: mips32.h:741
MIPS_CP0_MAPTIV_UC
#define MIPS_CP0_MAPTIV_UC
Definition: mips32.h:76
MIPS32_C0_GUESTCTL1
#define MIPS32_C0_GUESTCTL1
Definition: mips32.h:853
MIPS32_MMU_DUAL_VTLB_FTLB
#define MIPS32_MMU_DUAL_VTLB_FTLB
Definition: mips32.h:898
MIPS32_CONFIG0_AR_MASK
#define MIPS32_CONFIG0_AR_MASK
Definition: mips32.h:47
MIPS32_CFG1_DLSHIFT
#define MIPS32_CFG1_DLSHIFT
Definition: mips32.h:820
MIPS32_MMU_FIXED
#define MIPS32_MMU_FIXED
Definition: mips32.h:897
MIPS32_AND
#define MIPS32_AND(isa, dst, src, tar)
Definition: mips32.h:723
MIPS32_DSP_MFHI
#define MIPS32_DSP_MFHI(reg, ac)
Definition: mips32.h:797
MIPS32_REGLIST_C0_BADVADDR_INDEX
#define MIPS32_REGLIST_C0_BADVADDR_INDEX
Definition: mips32.h:234
MIPS32_DSP_MTHI
#define MIPS32_DSP_MTHI(reg, ac)
Definition: mips32.h:800
mips32_isa_mode
mips32_isa_mode
Definition: mips32.h:249
MIPS32_ISA_MMIPS32
@ MIPS32_ISA_MMIPS32
Definition: mips32.h:252
MIPS32_ISA_MIPS32
@ MIPS32_ISA_MIPS32
Definition: mips32.h:250
MIPS32_DSP_MFLO
#define MIPS32_DSP_MFLO(reg, ac)
Definition: mips32.h:798
MIPS32_ORI
#define MIPS32_ORI(isa, tar, src, val)
Definition: mips32.h:756
MIPS32_SLL
#define MIPS32_SLL(isa, dst, src, sa)
Definition: mips32.h:764
MIPS32_MFC0
#define MIPS32_MFC0(isa, gpr, cpr, sel)
Definition: mips32.h:743
MIPS32_CP0_STATUS_MX_SHIFT
#define MIPS32_CP0_STATUS_MX_SHIFT
Definition: mips32.h:81
MIPS32_CFG1_IASHIFT
#define MIPS32_CFG1_IASHIFT
Definition: mips32.h:816
mips32_isa_rel
mips32_isa_rel
Definition: mips32.h:267
MIPS32_RELEASE_1
@ MIPS32_RELEASE_1
Definition: mips32.h:268
MIPS32_RELEASE_6
@ MIPS32_RELEASE_6
Definition: mips32.h:270
MIPS32_RELEASE_2
@ MIPS32_RELEASE_2
Definition: mips32.h:269
MIPS32_REGLIST_C0_INDEX
#define MIPS32_REGLIST_C0_INDEX
Definition: mips32.h:230
mips32_cp0_regs
static const struct mips32_cp0 mips32_cp0_regs[]
mips32_cpu_entry
static const struct cpu_entry mips32_cpu_entry[]
MIPS32_B
#define MIPS32_B(isa, off)
Definition: mips32.h:726
MIPS32_MMU_BAT
#define MIPS32_MMU_BAT
Definition: mips32.h:896
MIPS32_SLTI
#define MIPS32_SLTI(isa, tar, src, val)
Definition: mips32.h:767
MIPS32_CONFIG1_FP_MASK
#define MIPS32_CONFIG1_FP_MASK
Definition: mips32.h:50
MIPS32_CP0_STATUS_FR_SHIFT
#define MIPS32_CP0_STATUS_FR_SHIFT
Definition: mips32.h:82
MIPS32_DSP_WRDSP
#define MIPS32_DSP_WRDSP(rs, mask)
Definition: mips32.h:802
MIPS32NUMCP0REGS
#define MIPS32NUMCP0REGS
Definition: mips32.h:206
MIPS32_DSP_RDDSP
#define MIPS32_DSP_RDDSP(rt, mask)
Definition: mips32.h:801
pracc_queue_free
void pracc_queue_free(struct pracc_queue_info *ctx)
Definition: mips32_pracc.c:339
mips32_pracc_write_regs
int mips32_pracc_write_regs(struct mips32_common *mips32)
Definition: mips32_pracc.c:873
mips32_pracc_queue_exec
int mips32_pracc_queue_exec(struct mips_ejtag *ejtag_info, struct pracc_queue_info *ctx, uint32_t *buf, bool check_last)
Definition: mips32_pracc.c:344
mips32_pracc_read_regs
int mips32_pracc_read_regs(struct mips32_common *mips32)
Definition: mips32_pracc.c:1087
pracc_queue_init
void pracc_queue_init(struct pracc_queue_info *ctx)
Definition: mips32_pracc.c:297
mips32_cp0_read
int mips32_cp0_read(struct mips_ejtag *ejtag_info, uint32_t *val, uint32_t cp0_reg, uint32_t cp0_sel)
mips32_cp0_read
Definition: mips32_pracc.c:552
pracc_add
void pracc_add(struct pracc_queue_info *ctx, uint32_t addr, uint32_t instr)
Definition: mips32_pracc.c:307
mips32_cp1_control_read
int mips32_cp1_control_read(struct mips_ejtag *ejtag_info, uint32_t *val, uint32_t cp1_c_reg)
mips32_cp1_control_read
Definition: mips32_pracc.c:591
mips32_cp0_write
int mips32_cp0_write(struct mips_ejtag *ejtag_info, uint32_t val, uint32_t cp0_reg, uint32_t cp0_sel)
mips32_cp0_write
Definition: mips32_pracc.c:573
PRACC_UPPER_BASE_ADDR
#define PRACC_UPPER_BASE_ADDR
Definition: mips32_pracc.h:25
PRACC_OUT_OFFSET
#define PRACC_OUT_OFFSET
Definition: mips32_pracc.h:28
LOWER16
#define LOWER16(addr)
Definition: mips32_pracc.h:32
pracc_swap16_array
static void pracc_swap16_array(struct mips_ejtag *ejtag_info, uint32_t *buf, int count)
Definition: mips32_pracc.h:121
UPPER16
#define UPPER16(addr)
Definition: mips32_pracc.h:31
MIPS32_PRACC_PARAM_OUT
#define MIPS32_PRACC_PARAM_OUT
Definition: mips32_pracc.h:23
NEG16
#define NEG16(v)
Definition: mips32_pracc.h:33
mips_cpu.h
PRID_IMP_MASK
#define PRID_IMP_MASK
Definition: mips_cpu.h:28
PRID_COMP_MASK
#define PRID_COMP_MASK
Definition: mips_cpu.h:13
PRID_COMP_LEXRA
#define PRID_COMP_LEXRA
Definition: mips_cpu.h:19
PRID_COMP_MTI
#define PRID_COMP_MTI
Definition: mips_cpu.h:16
PRID_IMP_MAPTIV_UP
#define PRID_IMP_MAPTIV_UP
Definition: mips_cpu.h:31
PRID_COMP_ALCHEMY
#define PRID_COMP_ALCHEMY
Definition: mips_cpu.h:18
PRID_IMP_M5150
#define PRID_IMP_M5150
Definition: mips_cpu.h:34
PRID_IMP_IAPTIV_CM
#define PRID_IMP_IAPTIV_CM
Definition: mips_cpu.h:32
PRID_COMP_INGENIC_E1
#define PRID_COMP_INGENIC_E1
Definition: mips_cpu.h:21
PRID_IMP_XBURST_REV1
#define PRID_IMP_XBURST_REV1
Definition: mips_cpu.h:36
PRID_IMP_IAPTIV
#define PRID_IMP_IAPTIV
Definition: mips_cpu.h:33
PRID_IMP_MAPTIV_UC
#define PRID_IMP_MAPTIV_UC
Definition: mips_cpu.h:30
mips_ejtag_get_idcode
int mips_ejtag_get_idcode(struct mips_ejtag *ejtag_info)
Definition: mips_ejtag.c:42
mips_ejtag_set_instr
void mips_ejtag_set_instr(struct mips_ejtag *ejtag_info, uint32_t new_instr)
Definition: mips_ejtag.c:22
mips_ejtag_get_impcode
int mips_ejtag_get_impcode(struct mips_ejtag *ejtag_info)
Definition: mips_ejtag.c:50
mips_ejtag_drscan_32
int mips_ejtag_drscan_32(struct mips_ejtag *ejtag_info, uint32_t *data)
Definition: mips_ejtag.c:130
ejtag_main_print_imp
void ejtag_main_print_imp(struct mips_ejtag *ejtag_info)
Definition: mips_ejtag.c:335
EJTAG_DCR_ENTRIES
#define EJTAG_DCR_ENTRIES
Definition: mips_ejtag.h:203
EJTAG_V20_IMP_NODB
#define EJTAG_V20_IMP_NODB
Definition: mips_ejtag.h:117
EJTAG_VERSION_20
#define EJTAG_VERSION_20
Definition: mips_ejtag.h:168
EJTAG_INST_CONTROL
#define EJTAG_INST_CONTROL
Definition: mips_ejtag.h:20
EJTAG_V20_IMP_NOIB
#define EJTAG_V20_IMP_NOIB
Definition: mips_ejtag.h:118
EJTAG_DCR_FDC
#define EJTAG_DCR_FDC
Definition: mips_ejtag.h:127
EJTAG_DCR_IB
#define EJTAG_DCR_IB
Definition: mips_ejtag.h:129
EJTAG_DCR_DB
#define EJTAG_DCR_DB
Definition: mips_ejtag.h:128
EJTAG_DCR_ENM
#define EJTAG_DCR_ENM
Definition: mips_ejtag.h:126
EJTAG_IMP_MIPS16
#define EJTAG_IMP_MIPS16
Definition: mips_ejtag.h:112
dcr_features
static const struct dcr_feature dcr_features[]
EJTAG_DCR
#define EJTAG_DCR
Definition: mips_ejtag.h:125
EJTAG_DCR_INTE
#define EJTAG_DCR_INTE
Definition: mips_ejtag.h:130
bit
static uint32_t bit(uint32_t value, unsigned int b)
Definition: opcodes.h:15
register_get_by_name
struct reg * register_get_by_name(struct reg_cache *first, const char *name, bool search_all)
Definition: register.c:50
register_get_last_cache_p
struct reg_cache ** register_get_last_cache_p(struct reg_cache **first)
Definition: register.c:72
reg_type
reg_type
Definition: register.h:19
REG_TYPE_INT
@ REG_TYPE_INT
Definition: register.h:21
REG_TYPE_IEEE_DOUBLE
@ REG_TYPE_IEEE_DOUBLE
Definition: register.h:37
REG_TYPE_IEEE_SINGLE
@ REG_TYPE_IEEE_SINGLE
Definition: register.h:36
target
struct target * target
Definition: rtt/rtt.c:26
BIT
#define BIT(nr)
Definition: stm32l4x.h:18
command_invocation
When run_command is called, a new instance will be created on the stack, filled with the proper value...
Definition: command.h:76
command_registration
Definition: command.h:234
command_registration::name
const char * name
Definition: command.h:235
cpu_entry
Definition: mips32.h:293
cpu_entry::vendor
const char * vendor
Definition: mips32.h:296
cpu_entry::cpu_name
const char * cpu_name
Definition: mips32.h:297
cpu_entry::prid
uint32_t prid
Definition: mips32.h:294
jtag_tap
Definition: jtag.h:101
mem_param
Definition: algorithm.h:20
mips32_algorithm
Definition: mips32.h:455
mips32_algorithm::isa_mode
enum mips32_isa_mode isa_mode
Definition: mips32.h:457
mips32_algorithm::common_magic
unsigned int common_magic
Definition: mips32.h:456
mips32_common
Definition: mips32.h:391
mips32_common::bp_scanned
int bp_scanned
Definition: mips32.h:430
mips32_common::dsp_imp
enum mips32_dsp_imp dsp_imp
Definition: mips32.h:404
mips32_common::fp_imp
enum mips32_fp_imp fp_imp
Definition: mips32.h:403
mips32_common::write_core_reg
int(* write_core_reg)(struct target *target, unsigned int num)
Definition: mips32.h:440
mips32_common::semihosting
int semihosting
Definition: mips32.h:407
mips32_common::common_magic
unsigned int common_magic
Definition: mips32.h:392
mips32_common::cpu_quirks
uint32_t cpu_quirks
Definition: mips32.h:425
mips32_common::num_data_bpoints
int num_data_bpoints
Definition: mips32.h:432
mips32_common::fpu_in_64bit
bool fpu_in_64bit
Definition: mips32.h:418
mips32_common::data_break_list
struct mips32_comparator * data_break_list
Definition: mips32.h:436
mips32_common::inst_break_list
struct mips32_comparator * inst_break_list
Definition: mips32.h:435
mips32_common::ejtag_info
struct mips_ejtag ejtag_info
Definition: mips32.h:396
mips32_common::fast_data_area
struct working_area * fast_data_area
Definition: mips32.h:428
mips32_common::core_regs
struct mips32_core_regs core_regs
Definition: mips32.h:398
mips32_common::num_data_bpoints_avail
int num_data_bpoints_avail
Definition: mips32.h:434
mips32_common::num_inst_bpoints
int num_inst_bpoints
Definition: mips32.h:431
mips32_common::prid
uint32_t prid
Definition: mips32.h:421
mips32_common::fpu_enabled
bool fpu_enabled
Definition: mips32.h:416
mips32_common::cp0_mask
uint32_t cp0_mask
Definition: mips32.h:413
mips32_common::read_core_reg
int(* read_core_reg)(struct target *target, unsigned int num)
Definition: mips32.h:439
mips32_common::isa_imp
enum mips32_isa_imp isa_imp
Definition: mips32.h:401
mips32_common::isa_mode
enum mips32_isa_mode isa_mode
Definition: mips32.h:400
mips32_common::isa_rel
enum mips32_isa_rel isa_rel
Definition: mips32.h:402
mips32_common::fdc
int fdc
Definition: mips32.h:406
mips32_common::core_cache
struct reg_cache * core_cache
Definition: mips32.h:395
mips32_common::num_inst_bpoints_avail
int num_inst_bpoints_avail
Definition: mips32.h:433
mips32_common::cpu_info
const struct cpu_entry * cpu_info
Definition: mips32.h:423
mips32_comparator
Definition: mips32.h:377
mips32_comparator::reg_address
uint32_t reg_address
Definition: mips32.h:380
mips32_core_reg
Definition: mips32.h:449
mips32_core_reg::target
struct target * target
Definition: mips32.h:451
mips32_core_reg::mips32_common
struct mips32_common * mips32_common
Definition: mips32.h:452
mips32_core_reg::num
uint32_t num
Definition: mips32.h:450
mips32_core_regs::fpr
uint64_t fpr[MIPS32_REG_FP_COUNT]
Definition: mips32.h:385
mips32_core_regs::gpr
uint32_t gpr[MIPS32_REG_GP_COUNT]
Definition: mips32.h:384
mips32_core_regs::cp0
uint32_t cp0[MIPS32_REG_C0_COUNT]
Definition: mips32.h:387
mips32_core_regs::dsp
uint32_t dsp[MIPS32_REG_DSP_COUNT]
Definition: mips32.h:388
mips32_core_regs::fpcr
uint32_t fpcr[MIPS32_REG_FPC_COUNT]
Definition: mips32.h:386
mips32_cp0
Definition: mips32.h:88
mips32_cp0::sel
unsigned int sel
Definition: mips32.h:90
mips32_cp0::reg
unsigned int reg
Definition: mips32.h:89
mips32_cp0::core
const unsigned int core
Definition: mips32.h:92
mips_ejtag
Definition: mips_ejtag.h:205
mips_ejtag::prid
uint32_t prid
Definition: mips_ejtag.h:209
mips_ejtag::ejtag_ctrl
uint32_t ejtag_ctrl
Definition: mips_ejtag.h:210
mips_ejtag::scan_delay
unsigned int scan_delay
Definition: mips_ejtag.h:217
mips_ejtag::idcode
uint32_t idcode
Definition: mips_ejtag.h:208
mips_ejtag::reg9
uint32_t reg9
Definition: mips_ejtag.h:216
mips_ejtag::config
uint32_t config[4]
Definition: mips_ejtag.h:213
mips_ejtag::ejtag_version
unsigned int ejtag_version
Definition: mips_ejtag.h:221
mips_ejtag::impcode
uint32_t impcode
Definition: mips_ejtag.h:207
mips_ejtag::ejtag_iba0_addr
uint32_t ejtag_iba0_addr
Definition: mips_ejtag.h:229
mips_ejtag::ejtag_iba_step_size
uint32_t ejtag_iba_step_size
Definition: mips_ejtag.h:241
mips_ejtag::endianness
uint32_t endianness
Definition: mips_ejtag.h:223
mips_ejtag::tap
struct jtag_tap * tap
Definition: mips_ejtag.h:206
mips_ejtag::ejtag_dba_step_size
uint32_t ejtag_dba_step_size
Definition: mips_ejtag.h:242
mips_ejtag::reg8
uint32_t reg8
Definition: mips_ejtag.h:215
mips_ejtag::ejtag_ibs_addr
uint32_t ejtag_ibs_addr
Definition: mips_ejtag.h:228
mips_ejtag::config_regs
uint32_t config_regs
Definition: mips_ejtag.h:212
mips_ejtag::ejtag_dbs_addr
uint32_t ejtag_dbs_addr
Definition: mips_ejtag.h:234
mips_ejtag::mode
int mode
Definition: mips_ejtag.h:218
mips_ejtag::ejtag_dba0_addr
uint32_t ejtag_dba0_addr
Definition: mips_ejtag.h:235
mips_ejtag::debug_caps
uint32_t debug_caps
Definition: mips_ejtag.h:227
mips_ejtag::isa
uint32_t isa
Definition: mips_ejtag.h:222
pracc_queue_info
Definition: mips32_pracc.h:46
pracc_queue_info::code_count
int code_count
Definition: mips32_pracc.h:50
pracc_queue_info::pracc_list
struct pa_list * pracc_list
Definition: mips32_pracc.h:53
pracc_queue_info::retval
int retval
Definition: mips32_pracc.h:49
pracc_queue_info::max_code
int max_code
Definition: mips32_pracc.h:52
pracc_queue_info::isa
unsigned int isa
Definition: mips32_pracc.h:48
pracc_queue_info::ejtag_info
struct mips_ejtag * ejtag_info
Definition: mips32_pracc.h:47
reg_arch_type
Definition: register.h:151
reg_arch_type::get
int(* get)(struct reg *reg)
Definition: register.h:152
reg_cache
Definition: register.h:144
reg_cache::name
const char * name
Definition: register.h:145
reg_cache::num_regs
unsigned int num_regs
Definition: register.h:148
reg_cache::reg_list
struct reg * reg_list
Definition: register.h:147
reg_cache::next
struct reg_cache * next
Definition: register.h:146
reg_data_type
Definition: register.h:99
reg_data_type::type
enum reg_type type
Definition: register.h:100
reg_feature
Definition: register.h:41
reg_param
Definition: algorithm.h:27
reg_param::size
uint32_t size
Definition: algorithm.h:29
reg_param::reg_name
const char * reg_name
Definition: algorithm.h:28
reg
Definition: register.h:111
reg::caller_save
bool caller_save
Definition: register.h:119
reg::valid
bool valid
Definition: register.h:126
reg::exist
bool exist
Definition: register.h:128
reg::size
uint32_t size
Definition: register.h:132
reg::group
const char * group
Definition: register.h:138
reg::value
uint8_t * value
Definition: register.h:122
reg::feature
struct reg_feature * feature
Definition: register.h:117
reg::reg_data_type
struct reg_data_type * reg_data_type
Definition: register.h:135
reg::number
uint32_t number
Definition: register.h:115
reg::arch_info
void * arch_info
Definition: register.h:140
reg::dirty
bool dirty
Definition: register.h:124
reg::type
const struct reg_arch_type * type
Definition: register.h:141
reg::name
const char * name
Definition: register.h:113
target_memory_check_block
Definition: target.h:340
target_memory_check_block::result
uint32_t result
Definition: target.h:343
target
Definition: target.h:116
target::state
enum target_state state
Definition: target.h:157
target::endianness
enum target_endianness endianness
Definition: target.h:155
target::reg_cache
struct reg_cache * reg_cache
Definition: target.h:158
target::arch_info
void * arch_info
Definition: target.h:164
timeout
Definition: psoc6.c:83
working_area
Definition: target.h:85
working_area::address
target_addr_t address
Definition: target.h:86
target_halt
int target_halt(struct target *target)
Definition: target.c:507
target_write_buffer
int target_write_buffer(struct target *target, target_addr_t address, uint32_t size, const uint8_t *buffer)
Definition: target.c:2342
target_read_buffer
int target_read_buffer(struct target *target, target_addr_t address, uint32_t size, uint8_t *buffer)
Definition: target.c:2407
target_run_algorithm
int target_run_algorithm(struct target *target, int num_mem_params, struct mem_param *mem_params, int num_reg_params, struct reg_param *reg_param, target_addr_t entry_point, target_addr_t exit_point, unsigned int timeout_ms, void *arch_info)
Downloads a target-specific native code algorithm to the target, and executes it.
Definition: target.c:773
target_alloc_working_area
int target_alloc_working_area(struct target *target, uint32_t size, struct working_area **area)
Definition: target.c:2060
target_write_u32
int target_write_u32(struct target *target, target_addr_t address, uint32_t value)
Definition: target.c:2641
target_free_working_area
int target_free_working_area(struct target *target, struct working_area *area)
Free a working area.
Definition: target.c:2118
target_read_u32
int target_read_u32(struct target *target, target_addr_t address, uint32_t *value)
Definition: target.c:2550
debug_reason_name
const char * debug_reason_name(const struct target *t)
Definition: target.c:247
target_wait_state
int target_wait_state(struct target *target, enum target_state state, unsigned int ms)
Definition: target.c:3214
get_current_target
struct target * get_current_target(struct command_context *cmd_ctx)
Definition: target.c:458
target_buffer_set_u32_array
void target_buffer_set_u32_array(struct target *target, uint8_t *buffer, uint32_t count, const uint32_t *srcbuf)
Definition: target.c:417
target_resume
int target_resume(struct target *target, int current, target_addr_t address, int handle_breakpoints, int debug_execution)
Make the target (re)start executing using its saved execution context (possibly with some modificatio...
Definition: target.c:556
target_register_class
target_register_class
Definition: target.h:110
ERROR_TARGET_NOT_HALTED
#define ERROR_TARGET_NOT_HALTED
Definition: target.h:790
target_was_examined
static bool target_was_examined(const struct target *target)
Definition: target.h:436
ERROR_TARGET_INVALID
#define ERROR_TARGET_INVALID
Definition: target.h:787
TARGET_HALTED
@ TARGET_HALTED
Definition: target.h:56
TARGET_BIG_ENDIAN
@ TARGET_BIG_ENDIAN
Definition: target.h:82
TARGET_LITTLE_ENDIAN
@ TARGET_LITTLE_ENDIAN
Definition: target.h:82
ERROR_TARGET_TIMEOUT
#define ERROR_TARGET_TIMEOUT
Definition: target.h:789
ERROR_TARGET_RESOURCE_NOT_AVAILABLE
#define ERROR_TARGET_RESOURCE_NOT_AVAILABLE
Definition: target.h:794
target_set_examined
static void target_set_examined(struct target *target)
Sets the examined flag for the given target.
Definition: target.h:443
ARRAY_SIZE
#define ARRAY_SIZE(x)
Compute the number of elements of a variable length array.
Definition: types.h:57
target_addr_t
uint64_t target_addr_t
Definition: types.h:335
NULL
#define NULL
Definition: usb.h:16
cmd
uint8_t cmd
Definition: vdebug.c:1
count
uint8_t count[4]
Definition: vdebug.c:22