Include dependency graph for mips32_pracc.c:

Functions
int	mips32_cp0_read (struct mips_ejtag ejtag_info, uint32_t val, uint32_t cp0_reg, uint32_t cp0_sel)
	mips32_cp0_read More...

int	mips32_cp0_write (struct mips_ejtag *ejtag_info, uint32_t val, uint32_t cp0_reg, uint32_t cp0_sel)
	mips32_cp0_write More...

int	mips32_cp1_control_read (struct mips_ejtag ejtag_info, uint32_t val, uint32_t cp1_c_reg)
	mips32_cp1_control_read More...

static int	mips32_pracc_clean_text_jump (struct mips_ejtag *ejtag_info)

static int	mips32_pracc_exec (struct mips_ejtag ejtag_info, struct pracc_queue_info ctx, uint32_t *param_out, bool check_last)

int	mips32_pracc_fastdata_xfer (struct mips_ejtag ejtag_info, struct working_area source, int write_t, uint32_t addr, int count, uint32_t *buf)

static int	mips32_pracc_fastdata_xfer_synchronize_cache (struct mips_ejtag *ejtag_info, uint32_t addr, int size, int count)
	mips32_pracc_fastdata_xfer_synchronize_cache - Synchronize cache for fast data transfer More...

static void	mips32_pracc_finish (struct mips_ejtag *ejtag_info)

int	mips32_pracc_queue_exec (struct mips_ejtag ejtag_info, struct pracc_queue_info ctx, uint32_t *buf, bool check_last)

static int	mips32_pracc_read_ctrl_addr (struct mips_ejtag *ejtag_info)

int	mips32_pracc_read_mem (struct mips_ejtag ejtag_info, uint32_t addr, int size, int count, void buf)

int	mips32_pracc_read_regs (struct mips32_common *mips32)

static int	mips32_pracc_read_u32 (struct mips_ejtag ejtag_info, uint32_t addr, uint32_t buf)

static void	mips32_pracc_store_regs (struct pracc_queue_info *ctx, unsigned int offset_gpr, unsigned int offset_cp0)

static void	mips32_pracc_store_regs_cp0_context (struct pracc_queue_info *ctx, unsigned int offset_cp0)

static void	mips32_pracc_store_regs_gpr (struct pracc_queue_info *ctx, unsigned int offset_gpr)

static void	mips32_pracc_store_regs_lohi (struct pracc_queue_info *ctx)

static void	mips32_pracc_store_regs_restore (struct pracc_queue_info *ctx)

static void	mips32_pracc_store_regs_set_base_addr (struct pracc_queue_info *ctx)

static int	mips32_pracc_synchronize_cache (struct mips_ejtag *ejtag_info, uint32_t start_addr, uint32_t end_addr, int cached, int rel)
	mips32_pracc_sync_cache More...

int	mips32_pracc_write_mem (struct mips_ejtag ejtag_info, uint32_t addr, int size, int count, const void buf)

static int	mips32_pracc_write_mem_generic (struct mips_ejtag ejtag_info, uint32_t addr, int size, int count, const void buf)

int	mips32_pracc_write_regs (struct mips32_common *mips32)

void	pracc_add (struct pracc_queue_info *ctx, uint32_t addr, uint32_t instr)

static void	pracc_add_li32 (struct pracc_queue_info *ctx, uint32_t reg_num, uint32_t data, bool optimize)

void	pracc_queue_free (struct pracc_queue_info *ctx)

void	pracc_queue_init (struct pracc_queue_info *ctx)

static int	wait_for_pracc_rw (struct mips_ejtag *ejtag_info)

Function Documentation

◆ mips32_cp0_read()

int mips32_cp0_read	(	struct mips_ejtag *	ejtag_info,
		uint32_t *	val,
		uint32_t	cp0_reg,
		uint32_t	cp0_sel
	)

mips32_cp0_read

Simulates mfc0 ASM instruction (Move From C0), i.e. implements copro C0 Register read.

Parameters

[in]	ejtag_info
[in]	val	Storage to hold read value
[in]	cp0_reg	Number of copro C0 register we want to read
[in]	cp0_sel	Select for the given C0 register

Returns: ERROR_OK on Success, ERROR_FAIL otherwise

Definition at line 552 of file mips32_pracc.c.

References pracc_queue_info::code_count, pracc_queue_info::ejtag_info, pracc_queue_info::isa, LOWER16, MIPS32_B, mips32_cpu_support_hazard_barrier(), MIPS32_EHB, MIPS32_LUI, MIPS32_MFC0, MIPS32_ORI, MIPS32_PRACC_PARAM_OUT, mips32_pracc_queue_exec(), MIPS32_SW, NEG16, pracc_add(), PRACC_OUT_OFFSET, pracc_queue_free(), pracc_queue_init(), PRACC_UPPER_BASE_ADDR, mips_ejtag::reg8, pracc_queue_info::retval, and UPPER16.

Referenced by COMMAND_HANDLER(), mips32_cp0_get_all_regs(), mips32_cp0_get_reg_by_name(), mips32_cp0_get_reg_by_number(), mips32_pracc_fastdata_xfer_synchronize_cache(), mips32_pracc_synchronize_cache(), mips32_pracc_write_mem(), mips32_read_c0_prid(), mips32_read_config_dsp(), mips32_read_config_fpu(), mips32_read_config_mmu(), and mips32_read_config_regs().

◆ mips32_cp0_write()

int mips32_cp0_write	(	struct mips_ejtag *	ejtag_info,
		uint32_t	val,
		uint32_t	cp0_reg,
		uint32_t	cp0_sel
	)

mips32_cp0_write

Simulates mtc0 ASM instruction (Move To C0), i.e. implements copro C0 Register read.

Parameters

[in]	ejtag_info
[in]	val	Value to be written
[in]	cp0_reg	Number of copro C0 register we want to write to
[in]	cp0_sel	Select for the given C0 register

Returns: ERROR_OK on Success, ERROR_FAIL otherwise

Definition at line 573 of file mips32_pracc.c.

References pracc_queue_info::code_count, pracc_queue_info::ejtag_info, pracc_queue_info::isa, MIPS32_B, mips32_cpu_support_hazard_barrier(), MIPS32_EHB, MIPS32_MFC0, MIPS32_MTC0, mips32_pracc_queue_exec(), NEG16, NULL, pracc_add(), pracc_add_li32(), pracc_queue_free(), pracc_queue_init(), and pracc_queue_info::retval.

Referenced by COMMAND_HANDLER(), mips32_cp0_set_reg_by_name(), and mips32_cp0_set_reg_by_number().

◆ mips32_cp1_control_read()

int mips32_cp1_control_read	(	struct mips_ejtag *	ejtag_info,
		uint32_t *	val,
		uint32_t	cp1_c_reg
	)

mips32_cp1_control_read

Simulates cfc1 ASM instruction (Move Control Word From Floating Point), i.e. implements copro C1 Control Register read.

Parameters

[in]	ejtag_info
[in]	val	Storage to hold read value
[in]	cp1_c_reg	Number of copro C1 control register we want to read

Returns: ERROR_OK on Success, ERROR_FAIL otherwise

Definition at line 591 of file mips32_pracc.c.

References pracc_queue_info::code_count, pracc_queue_info::ejtag_info, pracc_queue_info::isa, LOWER16, MIPS32_B, MIPS32_CFC1, MIPS32_EHB, MIPS32_LUI, MIPS32_MFC0, MIPS32_ORI, MIPS32_PRACC_PARAM_OUT, mips32_pracc_queue_exec(), MIPS32_SW, NEG16, pracc_add(), PRACC_OUT_OFFSET, pracc_queue_free(), pracc_queue_init(), PRACC_UPPER_BASE_ADDR, mips_ejtag::reg8, pracc_queue_info::retval, and UPPER16.

Referenced by mips32_read_config_fpu().

◆ mips32_pracc_clean_text_jump()

static int mips32_pracc_clean_text_jump ( struct mips_ejtag * ejtag_info )

static

Definition at line 115 of file mips32_pracc.c.

References EJTAG_INST_DATA, ERROR_OK, mips_ejtag::isa, MIPS32_J, MIPS32_NOP, mips32_pracc_finish(), mips32_pracc_read_ctrl_addr(), MIPS32_PRACC_TEXT, mips_ejtag_drscan_32_out(), mips_ejtag_set_instr(), mips_ejtag::mode, mips_ejtag::pa_addr, pracc_swap16_array(), and wait_for_pracc_rw().

Referenced by mips32_pracc_exec().

◆ mips32_pracc_exec()

static int mips32_pracc_exec	(	struct mips_ejtag *	ejtag_info,
		struct pracc_queue_info *	ctx,
		uint32_t *	param_out,
		bool	check_last
	)

static

◆ mips32_pracc_fastdata_xfer()

int mips32_pracc_fastdata_xfer	(	struct mips_ejtag *	ejtag_info,
		struct working_area *	source,
		int	write_t,
		uint32_t	addr,
		int	count,
		uint32_t *	buf
	)

Definition at line 1301 of file mips32_pracc.c.

References adapter_get_speed_khz(), addr, ARRAY_SIZE, count, EJTAG_INST_DATA, EJTAG_INST_FASTDATA, ERROR_FAIL, ERROR_OK, ERROR_TARGET_RESOURCE_NOT_AVAILABLE, mips_ejtag::fast_access_save, mips_ejtag::isa, jtag_add_clocks(), jtag_execute_queue(), LOG_DEBUG, LOG_ERROR, LOWER16, MIPS32_ADDI, MIPS32_BNE, mips32_cpu_support_hazard_barrier(), mips32_cpu_support_sync(), MIPS32_FASTDATA_HANDLER_SIZE, MIPS32_JR, MIPS32_JRHB, MIPS32_LUI, MIPS32_LW, MIPS32_MFC0, MIPS32_NOP, MIPS32_ORI, MIPS32_PRACC_FASTDATA_AREA, mips32_pracc_fastdata_xfer_synchronize_cache(), mips32_pracc_finish(), mips32_pracc_read_ctrl_addr(), MIPS32_PRACC_TEXT, mips32_pracc_write_mem(), MIPS32_SW, MIPS32_SYNC, MIPS32_XORI, mips_ejtag_drscan_32_out(), mips_ejtag_fastdata_scan(), mips_ejtag_set_instr(), mips_ejtag::mode, NEG16, mips_ejtag::pa_addr, pracc_swap16_array(), mips_ejtag::scan_delay, source, TARGET_PRIxADDR, UPPER16, and wait_for_pracc_rw().

Referenced by mips_m4k_bulk_read_memory(), and mips_m4k_bulk_write_memory().

◆ mips32_pracc_fastdata_xfer_synchronize_cache()

static int mips32_pracc_fastdata_xfer_synchronize_cache	(	struct mips_ejtag *	ejtag_info,
		uint32_t	addr,
		int	size,
		int	count
	)

static

mips32_pracc_fastdata_xfer_synchronize_cache - Synchronize cache for fast data transfer

Parameters

[in]	ejtag_info	EJTAG information structure
[in]	addr	Starting address for cache synchronization
[in]	size	Size of each data element
[in]	count	Number of data elements

Synchronizes the cache for fast data transfer based on the specified address and cache configuration. If the region is cacheable (write-back cache or write-through cache), it synchronizes the cache for the specified range. The synchronization is performed using the MIPS32 cache synchronization function.

Returns: ERROR_OK on success; error code on failure.

Check cacheability bits coherency algorithm is the region cacheable or uncached. If cacheable we have to synchronize the cache

Definition at line 1245 of file mips32_pracc.c.

References addr, count, ERROR_FAIL, ERROR_OK, KSEG0, KSEG1, KSEG2, KSEG3, KSEGX, KUSEG, LOG_DEBUG, MIPS32_CONFIG0_AR_MASK, MIPS32_CONFIG0_AR_SHIFT, MIPS32_CONFIG0_K0_MASK, MIPS32_CONFIG0_K0_SHIFT, MIPS32_CONFIG0_K23_MASK, MIPS32_CONFIG0_K23_SHIFT, MIPS32_CONFIG0_KU_MASK, MIPS32_CONFIG0_KU_SHIFT, mips32_cp0_read(), mips32_pracc_synchronize_cache(), MIPS32_RELEASE_2, and size.

Referenced by mips32_pracc_fastdata_xfer().

◆ mips32_pracc_finish()

static void mips32_pracc_finish ( struct mips_ejtag * ejtag_info )

static

Definition at line 108 of file mips32_pracc.c.

References ctrl, mips_ejtag::ejtag_ctrl, EJTAG_CTRL_PRACC, EJTAG_INST_CONTROL, mips_ejtag_drscan_32_out(), and mips_ejtag_set_instr().

Referenced by mips32_pracc_clean_text_jump(), mips32_pracc_exec(), and mips32_pracc_fastdata_xfer().

◆ mips32_pracc_queue_exec()

int mips32_pracc_queue_exec	(	struct mips_ejtag *	ejtag_info,
		struct pracc_queue_info *	ctx,
		uint32_t *	buf,
		bool	check_last
	)

Definition at line 344 of file mips32_pracc.c.

References adapter_get_speed_khz(), addr, pa_list::addr, buf_get_u32(), pracc_queue_info::code_count, ctrl, mips_ejtag::ejtag_ctrl, EJTAG_CTRL_PRACC, EJTAG_CTRL_PRNW, EJTAG_INST_ALL, mips_ejtag::endianness, ERROR_FAIL, ERROR_OK, pa_list::instr, mips_ejtag::isa, jtag_add_clocks(), jtag_execute_queue(), LOG_ERROR, mips32_pracc_exec(), MIPS32_PRACC_PARAM_OUT, MIPS32_PRACC_TEXT, mips_ejtag_add_scan_96(), mips_ejtag_set_instr(), mips_ejtag::mode, pracc_queue_info::pracc_list, pracc_queue_info::retval, mips_ejtag::scan_delay, pracc_queue_info::store_count, and SWAP16.

Referenced by ath79_spi_bitbang_chunk(), mips32_cp0_read(), mips32_cp0_write(), mips32_cp1_control_read(), mips32_pracc_read_dsp_reg(), mips32_pracc_read_mem(), mips32_pracc_read_regs(), mips32_pracc_read_u32(), mips32_pracc_synchronize_cache(), mips32_pracc_write_dsp_reg(), mips32_pracc_write_mem(), mips32_pracc_write_mem_generic(), mips32_pracc_write_regs(), mips_ejtag_config_step(), and mips_ejtag_exit_debug().

◆ mips32_pracc_read_ctrl_addr()

static int mips32_pracc_read_ctrl_addr ( struct mips_ejtag * ejtag_info )

static

Definition at line 95 of file mips32_pracc.c.

References EJTAG_INST_ADDRESS, ERROR_OK, mips_ejtag_drscan_32(), mips_ejtag_set_instr(), mips_ejtag::pa_addr, and wait_for_pracc_rw().

Referenced by mips32_pracc_clean_text_jump(), mips32_pracc_exec(), and mips32_pracc_fastdata_xfer().

◆ mips32_pracc_read_mem()

int mips32_pracc_read_mem	(	struct mips_ejtag *	ejtag_info,
		uint32_t	addr,
		int	size,
		int	count,
		void *	buf
	)

◆ mips32_pracc_read_regs()

int mips32_pracc_read_regs ( struct mips32_common * mips32 )

Definition at line 1087 of file mips32_pracc.c.

References ARRAY_SIZE, BIT, pracc_queue_info::code_count, mips32_common::core_regs, mips32_core_regs::cp0, mips32_core_regs::dsp, mips32_common::dsp_imp, mips32_common::ejtag_info, pracc_queue_info::ejtag_info, ERROR_OK, mips32_common::fp_imp, mips32_core_regs::fpcr, mips32_core_regs::fpr, mips32_common::fpu_in_64bit, mips32_core_regs::gpr, pracc_queue_info::isa, MIPS32_B, MIPS32_CFC1, MIPS32_CP0_STATUS_CU1_SHIFT, MIPS32_CP0_STATUS_MX_SHIFT, MIPS32_DSP_MFHI, MIPS32_DSP_MFLO, MIPS32_DSP_RDDSP, MIPS32_MFC1, MIPS32_MFHC1, MIPS32_MTC0, MIPS32_PRACC_PARAM_OUT, mips32_pracc_queue_exec(), mips32_pracc_store_regs(), mips32_pracc_store_regs_restore(), mips32_pracc_store_regs_set_base_addr(), MIPS32_REG_C0_STATUS_INDEX, MIPS32_SW, MIPS32_SWC1, NEG16, offset, pracc_add(), PRACC_OUT_OFFSET, pracc_queue_free(), pracc_queue_init(), mips_ejtag::reg8, mips_ejtag::reg9, and pracc_queue_info::retval.

Referenced by mips32_save_context().

◆ mips32_pracc_read_u32()

static int mips32_pracc_read_u32	(	struct mips_ejtag *	ejtag_info,
		uint32_t	addr,
		uint32_t *	buf
	)

static

Definition at line 448 of file mips32_pracc.c.

References addr, pracc_queue_info::code_count, pracc_queue_info::ejtag_info, pracc_queue_info::isa, LOWER16, MIPS32_B, mips32_cpu_support_sync(), MIPS32_LUI, MIPS32_LW, MIPS32_MFC0, MIPS32_PRACC_PARAM_OUT, mips32_pracc_queue_exec(), MIPS32_SW, MIPS32_SYNC, NEG16, pracc_add(), pracc_add_li32(), PRACC_OUT_OFFSET, pracc_queue_free(), pracc_queue_init(), PRACC_UPPER_BASE_ADDR, mips_ejtag::reg8, pracc_queue_info::retval, and UPPER16.

Referenced by mips32_pracc_read_mem().

◆ mips32_pracc_store_regs()

static void mips32_pracc_store_regs	(	struct pracc_queue_info *	ctx,
		unsigned int	offset_gpr,
		unsigned int	offset_cp0
	)

static

Definition at line 1077 of file mips32_pracc.c.

References mips32_pracc_store_regs_cp0_context(), mips32_pracc_store_regs_gpr(), mips32_pracc_store_regs_lohi(), mips32_pracc_store_regs_restore(), and mips32_pracc_store_regs_set_base_addr().

Referenced by mips32_pracc_read_regs().

◆ mips32_pracc_store_regs_cp0_context()

static void mips32_pracc_store_regs_cp0_context	(	struct pracc_queue_info *	ctx,
		unsigned int	offset_cp0
	)

static

Definition at line 1033 of file mips32_pracc.c.

References ARRAY_SIZE, pracc_queue_info::isa, MIPS32_MFC0, MIPS32_PRACC_PARAM_OUT, MIPS32_SW, offset, pracc_add(), and PRACC_OUT_OFFSET.

Referenced by mips32_pracc_store_regs().

◆ mips32_pracc_store_regs_gpr()

static void mips32_pracc_store_regs_gpr	(	struct pracc_queue_info *	ctx,
		unsigned int	offset_gpr
	)

static

Definition at line 1008 of file mips32_pracc.c.

References pracc_queue_info::isa, MIPS32_PRACC_PARAM_OUT, MIPS32_SW, pracc_add(), and PRACC_OUT_OFFSET.

Referenced by mips32_pracc_store_regs().

◆ mips32_pracc_store_regs_lohi()

static void mips32_pracc_store_regs_lohi ( struct pracc_queue_info * ctx )

static

Definition at line 1015 of file mips32_pracc.c.

References pracc_queue_info::isa, MIPS32_MFHI, MIPS32_MFLO, MIPS32_PRACC_PARAM_OUT, MIPS32_SW, pracc_add(), and PRACC_OUT_OFFSET.

Referenced by mips32_pracc_store_regs().

◆ mips32_pracc_store_regs_restore()

static void mips32_pracc_store_regs_restore ( struct pracc_queue_info * ctx )

static

Definition at line 1058 of file mips32_pracc.c.

References pracc_queue_info::isa, MIPS32_MFC0, MIPS32_PRACC_PARAM_OUT, MIPS32_SW, pracc_add(), and PRACC_OUT_OFFSET.

Referenced by mips32_pracc_read_regs(), and mips32_pracc_store_regs().

◆ mips32_pracc_store_regs_set_base_addr()

static void mips32_pracc_store_regs_set_base_addr ( struct pracc_queue_info * ctx )

static

Definition at line 997 of file mips32_pracc.c.

References pracc_queue_info::isa, MIPS32_LUI, MIPS32_MTC0, pracc_add(), and PRACC_UPPER_BASE_ADDR.

Referenced by mips32_pracc_read_regs(), and mips32_pracc_store_regs().

◆ mips32_pracc_synchronize_cache()

static int mips32_pracc_synchronize_cache	(	struct mips_ejtag *	ejtag_info,
		uint32_t	start_addr,
		uint32_t	end_addr,
		int	cached,
		int	rel
	)

static

mips32_pracc_sync_cache

Synchronize Caches to Make Instruction Writes Effective (ref. doc. MIPS32 Architecture For Programmers Volume II: The MIPS32 Instruction Set, Document Number: MD00086, Revision 2.00, June 9, 2003)

When the instruction stream is written, the SYNCI instruction should be used in conjunction with other instructions to make the newly-written instructions effective.

Explanation : A program that loads another program into memory is actually writing the D- side cache. The instructions it has loaded can't be executed until they reach the I-cache.

After the instructions have been written, the loader should arrange to write back any containing D-cache line and invalidate any locations already in the I-cache.

If the cache coherency attribute (CCA) is set to zero, it's a write through cache, there is no need to write back.

In the latest MIPS32/64 CPUs, MIPS provides the synci instruction, which does the whole job for a cache-line-sized chunk of the memory you just loaded: That is, it arranges a D-cache write-back (if CCA = 3) and an I-cache invalidate.

The line size is obtained with the rdhwr SYNCI_Step in release 2 or from cp0 config 1 register in release 1.

Find cache line size in bytes

Definition at line 638 of file mips32_pracc.c.

References pracc_queue_info::code_count, count, pracc_queue_info::ejtag_info, ERROR_FAIL, ERROR_OK, IS_PWR_OF_2, pracc_queue_info::isa, LOG_DEBUG, LOWER16, MIPS32_B, MIPS32_CACHE, MIPS32_CACHE_D_HIT_WRITEBACK, MIPS32_CACHE_I_HIT_INVALIDATE, MIPS32_CONFIG1_DL_MASK, MIPS32_CONFIG1_DL_SHIFT, mips32_cp0_read(), MIPS32_LUI, MIPS32_MFC0, MIPS32_NOP, MIPS32_PRACC_PARAM_OUT, mips32_pracc_queue_exec(), MIPS32_RDHWR, MIPS32_SW, MIPS32_SYNC, MIPS32_SYNCI, MIPS32_SYNCI_STEP, NEG16, NULL, pracc_add(), pracc_add_li32(), PRACC_OUT_OFFSET, pracc_queue_free(), pracc_queue_init(), PRACC_UPPER_BASE_ADDR, mips_ejtag::reg8, pracc_queue_info::retval, pracc_queue_info::store_count, and UPPER16.

Referenced by mips32_pracc_fastdata_xfer_synchronize_cache(), and mips32_pracc_write_mem().

◆ mips32_pracc_write_mem()

int mips32_pracc_write_mem	(	struct mips_ejtag *	ejtag_info,
		uint32_t	addr,
		int	size,
		int	count,
		const void *	buf
	)

If we are in the cacheable region and cache is activated, we must clean D$ (if Cache Coherency Attribute is set to 3) + invalidate I$ after we did the write, so that changes do not continue to live only in D$ (if CCA = 3), but to be replicated in I$ also (maybe we wrote the instructions)

Check cacheability bits coherency algorithm is the region cacheable or uncached. If cacheable we have to synchronize the cache

Definition at line 800 of file mips32_pracc.c.

References addr, pracc_queue_info::code_count, count, pracc_queue_info::ejtag_info, ERROR_FAIL, ERROR_OK, pracc_queue_info::isa, KSEG0, KSEG1, KSEG2, KSEG3, KSEGX, KUSEG, LOG_DEBUG, LOG_ERROR, MIPS32_B, MIPS32_CONFIG0_AR_MASK, MIPS32_CONFIG0_AR_SHIFT, MIPS32_CONFIG0_K0_MASK, MIPS32_CONFIG0_K0_SHIFT, MIPS32_CONFIG0_K23_MASK, MIPS32_CONFIG0_K23_SHIFT, MIPS32_CONFIG0_KU_MASK, MIPS32_CONFIG0_KU_SHIFT, mips32_cp0_read(), mips32_cpu_support_hazard_barrier(), mips32_cpu_support_sync(), MIPS32_EHB, MIPS32_NOP, mips32_pracc_queue_exec(), mips32_pracc_synchronize_cache(), mips32_pracc_write_mem_generic(), MIPS32_RELEASE_2, MIPS32_SYNC, NEG16, NULL, pracc_add(), pracc_queue_free(), pracc_queue_init(), pracc_queue_info::retval, and size.