OpenOCD
mips32.h
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1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 
3 /***************************************************************************
4  * Copyright (C) 2008 by Spencer Oliver *
5  * spen@spen-soft.co.uk *
6  * *
7  * Copyright (C) 2008 by David T.L. Wong *
8  * *
9  * Copyright (C) 2011 by Drasko DRASKOVIC *
10  * drasko.draskovic@gmail.com *
11  ***************************************************************************/
12 
13 #ifndef OPENOCD_TARGET_MIPS32_H
14 #define OPENOCD_TARGET_MIPS32_H
15 
16 #include <helper/bits.h>
17 
18 #include "target.h"
19 #include "mips32_pracc.h"
20 
21 #define MIPS32_COMMON_MAGIC 0xB320B320U
22 
27 #define KUSEG 0x00000000
28 #define KSEG0 0x80000000
29 #define KSEG1 0xa0000000
30 #define KSEG2 0xc0000000
31 #define KSEG3 0xe0000000
32 
34 #define KSEGX(a) ((a) & 0xe0000000)
35 
37 #define MIPS32_CONFIG0_KU_SHIFT 25
38 #define MIPS32_CONFIG0_KU_MASK (0x7 << MIPS32_CONFIG0_KU_SHIFT)
39 
40 #define MIPS32_CONFIG0_K0_SHIFT 0
41 #define MIPS32_CONFIG0_K0_MASK (0x7 << MIPS32_CONFIG0_K0_SHIFT)
42 
43 #define MIPS32_CONFIG0_K23_SHIFT 28
44 #define MIPS32_CONFIG0_K23_MASK (0x7 << MIPS32_CONFIG0_K23_SHIFT)
45 
46 #define MIPS32_CONFIG0_AR_SHIFT 10
47 #define MIPS32_CONFIG0_AR_MASK (0x7 << MIPS32_CONFIG0_AR_SHIFT)
48 
49 #define MIPS32_CONFIG1_FP_SHIFT 0
50 #define MIPS32_CONFIG1_FP_MASK BIT(MIPS32_CONFIG1_FP_SHIFT)
51 
52 #define MIPS32_CONFIG1_DL_SHIFT 10
53 #define MIPS32_CONFIG1_DL_MASK (0x7 << MIPS32_CONFIG1_DL_SHIFT)
54 
55 #define MIPS32_CONFIG3_CDMM_SHIFT 3
56 #define MIPS32_CONFIG3_CDMM_MASK BIT(MIPS32_CONFIG3_CDMM_SHIFT)
57 
58 #define MIPS32_CONFIG3_DSPP_SHIFT 10
59 #define MIPS32_CONFIG3_DSPP_MASK BIT(MIPS32_CONFIG3_DSPP_SHIFT)
60 
61 #define MIPS32_CONFIG3_DSPREV_SHIFT 11
62 #define MIPS32_CONFIG3_DSPREV_MASK BIT(MIPS32_CONFIG3_DSPREV_SHIFT)
63 
64 #define MIPS32_CONFIG3_ISA_SHIFT 14
65 #define MIPS32_CONFIG3_ISA_MASK (3 << MIPS32_CONFIG3_ISA_SHIFT)
66 
67 #define MIPS32_ARCH_REL1 0x0
68 #define MIPS32_ARCH_REL2 0x1
69 
70 #define MIPS32_SCAN_DELAY_LEGACY_MODE 2000000
71 
72 #define MIPS32NUMDSPREGS 7
73 
74 /* Bit Mask indicating CP0 register supported by this core */
75 #define MIPS_CP0_MK4 0x0001
76 #define MIPS_CP0_MAPTIV_UC 0x0002
77 #define MIPS_CP0_MAPTIV_UP 0x0004
78 #define MIPS_CP0_IAPTIV 0x0008
79 
80 /* CP0 Status register fields */
81 #define MIPS32_CP0_STATUS_MX_SHIFT 24
82 #define MIPS32_CP0_STATUS_FR_SHIFT 26
83 #define MIPS32_CP0_STATUS_CU1_SHIFT 29
84 
85 /* CP1 FIR register fields */
86 #define MIPS32_CP1_FIR_F64_SHIFT 22
87 
88 static const struct mips32_cp0 {
89  unsigned int reg;
90  unsigned int sel;
91  const char *name;
92  const unsigned int core;
93 } mips32_cp0_regs[] = {
94  {0, 0, "index", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UP},
95  {0, 1, "mvpcontrol", MIPS_CP0_IAPTIV},
96  {0, 2, "mvpconf0", MIPS_CP0_IAPTIV},
97  {0, 3, "mvpconf1", MIPS_CP0_IAPTIV},
98  {1, 0, "random", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UP},
99  {1, 1, "vpecontrol", MIPS_CP0_IAPTIV},
100  {1, 2, "vpeconf0", MIPS_CP0_IAPTIV},
101  {1, 3, "vpeconf1", MIPS_CP0_IAPTIV},
102  {1, 4, "yqmask", MIPS_CP0_IAPTIV},
103  {1, 5, "vpeschedule", MIPS_CP0_IAPTIV},
104  {1, 6, "vpeschefback", MIPS_CP0_IAPTIV},
105  {1, 7, "vpeopt", MIPS_CP0_IAPTIV},
106  {2, 0, "entrylo0", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UP},
107  {2, 1, "tcstatus", MIPS_CP0_IAPTIV},
108  {2, 2, "tcbind", MIPS_CP0_IAPTIV},
109  {2, 3, "tcrestart", MIPS_CP0_IAPTIV},
110  {2, 4, "tchalt", MIPS_CP0_IAPTIV},
111  {2, 5, "tccontext", MIPS_CP0_IAPTIV},
112  {2, 6, "tcschedule", MIPS_CP0_IAPTIV},
113  {2, 7, "tcschefback", MIPS_CP0_IAPTIV},
114  {3, 0, "entrylo1", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UP},
115  {3, 7, "tcopt", MIPS_CP0_IAPTIV},
116  {4, 0, "context", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UP},
118  {5, 0, "pagemask", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UP},
119  {5, 1, "pagegrain", MIPS_CP0_MAPTIV_UP},
120  {5, 2, "segctl0", MIPS_CP0_IAPTIV},
121  {5, 3, "segctl1", MIPS_CP0_IAPTIV},
122  {5, 4, "segctl2", MIPS_CP0_IAPTIV},
123  {6, 0, "wired", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UP},
124  {6, 1, "srsconf0", MIPS_CP0_IAPTIV},
125  {6, 2, "srsconf1", MIPS_CP0_IAPTIV},
126  {6, 3, "srsconf2", MIPS_CP0_IAPTIV},
127  {6, 4, "srsconf3", MIPS_CP0_IAPTIV},
128  {6, 5, "srsconf4", MIPS_CP0_IAPTIV},
131  {8, 1, "badinstr", MIPS_CP0_MAPTIV_UC | MIPS_CP0_MAPTIV_UP},
132  {8, 2, "badinstrp", MIPS_CP0_MAPTIV_UC | MIPS_CP0_MAPTIV_UP},
134  {10, 0, "entryhi", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UP},
139  {11, 4, "guestctl0ext", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UP | MIPS_CP0_MAPTIV_UC | MIPS_CP0_MK4},
143  {12, 3, "srsmap", MIPS_CP0_IAPTIV},
144  {12, 3, "srsmap1", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UC | MIPS_CP0_MAPTIV_UP},
145  {12, 4, "view_ipl", MIPS_CP0_MAPTIV_UC | MIPS_CP0_MAPTIV_UP | MIPS_CP0_MK4},
146  {12, 5, "srsmap2", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UC | MIPS_CP0_MAPTIV_UP},
150  {13, 5, "nestedexc", MIPS_CP0_MAPTIV_UC | MIPS_CP0_MAPTIV_UP | MIPS_CP0_MK4},
156  {15, 3, "cmgcrbase", MIPS_CP0_IAPTIV},
164  {17, 0, "lladdr", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UP | MIPS_CP0_MK4},
165  {18, 0, "watchlo0", MIPS_CP0_IAPTIV},
166  {18, 1, "watchlo1", MIPS_CP0_IAPTIV},
167  {18, 2, "watchlo2", MIPS_CP0_IAPTIV},
168  {18, 3, "watchlo3", MIPS_CP0_IAPTIV},
169  {19, 0, "watchhi0", MIPS_CP0_IAPTIV},
170  {19, 1, "watchhi1", MIPS_CP0_IAPTIV},
171  {19, 2, "watchhi2", MIPS_CP0_IAPTIV},
172  {19, 3, "watchhi3", MIPS_CP0_IAPTIV},
174  {23, 1, "tracecontrol", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UC | MIPS_CP0_MAPTIV_UP | MIPS_CP0_MK4},
175  {23, 2, "tracecontrol2", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UC | MIPS_CP0_MAPTIV_UP | MIPS_CP0_MK4},
176  {23, 3, "usertracedata1", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UC | MIPS_CP0_MAPTIV_UP | MIPS_CP0_MK4},
177  {23, 4, "tracebpc", MIPS_CP0_MAPTIV_UC | MIPS_CP0_MAPTIV_UP | MIPS_CP0_MK4},
178  {23, 4, "traceibpc", MIPS_CP0_IAPTIV},
179  {23, 5, "tracedbpc", MIPS_CP0_IAPTIV},
181  {24, 2, "tracecontrol3", MIPS_CP0_IAPTIV},
182  {24, 3, "usertracedata2", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UC | MIPS_CP0_MAPTIV_UP | MIPS_CP0_MK4},
188  {27, 0, "cacheerr", MIPS_CP0_IAPTIV},
189  {28, 0, "itaglo", MIPS_CP0_IAPTIV},
190  {28, 0, "taglo", MIPS_CP0_IAPTIV},
191  {28, 1, "idatalo", MIPS_CP0_IAPTIV},
192  {28, 1, "datalo", MIPS_CP0_IAPTIV},
193  {28, 2, "dtaglo", MIPS_CP0_IAPTIV},
194  {28, 3, "ddatalo", MIPS_CP0_IAPTIV},
195  {28, 4, "l23taglo", MIPS_CP0_IAPTIV},
196  {28, 5, "l23datalo", MIPS_CP0_IAPTIV},
197  {29, 1, "idatahi", MIPS_CP0_IAPTIV},
198  {29, 2, "dtaghi", MIPS_CP0_IAPTIV},
199  {29, 5, "l23datahi", MIPS_CP0_IAPTIV},
202  {31, 2, "kscratch1", MIPS_CP0_MAPTIV_UC | MIPS_CP0_MAPTIV_UP},
203  {31, 3, "kscratch2", MIPS_CP0_MAPTIV_UC | MIPS_CP0_MAPTIV_UP},
204 };
205 
206 #define MIPS32NUMCP0REGS (ARRAY_SIZE(mips32_cp0_regs))
207 
208 /* Insert extra NOPs after the DRET instruction on exit from debug. */
209 #define EJTAG_QUIRK_PAD_DRET BIT(0)
210 
211 /* offsets into mips32 core register cache */
212 enum {
213  MIPS32_PC = 37,
217 };
218 
219 /* offsets into mips32 core register cache */
220 
221 #define MIPS32_REG_GP_COUNT 34
222 #define MIPS32_REG_FP_COUNT 32
223 #define MIPS32_REG_FPC_COUNT 2
224 #define MIPS32_REG_C0_COUNT 5
225 #define MIPS32_REG_DSP_COUNT 7
226 
227 #define MIPS32_REGLIST_GP_INDEX 0
228 #define MIPS32_REGLIST_FP_INDEX (MIPS32_REGLIST_GP_INDEX + MIPS32_REG_GP_COUNT)
229 #define MIPS32_REGLIST_FPC_INDEX (MIPS32_REGLIST_FP_INDEX + MIPS32_REG_FP_COUNT)
230 #define MIPS32_REGLIST_C0_INDEX (MIPS32_REGLIST_FPC_INDEX + MIPS32_REG_FPC_COUNT)
231 #define MIPS32_REGLIST_DSP_INDEX (MIPS32_REGLIST_C0_INDEX + MIPS32_REG_C0_COUNT)
232 
233 #define MIPS32_REGLIST_C0_STATUS_INDEX (MIPS32_REGLIST_C0_INDEX + 0)
234 #define MIPS32_REGLIST_C0_BADVADDR_INDEX (MIPS32_REGLIST_C0_INDEX + 1)
235 #define MIPS32_REGLIST_C0_CAUSE_INDEX (MIPS32_REGLIST_C0_INDEX + 2)
236 #define MIPS32_REGLIST_C0_PC_INDEX (MIPS32_REGLIST_C0_INDEX + 3)
237 #define MIPS32_REGLIST_C0_GUESTCTL1_INDEX (MIPS32_REGLIST_C0_INDEX + 4)
238 
239 #define MIPS32_REG_C0_STATUS_INDEX 0
240 #define MIPS32_REG_C0_BADVADDR_INDEX 1
241 #define MIPS32_REG_C0_CAUSE_INDEX 2
242 #define MIPS32_REG_C0_PC_INDEX 3
243 #define MIPS32_REG_C0_GUESTCTL1_INDEX 4
244 
245 #define MIPS32_REGLIST_DSP_DSPCTL_INDEX (MIPS32_REGLIST_DSP_INDEX + 6)
246 
247 #define MIPS32_REG_DSP_DSPCTL_INDEX 6
248 
253 };
254 
260 };
261 
262 /* Release 2~5 does not have much change regarding to the ISA under User mode,
263 * therefore no new Architecture Revision(AR) level is assigned to them.
264 * Release 6 changed some instruction's encoding/mnemonic, removed instructions that
265 * has lost its purposes/none are using, and added some new instructions as well.
266 */
272 };
273 
281 };
282 #define MIPS32_CORE_MASK 0xFFFFFF00
283 #define MIPS32_VARIANT_MASK 0x00FF
284 
285 /* This struct contains mips cpu types with their name respectively.
286  * The PrID register format is as following:
287  * - Company Optionsp[31:24]
288  * - Company ID[23:16]
289  * - Processor ID[15:8]
290  * - Revision[7:0]
291  * Here the revision field represents the maximum value of revision.
292  */
293 static const struct cpu_entry {
294  uint32_t prid;
296  const char *vendor;
297  const char *cpu_name;
298 } mips32_cpu_entry[] = {
299  /* MIPS Technologies cores */
300  {0x000180FF, MIPS32, "MIPS", "4Kc"},
301  {0x000181FF, MIPS64, "MIPS", "5Kc"},
302  {0x000182FF, MIPS64, "MIPS", "20Kc"},
303  {0x000183FF, MIPS32, "MIPS", "4KM"},
304 
305  {0x000184FF, MIPS32, "MIPS", "4KEc"},
306  {0x000190FF, MIPS32, "MIPS", "4KEc"},
307 
308  {0x000185FF, MIPS32, "MIPS", "4KEm"},
309  {0x000191FF, MIPS32, "MIPS", "4KEm"},
310 
311  {0x000186FF, MIPS32, "MIPS", "4KSc"},
312  {0x000187FF, MIPS32, "MIPS", "M4K"},
313  {0x000188FF, MIPS64, "MIPS", "25Kf"},
314  {0x000189FF, MIPS64, "MIPS", "5KEc"},
315  {0x000192FF, MIPS32, "MIPS", "4KSD"},
316  {0x000193FF, MIPS32, "MIPS", "24Kc"},
317  {0x000195FF, MIPS32, "MIPS", "34Kc"},
318  {0x000196FF, MIPS32, "MIPS", "24KEc"},
319  {0x000197FF, MIPS32, "MIPS", "74Kc"},
320  {0x000199FF, MIPS32, "MIPS", "1004Kc"},
321  {0x00019AFF, MIPS32, "MIPS", "1074Kc"},
322  {0x00019BFF, MIPS32, "MIPS", "M14K"},
323  {0x00019CFF, MIPS32, "MIPS", "M14Kc"},
324  {0x00019DFF, MIPS32, "MIPS", "microAptiv_UC(M14KE)"},
325  {0x00019EFF, MIPS32, "MIPS", "microAptiv_UP(M14KEc)"},
326  {0x0001A0FF, MIPS32, "MIPS", "interAptiv"},
327  {0x0001A1FF, MIPS32, "MIPS", "interAptiv_CM"},
328  {0x0001A2FF, MIPS32, "MIPS", "proAptiv"},
329  {0x0001A3FF, MIPS32, "MIPS", "proAptiv_CM"},
330  {0x0001A6FF, MIPS32, "MIPS", "M5100"},
331  {0x0001A7FF, MIPS32, "MIPS", "M5150"},
332  {0x0001A8FF, MIPS32, "MIPS", "P5600"},
333  {0x0001A9FF, MIPS32, "MIPS", "I5500"},
334 
335  /* Broadcom */
336  {0x000200FF, MIPS32, "Broadcom", "Broadcom"},
337 
338  /* AMD Alchemy Series*/
339  /* NOTE: AMD/Alchemy series uses Company Option instead of
340  * Processor ID, to match the find function, Processor ID field
341  * is the copy of Company Option field */
342  {0x000300FF, MIPS32, "AMD Alchemy", "AU1000"},
343  {0x010301FF, MIPS32, "AMD Alchemy", "AU1500"},
344  {0x020302FF, MIPS32, "AMD Alchemy", "AU1100"},
345  {0x030303FF, MIPS32, "AMD Alchemy", "AU1550"},
346  {0x04030401, MIPS32, "AMD Alchemy", "AU1200"},
347  {0x040304FF, MIPS32, "AMD Alchemy", "AU1250"},
348  {0x050305FF, MIPS32, "AMD Alchemy", "AU1210"},
349 
350  /* Altera */
351  {0x001000FF, MIPS32, "Altera", "Altera"},
352 
353  /* Lexra */
354  {0x000B00FF, MIPS32, "Lexra", "Lexra"},
355 
356  /* Ingenic */
357  {0x00e102FF, MIPS32, "Ingenic", "Ingenic XBurst rev1"},
358 
359  {0xFFFFFFFF, MIPS32, "Unknown", "Unknown"}
360 };
361 
362 #define MIPS32_NUM_CPU_ENTRIES (ARRAY_SIZE(mips32_cpu_entry))
363 
369 };
370 
375 };
376 
378  int used;
379  uint32_t bp_value;
380  uint32_t reg_address;
381 };
382 
389 };
390 
392  unsigned int common_magic;
393 
394  void *arch_info;
396  struct mips_ejtag ejtag_info;
397 
399 
401  enum mips32_isa_imp isa_imp;
402  enum mips32_isa_rel isa_rel;
403  enum mips32_fp_imp fp_imp;
404  enum mips32_dsp_imp dsp_imp;
405 
406  int fdc;
408 
409  /* The cp0 registers implemented on different processor cores could be different, too.
410  * Here you can see most of the registers are implemented on interAptiv, which is
411  * a 2c4t SMP processor, it has more features than M-class processors, like vpe
412  * and other config registers for multhreading. */
413  uint32_t cp0_mask;
414 
415  /* FPU enabled (cp0.status.cu1) */
417  /* FPU mode (cp0.status.fr) */
419 
420  /* processor identification register */
421  uint32_t prid;
422  /* detected CPU type */
423  const struct cpu_entry *cpu_info;
424  /* CPU specific quirks */
425  uint32_t cpu_quirks;
426 
427  /* working area for fastdata access */
429 
437 
438  /* register cache to processor synchronization */
439  int (*read_core_reg)(struct target *target, unsigned int num);
440  int (*write_core_reg)(struct target *target, unsigned int num);
441 };
442 
443 static inline struct mips32_common *
445 {
446  return target->arch_info;
447 }
448 
450  uint32_t num;
451  struct target *target;
453 };
454 
456  unsigned int common_magic;
458 };
459 
460 #define MIPS32_OP_ADDU 0x21u
461 #define MIPS32_OP_ADDIU 0x09u
462 #define MIPS32_OP_ANDI 0x0Cu
463 #define MIPS32_OP_BEQ 0x04u
464 #define MIPS32_OP_BGTZ 0x07u
465 #define MIPS32_OP_BNE 0x05u
466 #define MIPS32_OP_ADD 0x20u
467 #define MIPS32_OP_ADDI 0x08u
468 #define MIPS32_OP_AND 0x24u
469 #define MIPS32_OP_CACHE 0x2Fu
470 #define MIPS32_OP_COP0 0x10u
471 #define MIPS32_OP_COP1 0x11u
472 #define MIPS32_OP_J 0x02u
473 #define MIPS32_OP_JR 0x08u
474 #define MIPS32_OP_LUI 0x0Fu
475 #define MIPS32_OP_LW 0x23u
476 #define MIPS32_OP_LWC1 0x31u
477 #define MIPS32_OP_LDC1 0x35u
478 #define MIPS32_OP_LB 0x20u
479 #define MIPS32_OP_LBU 0x24u
480 #define MIPS32_OP_LHU 0x25u
481 #define MIPS32_OP_MFHI 0x10u
482 #define MIPS32_OP_MTHI 0x11u
483 #define MIPS32_OP_MFLO 0x12u
484 #define MIPS32_OP_MTLO 0x13u
485 #define MIPS32_OP_MUL 0x02u
486 #define MIPS32_OP_RDHWR 0x3Bu
487 #define MIPS32_OP_SB 0x28u
488 #define MIPS32_OP_SH 0x29u
489 #define MIPS32_OP_SW 0x2Bu
490 #define MIPS32_OP_ORI 0x0Du
491 #define MIPS32_OP_XORI 0x0Eu
492 #define MIPS32_OP_XOR 0x26u
493 #define MIPS32_OP_SLTU 0x2Bu
494 #define MIPS32_OP_SRL 0x02u
495 #define MIPS32_OP_SRA 0x03u
496 #define MIPS32_OP_SYNCI 0x1Fu
497 #define MIPS32_OP_SLL 0x00u
498 #define MIPS32_OP_SLLV 0x04u
499 #define MIPS32_OP_SLTI 0x0Au
500 #define MIPS32_OP_MOVN 0x0Bu
501 #define MIPS32_OP_SWC1 0x39u
502 #define MIPS32_OP_SDC1 0x3Du
503 
504 #define MIPS32_OP_REGIMM 0x01u
505 #define MIPS32_OP_SDBBP 0x3Fu
506 #define MIPS32_OP_SPECIAL 0x00u
507 #define MIPS32_OP_SPECIAL2 0x07u
508 #define MIPS32_OP_SPECIAL3 0x1Fu
509 
510 #define MIPS32_COP_MF 0x00u
511 #define MIPS32_COP_CF 0x02u
512 #define MIPS32_COP_MFH 0x03u
513 #define MIPS32_COP_MT 0x04u
514 #define MIPS32_COP_MTH 0x07u
515 
516 #define MIPS32_R_INST(opcode, rs, rt, rd, shamt, funct) \
517  (((opcode) << 26) | ((rs) << 21) | ((rt) << 16) | ((rd) << 11) | ((shamt) << 6) | (funct))
518 #define MIPS32_I_INST(opcode, rs, rt, immd) \
519  (((opcode) << 26) | ((rs) << 21) | ((rt) << 16) | (immd))
520 #define MIPS32_J_INST(opcode, addr) (((opcode) << 26) | (addr))
521 
522 #define MIPS32_ISA_NOP 0
523 #define MIPS32_ISA_ADD(dst, src, tar) MIPS32_R_INST(MIPS32_OP_SPECIAL, src, tar, dst, 0, MIPS32_OP_ADD)
524 #define MIPS32_ISA_ADDI(tar, src, val) MIPS32_I_INST(MIPS32_OP_ADDI, src, tar, val)
525 #define MIPS32_ISA_ADDIU(tar, src, val) MIPS32_I_INST(MIPS32_OP_ADDIU, src, tar, val)
526 #define MIPS32_ISA_ADDU(dst, src, tar) MIPS32_R_INST(MIPS32_OP_SPECIAL, src, tar, dst, 0, MIPS32_OP_ADDU)
527 #define MIPS32_ISA_AND(dst, src, tar) MIPS32_R_INST(0, src, tar, dst, 0, MIPS32_OP_AND)
528 #define MIPS32_ISA_ANDI(tar, src, val) MIPS32_I_INST(MIPS32_OP_ANDI, src, tar, val)
529 
530 #define MIPS32_ISA_B(off) MIPS32_ISA_BEQ(0, 0, off)
531 #define MIPS32_ISA_BEQ(src, tar, off) MIPS32_I_INST(MIPS32_OP_BEQ, src, tar, off)
532 #define MIPS32_ISA_BGTZ(reg, off) MIPS32_I_INST(MIPS32_OP_BGTZ, reg, 0, off)
533 #define MIPS32_ISA_BNE(src, tar, off) MIPS32_I_INST(MIPS32_OP_BNE, src, tar, off)
534 #define MIPS32_ISA_CACHE(op, off, base) MIPS32_I_INST(MIPS32_OP_CACHE, base, op, off)
535 #define MIPS32_ISA_CFC1(gpr, cpr) MIPS32_R_INST(MIPS32_OP_COP1, MIPS32_COP_CF, gpr, cpr, 0, 0)
536 #define MIPS32_ISA_J(tar) MIPS32_J_INST(MIPS32_OP_J, (0x0FFFFFFFu & (tar)) >> 2)
537 #define MIPS32_ISA_JR(reg) MIPS32_R_INST(0, reg, 0, 0, 0, MIPS32_OP_JR)
538 #define MIPS32_ISA_JRHB(reg) MIPS32_R_INST(0, reg, 0, 0, 0x10, MIPS32_OP_JR)
539 
540 #define MIPS32_ISA_LB(reg, off, base) MIPS32_I_INST(MIPS32_OP_LB, base, reg, off)
541 #define MIPS32_ISA_LBU(reg, off, base) MIPS32_I_INST(MIPS32_OP_LBU, base, reg, off)
542 #define MIPS32_ISA_LHU(reg, off, base) MIPS32_I_INST(MIPS32_OP_LHU, base, reg, off)
543 #define MIPS32_ISA_LUI(reg, val) MIPS32_I_INST(MIPS32_OP_LUI, 0, reg, val)
544 #define MIPS32_ISA_LW(reg, off, base) MIPS32_I_INST(MIPS32_OP_LW, base, reg, off)
545 #define MIPS32_ISA_LWC1(reg, off, base) MIPS32_I_INST(MIPS32_OP_LWC1, base, reg, off)
546 #define MIPS32_ISA_LDC1(reg, off, base) MIPS32_I_INST(MIPS32_OP_LDC1, base, reg, off)
547 
548 #define MIPS32_ISA_MFC0(gpr, cpr, sel) MIPS32_R_INST(MIPS32_OP_COP0, MIPS32_COP_MF, gpr, cpr, 0, sel)
549 #define MIPS32_ISA_MTC0(gpr, cpr, sel) MIPS32_R_INST(MIPS32_OP_COP0, MIPS32_COP_MT, gpr, cpr, 0, sel)
550 #define MIPS32_ISA_MFC1(gpr, cpr) MIPS32_R_INST(MIPS32_OP_COP1, MIPS32_COP_MF, gpr, cpr, 0, 0)
551 #define MIPS32_ISA_MFHC1(gpr, cpr) MIPS32_R_INST(MIPS32_OP_COP1, MIPS32_COP_MFH, gpr, cpr, 0, 0)
552 #define MIPS32_ISA_MTC1(gpr, cpr) MIPS32_R_INST(MIPS32_OP_COP1, MIPS32_COP_MT, gpr, cpr, 0, 0)
553 #define MIPS32_ISA_MTHC1(gpr, cpr) MIPS32_R_INST(MIPS32_OP_COP1, MIPS32_COP_MTH, gpr, cpr, 0, 0)
554 #define MIPS32_ISA_MFLO(reg) MIPS32_R_INST(0, 0, 0, reg, 0, MIPS32_OP_MFLO)
555 #define MIPS32_ISA_MFHI(reg) MIPS32_R_INST(0, 0, 0, reg, 0, MIPS32_OP_MFHI)
556 #define MIPS32_ISA_MTLO(reg) MIPS32_R_INST(0, reg, 0, 0, 0, MIPS32_OP_MTLO)
557 #define MIPS32_ISA_MTHI(reg) MIPS32_R_INST(0, reg, 0, 0, 0, MIPS32_OP_MTHI)
558 
559 #define MIPS32_ISA_MUL(dst, src, t) MIPS32_R_INST(28, src, t, dst, 0, MIPS32_OP_MUL)
560 #define MIPS32_ISA_MOVN(dst, src, tar) MIPS32_R_INST(MIPS32_OP_SPECIAL, src, tar, dst, 0, MIPS32_OP_MOVN)
561 #define MIPS32_ISA_OR(dst, src, val) MIPS32_R_INST(0, src, val, dst, 0, 37)
562 #define MIPS32_ISA_ORI(tar, src, val) MIPS32_I_INST(MIPS32_OP_ORI, src, tar, val)
563 #define MIPS32_ISA_RDHWR(tar, dst) MIPS32_R_INST(MIPS32_OP_SPECIAL3, 0, tar, dst, 0, MIPS32_OP_RDHWR)
564 #define MIPS32_ISA_SB(reg, off, base) MIPS32_I_INST(MIPS32_OP_SB, base, reg, off)
565 #define MIPS32_ISA_SH(reg, off, base) MIPS32_I_INST(MIPS32_OP_SH, base, reg, off)
566 #define MIPS32_ISA_SW(reg, off, base) MIPS32_I_INST(MIPS32_OP_SW, base, reg, off)
567 #define MIPS32_ISA_SWC1(reg, off, base) MIPS32_I_INST(MIPS32_OP_SWC1, base, reg, off)
568 #define MIPS32_ISA_SDC1(reg, off, base) MIPS32_I_INST(MIPS32_OP_SDC1, base, reg, off)
569 
570 #define MIPS32_ISA_SLL(dst, src, sa) MIPS32_R_INST(MIPS32_OP_SPECIAL, 0, src, dst, sa, MIPS32_OP_SLL)
571 #define MIPS32_ISA_SLLV(dst, src, sa) MIPS32_R_INST(MIPS32_OP_SPECIAL, 0, src, dst, sa, MIPS32_OP_SLLV)
572 #define MIPS32_ISA_SLTI(tar, src, val) MIPS32_I_INST(MIPS32_OP_SLTI, src, tar, val)
573 #define MIPS32_ISA_SLTU(dst, src, tar) MIPS32_R_INST(MIPS32_OP_SPECIAL, src, tar, dst, 0, MIPS32_OP_SLTU)
574 #define MIPS32_ISA_SRA(reg, src, off) MIPS32_R_INST(MIPS32_OP_SPECIAL, 0, src, reg, off, MIPS32_OP_SRA)
575 #define MIPS32_ISA_SRL(reg, src, off) MIPS32_R_INST(MIPS32_OP_SPECIAL, 0, src, reg, off, MIPS32_OP_SRL)
576 #define MIPS32_ISA_SYNC 0xFu
577 #define MIPS32_ISA_SYNCI(off, base) MIPS32_I_INST(MIPS32_OP_REGIMM, base, MIPS32_OP_SYNCI, off)
578 
579 #define MIPS32_ISA_XOR(reg, val1, val2) MIPS32_R_INST(0, val1, val2, reg, 0, MIPS32_OP_XOR)
580 #define MIPS32_ISA_XORI(tar, src, val) MIPS32_I_INST(MIPS32_OP_XORI, src, tar, val)
581 
582 #define MIPS32_ISA_SYNCI_STEP 0x1 /* reg num od address step size to be used with synci instruction */
583 
590 #define MIPS32_CACHE_D_HIT_WRITEBACK ((0x1 << 0) | (0x6 << 2))
591 #define MIPS32_CACHE_I_HIT_INVALIDATE ((0x0 << 0) | (0x4 << 2))
592 
593 /* ejtag specific instructions */
594 #define MIPS32_ISA_DRET 0x4200001Fu
595 /* MIPS32_ISA_J_INST(MIPS32_ISA_OP_SPECIAL2, MIPS32_ISA_OP_SDBBP) */
596 #define MIPS32_ISA_SDBBP 0x7000003Fu
597 #define MIPS16_ISA_SDBBP 0xE801u
598 
599 /*MICRO MIPS INSTRUCTIONS, see doc MD00582 */
600 #define MMIPS32_POOL32A 0x00u
601 #define MMIPS32_POOL32F 0x15u
602 #define MMIPS32_POOL32FXF 0x3Bu
603 #define MMIPS32_POOL32AXF 0x3Cu
604 #define MMIPS32_POOL32B 0x08u
605 #define MMIPS32_POOL32I 0x10u
606 #define MMIPS32_OP_ADDI 0x04u
607 #define MMIPS32_OP_ADDIU 0x0Cu
608 #define MMIPS32_OP_ADDU 0x150u
609 #define MMIPS32_OP_AND 0x250u
610 #define MMIPS32_OP_ANDI 0x34u
611 #define MMIPS32_OP_BEQ 0x25u
612 #define MMIPS32_OP_BGTZ 0x06u
613 #define MMIPS32_OP_BNE 0x2Du
614 #define MMIPS32_OP_CACHE 0x06u
615 #define MMIPS32_OP_CFC1 0x40u
616 #define MMIPS32_OP_J 0x35u
617 #define MMIPS32_OP_JALR 0x03Cu
618 #define MMIPS32_OP_JALRHB 0x07Cu
619 #define MMIPS32_OP_LB 0x07u
620 #define MMIPS32_OP_LBU 0x05u
621 #define MMIPS32_OP_LHU 0x0Du
622 #define MMIPS32_OP_LUI 0x0Du
623 #define MMIPS32_OP_LW 0x3Fu
624 #define MMIPS32_OP_LWC1 0x27u
625 #define MMIPS32_OP_LDC1 0x2Fu
626 #define MMIPS32_OP_MFC0 0x03u
627 #define MMIPS32_OP_MFC1 0x80u
628 #define MMIPS32_OP_MFHC1 0xC0u
629 #define MMIPS32_OP_MTC0 0x0Bu
630 #define MMIPS32_OP_MTC1 0xA0u
631 #define MMIPS32_OP_MTHC1 0xE0u
632 #define MMIPS32_OP_MFLO 0x075u
633 #define MMIPS32_OP_MFHI 0x035u
634 #define MMIPS32_OP_MTLO 0x0F5u
635 #define MMIPS32_OP_MTHI 0x0B5u
636 #define MMIPS32_OP_MOVN 0x018u
637 #define MMIPS32_OP_ORI 0x14u
638 #define MMIPS32_OP_RDHWR 0x1ACu
639 #define MMIPS32_OP_SB 0x06u
640 #define MMIPS32_OP_SH 0x0Eu
641 #define MMIPS32_OP_SW 0x3Eu
642 #define MMIPS32_OP_SWC1 0x26u
643 #define MMIPS32_OP_SDC1 0x2Eu
644 #define MMIPS32_OP_SLTU 0x390u
645 #define MMIPS32_OP_SLL 0x000u
646 #define MMIPS32_OP_SLTI 0x24u
647 #define MMIPS32_OP_SRL 0x040u
648 #define MMIPS32_OP_SYNCI 0x10u
649 #define MMIPS32_OP_XOR 0x310u
650 #define MMIPS32_OP_XORI 0x1Cu
651 
652 #define MMIPS32_ADDI(tar, src, val) MIPS32_I_INST(MMIPS32_OP_ADDI, tar, src, val)
653 #define MMIPS32_ADDIU(tar, src, val) MIPS32_I_INST(MMIPS32_OP_ADDIU, tar, src, val)
654 #define MMIPS32_ADDU(dst, src, tar) MIPS32_R_INST(MMIPS32_POOL32A, tar, src, dst, 0, MMIPS32_OP_ADDU)
655 #define MMIPS32_AND(dst, src, tar) MIPS32_R_INST(MMIPS32_POOL32A, tar, src, dst, 0, MMIPS32_OP_AND)
656 #define MMIPS32_ANDI(tar, src, val) MIPS32_I_INST(MMIPS32_OP_ANDI, tar, src, val)
657 
658 #define MMIPS32_B(off) MMIPS32_BEQ(0, 0, off)
659 #define MMIPS32_BEQ(src, tar, off) MIPS32_I_INST(MMIPS32_OP_BEQ, tar, src, off)
660 #define MMIPS32_BGTZ(reg, off) MIPS32_I_INST(MMIPS32_POOL32I, MMIPS32_OP_BGTZ, reg, off)
661 #define MMIPS32_BNE(src, tar, off) MIPS32_I_INST(MMIPS32_OP_BNE, tar, src, off)
662 #define MMIPS32_CACHE(op, off, base) MIPS32_R_INST(MMIPS32_POOL32B, op, base, MMIPS32_OP_CACHE << 1, 0, off)
663 #define MMIPS32_CFC1(gpr, cpr) MIPS32_R_INST(MMIPS32_POOL32F, gpr, cpr, 0, MMIPS32_OP_CFC1, MMIPS32_POOL32FXF)
664 
665 #define MMIPS32_J(tar) MIPS32_J_INST(MMIPS32_OP_J, ((0x07FFFFFFu & ((tar) >> 1))))
666 #define MMIPS32_JR(reg) MIPS32_R_INST(MMIPS32_POOL32A, 0, reg, 0, MMIPS32_OP_JALR, MMIPS32_POOL32AXF)
667 #define MMIPS32_JRHB(reg) MIPS32_R_INST(MMIPS32_POOL32A, 0, reg, 0, MMIPS32_OP_JALRHB, MMIPS32_POOL32AXF)
668 #define MMIPS32_LB(reg, off, base) MIPS32_I_INST(MMIPS32_OP_LB, reg, base, off)
669 #define MMIPS32_LBU(reg, off, base) MIPS32_I_INST(MMIPS32_OP_LBU, reg, base, off)
670 #define MMIPS32_LHU(reg, off, base) MIPS32_I_INST(MMIPS32_OP_LHU, reg, base, off)
671 #define MMIPS32_LUI(reg, val) MIPS32_I_INST(MMIPS32_POOL32I, MMIPS32_OP_LUI, reg, val)
672 #define MMIPS32_LW(reg, off, base) MIPS32_I_INST(MMIPS32_OP_LW, reg, base, off)
673 #define MMIPS32_LWC1(reg, off, base) MIPS32_I_INST(MMIPS32_OP_LWC1, reg, base, off)
674 #define MMIPS32_LDC1(reg, off, base) MIPS32_I_INST(MMIPS32_OP_LDC1, reg, base, off)
675 
676 #define MMIPS32_MFC0(gpr, cpr, sel) MIPS32_R_INST(MMIPS32_POOL32A, gpr, cpr, sel,\
677  MMIPS32_OP_MFC0, MMIPS32_POOL32AXF)
678 #define MMIPS32_MFC1(gpr, cpr) MIPS32_R_INST(MMIPS32_POOL32F, gpr, cpr, 0, MMIPS32_OP_MFC1, MMIPS32_POOL32FXF)
679 #define MMIPS32_MFHC1(gpr, cpr) MIPS32_R_INST(MMIPS32_POOL32F, gpr, cpr, 0, MMIPS32_OP_MFHC1, MMIPS32_POOL32FXF)
680 #define MMIPS32_MFLO(reg) MIPS32_R_INST(MMIPS32_POOL32A, 0, reg, 0, MMIPS32_OP_MFLO, MMIPS32_POOL32AXF)
681 #define MMIPS32_MFHI(reg) MIPS32_R_INST(MMIPS32_POOL32A, 0, reg, 0, MMIPS32_OP_MFHI, MMIPS32_POOL32AXF)
682 #define MMIPS32_MTC0(gpr, cpr, sel) MIPS32_R_INST(MMIPS32_POOL32A, gpr, cpr, sel,\
683  MMIPS32_OP_MTC0, MMIPS32_POOL32AXF)
684 #define MMIPS32_MTC1(gpr, cpr) MIPS32_R_INST(MMIPS32_POOL32F, gpr, cpr, 0, MMIPS32_OP_MTC1, MMIPS32_POOL32FXF)
685 #define MMIPS32_MTHC1(gpr, cpr) MIPS32_R_INST(MMIPS32_POOL32F, gpr, cpr, 0, MMIPS32_OP_MTHC1, MMIPS32_POOL32FXF)
686 #define MMIPS32_MTLO(reg) MIPS32_R_INST(MMIPS32_POOL32A, 0, reg, 0, MMIPS32_OP_MTLO, MMIPS32_POOL32AXF)
687 #define MMIPS32_MTHI(reg) MIPS32_R_INST(MMIPS32_POOL32A, 0, reg, 0, MMIPS32_OP_MTHI, MMIPS32_POOL32AXF)
688 
689 #define MMIPS32_MOVN(dst, src, tar) MIPS32_R_INST(MMIPS32_POOL32A, tar, src, dst, 0, MMIPS32_OP_MOVN)
690 #define MMIPS32_NOP 0
691 #define MMIPS32_ORI(tar, src, val) MIPS32_I_INST(MMIPS32_OP_ORI, tar, src, val)
692 #define MMIPS32_RDHWR(tar, dst) MIPS32_R_INST(MMIPS32_POOL32A, dst, tar, 0, MMIPS32_OP_RDHWR, MMIPS32_POOL32AXF)
693 #define MMIPS32_SB(reg, off, base) MIPS32_I_INST(MMIPS32_OP_SB, reg, base, off)
694 #define MMIPS32_SH(reg, off, base) MIPS32_I_INST(MMIPS32_OP_SH, reg, base, off)
695 #define MMIPS32_SW(reg, off, base) MIPS32_I_INST(MMIPS32_OP_SW, reg, base, off)
696 #define MMIPS32_SWC1(reg, off, base) MIPS32_I_INST(MMIPS32_OP_SWC1, reg, base, off)
697 #define MMIPS32_SDC1(reg, off, base) MIPS32_I_INST(MMIPS32_OP_SDC1, reg, base, off)
698 
699 #define MMIPS32_SRL(reg, src, off) MIPS32_R_INST(MMIPS32_POOL32A, reg, src, off, 0, MMIPS32_OP_SRL)
700 #define MMIPS32_SLTU(dst, src, tar) MIPS32_R_INST(MMIPS32_POOL32A, tar, src, dst, 0, MMIPS32_OP_SLTU)
701 #define MMIPS32_SYNCI(off, base) MIPS32_I_INST(MMIPS32_POOL32I, MMIPS32_OP_SYNCI, base, off)
702 #define MMIPS32_SLL(dst, src, sa) MIPS32_R_INST(MMIPS32_POOL32A, dst, src, sa, 0, MMIPS32_OP_SLL)
703 #define MMIPS32_SLLV(dst, src, sa) MIPS32_R_INST(MMIPS32_POOL32A, dst, src, sa, 0, MMIPS32_OP_SLLV)
704 #define MMIPS32_SLTI(tar, src, val) MIPS32_I_INST(MMIPS32_OP_SLTI, tar, src, val)
705 #define MMIPS32_SYNC 0x00001A7Cu /* MIPS32_R_INST(MMIPS32_POOL32A, 0, 0, 0, 0x1ADu, MMIPS32_POOL32AXF) */
706 
707 #define MMIPS32_XOR(reg, val1, val2) MIPS32_R_INST(MMIPS32_POOL32A, val1, val2, reg, 0, MMIPS32_OP_XOR)
708 #define MMIPS32_XORI(tar, src, val) MIPS32_I_INST(MMIPS32_OP_XORI, tar, src, val)
709 
710 #define MMIPS32_SYNCI_STEP 0x1u /* reg num od address step size to be used with synci instruction */
711 
712 
713 /* ejtag specific instructions */
714 #define MMIPS32_DRET 0x0000E37Cu /* MIPS32_R_INST(MMIPS32_POOL32A, 0, 0, 0, 0x38D, MMIPS32_POOL32AXF) */
715 #define MMIPS32_SDBBP 0x0000DB7Cu /* MIPS32_R_INST(MMIPS32_POOL32A, 0, 0, 0, 0x1BD, MMIPS32_POOL32AXF) */
716 #define MMIPS16_SDBBP 0x46C0u /* POOL16C instr */
717 
718 /* instruction code with isa selection */
719 #define MIPS32_NOP 0 /* same for both isa's */
720 #define MIPS32_ADDI(isa, tar, src, val) (isa ? MMIPS32_ADDI(tar, src, val) : MIPS32_ISA_ADDI(tar, src, val))
721 #define MIPS32_ADDIU(isa, tar, src, val) (isa ? MMIPS32_ADDIU(tar, src, val) : MIPS32_ISA_ADDIU(tar, src, val))
722 #define MIPS32_ADDU(isa, dst, src, tar) (isa ? MMIPS32_ADDU(dst, src, tar) : MIPS32_ISA_ADDU(dst, src, tar))
723 #define MIPS32_AND(isa, dst, src, tar) (isa ? MMIPS32_AND(dst, src, tar) : MIPS32_ISA_AND(dst, src, tar))
724 #define MIPS32_ANDI(isa, tar, src, val) (isa ? MMIPS32_ANDI(tar, src, val) : MIPS32_ISA_ANDI(tar, src, val))
725 
726 #define MIPS32_B(isa, off) (isa ? MMIPS32_B(off) : MIPS32_ISA_B(off))
727 #define MIPS32_BEQ(isa, src, tar, off) (isa ? MMIPS32_BEQ(src, tar, off) : MIPS32_ISA_BEQ(src, tar, off))
728 #define MIPS32_BGTZ(isa, reg, off) (isa ? MMIPS32_BGTZ(reg, off) : MIPS32_ISA_BGTZ(reg, off))
729 #define MIPS32_BNE(isa, src, tar, off) (isa ? MMIPS32_BNE(src, tar, off) : MIPS32_ISA_BNE(src, tar, off))
730 #define MIPS32_CACHE(isa, op, off, base) (isa ? MMIPS32_CACHE(op, off, base) : MIPS32_ISA_CACHE(op, off, base))
731 #define MIPS32_CFC1(isa, gpr, cpr) (isa ? MMIPS32_CFC1(gpr, cpr) : MIPS32_ISA_CFC1(gpr, cpr))
732 
733 #define MIPS32_J(isa, tar) (isa ? MMIPS32_J(tar) : MIPS32_ISA_J(tar))
734 #define MIPS32_JR(isa, reg) (isa ? MMIPS32_JR(reg) : MIPS32_ISA_JR(reg))
735 #define MIPS32_JRHB(isa, reg) (isa ? MMIPS32_JRHB(reg) : MIPS32_ISA_JRHB(reg))
736 #define MIPS32_LB(isa, reg, off, base) (isa ? MMIPS32_LB(reg, off, base) : MIPS32_ISA_LB(reg, off, base))
737 #define MIPS32_LBU(isa, reg, off, base) (isa ? MMIPS32_LBU(reg, off, base) : MIPS32_ISA_LBU(reg, off, base))
738 #define MIPS32_LHU(isa, reg, off, base) (isa ? MMIPS32_LHU(reg, off, base) : MIPS32_ISA_LHU(reg, off, base))
739 #define MIPS32_LW(isa, reg, off, base) (isa ? MMIPS32_LW(reg, off, base) : MIPS32_ISA_LW(reg, off, base))
740 #define MIPS32_LWC1(isa, reg, off, base) (isa ? MMIPS32_LWC1(reg, off, base) : MIPS32_ISA_LWC1(reg, off, base))
741 #define MIPS32_LUI(isa, reg, val) (isa ? MMIPS32_LUI(reg, val) : MIPS32_ISA_LUI(reg, val))
742 
743 #define MIPS32_MFC0(isa, gpr, cpr, sel) (isa ? MMIPS32_MFC0(gpr, cpr, sel) : MIPS32_ISA_MFC0(gpr, cpr, sel))
744 #define MIPS32_MTC0(isa, gpr, cpr, sel) (isa ? MMIPS32_MTC0(gpr, cpr, sel) : MIPS32_ISA_MTC0(gpr, cpr, sel))
745 #define MIPS32_MFC1(isa, gpr, cpr) (isa ? MMIPS32_MFC1(gpr, cpr) : MIPS32_ISA_MFC1(gpr, cpr))
746 #define MIPS32_MFHC1(isa, gpr, cpr) (isa ? MMIPS32_MFHC1(gpr, cpr) : MIPS32_ISA_MFHC1(gpr, cpr))
747 #define MIPS32_MTC1(isa, gpr, cpr) (isa ? MMIPS32_MTC1(gpr, cpr) : MIPS32_ISA_MTC1(gpr, cpr))
748 #define MIPS32_MTHC1(isa, gpr, cpr) (isa ? MMIPS32_MTHC1(gpr, cpr) : MIPS32_ISA_MTHC1(gpr, cpr))
749 #define MIPS32_MFLO(isa, reg) (isa ? MMIPS32_MFLO(reg) : MIPS32_ISA_MFLO(reg))
750 #define MIPS32_MFHI(isa, reg) (isa ? MMIPS32_MFHI(reg) : MIPS32_ISA_MFHI(reg))
751 #define MIPS32_MTLO(isa, reg) (isa ? MMIPS32_MTLO(reg) : MIPS32_ISA_MTLO(reg))
752 #define MIPS32_MTHI(isa, reg) (isa ? MMIPS32_MTHI(reg) : MIPS32_ISA_MTHI(reg))
753 
754 #define MIPS32_MUL(isa, dst, src, t) (MIPS32_ISA_MUL(dst, src, t))
755 #define MIPS32_MOVN(isa, dst, src, tar) (isa ? MMIPS32_MOVN(dst, src, tar) : MIPS32_ISA_MOVN(dst, src, tar))
756 #define MIPS32_ORI(isa, tar, src, val) (isa ? MMIPS32_ORI(tar, src, val) : MIPS32_ISA_ORI(tar, src, val))
757 #define MIPS32_RDHWR(isa, tar, dst) (isa ? MMIPS32_RDHWR(tar, dst) : MIPS32_ISA_RDHWR(tar, dst))
758 #define MIPS32_SB(isa, reg, off, base) (isa ? MMIPS32_SB(reg, off, base) : MIPS32_ISA_SB(reg, off, base))
759 #define MIPS32_SH(isa, reg, off, base) (isa ? MMIPS32_SH(reg, off, base) : MIPS32_ISA_SH(reg, off, base))
760 #define MIPS32_SW(isa, reg, off, base) (isa ? MMIPS32_SW(reg, off, base) : MIPS32_ISA_SW(reg, off, base))
761 #define MIPS32_SWC1(isa, reg, off, base) (isa ? MMIPS32_SWC1(reg, off, base) : MIPS32_ISA_SWC1(reg, off, base))
762 #define MIPS32_SDC1(isa, reg, off, base) (isa ? MMIPS32_SDC1(reg, off, base) : MIPS32_ISA_SDC1(reg, off, base))
763 
764 #define MIPS32_SLL(isa, dst, src, sa) (isa ? MMIPS32_SLL(dst, src, sa) : MIPS32_ISA_SLL(dst, src, sa))
765 #define MIPS32_EHB(isa) (isa ? MMIPS32_SLL(0, 0, 3) : MIPS32_ISA_SLL(0, 0, 3))
766 #define MIPS32_SLLV(isa, dst, src, sa) (MIPS32_ISA_SLLV(dst, src, sa))
767 #define MIPS32_SLTI(isa, tar, src, val) (isa ? MMIPS32_SLTI(tar, src, val) : MIPS32_ISA_SLTI(tar, src, val))
768 #define MIPS32_SLTU(isa, dst, src, tar) (isa ? MMIPS32_SLTU(dst, src, tar) : MIPS32_ISA_SLTU(dst, src, tar))
769 #define MIPS32_SRL(isa, reg, src, off) (isa ? MMIPS32_SRL(reg, src, off) : MIPS32_ISA_SRL(reg, src, off))
770 
771 #define MIPS32_SYNCI(isa, off, base) (isa ? MMIPS32_SYNCI(off, base) : MIPS32_ISA_SYNCI(off, base))
772 #define MIPS32_SYNC(isa) (isa ? MMIPS32_SYNC : MIPS32_ISA_SYNC)
773 #define MIPS32_XOR(isa, reg, val1, val2) (isa ? MMIPS32_XOR(reg, val1, val2) : MIPS32_ISA_XOR(reg, val1, val2))
774 #define MIPS32_XORI(isa, tar, src, val) (isa ? MMIPS32_XORI(tar, src, val) : MIPS32_ISA_XORI(tar, src, val))
775 
776 #define MIPS32_SYNCI_STEP 0x1
777 
778 /* ejtag specific instructions */
779 #define MIPS32_DRET(isa) (isa ? MMIPS32_DRET : MIPS32_ISA_DRET)
780 #define MIPS32_SDBBP(isa) (isa ? MMIPS32_SDBBP : MIPS32_ISA_SDBBP)
781 
782 #define MIPS16_SDBBP(isa) (isa ? MMIPS16_SDBBP : MIPS16_ISA_SDBBP)
783 
784 /* ejtag specific instructions */
785 #define MICRO_MIPS32_SDBBP 0x000046C0
786 #define MICRO_MIPS_SDBBP 0x46C0
787 #define MIPS32_DSP_ENABLE 0x1000000
788 
789 #define MIPS32_S_INST(rs, rac, opcode) \
790  (((rs) << 21) | ((rac) << 11) | (opcode))
791 
792 #define MIPS32_DSP_R_INST(rt, immd, opcode, extrw) \
793  ((0x1F << 26) | ((immd) << 16) | ((rt) << 11) | ((opcode) << 6) | (extrw))
794 #define MIPS32_DSP_W_INST(rs, immd, opcode, extrw) \
795  ((0x1F << 26) | ((rs) << 21) | ((immd) << 11) | ((opcode) << 6) | (extrw))
796 
797 #define MIPS32_DSP_MFHI(reg, ac) MIPS32_R_INST(0, ac, 0, reg, 0, MIPS32_OP_MFHI)
798 #define MIPS32_DSP_MFLO(reg, ac) MIPS32_R_INST(0, ac, 0, reg, 0, MIPS32_OP_MFLO)
799 #define MIPS32_DSP_MTLO(reg, ac) MIPS32_S_INST(reg, ac, MIPS32_OP_MTLO)
800 #define MIPS32_DSP_MTHI(reg, ac) MIPS32_S_INST(reg, ac, MIPS32_OP_MTHI)
801 #define MIPS32_DSP_RDDSP(rt, mask) MIPS32_DSP_R_INST(rt, mask, 0x12, 0x38)
802 #define MIPS32_DSP_WRDSP(rs, mask) MIPS32_DSP_W_INST(rs, mask, 0x13, 0x38)
803 
804 
805 /*
806  * MIPS32 Config1 Register (CP0 Register 16, Select 1)
807  */
808 #define MIPS32_CFG1_M 0x80000000 /* Config2 implemented */
809 #define MIPS32_CFG1_MMUSMASK 0x7e000000 /* mmu size - 1 */
810 #define MIPS32_CFG1_MMUSSHIFT 25
811 #define MIPS32_CFG1_ISMASK 0x01c00000 /* icache lines 64<<n */
812 #define MIPS32_CFG1_ISSHIFT 22
813 #define MIPS32_CFG1_ILMASK 0x00380000 /* icache line size 2<<n */
814 #define MIPS32_CFG1_ILSHIFT 19
815 #define MIPS32_CFG1_IAMASK 0x00070000 /* icache ways - 1 */
816 #define MIPS32_CFG1_IASHIFT 16
817 #define MIPS32_CFG1_DSMASK 0x0000e000 /* dcache lines 64<<n */
818 #define MIPS32_CFG1_DSSHIFT 13
819 #define MIPS32_CFG1_DLMASK 0x00001c00 /* dcache line size 2<<n */
820 #define MIPS32_CFG1_DLSHIFT 10
821 #define MIPS32_CFG1_DAMASK 0x00000380 /* dcache ways - 1 */
822 #define MIPS32_CFG1_DASHIFT 7
823 #define MIPS32_CFG1_C2 0x00000040 /* Coprocessor 2 present */
824 #define MIPS32_CFG1_MD 0x00000020 /* MDMX implemented */
825 #define MIPS32_CFG1_PC 0x00000010 /* performance counters implemented */
826 #define MIPS32_CFG1_WR 0x00000008 /* watch registers implemented */
827 #define MIPS32_CFG1_CA 0x00000004 /* compression (mips16) implemented */
828 #define MIPS32_CFG1_EP 0x00000002 /* ejtag implemented */
829 #define MIPS32_CFG1_FP 0x00000001 /* fpu implemented */
830 
831 /*
832  * MIPS32 Coprocessor 0 register numbers
833  */
834 #define MIPS32_C0_INDEX 0
835 #define MIPS32_C0_INX 0
836 #define MIPS32_C0_RANDOM 1
837 #define MIPS32_C0_RAND 1
838 #define MIPS32_C0_ENTRYLO0 2
839 #define MIPS32_C0_TLBLO0 2
840 #define MIPS32_C0_ENTRYLO1 3
841 #define MIPS32_C0_TLBLO1 3
842 #define MIPS32_C0_CONTEXT 4
843 #define MIPS32_C0_CTXT 4
844 #define MIPS32_C0_PAGEMASK 5
845 #define MIPS32_C0_PAGEGRAIN (5, 1)
846 #define MIPS32_C0_WIRED 6
847 #define MIPS32_C0_HWRENA 7
848 #define MIPS32_C0_BADVADDR 8
849 #define MIPS32_C0_VADDR 8
850 #define MIPS32_C0_COUNT 9
851 #define MIPS32_C0_ENTRYHI 10
852 #define MIPS32_C0_TLBHI 10
853 #define MIPS32_C0_GUESTCTL1 10
854 #define MIPS32_C0_COMPARE 11
855 #define MIPS32_C0_STATUS 12
856 #define MIPS32_C0_SR 12
857 #define MIPS32_C0_INTCTL (12, 1)
858 #define MIPS32_C0_SRSCTL (12, 2)
859 #define MIPS32_C0_SRSMAP (12, 3)
860 #define MIPS32_C0_CAUSE 13
861 #define MIPS32_C0_CR 13
862 #define MIPS32_C0_EPC 14
863 #define MIPS32_C0_PRID 15
864 #define MIPS32_C0_EBASE (15, 1)
865 #define MIPS32_C0_CONFIG 16
866 #define MIPS32_C0_CONFIG0 (16, 0)
867 #define MIPS32_C0_CONFIG1 (16, 1)
868 #define MIPS32_C0_CONFIG2 (16, 2)
869 #define MIPS32_C0_CONFIG3 (16, 3)
870 #define MIPS32_C0_LLADDR 17
871 #define MIPS32_C0_WATCHLO 18
872 #define MIPS32_C0_WATCHHI 19
873 #define MIPS32_C0_DEBUG 23
874 #define MIPS32_C0_DEPC 24
875 #define MIPS32_C0_PERFCNT 25
876 #define MIPS32_C0_ERRCTL 26
877 #define MIPS32_C0_CACHEERR 27
878 #define MIPS32_C0_TAGLO 28
879 #define MIPS32_C0_ITAGLO 28
880 #define MIPS32_C0_DTAGLO (28, 2)
881 #define MIPS32_C0_TAGLO2 (28, 4)
882 #define MIPS32_C0_DATALO (28, 1)
883 #define MIPS32_C0_IDATALO (28, 1)
884 #define MIPS32_C0_DDATALO (28, 3)
885 #define MIPS32_C0_DATALO2 (28, 5)
886 #define MIPS32_C0_TAGHI 29
887 #define MIPS32_C0_ITAGHI 29
888 #define MIPS32_C0_DATAHI (29, 1)
889 #define MIPS32_C0_ERRPC 30
890 #define MIPS32_C0_DESAVE 31
891 
892 /*
893  * MIPS32 MMU types
894  */
895 #define MIPS32_MMU_TLB 1
896 #define MIPS32_MMU_BAT 2
897 #define MIPS32_MMU_FIXED 3
898 #define MIPS32_MMU_DUAL_VTLB_FTLB 4
899 
900 extern const struct command_registration mips32_command_handlers[];
901 
902 int mips32_arch_state(struct target *target);
903 
905  struct mips32_common *mips32, struct jtag_tap *tap);
906 
908 int mips32_save_context(struct target *target);
909 
911 
913  int num_mem_params, struct mem_param *mem_params,
914  int num_reg_params, struct reg_param *reg_params,
915  target_addr_t entry_point, target_addr_t exit_point,
916  unsigned int timeout_ms, void *arch_info);
917 
919 
920 int mips32_enable_interrupts(struct target *target, int enable);
921 
922 int mips32_examine(struct target *target);
923 
924 int mips32_cpu_probe(struct target *target);
925 
927 
929 
931  struct reg **reg_list[], int *reg_list_size,
932  enum target_register_class reg_class);
934  uint32_t count, uint32_t *checksum);
936  struct target_memory_check_block *blocks, int num_blocks, uint8_t erased_value);
937 
938 bool mips32_cpu_support_sync(struct mips_ejtag *ejtag_info);
939 bool mips32_cpu_support_hazard_barrier(struct mips_ejtag *ejtag_info);
940 
941 #endif /* OPENOCD_TARGET_MIPS32_H */
#define MIPS32_REG_DSP_COUNT
Definition: mips32.h:225
struct reg_cache * mips32_build_reg_cache(struct target *target)
Definition: mips32.c:501
bool mips32_cpu_support_sync(struct mips_ejtag *ejtag_info)
mips32_cpu_support_sync - Checks CPU supports ordering
Definition: mips32.c:963
const struct command_registration mips32_command_handlers[]
Definition: mips32.c:2414
int mips32_read_config_regs(struct target *target)
Definition: mips32.c:1155
int mips32_checksum_memory(struct target *target, target_addr_t address, uint32_t count, uint32_t *checksum)
Definition: mips32.c:1229
@ MIPS32_FIR
Definition: mips32.h:214
@ MIPS32_PC
Definition: mips32.h:213
@ MIPS32_DSPCTL
Definition: mips32.h:215
@ MIPS32NUMCOREREGS
Definition: mips32.h:216
static struct mips32_common * target_to_mips32(struct target *target)
Definition: mips32.h:444
#define MIPS32_REG_GP_COUNT
Definition: mips32.h:221
mips32_isa_supported
Definition: mips32.h:274
@ MIPS32_AT_RESET_AND_MICROMIPS
Definition: mips32.h:279
@ MICROMIPS_AT_RESET_AND_MIPS32
Definition: mips32.h:280
@ MIPS64
Definition: mips32.h:277
@ MICROMIPS_ONLY
Definition: mips32.h:278
@ MIPS16
Definition: mips32.h:275
@ MIPS32
Definition: mips32.h:276
int mips32_configure_break_unit(struct target *target)
Definition: mips32.c:804
#define MIPS_CP0_MK4
Definition: mips32.h:75
mips32_fp_imp
Definition: mips32.h:364
@ MIPS32_FP_IMP_64
Definition: mips32.h:367
@ MIPS32_FP_IMP_NONE
Definition: mips32.h:365
@ MIPS32_FP_IMP_32
Definition: mips32.h:366
@ MIPS32_FP_IMP_UNKNOWN
Definition: mips32.h:368
int mips32_arch_state(struct target *target)
Definition: mips32.c:484
int mips32_cpu_probe(struct target *target)
mips32_cpu_probe - Detects processor type and applies necessary quirks.
Definition: mips32.c:995
#define MIPS32_REG_FP_COUNT
Definition: mips32.h:222
#define MIPS_CP0_IAPTIV
Definition: mips32.h:78
int mips32_run_algorithm(struct target *target, int num_mem_params, struct mem_param *mem_params, int num_reg_params, struct reg_param *reg_params, target_addr_t entry_point, target_addr_t exit_point, unsigned int timeout_ms, void *arch_info)
Definition: mips32.c:616
#define MIPS_CP0_MAPTIV_UP
Definition: mips32.h:77
int mips32_examine(struct target *target)
Definition: mips32.c:732
int mips32_init_arch_info(struct target *target, struct mips32_common *mips32, struct jtag_tap *tap)
Definition: mips32.c:560
bool mips32_cpu_support_hazard_barrier(struct mips_ejtag *ejtag_info)
mips32_cpu_support_hazard_barrier - Checks CPU supports hazard barrier
Definition: mips32.c:976
mips32_isa_imp
Definition: mips32.h:255
@ MMIPS32_ONLY
Definition: mips32.h:257
@ MIPS32_MMIPS32
Definition: mips32.h:259
@ MIPS32_MIPS16
Definition: mips32.h:258
@ MIPS32_ONLY
Definition: mips32.h:256
#define MIPS32_REG_C0_COUNT
Definition: mips32.h:224
int mips32_save_context(struct target *target)
Definition: mips32.c:446
#define MIPS_CP0_MAPTIV_UC
Definition: mips32.h:76
int mips32_enable_interrupts(struct target *target, int enable)
Definition: mips32.c:860
int mips32_blank_check_memory(struct target *target, struct target_memory_check_block *blocks, int num_blocks, uint8_t erased_value)
Checks whether a memory region is erased.
Definition: mips32.c:1312
int mips32_register_commands(struct command_context *cmd_ctx)
mips32_isa_mode
Definition: mips32.h:249
@ MIPS32_ISA_MIPS16E
Definition: mips32.h:251
@ MIPS32_ISA_MMIPS32
Definition: mips32.h:252
@ MIPS32_ISA_MIPS32
Definition: mips32.h:250
int mips32_restore_context(struct target *target)
Definition: mips32.c:468
#define MIPS32_REG_FPC_COUNT
Definition: mips32.h:223
mips32_isa_rel
Definition: mips32.h:267
@ MIPS32_RELEASE_1
Definition: mips32.h:268
@ MIPS32_RELEASE_6
Definition: mips32.h:270
@ MIPS32_RELEASE_2
Definition: mips32.h:269
@ MIPS32_RELEASE_UNKNOWN
Definition: mips32.h:271
static const struct mips32_cp0 mips32_cp0_regs[]
int mips32_get_gdb_reg_list(struct target *target, struct reg **reg_list[], int *reg_list_size, enum target_register_class reg_class)
Definition: mips32.c:429
static const struct cpu_entry mips32_cpu_entry[]
mips32_dsp_imp
Definition: mips32.h:371
@ MIPS32_DSP_IMP_REV1
Definition: mips32.h:373
@ MIPS32_DSP_IMP_REV2
Definition: mips32.h:374
@ MIPS32_DSP_IMP_NONE
Definition: mips32.h:372
struct target * target
Definition: rtt/rtt.c:26
Definition: mips32.h:293
const char * vendor
Definition: mips32.h:296
enum mips32_isa_supported isa
Definition: mips32.h:295
const char * cpu_name
Definition: mips32.h:297
uint32_t prid
Definition: mips32.h:294
Definition: jtag.h:101
enum mips32_isa_mode isa_mode
Definition: mips32.h:457
unsigned int common_magic
Definition: mips32.h:456
int bp_scanned
Definition: mips32.h:430
enum mips32_dsp_imp dsp_imp
Definition: mips32.h:404
enum mips32_fp_imp fp_imp
Definition: mips32.h:403
int(* write_core_reg)(struct target *target, unsigned int num)
Definition: mips32.h:440
int semihosting
Definition: mips32.h:407
unsigned int common_magic
Definition: mips32.h:392
uint32_t cpu_quirks
Definition: mips32.h:425
int num_data_bpoints
Definition: mips32.h:432
bool fpu_in_64bit
Definition: mips32.h:418
struct mips32_comparator * data_break_list
Definition: mips32.h:436
struct mips32_comparator * inst_break_list
Definition: mips32.h:435
struct mips_ejtag ejtag_info
Definition: mips32.h:396
struct working_area * fast_data_area
Definition: mips32.h:428
struct mips32_core_regs core_regs
Definition: mips32.h:398
int num_data_bpoints_avail
Definition: mips32.h:434
int num_inst_bpoints
Definition: mips32.h:431
uint32_t prid
Definition: mips32.h:421
bool fpu_enabled
Definition: mips32.h:416
uint32_t cp0_mask
Definition: mips32.h:413
int(* read_core_reg)(struct target *target, unsigned int num)
Definition: mips32.h:439
enum mips32_isa_imp isa_imp
Definition: mips32.h:401
enum mips32_isa_mode isa_mode
Definition: mips32.h:400
void * arch_info
Definition: mips32.h:394
enum mips32_isa_rel isa_rel
Definition: mips32.h:402
struct reg_cache * core_cache
Definition: mips32.h:395
int num_inst_bpoints_avail
Definition: mips32.h:433
const struct cpu_entry * cpu_info
Definition: mips32.h:423
uint32_t bp_value
Definition: mips32.h:379
uint32_t reg_address
Definition: mips32.h:380
struct target * target
Definition: mips32.h:451
struct mips32_common * mips32_common
Definition: mips32.h:452
uint32_t num
Definition: mips32.h:450
uint64_t fpr[MIPS32_REG_FP_COUNT]
Definition: mips32.h:385
uint32_t gpr[MIPS32_REG_GP_COUNT]
Definition: mips32.h:384
uint32_t cp0[MIPS32_REG_C0_COUNT]
Definition: mips32.h:387
uint32_t dsp[MIPS32_REG_DSP_COUNT]
Definition: mips32.h:388
uint32_t fpcr[MIPS32_REG_FPC_COUNT]
Definition: mips32.h:386
const char * name
Definition: mips32.h:91
unsigned int sel
Definition: mips32.h:90
unsigned int reg
Definition: mips32.h:89
const unsigned int core
Definition: mips32.h:92
struct reg * reg_list
Definition: register.h:147
Definition: register.h:111
Definition: target.h:116
void * arch_info
Definition: target.h:164
target_register_class
Definition: target.h:110
uint64_t target_addr_t
Definition: types.h:335
uint8_t count[4]
Definition: vdebug.c:22