Include dependency graph for mips32.h:

This graph shows which files directly or indirectly include this file:

Data Structures
struct	cpu_entry

struct	mips32_algorithm

struct	mips32_common

struct	mips32_comparator

struct	mips32_core_reg

struct	mips32_core_regs

struct	mips32_cp0

Macros
#define	EJTAG_QUIRK_PAD_DRET BIT(0)

#define	KSEG0 0x80000000

#define	KSEG1 0xa0000000

#define	KSEG2 0xc0000000

#define	KSEG3 0xe0000000

#define	KSEGX(a) ((a) & 0xe0000000)
	Returns the kernel segment base of a given address. More...

#define	KUSEG 0x00000000
	Memory segments (32bit kernel mode addresses) These are the traditional names used in the 32-bit universe. More...

#define	MICRO_MIPS32_SDBBP 0x000046C0

#define	MICRO_MIPS_SDBBP 0x46C0

#define	MIPS16_ISA_SDBBP 0xE801u

#define	MIPS16_SDBBP(isa) (isa ? MMIPS16_SDBBP : MIPS16_ISA_SDBBP)

#define	MIPS32_ADDI(isa, tar, src, val) (isa ? MMIPS32_ADDI(tar, src, val) : MIPS32_ISA_ADDI(tar, src, val))

#define	MIPS32_ADDIU(isa, tar, src, val) (isa ? MMIPS32_ADDIU(tar, src, val) : MIPS32_ISA_ADDIU(tar, src, val))

#define	MIPS32_ADDU(isa, dst, src, tar) (isa ? MMIPS32_ADDU(dst, src, tar) : MIPS32_ISA_ADDU(dst, src, tar))

#define	MIPS32_AND(isa, dst, src, tar) (isa ? MMIPS32_AND(dst, src, tar) : MIPS32_ISA_AND(dst, src, tar))

#define	MIPS32_ANDI(isa, tar, src, val) (isa ? MMIPS32_ANDI(tar, src, val) : MIPS32_ISA_ANDI(tar, src, val))

#define	MIPS32_ARCH_REL1 0x0

#define	MIPS32_ARCH_REL2 0x1

#define	MIPS32_B(isa, off) (isa ? MMIPS32_B(off) : MIPS32_ISA_B(off))

#define	MIPS32_BEQ(isa, src, tar, off) (isa ? MMIPS32_BEQ(src, tar, off) : MIPS32_ISA_BEQ(src, tar, off))

#define	MIPS32_BGTZ(isa, reg, off) (isa ? MMIPS32_BGTZ(reg, off) : MIPS32_ISA_BGTZ(reg, off))

#define	MIPS32_BNE(isa, src, tar, off) (isa ? MMIPS32_BNE(src, tar, off) : MIPS32_ISA_BNE(src, tar, off))

#define	MIPS32_C0_BADVADDR 8

#define	MIPS32_C0_CACHEERR 27

#define	MIPS32_C0_CAUSE 13

#define	MIPS32_C0_COMPARE 11

#define	MIPS32_C0_CONFIG 16

#define	MIPS32_C0_CONFIG0 (16, 0)

#define	MIPS32_C0_CONFIG1 (16, 1)

#define	MIPS32_C0_CONFIG2 (16, 2)

#define	MIPS32_C0_CONFIG3 (16, 3)

#define	MIPS32_C0_CONTEXT 4

#define	MIPS32_C0_COUNT 9

#define	MIPS32_C0_CR 13

#define	MIPS32_C0_CTXT 4

#define	MIPS32_C0_DATAHI (29, 1)

#define	MIPS32_C0_DATALO (28, 1)

#define	MIPS32_C0_DATALO2 (28, 5)

#define	MIPS32_C0_DDATALO (28, 3)

#define	MIPS32_C0_DEBUG 23

#define	MIPS32_C0_DEPC 24

#define	MIPS32_C0_DESAVE 31

#define	MIPS32_C0_DTAGLO (28, 2)

#define	MIPS32_C0_EBASE (15, 1)

#define	MIPS32_C0_ENTRYHI 10

#define	MIPS32_C0_ENTRYLO0 2

#define	MIPS32_C0_ENTRYLO1 3

#define	MIPS32_C0_EPC 14

#define	MIPS32_C0_ERRCTL 26

#define	MIPS32_C0_ERRPC 30

#define	MIPS32_C0_GUESTCTL1 10

#define	MIPS32_C0_HWRENA 7

#define	MIPS32_C0_IDATALO (28, 1)

#define	MIPS32_C0_INDEX 0

#define	MIPS32_C0_INTCTL (12, 1)

#define	MIPS32_C0_INX 0

#define	MIPS32_C0_ITAGHI 29

#define	MIPS32_C0_ITAGLO 28

#define	MIPS32_C0_LLADDR 17

#define	MIPS32_C0_PAGEGRAIN (5, 1)

#define	MIPS32_C0_PAGEMASK 5

#define	MIPS32_C0_PERFCNT 25

#define	MIPS32_C0_PRID 15

#define	MIPS32_C0_RAND 1

#define	MIPS32_C0_RANDOM 1

#define	MIPS32_C0_SR 12

#define	MIPS32_C0_SRSCTL (12, 2)

#define	MIPS32_C0_SRSMAP (12, 3)

#define	MIPS32_C0_STATUS 12

#define	MIPS32_C0_TAGHI 29

#define	MIPS32_C0_TAGLO 28

#define	MIPS32_C0_TAGLO2 (28, 4)

#define	MIPS32_C0_TLBHI 10

#define	MIPS32_C0_TLBLO0 2

#define	MIPS32_C0_TLBLO1 3

#define	MIPS32_C0_VADDR 8

#define	MIPS32_C0_WATCHHI 19

#define	MIPS32_C0_WATCHLO 18

#define	MIPS32_C0_WIRED 6

#define	MIPS32_CACHE(isa, op, off, base) (isa ? MMIPS32_CACHE(op, off, base) : MIPS32_ISA_CACHE(op, off, base))

#define	MIPS32_CACHE_D_HIT_WRITEBACK ((0x1 << 0) \| (0x6 << 2))
	Cache operations definitions Operation field is 5 bits long : 1) bits 1..0 hold cache type 2) bits 4..2 hold operation code. More...

#define	MIPS32_CACHE_I_HIT_INVALIDATE ((0x0 << 0) \| (0x4 << 2))

#define	MIPS32_CFC1(isa, gpr, cpr) (isa ? MMIPS32_CFC1(gpr, cpr) : MIPS32_ISA_CFC1(gpr, cpr))

#define	MIPS32_CFG1_C2 0x00000040 /* Coprocessor 2 present */

#define	MIPS32_CFG1_CA 0x00000004 /* compression (mips16) implemented */

#define	MIPS32_CFG1_DAMASK 0x00000380 /* dcache ways - 1 */

#define	MIPS32_CFG1_DASHIFT 7

#define	MIPS32_CFG1_DLMASK 0x00001c00 /* dcache line size 2<<n */

#define	MIPS32_CFG1_DLSHIFT 10

#define	MIPS32_CFG1_DSMASK 0x0000e000 /* dcache lines 64<<n */

#define	MIPS32_CFG1_DSSHIFT 13

#define	MIPS32_CFG1_EP 0x00000002 /* ejtag implemented */

#define	MIPS32_CFG1_FP 0x00000001 /* fpu implemented */

#define	MIPS32_CFG1_IAMASK 0x00070000 /* icache ways - 1 */

#define	MIPS32_CFG1_IASHIFT 16

#define	MIPS32_CFG1_ILMASK 0x00380000 /* icache line size 2<<n */

#define	MIPS32_CFG1_ILSHIFT 19

#define	MIPS32_CFG1_ISMASK 0x01c00000 /* icache lines 64<<n */

#define	MIPS32_CFG1_ISSHIFT 22

#define	MIPS32_CFG1_M 0x80000000 /* Config2 implemented */

#define	MIPS32_CFG1_MD 0x00000020 /* MDMX implemented */

#define	MIPS32_CFG1_MMUSMASK 0x7e000000 /* mmu size - 1 */

#define	MIPS32_CFG1_MMUSSHIFT 25

#define	MIPS32_CFG1_PC 0x00000010 /* performance counters implemented */

#define	MIPS32_CFG1_WR 0x00000008 /* watch registers implemented */

#define	MIPS32_COMMON_MAGIC 0xB320B320U

#define	MIPS32_CONFIG0_AR_MASK (0x7 << MIPS32_CONFIG0_AR_SHIFT)

#define	MIPS32_CONFIG0_AR_SHIFT 10

#define	MIPS32_CONFIG0_K0_MASK (0x7 << MIPS32_CONFIG0_K0_SHIFT)

#define	MIPS32_CONFIG0_K0_SHIFT 0

#define	MIPS32_CONFIG0_K23_MASK (0x7 << MIPS32_CONFIG0_K23_SHIFT)

#define	MIPS32_CONFIG0_K23_SHIFT 28

#define	MIPS32_CONFIG0_KU_MASK (0x7 << MIPS32_CONFIG0_KU_SHIFT)

#define	MIPS32_CONFIG0_KU_SHIFT 25
	CP0 CONFIG register fields. More...

#define	MIPS32_CONFIG1_DL_MASK (0x7 << MIPS32_CONFIG1_DL_SHIFT)

#define	MIPS32_CONFIG1_DL_SHIFT 10

#define	MIPS32_CONFIG1_FP_MASK BIT(MIPS32_CONFIG1_FP_SHIFT)

#define	MIPS32_CONFIG1_FP_SHIFT 0

#define	MIPS32_CONFIG3_CDMM_MASK BIT(MIPS32_CONFIG3_CDMM_SHIFT)

#define	MIPS32_CONFIG3_CDMM_SHIFT 3

#define	MIPS32_CONFIG3_DSPP_MASK BIT(MIPS32_CONFIG3_DSPP_SHIFT)

#define	MIPS32_CONFIG3_DSPP_SHIFT 10

#define	MIPS32_CONFIG3_DSPREV_MASK BIT(MIPS32_CONFIG3_DSPREV_SHIFT)

#define	MIPS32_CONFIG3_DSPREV_SHIFT 11

#define	MIPS32_CONFIG3_ISA_MASK (3 << MIPS32_CONFIG3_ISA_SHIFT)

#define	MIPS32_CONFIG3_ISA_SHIFT 14

#define	MIPS32_COP_CF 0x02u

#define	MIPS32_COP_MF 0x00u

#define	MIPS32_COP_MFH 0x03u

#define	MIPS32_COP_MT 0x04u

#define	MIPS32_COP_MTH 0x07u

#define	MIPS32_CORE_MASK 0xFFFFFF00

#define	MIPS32_CP0_STATUS_CU1_SHIFT 29

#define	MIPS32_CP0_STATUS_FR_SHIFT 26

#define	MIPS32_CP0_STATUS_MX_SHIFT 24

#define	MIPS32_CP1_FIR_F64_SHIFT 22

#define	MIPS32_DRET(isa) (isa ? MMIPS32_DRET : MIPS32_ISA_DRET)

#define	MIPS32_DSP_ENABLE 0x1000000

#define	MIPS32_DSP_MFHI(reg, ac) MIPS32_R_INST(0, ac, 0, reg, 0, MIPS32_OP_MFHI)

#define	MIPS32_DSP_MFLO(reg, ac) MIPS32_R_INST(0, ac, 0, reg, 0, MIPS32_OP_MFLO)

#define	MIPS32_DSP_MTHI(reg, ac) MIPS32_S_INST(reg, ac, MIPS32_OP_MTHI)

#define	MIPS32_DSP_MTLO(reg, ac) MIPS32_S_INST(reg, ac, MIPS32_OP_MTLO)

#define	MIPS32_DSP_R_INST(rt, immd, opcode, extrw) ((0x1F << 26) \| ((immd) << 16) \| ((rt) << 11) \| ((opcode) << 6) \| (extrw))

#define	MIPS32_DSP_RDDSP(rt, mask) MIPS32_DSP_R_INST(rt, mask, 0x12, 0x38)

#define	MIPS32_DSP_W_INST(rs, immd, opcode, extrw) ((0x1F << 26) \| ((rs) << 21) \| ((immd) << 11) \| ((opcode) << 6) \| (extrw))

#define	MIPS32_DSP_WRDSP(rs, mask) MIPS32_DSP_W_INST(rs, mask, 0x13, 0x38)

#define	MIPS32_EHB(isa) (isa ? MMIPS32_SLL(0, 0, 3) : MIPS32_ISA_SLL(0, 0, 3))

#define	MIPS32_I_INST(opcode, rs, rt, immd) (((opcode) << 26) \| ((rs) << 21) \| ((rt) << 16) \| (immd))

#define	MIPS32_ISA_ADD(dst, src, tar) MIPS32_R_INST(MIPS32_OP_SPECIAL, src, tar, dst, 0, MIPS32_OP_ADD)

#define	MIPS32_ISA_ADDI(tar, src, val) MIPS32_I_INST(MIPS32_OP_ADDI, src, tar, val)

#define	MIPS32_ISA_ADDIU(tar, src, val) MIPS32_I_INST(MIPS32_OP_ADDIU, src, tar, val)

#define	MIPS32_ISA_ADDU(dst, src, tar) MIPS32_R_INST(MIPS32_OP_SPECIAL, src, tar, dst, 0, MIPS32_OP_ADDU)

#define	MIPS32_ISA_AND(dst, src, tar) MIPS32_R_INST(0, src, tar, dst, 0, MIPS32_OP_AND)

#define	MIPS32_ISA_ANDI(tar, src, val) MIPS32_I_INST(MIPS32_OP_ANDI, src, tar, val)

#define	MIPS32_ISA_B(off) MIPS32_ISA_BEQ(0, 0, off)

#define	MIPS32_ISA_BEQ(src, tar, off) MIPS32_I_INST(MIPS32_OP_BEQ, src, tar, off)

#define	MIPS32_ISA_BGTZ(reg, off) MIPS32_I_INST(MIPS32_OP_BGTZ, reg, 0, off)

#define	MIPS32_ISA_BNE(src, tar, off) MIPS32_I_INST(MIPS32_OP_BNE, src, tar, off)

#define	MIPS32_ISA_CACHE(op, off, base) MIPS32_I_INST(MIPS32_OP_CACHE, base, op, off)

#define	MIPS32_ISA_CFC1(gpr, cpr) MIPS32_R_INST(MIPS32_OP_COP1, MIPS32_COP_CF, gpr, cpr, 0, 0)

#define	MIPS32_ISA_DRET 0x4200001Fu

#define	MIPS32_ISA_J(tar) MIPS32_J_INST(MIPS32_OP_J, (0x0FFFFFFFu & (tar)) >> 2)

#define	MIPS32_ISA_JR(reg) MIPS32_R_INST(0, reg, 0, 0, 0, MIPS32_OP_JR)

#define	MIPS32_ISA_JRHB(reg) MIPS32_R_INST(0, reg, 0, 0, 0x10, MIPS32_OP_JR)

#define	MIPS32_ISA_LB(reg, off, base) MIPS32_I_INST(MIPS32_OP_LB, base, reg, off)

#define	MIPS32_ISA_LBU(reg, off, base) MIPS32_I_INST(MIPS32_OP_LBU, base, reg, off)

#define	MIPS32_ISA_LDC1(reg, off, base) MIPS32_I_INST(MIPS32_OP_LDC1, base, reg, off)

#define	MIPS32_ISA_LHU(reg, off, base) MIPS32_I_INST(MIPS32_OP_LHU, base, reg, off)

#define	MIPS32_ISA_LUI(reg, val) MIPS32_I_INST(MIPS32_OP_LUI, 0, reg, val)

#define	MIPS32_ISA_LW(reg, off, base) MIPS32_I_INST(MIPS32_OP_LW, base, reg, off)

#define	MIPS32_ISA_LWC1(reg, off, base) MIPS32_I_INST(MIPS32_OP_LWC1, base, reg, off)

#define	MIPS32_ISA_MFC0(gpr, cpr, sel) MIPS32_R_INST(MIPS32_OP_COP0, MIPS32_COP_MF, gpr, cpr, 0, sel)

#define	MIPS32_ISA_MFC1(gpr, cpr) MIPS32_R_INST(MIPS32_OP_COP1, MIPS32_COP_MF, gpr, cpr, 0, 0)

#define	MIPS32_ISA_MFHC1(gpr, cpr) MIPS32_R_INST(MIPS32_OP_COP1, MIPS32_COP_MFH, gpr, cpr, 0, 0)

#define	MIPS32_ISA_MFHI(reg) MIPS32_R_INST(0, 0, 0, reg, 0, MIPS32_OP_MFHI)

#define	MIPS32_ISA_MFLO(reg) MIPS32_R_INST(0, 0, 0, reg, 0, MIPS32_OP_MFLO)

#define	MIPS32_ISA_MOVN(dst, src, tar) MIPS32_R_INST(MIPS32_OP_SPECIAL, src, tar, dst, 0, MIPS32_OP_MOVN)

#define	MIPS32_ISA_MTC0(gpr, cpr, sel) MIPS32_R_INST(MIPS32_OP_COP0, MIPS32_COP_MT, gpr, cpr, 0, sel)

#define	MIPS32_ISA_MTC1(gpr, cpr) MIPS32_R_INST(MIPS32_OP_COP1, MIPS32_COP_MT, gpr, cpr, 0, 0)

#define	MIPS32_ISA_MTHC1(gpr, cpr) MIPS32_R_INST(MIPS32_OP_COP1, MIPS32_COP_MTH, gpr, cpr, 0, 0)

#define	MIPS32_ISA_MTHI(reg) MIPS32_R_INST(0, reg, 0, 0, 0, MIPS32_OP_MTHI)

#define	MIPS32_ISA_MTLO(reg) MIPS32_R_INST(0, reg, 0, 0, 0, MIPS32_OP_MTLO)

#define	MIPS32_ISA_MUL(dst, src, t) MIPS32_R_INST(28, src, t, dst, 0, MIPS32_OP_MUL)

#define	MIPS32_ISA_NOP 0

#define	MIPS32_ISA_OR(dst, src, val) MIPS32_R_INST(0, src, val, dst, 0, 37)

#define	MIPS32_ISA_ORI(tar, src, val) MIPS32_I_INST(MIPS32_OP_ORI, src, tar, val)

#define	MIPS32_ISA_RDHWR(tar, dst) MIPS32_R_INST(MIPS32_OP_SPECIAL3, 0, tar, dst, 0, MIPS32_OP_RDHWR)

#define	MIPS32_ISA_SB(reg, off, base) MIPS32_I_INST(MIPS32_OP_SB, base, reg, off)

#define	MIPS32_ISA_SDBBP 0x7000003Fu

#define	MIPS32_ISA_SDC1(reg, off, base) MIPS32_I_INST(MIPS32_OP_SDC1, base, reg, off)

#define	MIPS32_ISA_SH(reg, off, base) MIPS32_I_INST(MIPS32_OP_SH, base, reg, off)

#define	MIPS32_ISA_SLL(dst, src, sa) MIPS32_R_INST(MIPS32_OP_SPECIAL, 0, src, dst, sa, MIPS32_OP_SLL)

#define	MIPS32_ISA_SLLV(dst, src, sa) MIPS32_R_INST(MIPS32_OP_SPECIAL, 0, src, dst, sa, MIPS32_OP_SLLV)

#define	MIPS32_ISA_SLTI(tar, src, val) MIPS32_I_INST(MIPS32_OP_SLTI, src, tar, val)

#define	MIPS32_ISA_SLTU(dst, src, tar) MIPS32_R_INST(MIPS32_OP_SPECIAL, src, tar, dst, 0, MIPS32_OP_SLTU)

#define	MIPS32_ISA_SRA(reg, src, off) MIPS32_R_INST(MIPS32_OP_SPECIAL, 0, src, reg, off, MIPS32_OP_SRA)

#define	MIPS32_ISA_SRL(reg, src, off) MIPS32_R_INST(MIPS32_OP_SPECIAL, 0, src, reg, off, MIPS32_OP_SRL)

#define	MIPS32_ISA_SW(reg, off, base) MIPS32_I_INST(MIPS32_OP_SW, base, reg, off)

#define	MIPS32_ISA_SWC1(reg, off, base) MIPS32_I_INST(MIPS32_OP_SWC1, base, reg, off)

#define	MIPS32_ISA_SYNC 0xFu

#define	MIPS32_ISA_SYNCI(off, base) MIPS32_I_INST(MIPS32_OP_REGIMM, base, MIPS32_OP_SYNCI, off)

#define	MIPS32_ISA_SYNCI_STEP 0x1 /* reg num od address step size to be used with synci instruction */

#define	MIPS32_ISA_XOR(reg, val1, val2) MIPS32_R_INST(0, val1, val2, reg, 0, MIPS32_OP_XOR)

#define	MIPS32_ISA_XORI(tar, src, val) MIPS32_I_INST(MIPS32_OP_XORI, src, tar, val)

#define	MIPS32_J(isa, tar) (isa ? MMIPS32_J(tar) : MIPS32_ISA_J(tar))

#define	MIPS32_J_INST(opcode, addr) (((opcode) << 26) \| (addr))

#define	MIPS32_JR(isa, reg) (isa ? MMIPS32_JR(reg) : MIPS32_ISA_JR(reg))

#define	MIPS32_JRHB(isa, reg) (isa ? MMIPS32_JRHB(reg) : MIPS32_ISA_JRHB(reg))

#define	MIPS32_LB(isa, reg, off, base) (isa ? MMIPS32_LB(reg, off, base) : MIPS32_ISA_LB(reg, off, base))

#define	MIPS32_LBU(isa, reg, off, base) (isa ? MMIPS32_LBU(reg, off, base) : MIPS32_ISA_LBU(reg, off, base))

#define	MIPS32_LHU(isa, reg, off, base) (isa ? MMIPS32_LHU(reg, off, base) : MIPS32_ISA_LHU(reg, off, base))

#define	MIPS32_LUI(isa, reg, val) (isa ? MMIPS32_LUI(reg, val) : MIPS32_ISA_LUI(reg, val))

#define	MIPS32_LW(isa, reg, off, base) (isa ? MMIPS32_LW(reg, off, base) : MIPS32_ISA_LW(reg, off, base))

#define	MIPS32_LWC1(isa, reg, off, base) (isa ? MMIPS32_LWC1(reg, off, base) : MIPS32_ISA_LWC1(reg, off, base))

#define	MIPS32_MFC0(isa, gpr, cpr, sel) (isa ? MMIPS32_MFC0(gpr, cpr, sel) : MIPS32_ISA_MFC0(gpr, cpr, sel))

#define	MIPS32_MFC1(isa, gpr, cpr) (isa ? MMIPS32_MFC1(gpr, cpr) : MIPS32_ISA_MFC1(gpr, cpr))

#define	MIPS32_MFHC1(isa, gpr, cpr) (isa ? MMIPS32_MFHC1(gpr, cpr) : MIPS32_ISA_MFHC1(gpr, cpr))

#define	MIPS32_MFHI(isa, reg) (isa ? MMIPS32_MFHI(reg) : MIPS32_ISA_MFHI(reg))

#define	MIPS32_MFLO(isa, reg) (isa ? MMIPS32_MFLO(reg) : MIPS32_ISA_MFLO(reg))

#define	MIPS32_MMU_BAT 2

#define	MIPS32_MMU_DUAL_VTLB_FTLB 4

#define	MIPS32_MMU_FIXED 3

#define	MIPS32_MMU_TLB 1

#define	MIPS32_MOVN(isa, dst, src, tar) (isa ? MMIPS32_MOVN(dst, src, tar) : MIPS32_ISA_MOVN(dst, src, tar))

#define	MIPS32_MTC0(isa, gpr, cpr, sel) (isa ? MMIPS32_MTC0(gpr, cpr, sel) : MIPS32_ISA_MTC0(gpr, cpr, sel))

#define	MIPS32_MTC1(isa, gpr, cpr) (isa ? MMIPS32_MTC1(gpr, cpr) : MIPS32_ISA_MTC1(gpr, cpr))

#define	MIPS32_MTHC1(isa, gpr, cpr) (isa ? MMIPS32_MTHC1(gpr, cpr) : MIPS32_ISA_MTHC1(gpr, cpr))

#define	MIPS32_MTHI(isa, reg) (isa ? MMIPS32_MTHI(reg) : MIPS32_ISA_MTHI(reg))

#define	MIPS32_MTLO(isa, reg) (isa ? MMIPS32_MTLO(reg) : MIPS32_ISA_MTLO(reg))

#define	MIPS32_MUL(isa, dst, src, t) (MIPS32_ISA_MUL(dst, src, t))

#define	MIPS32_NOP 0 /* same for both isa's */

#define	MIPS32_NUM_CPU_ENTRIES (ARRAY_SIZE(mips32_cpu_entry))

#define	MIPS32_OP_ADD 0x20u

#define	MIPS32_OP_ADDI 0x08u

#define	MIPS32_OP_ADDIU 0x09u

#define	MIPS32_OP_ADDU 0x21u

#define	MIPS32_OP_AND 0x24u

#define	MIPS32_OP_ANDI 0x0Cu

#define	MIPS32_OP_BEQ 0x04u

#define	MIPS32_OP_BGTZ 0x07u

#define	MIPS32_OP_BNE 0x05u

#define	MIPS32_OP_CACHE 0x2Fu

#define	MIPS32_OP_COP0 0x10u

#define	MIPS32_OP_COP1 0x11u

#define	MIPS32_OP_J 0x02u

#define	MIPS32_OP_JR 0x08u

#define	MIPS32_OP_LB 0x20u

#define	MIPS32_OP_LBU 0x24u

#define	MIPS32_OP_LDC1 0x35u

#define	MIPS32_OP_LHU 0x25u

#define	MIPS32_OP_LUI 0x0Fu

#define	MIPS32_OP_LW 0x23u

#define	MIPS32_OP_LWC1 0x31u

#define	MIPS32_OP_MFHI 0x10u

#define	MIPS32_OP_MFLO 0x12u

#define	MIPS32_OP_MOVN 0x0Bu

#define	MIPS32_OP_MTHI 0x11u

#define	MIPS32_OP_MTLO 0x13u

#define	MIPS32_OP_MUL 0x02u

#define	MIPS32_OP_ORI 0x0Du

#define	MIPS32_OP_RDHWR 0x3Bu

#define	MIPS32_OP_REGIMM 0x01u

#define	MIPS32_OP_SB 0x28u

#define	MIPS32_OP_SDBBP 0x3Fu

#define	MIPS32_OP_SDC1 0x3Du

#define	MIPS32_OP_SH 0x29u

#define	MIPS32_OP_SLL 0x00u

#define	MIPS32_OP_SLLV 0x04u

#define	MIPS32_OP_SLTI 0x0Au

#define	MIPS32_OP_SLTU 0x2Bu

#define	MIPS32_OP_SPECIAL 0x00u

#define	MIPS32_OP_SPECIAL2 0x07u

#define	MIPS32_OP_SPECIAL3 0x1Fu

#define	MIPS32_OP_SRA 0x03u

#define	MIPS32_OP_SRL 0x02u

#define	MIPS32_OP_SW 0x2Bu

#define	MIPS32_OP_SWC1 0x39u

#define	MIPS32_OP_SYNCI 0x1Fu

#define	MIPS32_OP_XOR 0x26u

#define	MIPS32_OP_XORI 0x0Eu

#define	MIPS32_ORI(isa, tar, src, val) (isa ? MMIPS32_ORI(tar, src, val) : MIPS32_ISA_ORI(tar, src, val))

#define	MIPS32_R_INST(opcode, rs, rt, rd, shamt, funct) (((opcode) << 26) \| ((rs) << 21) \| ((rt) << 16) \| ((rd) << 11) \| ((shamt) << 6) \| (funct))

#define	MIPS32_RDHWR(isa, tar, dst) (isa ? MMIPS32_RDHWR(tar, dst) : MIPS32_ISA_RDHWR(tar, dst))

#define	MIPS32_REG_C0_BADVADDR_INDEX 1

#define	MIPS32_REG_C0_CAUSE_INDEX 2

#define	MIPS32_REG_C0_COUNT 5

#define	MIPS32_REG_C0_GUESTCTL1_INDEX 4

#define	MIPS32_REG_C0_PC_INDEX 3

#define	MIPS32_REG_C0_STATUS_INDEX 0

#define	MIPS32_REG_DSP_COUNT 7

#define	MIPS32_REG_DSP_DSPCTL_INDEX 6

#define	MIPS32_REG_FP_COUNT 32

#define	MIPS32_REG_FPC_COUNT 2

#define	MIPS32_REG_GP_COUNT 34

#define	MIPS32_REGLIST_C0_BADVADDR_INDEX (MIPS32_REGLIST_C0_INDEX + 1)

#define	MIPS32_REGLIST_C0_CAUSE_INDEX (MIPS32_REGLIST_C0_INDEX + 2)

#define	MIPS32_REGLIST_C0_GUESTCTL1_INDEX (MIPS32_REGLIST_C0_INDEX + 4)

#define	MIPS32_REGLIST_C0_INDEX (MIPS32_REGLIST_FPC_INDEX + MIPS32_REG_FPC_COUNT)

#define	MIPS32_REGLIST_C0_PC_INDEX (MIPS32_REGLIST_C0_INDEX + 3)

#define	MIPS32_REGLIST_C0_STATUS_INDEX (MIPS32_REGLIST_C0_INDEX + 0)

#define	MIPS32_REGLIST_DSP_DSPCTL_INDEX (MIPS32_REGLIST_DSP_INDEX + 6)

#define	MIPS32_REGLIST_DSP_INDEX (MIPS32_REGLIST_C0_INDEX + MIPS32_REG_C0_COUNT)

#define	MIPS32_REGLIST_FP_INDEX (MIPS32_REGLIST_GP_INDEX + MIPS32_REG_GP_COUNT)

#define	MIPS32_REGLIST_FPC_INDEX (MIPS32_REGLIST_FP_INDEX + MIPS32_REG_FP_COUNT)

#define	MIPS32_REGLIST_GP_INDEX 0

#define	MIPS32_S_INST(rs, rac, opcode) (((rs) << 21) \| ((rac) << 11) \| (opcode))

#define	MIPS32_SB(isa, reg, off, base) (isa ? MMIPS32_SB(reg, off, base) : MIPS32_ISA_SB(reg, off, base))

#define	MIPS32_SCAN_DELAY_LEGACY_MODE 2000000

#define	MIPS32_SDBBP(isa) (isa ? MMIPS32_SDBBP : MIPS32_ISA_SDBBP)

#define	MIPS32_SDC1(isa, reg, off, base) (isa ? MMIPS32_SDC1(reg, off, base) : MIPS32_ISA_SDC1(reg, off, base))

#define	MIPS32_SH(isa, reg, off, base) (isa ? MMIPS32_SH(reg, off, base) : MIPS32_ISA_SH(reg, off, base))

#define	MIPS32_SLL(isa, dst, src, sa) (isa ? MMIPS32_SLL(dst, src, sa) : MIPS32_ISA_SLL(dst, src, sa))

#define	MIPS32_SLLV(isa, dst, src, sa) (MIPS32_ISA_SLLV(dst, src, sa))

#define	MIPS32_SLTI(isa, tar, src, val) (isa ? MMIPS32_SLTI(tar, src, val) : MIPS32_ISA_SLTI(tar, src, val))

#define	MIPS32_SLTU(isa, dst, src, tar) (isa ? MMIPS32_SLTU(dst, src, tar) : MIPS32_ISA_SLTU(dst, src, tar))

#define	MIPS32_SRL(isa, reg, src, off) (isa ? MMIPS32_SRL(reg, src, off) : MIPS32_ISA_SRL(reg, src, off))

#define	MIPS32_SW(isa, reg, off, base) (isa ? MMIPS32_SW(reg, off, base) : MIPS32_ISA_SW(reg, off, base))

#define	MIPS32_SWC1(isa, reg, off, base) (isa ? MMIPS32_SWC1(reg, off, base) : MIPS32_ISA_SWC1(reg, off, base))

#define	MIPS32_SYNC(isa) (isa ? MMIPS32_SYNC : MIPS32_ISA_SYNC)

#define	MIPS32_SYNCI(isa, off, base) (isa ? MMIPS32_SYNCI(off, base) : MIPS32_ISA_SYNCI(off, base))

#define	MIPS32_SYNCI_STEP 0x1

#define	MIPS32_VARIANT_MASK 0x00FF

#define	MIPS32_XOR(isa, reg, val1, val2) (isa ? MMIPS32_XOR(reg, val1, val2) : MIPS32_ISA_XOR(reg, val1, val2))

#define	MIPS32_XORI(isa, tar, src, val) (isa ? MMIPS32_XORI(tar, src, val) : MIPS32_ISA_XORI(tar, src, val))

#define	MIPS32NUMCP0REGS (ARRAY_SIZE(mips32_cp0_regs))

#define	MIPS32NUMDSPREGS 7

#define	MIPS_CP0_IAPTIV 0x0008

#define	MIPS_CP0_MAPTIV_UC 0x0002

#define	MIPS_CP0_MAPTIV_UP 0x0004

#define	MIPS_CP0_MK4 0x0001

#define	MMIPS16_SDBBP 0x46C0u /* POOL16C instr */

#define	MMIPS32_ADDI(tar, src, val) MIPS32_I_INST(MMIPS32_OP_ADDI, tar, src, val)

#define	MMIPS32_ADDIU(tar, src, val) MIPS32_I_INST(MMIPS32_OP_ADDIU, tar, src, val)

#define	MMIPS32_ADDU(dst, src, tar) MIPS32_R_INST(MMIPS32_POOL32A, tar, src, dst, 0, MMIPS32_OP_ADDU)

#define	MMIPS32_AND(dst, src, tar) MIPS32_R_INST(MMIPS32_POOL32A, tar, src, dst, 0, MMIPS32_OP_AND)

#define	MMIPS32_ANDI(tar, src, val) MIPS32_I_INST(MMIPS32_OP_ANDI, tar, src, val)

#define	MMIPS32_B(off) MMIPS32_BEQ(0, 0, off)

#define	MMIPS32_BEQ(src, tar, off) MIPS32_I_INST(MMIPS32_OP_BEQ, tar, src, off)

#define	MMIPS32_BGTZ(reg, off) MIPS32_I_INST(MMIPS32_POOL32I, MMIPS32_OP_BGTZ, reg, off)

#define	MMIPS32_BNE(src, tar, off) MIPS32_I_INST(MMIPS32_OP_BNE, tar, src, off)

#define	MMIPS32_CACHE(op, off, base) MIPS32_R_INST(MMIPS32_POOL32B, op, base, MMIPS32_OP_CACHE << 1, 0, off)

#define	MMIPS32_CFC1(gpr, cpr) MIPS32_R_INST(MMIPS32_POOL32F, gpr, cpr, 0, MMIPS32_OP_CFC1, MMIPS32_POOL32FXF)

#define	MMIPS32_DRET 0x0000E37Cu /* MIPS32_R_INST(MMIPS32_POOL32A, 0, 0, 0, 0x38D, MMIPS32_POOL32AXF) */

#define	MMIPS32_J(tar) MIPS32_J_INST(MMIPS32_OP_J, ((0x07FFFFFFu & ((tar) >> 1))))

#define	MMIPS32_JR(reg) MIPS32_R_INST(MMIPS32_POOL32A, 0, reg, 0, MMIPS32_OP_JALR, MMIPS32_POOL32AXF)

#define	MMIPS32_JRHB(reg) MIPS32_R_INST(MMIPS32_POOL32A, 0, reg, 0, MMIPS32_OP_JALRHB, MMIPS32_POOL32AXF)

#define	MMIPS32_LB(reg, off, base) MIPS32_I_INST(MMIPS32_OP_LB, reg, base, off)

#define	MMIPS32_LBU(reg, off, base) MIPS32_I_INST(MMIPS32_OP_LBU, reg, base, off)

#define	MMIPS32_LDC1(reg, off, base) MIPS32_I_INST(MMIPS32_OP_LDC1, reg, base, off)

#define	MMIPS32_LHU(reg, off, base) MIPS32_I_INST(MMIPS32_OP_LHU, reg, base, off)

#define	MMIPS32_LUI(reg, val) MIPS32_I_INST(MMIPS32_POOL32I, MMIPS32_OP_LUI, reg, val)

#define	MMIPS32_LW(reg, off, base) MIPS32_I_INST(MMIPS32_OP_LW, reg, base, off)

#define	MMIPS32_LWC1(reg, off, base) MIPS32_I_INST(MMIPS32_OP_LWC1, reg, base, off)

#define	MMIPS32_MFC0(gpr, cpr, sel)

#define	MMIPS32_MFC1(gpr, cpr) MIPS32_R_INST(MMIPS32_POOL32F, gpr, cpr, 0, MMIPS32_OP_MFC1, MMIPS32_POOL32FXF)

#define	MMIPS32_MFHC1(gpr, cpr) MIPS32_R_INST(MMIPS32_POOL32F, gpr, cpr, 0, MMIPS32_OP_MFHC1, MMIPS32_POOL32FXF)

#define	MMIPS32_MFHI(reg) MIPS32_R_INST(MMIPS32_POOL32A, 0, reg, 0, MMIPS32_OP_MFHI, MMIPS32_POOL32AXF)

#define	MMIPS32_MFLO(reg) MIPS32_R_INST(MMIPS32_POOL32A, 0, reg, 0, MMIPS32_OP_MFLO, MMIPS32_POOL32AXF)

#define	MMIPS32_MOVN(dst, src, tar) MIPS32_R_INST(MMIPS32_POOL32A, tar, src, dst, 0, MMIPS32_OP_MOVN)

#define	MMIPS32_MTC0(gpr, cpr, sel)

#define	MMIPS32_MTC1(gpr, cpr) MIPS32_R_INST(MMIPS32_POOL32F, gpr, cpr, 0, MMIPS32_OP_MTC1, MMIPS32_POOL32FXF)

#define	MMIPS32_MTHC1(gpr, cpr) MIPS32_R_INST(MMIPS32_POOL32F, gpr, cpr, 0, MMIPS32_OP_MTHC1, MMIPS32_POOL32FXF)

#define	MMIPS32_MTHI(reg) MIPS32_R_INST(MMIPS32_POOL32A, 0, reg, 0, MMIPS32_OP_MTHI, MMIPS32_POOL32AXF)

#define	MMIPS32_MTLO(reg) MIPS32_R_INST(MMIPS32_POOL32A, 0, reg, 0, MMIPS32_OP_MTLO, MMIPS32_POOL32AXF)

#define	MMIPS32_NOP 0

#define	MMIPS32_OP_ADDI 0x04u

#define	MMIPS32_OP_ADDIU 0x0Cu

#define	MMIPS32_OP_ADDU 0x150u

#define	MMIPS32_OP_AND 0x250u

#define	MMIPS32_OP_ANDI 0x34u

#define	MMIPS32_OP_BEQ 0x25u

#define	MMIPS32_OP_BGTZ 0x06u

#define	MMIPS32_OP_BNE 0x2Du

#define	MMIPS32_OP_CACHE 0x06u

#define	MMIPS32_OP_CFC1 0x40u

#define	MMIPS32_OP_J 0x35u

#define	MMIPS32_OP_JALR 0x03Cu

#define	MMIPS32_OP_JALRHB 0x07Cu

#define	MMIPS32_OP_LB 0x07u

#define	MMIPS32_OP_LBU 0x05u

#define	MMIPS32_OP_LDC1 0x2Fu

#define	MMIPS32_OP_LHU 0x0Du

#define	MMIPS32_OP_LUI 0x0Du

#define	MMIPS32_OP_LW 0x3Fu

#define	MMIPS32_OP_LWC1 0x27u

#define	MMIPS32_OP_MFC0 0x03u

#define	MMIPS32_OP_MFC1 0x80u

#define	MMIPS32_OP_MFHC1 0xC0u

#define	MMIPS32_OP_MFHI 0x035u

#define	MMIPS32_OP_MFLO 0x075u

#define	MMIPS32_OP_MOVN 0x018u

#define	MMIPS32_OP_MTC0 0x0Bu

#define	MMIPS32_OP_MTC1 0xA0u

#define	MMIPS32_OP_MTHC1 0xE0u

#define	MMIPS32_OP_MTHI 0x0B5u

#define	MMIPS32_OP_MTLO 0x0F5u

#define	MMIPS32_OP_ORI 0x14u

#define	MMIPS32_OP_RDHWR 0x1ACu

#define	MMIPS32_OP_SB 0x06u

#define	MMIPS32_OP_SDC1 0x2Eu

#define	MMIPS32_OP_SH 0x0Eu

#define	MMIPS32_OP_SLL 0x000u

#define	MMIPS32_OP_SLTI 0x24u

#define	MMIPS32_OP_SLTU 0x390u

#define	MMIPS32_OP_SRL 0x040u

#define	MMIPS32_OP_SW 0x3Eu

#define	MMIPS32_OP_SWC1 0x26u

#define	MMIPS32_OP_SYNCI 0x10u

#define	MMIPS32_OP_XOR 0x310u

#define	MMIPS32_OP_XORI 0x1Cu

#define	MMIPS32_ORI(tar, src, val) MIPS32_I_INST(MMIPS32_OP_ORI, tar, src, val)

#define	MMIPS32_POOL32A 0x00u

#define	MMIPS32_POOL32AXF 0x3Cu

#define	MMIPS32_POOL32B 0x08u

#define	MMIPS32_POOL32F 0x15u

#define	MMIPS32_POOL32FXF 0x3Bu

#define	MMIPS32_POOL32I 0x10u

#define	MMIPS32_RDHWR(tar, dst) MIPS32_R_INST(MMIPS32_POOL32A, dst, tar, 0, MMIPS32_OP_RDHWR, MMIPS32_POOL32AXF)

#define	MMIPS32_SB(reg, off, base) MIPS32_I_INST(MMIPS32_OP_SB, reg, base, off)

#define	MMIPS32_SDBBP 0x0000DB7Cu /* MIPS32_R_INST(MMIPS32_POOL32A, 0, 0, 0, 0x1BD, MMIPS32_POOL32AXF) */

#define	MMIPS32_SDC1(reg, off, base) MIPS32_I_INST(MMIPS32_OP_SDC1, reg, base, off)

#define	MMIPS32_SH(reg, off, base) MIPS32_I_INST(MMIPS32_OP_SH, reg, base, off)

#define	MMIPS32_SLL(dst, src, sa) MIPS32_R_INST(MMIPS32_POOL32A, dst, src, sa, 0, MMIPS32_OP_SLL)

#define	MMIPS32_SLLV(dst, src, sa) MIPS32_R_INST(MMIPS32_POOL32A, dst, src, sa, 0, MMIPS32_OP_SLLV)

#define	MMIPS32_SLTI(tar, src, val) MIPS32_I_INST(MMIPS32_OP_SLTI, tar, src, val)

#define	MMIPS32_SLTU(dst, src, tar) MIPS32_R_INST(MMIPS32_POOL32A, tar, src, dst, 0, MMIPS32_OP_SLTU)

#define	MMIPS32_SRL(reg, src, off) MIPS32_R_INST(MMIPS32_POOL32A, reg, src, off, 0, MMIPS32_OP_SRL)

#define	MMIPS32_SW(reg, off, base) MIPS32_I_INST(MMIPS32_OP_SW, reg, base, off)

#define	MMIPS32_SWC1(reg, off, base) MIPS32_I_INST(MMIPS32_OP_SWC1, reg, base, off)

#define	MMIPS32_SYNC 0x00001A7Cu /* MIPS32_R_INST(MMIPS32_POOL32A, 0, 0, 0, 0x1ADu, MMIPS32_POOL32AXF) */

#define	MMIPS32_SYNCI(off, base) MIPS32_I_INST(MMIPS32_POOL32I, MMIPS32_OP_SYNCI, base, off)

#define	MMIPS32_SYNCI_STEP 0x1u /* reg num od address step size to be used with synci instruction */

#define	MMIPS32_XOR(reg, val1, val2) MIPS32_R_INST(MMIPS32_POOL32A, val1, val2, reg, 0, MMIPS32_OP_XOR)

#define	MMIPS32_XORI(tar, src, val) MIPS32_I_INST(MMIPS32_OP_XORI, tar, src, val)

Enumerations
enum	{ MIPS32_PC = 37 , MIPS32_FIR = 71 , MIPS32_DSPCTL = 78 , MIPS32NUMCOREREGS }

enum	mips32_dsp_imp { MIPS32_DSP_IMP_NONE = 0 , MIPS32_DSP_IMP_REV1 = 1 , MIPS32_DSP_IMP_REV2 = 2 }

enum	mips32_fp_imp { MIPS32_FP_IMP_NONE = 0 , MIPS32_FP_IMP_32 = 1 , MIPS32_FP_IMP_64 = 2 , MIPS32_FP_IMP_UNKNOWN = 3 }

enum	mips32_isa_imp { MIPS32_ONLY = 0 , MMIPS32_ONLY = 1 , MIPS32_MIPS16 = 2 , MIPS32_MMIPS32 = 3 }

enum	mips32_isa_mode { MIPS32_ISA_MIPS32 = 0 , MIPS32_ISA_MIPS16E = 1 , MIPS32_ISA_MMIPS32 = 3 }

enum	mips32_isa_rel { MIPS32_RELEASE_1 = 0 , MIPS32_RELEASE_2 = 1 , MIPS32_RELEASE_6 = 2 , MIPS32_RELEASE_UNKNOWN }

enum	mips32_isa_supported { MIPS16 , MIPS32 , MIPS64 , MICROMIPS_ONLY , MIPS32_AT_RESET_AND_MICROMIPS , MICROMIPS_AT_RESET_AND_MIPS32 }

Functions
int	mips32_arch_state (struct target *target)

int	mips32_blank_check_memory (struct target target, struct target_memory_check_block blocks, int num_blocks, uint8_t erased_value)
	Checks whether a memory region is erased. More...

struct reg_cache *	mips32_build_reg_cache (struct target *target)

int	mips32_checksum_memory (struct target target, target_addr_t address, uint32_t count, uint32_t checksum)

int	mips32_configure_break_unit (struct target *target)

int	mips32_cpu_probe (struct target *target)
	mips32_cpu_probe - Detects processor type and applies necessary quirks. More...

bool	mips32_cpu_support_hazard_barrier (struct mips_ejtag *ejtag_info)
	mips32_cpu_support_hazard_barrier - Checks CPU supports hazard barrier More...

bool	mips32_cpu_support_sync (struct mips_ejtag *ejtag_info)
	mips32_cpu_support_sync - Checks CPU supports ordering More...

int	mips32_enable_interrupts (struct target *target, int enable)

int	mips32_examine (struct target *target)

int	mips32_get_gdb_reg_list (struct target target, struct reg reg_list[], int reg_list_size, enum target_register_class reg_class)

int	mips32_init_arch_info (struct target target, struct mips32_common mips32, struct jtag_tap *tap)

int	mips32_read_config_regs (struct target *target)

int	mips32_register_commands (struct command_context *cmd_ctx)

int	mips32_restore_context (struct target *target)

int	mips32_run_algorithm (struct target target, int num_mem_params, struct mem_param mem_params, int num_reg_params, struct reg_param reg_params, target_addr_t entry_point, target_addr_t exit_point, unsigned int timeout_ms, void arch_info)

int	mips32_save_context (struct target *target)

static struct mips32_common *	target_to_mips32 (struct target *target)

Variables
const struct command_registration	mips32_command_handlers []

static const struct mips32_cp0	mips32_cp0_regs []

static const struct cpu_entry	mips32_cpu_entry []

Macro Definition Documentation

◆ EJTAG_QUIRK_PAD_DRET

#define EJTAG_QUIRK_PAD_DRET BIT(0)

Definition at line 209 of file mips32.h.

◆ KSEG0

#define KSEG0 0x80000000

Definition at line 28 of file mips32.h.

◆ KSEG1

#define KSEG1 0xa0000000

Definition at line 29 of file mips32.h.

◆ KSEG2

#define KSEG2 0xc0000000

Definition at line 30 of file mips32.h.

◆ KSEG3

#define KSEG3 0xe0000000

Definition at line 31 of file mips32.h.

◆ KSEGX

#define KSEGX ( a ) ((a) & 0xe0000000)

Returns the kernel segment base of a given address.

Definition at line 34 of file mips32.h.

◆ KUSEG

#define KUSEG 0x00000000

Memory segments (32bit kernel mode addresses) These are the traditional names used in the 32-bit universe.

Definition at line 27 of file mips32.h.

◆ MICRO_MIPS32_SDBBP

#define MICRO_MIPS32_SDBBP 0x000046C0

Definition at line 785 of file mips32.h.

◆ MICRO_MIPS_SDBBP

#define MICRO_MIPS_SDBBP 0x46C0

Definition at line 786 of file mips32.h.

◆ MIPS16_ISA_SDBBP

#define MIPS16_ISA_SDBBP 0xE801u

Definition at line 597 of file mips32.h.

◆ MIPS16_SDBBP

#define MIPS16_SDBBP ( isa ) (isa ? MMIPS16_SDBBP : MIPS16_ISA_SDBBP)

Definition at line 782 of file mips32.h.

◆ MIPS32_ADDI

#define MIPS32_ADDI	(	isa,
		tar,
		src,
		val
	)	(isa ? MMIPS32_ADDI(tar, src, val) : MIPS32_ISA_ADDI(tar, src, val))

Definition at line 720 of file mips32.h.

◆ MIPS32_ADDIU

#define MIPS32_ADDIU	(	isa,
		tar,
		src,
		val
	)	(isa ? MMIPS32_ADDIU(tar, src, val) : MIPS32_ISA_ADDIU(tar, src, val))

Definition at line 721 of file mips32.h.

◆ MIPS32_ADDU

#define MIPS32_ADDU	(	isa,
		dst,
		src,
		tar
	)	(isa ? MMIPS32_ADDU(dst, src, tar) : MIPS32_ISA_ADDU(dst, src, tar))

Definition at line 722 of file mips32.h.

◆ MIPS32_AND

#define MIPS32_AND	(	isa,
		dst,
		src,
		tar
	)	(isa ? MMIPS32_AND(dst, src, tar) : MIPS32_ISA_AND(dst, src, tar))

Definition at line 723 of file mips32.h.

◆ MIPS32_ANDI

#define MIPS32_ANDI	(	isa,
		tar,
		src,
		val
	)	(isa ? MMIPS32_ANDI(tar, src, val) : MIPS32_ISA_ANDI(tar, src, val))

Definition at line 724 of file mips32.h.

◆ MIPS32_ARCH_REL1

#define MIPS32_ARCH_REL1 0x0

Definition at line 67 of file mips32.h.

◆ MIPS32_ARCH_REL2

#define MIPS32_ARCH_REL2 0x1

Definition at line 68 of file mips32.h.

◆ MIPS32_B

#define MIPS32_B	(	isa,
		off
	)	(isa ? MMIPS32_B(off) : MIPS32_ISA_B(off))

Definition at line 726 of file mips32.h.

◆ MIPS32_BEQ

#define MIPS32_BEQ	(	isa,
		src,
		tar,
		off
	)	(isa ? MMIPS32_BEQ(src, tar, off) : MIPS32_ISA_BEQ(src, tar, off))

Definition at line 727 of file mips32.h.

◆ MIPS32_BGTZ

#define MIPS32_BGTZ	(	isa,
		reg,
		off
	)	(isa ? MMIPS32_BGTZ(reg, off) : MIPS32_ISA_BGTZ(reg, off))

Definition at line 728 of file mips32.h.

◆ MIPS32_BNE

#define MIPS32_BNE	(	isa,
		src,
		tar,
		off
	)	(isa ? MMIPS32_BNE(src, tar, off) : MIPS32_ISA_BNE(src, tar, off))

Definition at line 729 of file mips32.h.

◆ MIPS32_C0_BADVADDR

#define MIPS32_C0_BADVADDR 8

Definition at line 848 of file mips32.h.

◆ MIPS32_C0_CACHEERR

#define MIPS32_C0_CACHEERR 27

Definition at line 877 of file mips32.h.

◆ MIPS32_C0_CAUSE

#define MIPS32_C0_CAUSE 13

Definition at line 860 of file mips32.h.

◆ MIPS32_C0_COMPARE

#define MIPS32_C0_COMPARE 11

Definition at line 854 of file mips32.h.

◆ MIPS32_C0_CONFIG

#define MIPS32_C0_CONFIG 16

Definition at line 865 of file mips32.h.

◆ MIPS32_C0_CONFIG0

#define MIPS32_C0_CONFIG0 (16, 0)

Definition at line 866 of file mips32.h.

◆ MIPS32_C0_CONFIG1

#define MIPS32_C0_CONFIG1 (16, 1)

Definition at line 867 of file mips32.h.

◆ MIPS32_C0_CONFIG2

#define MIPS32_C0_CONFIG2 (16, 2)

Definition at line 868 of file mips32.h.

◆ MIPS32_C0_CONFIG3

#define MIPS32_C0_CONFIG3 (16, 3)

Definition at line 869 of file mips32.h.

◆ MIPS32_C0_CONTEXT

#define MIPS32_C0_CONTEXT 4

Definition at line 842 of file mips32.h.

◆ MIPS32_C0_COUNT

#define MIPS32_C0_COUNT 9

Definition at line 850 of file mips32.h.

◆ MIPS32_C0_CR

#define MIPS32_C0_CR 13

Definition at line 861 of file mips32.h.

◆ MIPS32_C0_CTXT

#define MIPS32_C0_CTXT 4

Definition at line 843 of file mips32.h.

◆ MIPS32_C0_DATAHI

#define MIPS32_C0_DATAHI (29, 1)

Definition at line 888 of file mips32.h.

◆ MIPS32_C0_DATALO

#define MIPS32_C0_DATALO (28, 1)

Definition at line 882 of file mips32.h.

◆ MIPS32_C0_DATALO2

#define MIPS32_C0_DATALO2 (28, 5)

Definition at line 885 of file mips32.h.

◆ MIPS32_C0_DDATALO

#define MIPS32_C0_DDATALO (28, 3)

Definition at line 884 of file mips32.h.

◆ MIPS32_C0_DEBUG

#define MIPS32_C0_DEBUG 23

Definition at line 873 of file mips32.h.

◆ MIPS32_C0_DEPC

#define MIPS32_C0_DEPC 24

Definition at line 874 of file mips32.h.

◆ MIPS32_C0_DESAVE

#define MIPS32_C0_DESAVE 31

Definition at line 890 of file mips32.h.

◆ MIPS32_C0_DTAGLO

#define MIPS32_C0_DTAGLO (28, 2)

Definition at line 880 of file mips32.h.

◆ MIPS32_C0_EBASE

#define MIPS32_C0_EBASE (15, 1)

Definition at line 864 of file mips32.h.

◆ MIPS32_C0_ENTRYHI

#define MIPS32_C0_ENTRYHI 10

Definition at line 851 of file mips32.h.

◆ MIPS32_C0_ENTRYLO0

#define MIPS32_C0_ENTRYLO0 2

Definition at line 838 of file mips32.h.

◆ MIPS32_C0_ENTRYLO1

#define MIPS32_C0_ENTRYLO1 3

Definition at line 840 of file mips32.h.

◆ MIPS32_C0_EPC

#define MIPS32_C0_EPC 14

Definition at line 862 of file mips32.h.

◆ MIPS32_C0_ERRCTL

#define MIPS32_C0_ERRCTL 26

Definition at line 876 of file mips32.h.

◆ MIPS32_C0_ERRPC

#define MIPS32_C0_ERRPC 30

Definition at line 889 of file mips32.h.

◆ MIPS32_C0_GUESTCTL1

#define MIPS32_C0_GUESTCTL1 10

Definition at line 853 of file mips32.h.

◆ MIPS32_C0_HWRENA

#define MIPS32_C0_HWRENA 7

Definition at line 847 of file mips32.h.

◆ MIPS32_C0_IDATALO

#define MIPS32_C0_IDATALO (28, 1)

Definition at line 883 of file mips32.h.

◆ MIPS32_C0_INDEX

#define MIPS32_C0_INDEX 0

Definition at line 834 of file mips32.h.

◆ MIPS32_C0_INTCTL

#define MIPS32_C0_INTCTL (12, 1)

Definition at line 857 of file mips32.h.

◆ MIPS32_C0_INX

#define MIPS32_C0_INX 0

Definition at line 835 of file mips32.h.

◆ MIPS32_C0_ITAGHI

#define MIPS32_C0_ITAGHI 29

Definition at line 887 of file mips32.h.

◆ MIPS32_C0_ITAGLO

#define MIPS32_C0_ITAGLO 28

Definition at line 879 of file mips32.h.

◆ MIPS32_C0_LLADDR

#define MIPS32_C0_LLADDR 17

Definition at line 870 of file mips32.h.

◆ MIPS32_C0_PAGEGRAIN

#define MIPS32_C0_PAGEGRAIN (5, 1)

Definition at line 845 of file mips32.h.

◆ MIPS32_C0_PAGEMASK

#define MIPS32_C0_PAGEMASK 5

Definition at line 844 of file mips32.h.

◆ MIPS32_C0_PERFCNT

#define MIPS32_C0_PERFCNT 25

Definition at line 875 of file mips32.h.

◆ MIPS32_C0_PRID

#define MIPS32_C0_PRID 15

Definition at line 863 of file mips32.h.

◆ MIPS32_C0_RAND

#define MIPS32_C0_RAND 1

Definition at line 837 of file mips32.h.

◆ MIPS32_C0_RANDOM

#define MIPS32_C0_RANDOM 1

Definition at line 836 of file mips32.h.

◆ MIPS32_C0_SR

#define MIPS32_C0_SR 12

Definition at line 856 of file mips32.h.

◆ MIPS32_C0_SRSCTL

#define MIPS32_C0_SRSCTL (12, 2)

Definition at line 858 of file mips32.h.

◆ MIPS32_C0_SRSMAP

#define MIPS32_C0_SRSMAP (12, 3)

Definition at line 859 of file mips32.h.

◆ MIPS32_C0_STATUS

#define MIPS32_C0_STATUS 12

Definition at line 855 of file mips32.h.

◆ MIPS32_C0_TAGHI

#define MIPS32_C0_TAGHI 29

Definition at line 886 of file mips32.h.

◆ MIPS32_C0_TAGLO

#define MIPS32_C0_TAGLO 28

Definition at line 878 of file mips32.h.

◆ MIPS32_C0_TAGLO2

#define MIPS32_C0_TAGLO2 (28, 4)

Definition at line 881 of file mips32.h.

◆ MIPS32_C0_TLBHI

#define MIPS32_C0_TLBHI 10

Definition at line 852 of file mips32.h.

◆ MIPS32_C0_TLBLO0

#define MIPS32_C0_TLBLO0 2

Definition at line 839 of file mips32.h.

◆ MIPS32_C0_TLBLO1

#define MIPS32_C0_TLBLO1 3

Definition at line 841 of file mips32.h.

◆ MIPS32_C0_VADDR

#define MIPS32_C0_VADDR 8

Definition at line 849 of file mips32.h.

◆ MIPS32_C0_WATCHHI

#define MIPS32_C0_WATCHHI 19

Definition at line 872 of file mips32.h.

◆ MIPS32_C0_WATCHLO

#define MIPS32_C0_WATCHLO 18

Definition at line 871 of file mips32.h.

◆ MIPS32_C0_WIRED

#define MIPS32_C0_WIRED 6

Definition at line 846 of file mips32.h.

◆ MIPS32_CACHE

#define MIPS32_CACHE	(	isa,
		op,
		off,
		base
	)	(isa ? MMIPS32_CACHE(op, off, base) : MIPS32_ISA_CACHE(op, off, base))

Definition at line 730 of file mips32.h.

◆ MIPS32_CACHE_D_HIT_WRITEBACK

#define MIPS32_CACHE_D_HIT_WRITEBACK ((0x1 << 0) | (0x6 << 2))

Cache operations definitions Operation field is 5 bits long : 1) bits 1..0 hold cache type 2) bits 4..2 hold operation code.

Definition at line 590 of file mips32.h.

◆ MIPS32_CACHE_I_HIT_INVALIDATE

#define MIPS32_CACHE_I_HIT_INVALIDATE ((0x0 << 0) | (0x4 << 2))

Definition at line 591 of file mips32.h.

◆ MIPS32_CFC1

#define MIPS32_CFC1	(	isa,
		gpr,
		cpr
	)	(isa ? MMIPS32_CFC1(gpr, cpr) : MIPS32_ISA_CFC1(gpr, cpr))

Definition at line 731 of file mips32.h.

◆ MIPS32_CFG1_C2

#define MIPS32_CFG1_C2 0x00000040 /* Coprocessor 2 present */

Definition at line 823 of file mips32.h.

◆ MIPS32_CFG1_CA

#define MIPS32_CFG1_CA 0x00000004 /* compression (mips16) implemented */

Definition at line 827 of file mips32.h.

◆ MIPS32_CFG1_DAMASK

#define MIPS32_CFG1_DAMASK 0x00000380 /* dcache ways - 1 */

Definition at line 821 of file mips32.h.

◆ MIPS32_CFG1_DASHIFT

#define MIPS32_CFG1_DASHIFT 7

Definition at line 822 of file mips32.h.

◆ MIPS32_CFG1_DLMASK

#define MIPS32_CFG1_DLMASK 0x00001c00 /* dcache line size 2<<n */

Definition at line 819 of file mips32.h.

◆ MIPS32_CFG1_DLSHIFT

#define MIPS32_CFG1_DLSHIFT 10

Definition at line 820 of file mips32.h.

◆ MIPS32_CFG1_DSMASK

#define MIPS32_CFG1_DSMASK 0x0000e000 /* dcache lines 64<<n */

Definition at line 817 of file mips32.h.

◆ MIPS32_CFG1_DSSHIFT

#define MIPS32_CFG1_DSSHIFT 13

Definition at line 818 of file mips32.h.

◆ MIPS32_CFG1_EP

#define MIPS32_CFG1_EP 0x00000002 /* ejtag implemented */

Definition at line 828 of file mips32.h.

◆ MIPS32_CFG1_FP

#define MIPS32_CFG1_FP 0x00000001 /* fpu implemented */

Definition at line 829 of file mips32.h.

◆ MIPS32_CFG1_IAMASK

#define MIPS32_CFG1_IAMASK 0x00070000 /* icache ways - 1 */

Definition at line 815 of file mips32.h.

◆ MIPS32_CFG1_IASHIFT

#define MIPS32_CFG1_IASHIFT 16

Definition at line 816 of file mips32.h.

◆ MIPS32_CFG1_ILMASK

#define MIPS32_CFG1_ILMASK 0x00380000 /* icache line size 2<<n */

Definition at line 813 of file mips32.h.

◆ MIPS32_CFG1_ILSHIFT

#define MIPS32_CFG1_ILSHIFT 19

Definition at line 814 of file mips32.h.

◆ MIPS32_CFG1_ISMASK

#define MIPS32_CFG1_ISMASK 0x01c00000 /* icache lines 64<<n */

Definition at line 811 of file mips32.h.

◆ MIPS32_CFG1_ISSHIFT

#define MIPS32_CFG1_ISSHIFT 22

Definition at line 812 of file mips32.h.

◆ MIPS32_CFG1_M

#define MIPS32_CFG1_M 0x80000000 /* Config2 implemented */

Definition at line 808 of file mips32.h.

◆ MIPS32_CFG1_MD

#define MIPS32_CFG1_MD 0x00000020 /* MDMX implemented */

Definition at line 824 of file mips32.h.

◆ MIPS32_CFG1_MMUSMASK

#define MIPS32_CFG1_MMUSMASK 0x7e000000 /* mmu size - 1 */

Definition at line 809 of file mips32.h.

◆ MIPS32_CFG1_MMUSSHIFT

#define MIPS32_CFG1_MMUSSHIFT 25

Definition at line 810 of file mips32.h.

◆ MIPS32_CFG1_PC

#define MIPS32_CFG1_PC 0x00000010 /* performance counters implemented */

Definition at line 825 of file mips32.h.

◆ MIPS32_CFG1_WR

#define MIPS32_CFG1_WR 0x00000008 /* watch registers implemented */

Definition at line 826 of file mips32.h.

◆ MIPS32_COMMON_MAGIC

#define MIPS32_COMMON_MAGIC 0xB320B320U

Definition at line 21 of file mips32.h.

◆ MIPS32_CONFIG0_AR_MASK

#define MIPS32_CONFIG0_AR_MASK (0x7 << MIPS32_CONFIG0_AR_SHIFT)

Definition at line 47 of file mips32.h.

◆ MIPS32_CONFIG0_AR_SHIFT

#define MIPS32_CONFIG0_AR_SHIFT 10

Definition at line 46 of file mips32.h.

◆ MIPS32_CONFIG0_K0_MASK

#define MIPS32_CONFIG0_K0_MASK (0x7 << MIPS32_CONFIG0_K0_SHIFT)

Definition at line 41 of file mips32.h.

◆ MIPS32_CONFIG0_K0_SHIFT

#define MIPS32_CONFIG0_K0_SHIFT 0

Definition at line 40 of file mips32.h.

◆ MIPS32_CONFIG0_K23_MASK

#define MIPS32_CONFIG0_K23_MASK (0x7 << MIPS32_CONFIG0_K23_SHIFT)

Definition at line 44 of file mips32.h.

◆ MIPS32_CONFIG0_K23_SHIFT

#define MIPS32_CONFIG0_K23_SHIFT 28

Definition at line 43 of file mips32.h.

◆ MIPS32_CONFIG0_KU_MASK

#define MIPS32_CONFIG0_KU_MASK (0x7 << MIPS32_CONFIG0_KU_SHIFT)

Definition at line 38 of file mips32.h.

◆ MIPS32_CONFIG0_KU_SHIFT

#define MIPS32_CONFIG0_KU_SHIFT 25

CP0 CONFIG register fields.

Definition at line 37 of file mips32.h.

◆ MIPS32_CONFIG1_DL_MASK

#define MIPS32_CONFIG1_DL_MASK (0x7 << MIPS32_CONFIG1_DL_SHIFT)

Definition at line 53 of file mips32.h.

◆ MIPS32_CONFIG1_DL_SHIFT

#define MIPS32_CONFIG1_DL_SHIFT 10

Definition at line 52 of file mips32.h.

◆ MIPS32_CONFIG1_FP_MASK

#define MIPS32_CONFIG1_FP_MASK BIT(MIPS32_CONFIG1_FP_SHIFT)

Definition at line 50 of file mips32.h.

◆ MIPS32_CONFIG1_FP_SHIFT

#define MIPS32_CONFIG1_FP_SHIFT 0

Definition at line 49 of file mips32.h.

◆ MIPS32_CONFIG3_CDMM_MASK

#define MIPS32_CONFIG3_CDMM_MASK BIT(MIPS32_CONFIG3_CDMM_SHIFT)

Definition at line 56 of file mips32.h.

◆ MIPS32_CONFIG3_CDMM_SHIFT

#define MIPS32_CONFIG3_CDMM_SHIFT 3

Definition at line 55 of file mips32.h.

◆ MIPS32_CONFIG3_DSPP_MASK

#define MIPS32_CONFIG3_DSPP_MASK BIT(MIPS32_CONFIG3_DSPP_SHIFT)

Definition at line 59 of file mips32.h.

◆ MIPS32_CONFIG3_DSPP_SHIFT

#define MIPS32_CONFIG3_DSPP_SHIFT 10

Definition at line 58 of file mips32.h.

◆ MIPS32_CONFIG3_DSPREV_MASK

#define MIPS32_CONFIG3_DSPREV_MASK BIT(MIPS32_CONFIG3_DSPREV_SHIFT)

Definition at line 62 of file mips32.h.

◆ MIPS32_CONFIG3_DSPREV_SHIFT

#define MIPS32_CONFIG3_DSPREV_SHIFT 11

Definition at line 61 of file mips32.h.

◆ MIPS32_CONFIG3_ISA_MASK

#define MIPS32_CONFIG3_ISA_MASK (3 << MIPS32_CONFIG3_ISA_SHIFT)

Definition at line 65 of file mips32.h.

◆ MIPS32_CONFIG3_ISA_SHIFT

#define MIPS32_CONFIG3_ISA_SHIFT 14

Definition at line 64 of file mips32.h.

◆ MIPS32_COP_CF

#define MIPS32_COP_CF 0x02u

Definition at line 511 of file mips32.h.

◆ MIPS32_COP_MF

#define MIPS32_COP_MF 0x00u

Definition at line 510 of file mips32.h.

◆ MIPS32_COP_MFH

#define MIPS32_COP_MFH 0x03u

Definition at line 512 of file mips32.h.

◆ MIPS32_COP_MT

#define MIPS32_COP_MT 0x04u

Definition at line 513 of file mips32.h.

◆ MIPS32_COP_MTH

#define MIPS32_COP_MTH 0x07u

Definition at line 514 of file mips32.h.

◆ MIPS32_CORE_MASK

#define MIPS32_CORE_MASK 0xFFFFFF00

Definition at line 282 of file mips32.h.

◆ MIPS32_CP0_STATUS_CU1_SHIFT

#define MIPS32_CP0_STATUS_CU1_SHIFT 29

Definition at line 83 of file mips32.h.

◆ MIPS32_CP0_STATUS_FR_SHIFT

#define MIPS32_CP0_STATUS_FR_SHIFT 26

Definition at line 82 of file mips32.h.

◆ MIPS32_CP0_STATUS_MX_SHIFT

#define MIPS32_CP0_STATUS_MX_SHIFT 24

Definition at line 81 of file mips32.h.

◆ MIPS32_CP1_FIR_F64_SHIFT

#define MIPS32_CP1_FIR_F64_SHIFT 22

Definition at line 86 of file mips32.h.

◆ MIPS32_DRET

#define MIPS32_DRET ( isa ) (isa ? MMIPS32_DRET : MIPS32_ISA_DRET)

Definition at line 779 of file mips32.h.

◆ MIPS32_DSP_ENABLE

#define MIPS32_DSP_ENABLE 0x1000000

Definition at line 787 of file mips32.h.

◆ MIPS32_DSP_MFHI

#define MIPS32_DSP_MFHI	(	reg,
		ac
	)	MIPS32_R_INST(0, ac, 0, reg, 0, MIPS32_OP_MFHI)

Definition at line 797 of file mips32.h.

◆ MIPS32_DSP_MFLO

#define MIPS32_DSP_MFLO	(	reg,
		ac
	)	MIPS32_R_INST(0, ac, 0, reg, 0, MIPS32_OP_MFLO)

Definition at line 798 of file mips32.h.

◆ MIPS32_DSP_MTHI

#define MIPS32_DSP_MTHI	(	reg,
		ac
	)	MIPS32_S_INST(reg, ac, MIPS32_OP_MTHI)

Definition at line 800 of file mips32.h.

◆ MIPS32_DSP_MTLO

#define MIPS32_DSP_MTLO	(	reg,
		ac
	)	MIPS32_S_INST(reg, ac, MIPS32_OP_MTLO)

Definition at line 799 of file mips32.h.

◆ MIPS32_DSP_R_INST

#define MIPS32_DSP_R_INST	(	rt,
		immd,
		opcode,
		extrw
	)	((0x1F << 26) \| ((immd) << 16) \| ((rt) << 11) \| ((opcode) << 6) \| (extrw))

Definition at line 792 of file mips32.h.

◆ MIPS32_DSP_RDDSP

#define MIPS32_DSP_RDDSP	(	rt,
		mask
	)	MIPS32_DSP_R_INST(rt, mask, 0x12, 0x38)

Definition at line 801 of file mips32.h.

◆ MIPS32_DSP_W_INST

#define MIPS32_DSP_W_INST	(	rs,
		immd,
		opcode,
		extrw
	)	((0x1F << 26) \| ((rs) << 21) \| ((immd) << 11) \| ((opcode) << 6) \| (extrw))

Definition at line 794 of file mips32.h.

◆ MIPS32_DSP_WRDSP

#define MIPS32_DSP_WRDSP	(	rs,
		mask
	)	MIPS32_DSP_W_INST(rs, mask, 0x13, 0x38)

Definition at line 802 of file mips32.h.

◆ MIPS32_EHB

#define MIPS32_EHB ( isa ) (isa ? MMIPS32_SLL(0, 0, 3) : MIPS32_ISA_SLL(0, 0, 3))

Definition at line 765 of file mips32.h.

◆ MIPS32_I_INST

#define MIPS32_I_INST	(	opcode,
		rs,
		rt,
		immd
	)	(((opcode) << 26) \| ((rs) << 21) \| ((rt) << 16) \| (immd))

Definition at line 518 of file mips32.h.

◆ MIPS32_ISA_ADD

#define MIPS32_ISA_ADD	(	dst,
		src,
		tar
	)	MIPS32_R_INST(MIPS32_OP_SPECIAL, src, tar, dst, 0, MIPS32_OP_ADD)

Definition at line 523 of file mips32.h.

◆ MIPS32_ISA_ADDI

#define MIPS32_ISA_ADDI	(	tar,
		src,
		val
	)	MIPS32_I_INST(MIPS32_OP_ADDI, src, tar, val)

Definition at line 524 of file mips32.h.

◆ MIPS32_ISA_ADDIU

#define MIPS32_ISA_ADDIU	(	tar,
		src,
		val
	)	MIPS32_I_INST(MIPS32_OP_ADDIU, src, tar, val)

Definition at line 525 of file mips32.h.

◆ MIPS32_ISA_ADDU

#define MIPS32_ISA_ADDU	(	dst,
		src,
		tar
	)	MIPS32_R_INST(MIPS32_OP_SPECIAL, src, tar, dst, 0, MIPS32_OP_ADDU)

Definition at line 526 of file mips32.h.

◆ MIPS32_ISA_AND

#define MIPS32_ISA_AND	(	dst,
		src,
		tar
	)	MIPS32_R_INST(0, src, tar, dst, 0, MIPS32_OP_AND)

Definition at line 527 of file mips32.h.

◆ MIPS32_ISA_ANDI

#define MIPS32_ISA_ANDI	(	tar,
		src,
		val
	)	MIPS32_I_INST(MIPS32_OP_ANDI, src, tar, val)

Definition at line 528 of file mips32.h.

◆ MIPS32_ISA_B

#define MIPS32_ISA_B ( off ) MIPS32_ISA_BEQ(0, 0, off)

Definition at line 530 of file mips32.h.

◆ MIPS32_ISA_BEQ

#define MIPS32_ISA_BEQ	(	src,
		tar,
		off
	)	MIPS32_I_INST(MIPS32_OP_BEQ, src, tar, off)

Definition at line 531 of file mips32.h.

◆ MIPS32_ISA_BGTZ

#define MIPS32_ISA_BGTZ	(	reg,
		off
	)	MIPS32_I_INST(MIPS32_OP_BGTZ, reg, 0, off)

Definition at line 532 of file mips32.h.

◆ MIPS32_ISA_BNE

#define MIPS32_ISA_BNE	(	src,
		tar,
		off
	)	MIPS32_I_INST(MIPS32_OP_BNE, src, tar, off)

Definition at line 533 of file mips32.h.

◆ MIPS32_ISA_CACHE

#define MIPS32_ISA_CACHE	(	op,
		off,
		base
	)	MIPS32_I_INST(MIPS32_OP_CACHE, base, op, off)

Definition at line 534 of file mips32.h.

◆ MIPS32_ISA_CFC1

#define MIPS32_ISA_CFC1	(	gpr,
		cpr
	)	MIPS32_R_INST(MIPS32_OP_COP1, MIPS32_COP_CF, gpr, cpr, 0, 0)

Definition at line 535 of file mips32.h.

◆ MIPS32_ISA_DRET

#define MIPS32_ISA_DRET 0x4200001Fu

Definition at line 594 of file mips32.h.

◆ MIPS32_ISA_J

#define MIPS32_ISA_J ( tar ) MIPS32_J_INST(MIPS32_OP_J, (0x0FFFFFFFu & (tar)) >> 2)

Definition at line 536 of file mips32.h.

◆ MIPS32_ISA_JR

#define MIPS32_ISA_JR ( reg ) MIPS32_R_INST(0, reg, 0, 0, 0, MIPS32_OP_JR)

Definition at line 537 of file mips32.h.

◆ MIPS32_ISA_JRHB

#define MIPS32_ISA_JRHB ( reg ) MIPS32_R_INST(0, reg, 0, 0, 0x10, MIPS32_OP_JR)

Definition at line 538 of file mips32.h.

◆ MIPS32_ISA_LB

#define MIPS32_ISA_LB	(	reg,
		off,
		base
	)	MIPS32_I_INST(MIPS32_OP_LB, base, reg, off)

Definition at line 540 of file mips32.h.

◆ MIPS32_ISA_LBU

#define MIPS32_ISA_LBU	(	reg,
		off,
		base
	)	MIPS32_I_INST(MIPS32_OP_LBU, base, reg, off)

Definition at line 541 of file mips32.h.

◆ MIPS32_ISA_LDC1

#define MIPS32_ISA_LDC1	(	reg,
		off,
		base
	)	MIPS32_I_INST(MIPS32_OP_LDC1, base, reg, off)

Definition at line 546 of file mips32.h.

◆ MIPS32_ISA_LHU

#define MIPS32_ISA_LHU	(	reg,
		off,
		base
	)	MIPS32_I_INST(MIPS32_OP_LHU, base, reg, off)

Definition at line 542 of file mips32.h.

◆ MIPS32_ISA_LUI

#define MIPS32_ISA_LUI	(	reg,
		val
	)	MIPS32_I_INST(MIPS32_OP_LUI, 0, reg, val)

Definition at line 543 of file mips32.h.

◆ MIPS32_ISA_LW

#define MIPS32_ISA_LW	(	reg,
		off,
		base
	)	MIPS32_I_INST(MIPS32_OP_LW, base, reg, off)

Definition at line 544 of file mips32.h.

◆ MIPS32_ISA_LWC1

#define MIPS32_ISA_LWC1	(	reg,
		off,
		base
	)	MIPS32_I_INST(MIPS32_OP_LWC1, base, reg, off)

Definition at line 545 of file mips32.h.

◆ MIPS32_ISA_MFC0

#define MIPS32_ISA_MFC0	(	gpr,
		cpr,
		sel
	)	MIPS32_R_INST(MIPS32_OP_COP0, MIPS32_COP_MF, gpr, cpr, 0, sel)

Definition at line 548 of file mips32.h.

◆ MIPS32_ISA_MFC1

#define MIPS32_ISA_MFC1	(	gpr,
		cpr
	)	MIPS32_R_INST(MIPS32_OP_COP1, MIPS32_COP_MF, gpr, cpr, 0, 0)

Definition at line 550 of file mips32.h.

◆ MIPS32_ISA_MFHC1

#define MIPS32_ISA_MFHC1	(	gpr,
		cpr
	)	MIPS32_R_INST(MIPS32_OP_COP1, MIPS32_COP_MFH, gpr, cpr, 0, 0)

Definition at line 551 of file mips32.h.

◆ MIPS32_ISA_MFHI

#define MIPS32_ISA_MFHI ( reg ) MIPS32_R_INST(0, 0, 0, reg, 0, MIPS32_OP_MFHI)

Definition at line 555 of file mips32.h.

◆ MIPS32_ISA_MFLO

#define MIPS32_ISA_MFLO ( reg ) MIPS32_R_INST(0, 0, 0, reg, 0, MIPS32_OP_MFLO)

Definition at line 554 of file mips32.h.

◆ MIPS32_ISA_MOVN

#define MIPS32_ISA_MOVN	(	dst,
		src,
		tar
	)	MIPS32_R_INST(MIPS32_OP_SPECIAL, src, tar, dst, 0, MIPS32_OP_MOVN)

Definition at line 560 of file mips32.h.

◆ MIPS32_ISA_MTC0

#define MIPS32_ISA_MTC0	(	gpr,
		cpr,
		sel
	)	MIPS32_R_INST(MIPS32_OP_COP0, MIPS32_COP_MT, gpr, cpr, 0, sel)

Definition at line 549 of file mips32.h.

◆ MIPS32_ISA_MTC1

#define MIPS32_ISA_MTC1	(	gpr,
		cpr
	)	MIPS32_R_INST(MIPS32_OP_COP1, MIPS32_COP_MT, gpr, cpr, 0, 0)

Definition at line 552 of file mips32.h.

◆ MIPS32_ISA_MTHC1

#define MIPS32_ISA_MTHC1	(	gpr,
		cpr
	)	MIPS32_R_INST(MIPS32_OP_COP1, MIPS32_COP_MTH, gpr, cpr, 0, 0)

Definition at line 553 of file mips32.h.

◆ MIPS32_ISA_MTHI

#define MIPS32_ISA_MTHI ( reg ) MIPS32_R_INST(0, reg, 0, 0, 0, MIPS32_OP_MTHI)

Definition at line 557 of file mips32.h.

◆ MIPS32_ISA_MTLO

#define MIPS32_ISA_MTLO ( reg ) MIPS32_R_INST(0, reg, 0, 0, 0, MIPS32_OP_MTLO)

Definition at line 556 of file mips32.h.

◆ MIPS32_ISA_MUL

#define MIPS32_ISA_MUL	(	dst,
		src,
		t
	)	MIPS32_R_INST(28, src, t, dst, 0, MIPS32_OP_MUL)

Definition at line 559 of file mips32.h.

◆ MIPS32_ISA_NOP

#define MIPS32_ISA_NOP 0

Definition at line 522 of file mips32.h.

◆ MIPS32_ISA_OR

#define MIPS32_ISA_OR	(	dst,
		src,
		val
	)	MIPS32_R_INST(0, src, val, dst, 0, 37)

Definition at line 561 of file mips32.h.

◆ MIPS32_ISA_ORI

#define MIPS32_ISA_ORI	(	tar,
		src,
		val
	)	MIPS32_I_INST(MIPS32_OP_ORI, src, tar, val)

Definition at line 562 of file mips32.h.

◆ MIPS32_ISA_RDHWR

#define MIPS32_ISA_RDHWR	(	tar,
		dst
	)	MIPS32_R_INST(MIPS32_OP_SPECIAL3, 0, tar, dst, 0, MIPS32_OP_RDHWR)

Definition at line 563 of file mips32.h.

◆ MIPS32_ISA_SB

#define MIPS32_ISA_SB	(	reg,
		off,
		base
	)	MIPS32_I_INST(MIPS32_OP_SB, base, reg, off)

Definition at line 564 of file mips32.h.

◆ MIPS32_ISA_SDBBP

#define MIPS32_ISA_SDBBP 0x7000003Fu

Definition at line 596 of file mips32.h.

◆ MIPS32_ISA_SDC1

#define MIPS32_ISA_SDC1	(	reg,
		off,
		base
	)	MIPS32_I_INST(MIPS32_OP_SDC1, base, reg, off)

Definition at line 568 of file mips32.h.

◆ MIPS32_ISA_SH

#define MIPS32_ISA_SH	(	reg,
		off,
		base
	)	MIPS32_I_INST(MIPS32_OP_SH, base, reg, off)

Definition at line 565 of file mips32.h.

◆ MIPS32_ISA_SLL

#define MIPS32_ISA_SLL	(	dst,
		src,
		sa
	)	MIPS32_R_INST(MIPS32_OP_SPECIAL, 0, src, dst, sa, MIPS32_OP_SLL)

Definition at line 570 of file mips32.h.

◆ MIPS32_ISA_SLLV

#define MIPS32_ISA_SLLV	(	dst,
		src,
		sa
	)	MIPS32_R_INST(MIPS32_OP_SPECIAL, 0, src, dst, sa, MIPS32_OP_SLLV)

Definition at line 571 of file mips32.h.

◆ MIPS32_ISA_SLTI

#define MIPS32_ISA_SLTI	(	tar,
		src,
		val
	)	MIPS32_I_INST(MIPS32_OP_SLTI, src, tar, val)

Definition at line 572 of file mips32.h.

◆ MIPS32_ISA_SLTU

#define MIPS32_ISA_SLTU	(	dst,
		src,
		tar
	)	MIPS32_R_INST(MIPS32_OP_SPECIAL, src, tar, dst, 0, MIPS32_OP_SLTU)

Definition at line 573 of file mips32.h.

◆ MIPS32_ISA_SRA

#define MIPS32_ISA_SRA	(	reg,
		src,
		off
	)	MIPS32_R_INST(MIPS32_OP_SPECIAL, 0, src, reg, off, MIPS32_OP_SRA)

Definition at line 574 of file mips32.h.

◆ MIPS32_ISA_SRL

#define MIPS32_ISA_SRL	(	reg,
		src,
		off
	)	MIPS32_R_INST(MIPS32_OP_SPECIAL, 0, src, reg, off, MIPS32_OP_SRL)

Definition at line 575 of file mips32.h.

◆ MIPS32_ISA_SW

#define MIPS32_ISA_SW	(	reg,
		off,
		base
	)	MIPS32_I_INST(MIPS32_OP_SW, base, reg, off)

Definition at line 566 of file mips32.h.

◆ MIPS32_ISA_SWC1

#define MIPS32_ISA_SWC1	(	reg,
		off,
		base
	)	MIPS32_I_INST(MIPS32_OP_SWC1, base, reg, off)

Definition at line 567 of file mips32.h.

◆ MIPS32_ISA_SYNC

#define MIPS32_ISA_SYNC 0xFu

Definition at line 576 of file mips32.h.

◆ MIPS32_ISA_SYNCI

#define MIPS32_ISA_SYNCI	(	off,
		base
	)	MIPS32_I_INST(MIPS32_OP_REGIMM, base, MIPS32_OP_SYNCI, off)

Definition at line 577 of file mips32.h.

◆ MIPS32_ISA_SYNCI_STEP

#define MIPS32_ISA_SYNCI_STEP 0x1 /* reg num od address step size to be used with synci instruction */

Definition at line 582 of file mips32.h.

◆ MIPS32_ISA_XOR

#define MIPS32_ISA_XOR	(	reg,
		val1,
		val2
	)	MIPS32_R_INST(0, val1, val2, reg, 0, MIPS32_OP_XOR)

Definition at line 579 of file mips32.h.

◆ MIPS32_ISA_XORI

#define MIPS32_ISA_XORI	(	tar,
		src,
		val
	)	MIPS32_I_INST(MIPS32_OP_XORI, src, tar, val)

Definition at line 580 of file mips32.h.

◆ MIPS32_J

#define MIPS32_J	(	isa,
		tar
	)	(isa ? MMIPS32_J(tar) : MIPS32_ISA_J(tar))

Definition at line 733 of file mips32.h.

◆ MIPS32_J_INST

#define MIPS32_J_INST	(	opcode,
		addr
	)	(((opcode) << 26) \| (addr))

Definition at line 520 of file mips32.h.

◆ MIPS32_JR

#define MIPS32_JR	(	isa,
		reg
	)	(isa ? MMIPS32_JR(reg) : MIPS32_ISA_JR(reg))

Definition at line 734 of file mips32.h.

◆ MIPS32_JRHB

#define MIPS32_JRHB	(	isa,
		reg
	)	(isa ? MMIPS32_JRHB(reg) : MIPS32_ISA_JRHB(reg))

Definition at line 735 of file mips32.h.

◆ MIPS32_LB

#define MIPS32_LB	(	isa,
		reg,
		off,
		base
	)	(isa ? MMIPS32_LB(reg, off, base) : MIPS32_ISA_LB(reg, off, base))

Definition at line 736 of file mips32.h.

◆ MIPS32_LBU

#define MIPS32_LBU	(	isa,
		reg,
		off,
		base
	)	(isa ? MMIPS32_LBU(reg, off, base) : MIPS32_ISA_LBU(reg, off, base))

Definition at line 737 of file mips32.h.

◆ MIPS32_LHU

#define MIPS32_LHU	(	isa,
		reg,
		off,
		base
	)	(isa ? MMIPS32_LHU(reg, off, base) : MIPS32_ISA_LHU(reg, off, base))

Definition at line 738 of file mips32.h.

◆ MIPS32_LUI

#define MIPS32_LUI	(	isa,
		reg,
		val
	)	(isa ? MMIPS32_LUI(reg, val) : MIPS32_ISA_LUI(reg, val))

Definition at line 741 of file mips32.h.

◆ MIPS32_LW

#define MIPS32_LW	(	isa,
		reg,
		off,
		base
	)	(isa ? MMIPS32_LW(reg, off, base) : MIPS32_ISA_LW(reg, off, base))

Definition at line 739 of file mips32.h.

◆ MIPS32_LWC1

#define MIPS32_LWC1	(	isa,
		reg,
		off,
		base
	)	(isa ? MMIPS32_LWC1(reg, off, base) : MIPS32_ISA_LWC1(reg, off, base))

Definition at line 740 of file mips32.h.

◆ MIPS32_MFC0

#define MIPS32_MFC0	(	isa,
		gpr,
		cpr,
		sel
	)	(isa ? MMIPS32_MFC0(gpr, cpr, sel) : MIPS32_ISA_MFC0(gpr, cpr, sel))

Definition at line 743 of file mips32.h.

◆ MIPS32_MFC1

#define MIPS32_MFC1	(	isa,
		gpr,
		cpr
	)	(isa ? MMIPS32_MFC1(gpr, cpr) : MIPS32_ISA_MFC1(gpr, cpr))

Definition at line 745 of file mips32.h.

◆ MIPS32_MFHC1

#define MIPS32_MFHC1	(	isa,
		gpr,
		cpr
	)	(isa ? MMIPS32_MFHC1(gpr, cpr) : MIPS32_ISA_MFHC1(gpr, cpr))

Definition at line 746 of file mips32.h.

◆ MIPS32_MFHI

#define MIPS32_MFHI	(	isa,
		reg
	)	(isa ? MMIPS32_MFHI(reg) : MIPS32_ISA_MFHI(reg))

Definition at line 750 of file mips32.h.

◆ MIPS32_MFLO

#define MIPS32_MFLO	(	isa,
		reg
	)	(isa ? MMIPS32_MFLO(reg) : MIPS32_ISA_MFLO(reg))

Definition at line 749 of file mips32.h.

◆ MIPS32_MMU_BAT

#define MIPS32_MMU_BAT 2

Definition at line 896 of file mips32.h.

◆ MIPS32_MMU_DUAL_VTLB_FTLB

#define MIPS32_MMU_DUAL_VTLB_FTLB 4

Definition at line 898 of file mips32.h.

◆ MIPS32_MMU_FIXED

#define MIPS32_MMU_FIXED 3

Definition at line 897 of file mips32.h.

◆ MIPS32_MMU_TLB

#define MIPS32_MMU_TLB 1

Definition at line 895 of file mips32.h.

◆ MIPS32_MOVN

#define MIPS32_MOVN	(	isa,
		dst,
		src,
		tar
	)	(isa ? MMIPS32_MOVN(dst, src, tar) : MIPS32_ISA_MOVN(dst, src, tar))

Definition at line 755 of file mips32.h.

◆ MIPS32_MTC0

#define MIPS32_MTC0	(	isa,
		gpr,
		cpr,
		sel
	)	(isa ? MMIPS32_MTC0(gpr, cpr, sel) : MIPS32_ISA_MTC0(gpr, cpr, sel))

Definition at line 744 of file mips32.h.

◆ MIPS32_MTC1

#define MIPS32_MTC1	(	isa,
		gpr,
		cpr
	)	(isa ? MMIPS32_MTC1(gpr, cpr) : MIPS32_ISA_MTC1(gpr, cpr))

Definition at line 747 of file mips32.h.

◆ MIPS32_MTHC1

#define MIPS32_MTHC1	(	isa,
		gpr,
		cpr
	)	(isa ? MMIPS32_MTHC1(gpr, cpr) : MIPS32_ISA_MTHC1(gpr, cpr))

Definition at line 748 of file mips32.h.

◆ MIPS32_MTHI

#define MIPS32_MTHI	(	isa,
		reg
	)	(isa ? MMIPS32_MTHI(reg) : MIPS32_ISA_MTHI(reg))

Definition at line 752 of file mips32.h.

◆ MIPS32_MTLO

#define MIPS32_MTLO	(	isa,
		reg
	)	(isa ? MMIPS32_MTLO(reg) : MIPS32_ISA_MTLO(reg))

Definition at line 751 of file mips32.h.

◆ MIPS32_MUL

#define MIPS32_MUL	(	isa,
		dst,
		src,
		t
	)	(MIPS32_ISA_MUL(dst, src, t))

Definition at line 754 of file mips32.h.

◆ MIPS32_NOP

#define MIPS32_NOP 0 /* same for both isa's */

Definition at line 719 of file mips32.h.

◆ MIPS32_NUM_CPU_ENTRIES

#define MIPS32_NUM_CPU_ENTRIES (ARRAY_SIZE(mips32_cpu_entry))

Definition at line 362 of file mips32.h.

◆ MIPS32_OP_ADD

#define MIPS32_OP_ADD 0x20u

Definition at line 466 of file mips32.h.

◆ MIPS32_OP_ADDI

#define MIPS32_OP_ADDI 0x08u

Definition at line 467 of file mips32.h.

◆ MIPS32_OP_ADDIU

#define MIPS32_OP_ADDIU 0x09u

Definition at line 461 of file mips32.h.

◆ MIPS32_OP_ADDU

#define MIPS32_OP_ADDU 0x21u

Definition at line 460 of file mips32.h.

◆ MIPS32_OP_AND

#define MIPS32_OP_AND 0x24u

Definition at line 468 of file mips32.h.

◆ MIPS32_OP_ANDI

#define MIPS32_OP_ANDI 0x0Cu

Definition at line 462 of file mips32.h.

◆ MIPS32_OP_BEQ

#define MIPS32_OP_BEQ 0x04u

Definition at line 463 of file mips32.h.

◆ MIPS32_OP_BGTZ

#define MIPS32_OP_BGTZ 0x07u

Definition at line 464 of file mips32.h.

◆ MIPS32_OP_BNE

#define MIPS32_OP_BNE 0x05u

Definition at line 465 of file mips32.h.

◆ MIPS32_OP_CACHE

#define MIPS32_OP_CACHE 0x2Fu

Definition at line 469 of file mips32.h.

◆ MIPS32_OP_COP0

#define MIPS32_OP_COP0 0x10u

Definition at line 470 of file mips32.h.

◆ MIPS32_OP_COP1

#define MIPS32_OP_COP1 0x11u

Definition at line 471 of file mips32.h.

◆ MIPS32_OP_J

#define MIPS32_OP_J 0x02u

Definition at line 472 of file mips32.h.

◆ MIPS32_OP_JR

#define MIPS32_OP_JR 0x08u

Definition at line 473 of file mips32.h.

◆ MIPS32_OP_LB

#define MIPS32_OP_LB 0x20u

Definition at line 478 of file mips32.h.

◆ MIPS32_OP_LBU

#define MIPS32_OP_LBU 0x24u

Definition at line 479 of file mips32.h.

◆ MIPS32_OP_LDC1

#define MIPS32_OP_LDC1 0x35u

Definition at line 477 of file mips32.h.

◆ MIPS32_OP_LHU

#define MIPS32_OP_LHU 0x25u

Definition at line 480 of file mips32.h.

◆ MIPS32_OP_LUI

#define MIPS32_OP_LUI 0x0Fu

Definition at line 474 of file mips32.h.

◆ MIPS32_OP_LW

#define MIPS32_OP_LW 0x23u

Definition at line 475 of file mips32.h.

◆ MIPS32_OP_LWC1

#define MIPS32_OP_LWC1 0x31u

Definition at line 476 of file mips32.h.

◆ MIPS32_OP_MFHI

#define MIPS32_OP_MFHI 0x10u

Definition at line 481 of file mips32.h.

◆ MIPS32_OP_MFLO

#define MIPS32_OP_MFLO 0x12u

Definition at line 483 of file mips32.h.

◆ MIPS32_OP_MOVN

#define MIPS32_OP_MOVN 0x0Bu

Definition at line 500 of file mips32.h.

◆ MIPS32_OP_MTHI

#define MIPS32_OP_MTHI 0x11u

Definition at line 482 of file mips32.h.

◆ MIPS32_OP_MTLO

#define MIPS32_OP_MTLO 0x13u

Definition at line 484 of file mips32.h.

◆ MIPS32_OP_MUL

#define MIPS32_OP_MUL 0x02u

Definition at line 485 of file mips32.h.

◆ MIPS32_OP_ORI

#define MIPS32_OP_ORI 0x0Du

Definition at line 490 of file mips32.h.

◆ MIPS32_OP_RDHWR

#define MIPS32_OP_RDHWR 0x3Bu

Definition at line 486 of file mips32.h.

◆ MIPS32_OP_REGIMM

#define MIPS32_OP_REGIMM 0x01u

Definition at line 504 of file mips32.h.

◆ MIPS32_OP_SB

#define MIPS32_OP_SB 0x28u

Definition at line 487 of file mips32.h.

◆ MIPS32_OP_SDBBP

#define MIPS32_OP_SDBBP 0x3Fu

Definition at line 505 of file mips32.h.

◆ MIPS32_OP_SDC1

#define MIPS32_OP_SDC1 0x3Du

Definition at line 502 of file mips32.h.

◆ MIPS32_OP_SH

#define MIPS32_OP_SH 0x29u

Definition at line 488 of file mips32.h.

◆ MIPS32_OP_SLL

#define MIPS32_OP_SLL 0x00u

Definition at line 497 of file mips32.h.

◆ MIPS32_OP_SLLV

#define MIPS32_OP_SLLV 0x04u

Definition at line 498 of file mips32.h.

◆ MIPS32_OP_SLTI

#define MIPS32_OP_SLTI 0x0Au

Definition at line 499 of file mips32.h.

◆ MIPS32_OP_SLTU

#define MIPS32_OP_SLTU 0x2Bu

Definition at line 493 of file mips32.h.

◆ MIPS32_OP_SPECIAL

#define MIPS32_OP_SPECIAL 0x00u

Definition at line 506 of file mips32.h.

◆ MIPS32_OP_SPECIAL2

#define MIPS32_OP_SPECIAL2 0x07u

Definition at line 507 of file mips32.h.

◆ MIPS32_OP_SPECIAL3

#define MIPS32_OP_SPECIAL3 0x1Fu

Definition at line 508 of file mips32.h.

◆ MIPS32_OP_SRA

#define MIPS32_OP_SRA 0x03u

Definition at line 495 of file mips32.h.

◆ MIPS32_OP_SRL

#define MIPS32_OP_SRL 0x02u

Definition at line 494 of file mips32.h.

◆ MIPS32_OP_SW

#define MIPS32_OP_SW 0x2Bu

Definition at line 489 of file mips32.h.

◆ MIPS32_OP_SWC1

#define MIPS32_OP_SWC1 0x39u

Definition at line 501 of file mips32.h.

◆ MIPS32_OP_SYNCI

#define MIPS32_OP_SYNCI 0x1Fu

Definition at line 496 of file mips32.h.

◆ MIPS32_OP_XOR

#define MIPS32_OP_XOR 0x26u

Definition at line 492 of file mips32.h.

◆ MIPS32_OP_XORI

#define MIPS32_OP_XORI 0x0Eu

Definition at line 491 of file mips32.h.

◆ MIPS32_ORI

#define MIPS32_ORI	(	isa,
		tar,
		src,
		val
	)	(isa ? MMIPS32_ORI(tar, src, val) : MIPS32_ISA_ORI(tar, src, val))

Definition at line 756 of file mips32.h.

◆ MIPS32_R_INST

#define MIPS32_R_INST	(	opcode,
		rs,
		rt,
		rd,
		shamt,
		funct
	)	(((opcode) << 26) \| ((rs) << 21) \| ((rt) << 16) \| ((rd) << 11) \| ((shamt) << 6) \| (funct))

Definition at line 516 of file mips32.h.

◆ MIPS32_RDHWR

#define MIPS32_RDHWR	(	isa,
		tar,
		dst
	)	(isa ? MMIPS32_RDHWR(tar, dst) : MIPS32_ISA_RDHWR(tar, dst))

Definition at line 757 of file mips32.h.

◆ MIPS32_REG_C0_BADVADDR_INDEX

#define MIPS32_REG_C0_BADVADDR_INDEX 1

Definition at line 240 of file mips32.h.

◆ MIPS32_REG_C0_CAUSE_INDEX

#define MIPS32_REG_C0_CAUSE_INDEX 2

Definition at line 241 of file mips32.h.

◆ MIPS32_REG_C0_COUNT

#define MIPS32_REG_C0_COUNT 5

Definition at line 224 of file mips32.h.

◆ MIPS32_REG_C0_GUESTCTL1_INDEX

#define MIPS32_REG_C0_GUESTCTL1_INDEX 4

Definition at line 243 of file mips32.h.

◆ MIPS32_REG_C0_PC_INDEX

#define MIPS32_REG_C0_PC_INDEX 3

Definition at line 242 of file mips32.h.

◆ MIPS32_REG_C0_STATUS_INDEX

#define MIPS32_REG_C0_STATUS_INDEX 0

Definition at line 239 of file mips32.h.

◆ MIPS32_REG_DSP_COUNT

#define MIPS32_REG_DSP_COUNT 7

Definition at line 225 of file mips32.h.

◆ MIPS32_REG_DSP_DSPCTL_INDEX

#define MIPS32_REG_DSP_DSPCTL_INDEX 6

Definition at line 247 of file mips32.h.

◆ MIPS32_REG_FP_COUNT

#define MIPS32_REG_FP_COUNT 32

Definition at line 222 of file mips32.h.

◆ MIPS32_REG_FPC_COUNT

#define MIPS32_REG_FPC_COUNT 2

Definition at line 223 of file mips32.h.

◆ MIPS32_REG_GP_COUNT

#define MIPS32_REG_GP_COUNT 34

Definition at line 221 of file mips32.h.

◆ MIPS32_REGLIST_C0_BADVADDR_INDEX

#define MIPS32_REGLIST_C0_BADVADDR_INDEX (MIPS32_REGLIST_C0_INDEX + 1)

Definition at line 234 of file mips32.h.

◆ MIPS32_REGLIST_C0_CAUSE_INDEX

#define MIPS32_REGLIST_C0_CAUSE_INDEX (MIPS32_REGLIST_C0_INDEX + 2)

Definition at line 235 of file mips32.h.

◆ MIPS32_REGLIST_C0_GUESTCTL1_INDEX

#define MIPS32_REGLIST_C0_GUESTCTL1_INDEX (MIPS32_REGLIST_C0_INDEX + 4)

Definition at line 237 of file mips32.h.

◆ MIPS32_REGLIST_C0_INDEX

#define MIPS32_REGLIST_C0_INDEX (MIPS32_REGLIST_FPC_INDEX + MIPS32_REG_FPC_COUNT)

Definition at line 230 of file mips32.h.

◆ MIPS32_REGLIST_C0_PC_INDEX

#define MIPS32_REGLIST_C0_PC_INDEX (MIPS32_REGLIST_C0_INDEX + 3)

Definition at line 236 of file mips32.h.

◆ MIPS32_REGLIST_C0_STATUS_INDEX

#define MIPS32_REGLIST_C0_STATUS_INDEX (MIPS32_REGLIST_C0_INDEX + 0)

Definition at line 233 of file mips32.h.

◆ MIPS32_REGLIST_DSP_DSPCTL_INDEX

#define MIPS32_REGLIST_DSP_DSPCTL_INDEX (MIPS32_REGLIST_DSP_INDEX + 6)

Definition at line 245 of file mips32.h.

◆ MIPS32_REGLIST_DSP_INDEX

#define MIPS32_REGLIST_DSP_INDEX (MIPS32_REGLIST_C0_INDEX + MIPS32_REG_C0_COUNT)

Definition at line 231 of file mips32.h.

◆ MIPS32_REGLIST_FP_INDEX

#define MIPS32_REGLIST_FP_INDEX (MIPS32_REGLIST_GP_INDEX + MIPS32_REG_GP_COUNT)

Definition at line 228 of file mips32.h.

◆ MIPS32_REGLIST_FPC_INDEX

#define MIPS32_REGLIST_FPC_INDEX (MIPS32_REGLIST_FP_INDEX + MIPS32_REG_FP_COUNT)

Definition at line 229 of file mips32.h.

◆ MIPS32_REGLIST_GP_INDEX

#define MIPS32_REGLIST_GP_INDEX 0

Definition at line 227 of file mips32.h.

◆ MIPS32_S_INST

#define MIPS32_S_INST	(	rs,
		rac,
		opcode
	)	(((rs) << 21) \| ((rac) << 11) \| (opcode))

Definition at line 789 of file mips32.h.

◆ MIPS32_SB

#define MIPS32_SB	(	isa,
		reg,
		off,
		base
	)	(isa ? MMIPS32_SB(reg, off, base) : MIPS32_ISA_SB(reg, off, base))

Definition at line 758 of file mips32.h.

◆ MIPS32_SCAN_DELAY_LEGACY_MODE

#define MIPS32_SCAN_DELAY_LEGACY_MODE 2000000

Definition at line 70 of file mips32.h.

◆ MIPS32_SDBBP

#define MIPS32_SDBBP ( isa ) (isa ? MMIPS32_SDBBP : MIPS32_ISA_SDBBP)

Definition at line 780 of file mips32.h.

◆ MIPS32_SDC1

#define MIPS32_SDC1	(	isa,
		reg,
		off,
		base
	)	(isa ? MMIPS32_SDC1(reg, off, base) : MIPS32_ISA_SDC1(reg, off, base))

Definition at line 762 of file mips32.h.

◆ MIPS32_SH

#define MIPS32_SH	(	isa,
		reg,
		off,
		base
	)	(isa ? MMIPS32_SH(reg, off, base) : MIPS32_ISA_SH(reg, off, base))

Definition at line 759 of file mips32.h.

◆ MIPS32_SLL

#define MIPS32_SLL	(	isa,
		dst,
		src,
		sa
	)	(isa ? MMIPS32_SLL(dst, src, sa) : MIPS32_ISA_SLL(dst, src, sa))

Definition at line 764 of file mips32.h.

◆ MIPS32_SLLV

#define MIPS32_SLLV	(	isa,
		dst,
		src,
		sa
	)	(MIPS32_ISA_SLLV(dst, src, sa))

Definition at line 766 of file mips32.h.

◆ MIPS32_SLTI

#define MIPS32_SLTI	(	isa,
		tar,
		src,
		val
	)	(isa ? MMIPS32_SLTI(tar, src, val) : MIPS32_ISA_SLTI(tar, src, val))

Definition at line 767 of file mips32.h.

◆ MIPS32_SLTU

#define MIPS32_SLTU	(	isa,
		dst,
		src,
		tar
	)	(isa ? MMIPS32_SLTU(dst, src, tar) : MIPS32_ISA_SLTU(dst, src, tar))

Definition at line 768 of file mips32.h.

◆ MIPS32_SRL

#define MIPS32_SRL	(	isa,
		reg,
		src,
		off
	)	(isa ? MMIPS32_SRL(reg, src, off) : MIPS32_ISA_SRL(reg, src, off))

Definition at line 769 of file mips32.h.

◆ MIPS32_SW

#define MIPS32_SW	(	isa,
		reg,
		off,
		base
	)	(isa ? MMIPS32_SW(reg, off, base) : MIPS32_ISA_SW(reg, off, base))

Definition at line 760 of file mips32.h.

◆ MIPS32_SWC1

#define MIPS32_SWC1	(	isa,
		reg,
		off,
		base
	)	(isa ? MMIPS32_SWC1(reg, off, base) : MIPS32_ISA_SWC1(reg, off, base))

Definition at line 761 of file mips32.h.

◆ MIPS32_SYNC

#define MIPS32_SYNC ( isa ) (isa ? MMIPS32_SYNC : MIPS32_ISA_SYNC)

Definition at line 772 of file mips32.h.

◆ MIPS32_SYNCI

#define MIPS32_SYNCI	(	isa,
		off,
		base
	)	(isa ? MMIPS32_SYNCI(off, base) : MIPS32_ISA_SYNCI(off, base))

Definition at line 771 of file mips32.h.

◆ MIPS32_SYNCI_STEP

#define MIPS32_SYNCI_STEP 0x1

Definition at line 776 of file mips32.h.

◆ MIPS32_VARIANT_MASK

#define MIPS32_VARIANT_MASK 0x00FF

Definition at line 283 of file mips32.h.

◆ MIPS32_XOR

#define MIPS32_XOR	(	isa,
		reg,
		val1,
		val2
	)	(isa ? MMIPS32_XOR(reg, val1, val2) : MIPS32_ISA_XOR(reg, val1, val2))

Definition at line 773 of file mips32.h.

◆ MIPS32_XORI

#define MIPS32_XORI	(	isa,
		tar,
		src,
		val
	)	(isa ? MMIPS32_XORI(tar, src, val) : MIPS32_ISA_XORI(tar, src, val))

Definition at line 774 of file mips32.h.

◆ MIPS32NUMCP0REGS

#define MIPS32NUMCP0REGS (ARRAY_SIZE(mips32_cp0_regs))

Definition at line 206 of file mips32.h.

◆ MIPS32NUMDSPREGS

#define MIPS32NUMDSPREGS 7

Definition at line 72 of file mips32.h.

◆ MIPS_CP0_IAPTIV

#define MIPS_CP0_IAPTIV 0x0008

Definition at line 78 of file mips32.h.

◆ MIPS_CP0_MAPTIV_UC

#define MIPS_CP0_MAPTIV_UC 0x0002

Definition at line 76 of file mips32.h.

◆ MIPS_CP0_MAPTIV_UP

#define MIPS_CP0_MAPTIV_UP 0x0004

Definition at line 77 of file mips32.h.

◆ MIPS_CP0_MK4

#define MIPS_CP0_MK4 0x0001

Definition at line 75 of file mips32.h.

◆ MMIPS16_SDBBP

#define MMIPS16_SDBBP 0x46C0u /* POOL16C instr */

Definition at line 716 of file mips32.h.

◆ MMIPS32_ADDI

#define MMIPS32_ADDI	(	tar,
		src,
		val
	)	MIPS32_I_INST(MMIPS32_OP_ADDI, tar, src, val)

Definition at line 652 of file mips32.h.

◆ MMIPS32_ADDIU

#define MMIPS32_ADDIU	(	tar,
		src,
		val
	)	MIPS32_I_INST(MMIPS32_OP_ADDIU, tar, src, val)

Definition at line 653 of file mips32.h.

◆ MMIPS32_ADDU

#define MMIPS32_ADDU	(	dst,
		src,
		tar
	)	MIPS32_R_INST(MMIPS32_POOL32A, tar, src, dst, 0, MMIPS32_OP_ADDU)

Definition at line 654 of file mips32.h.

◆ MMIPS32_AND

#define MMIPS32_AND	(	dst,
		src,
		tar
	)	MIPS32_R_INST(MMIPS32_POOL32A, tar, src, dst, 0, MMIPS32_OP_AND)

Definition at line 655 of file mips32.h.

◆ MMIPS32_ANDI

#define MMIPS32_ANDI	(	tar,
		src,
		val
	)	MIPS32_I_INST(MMIPS32_OP_ANDI, tar, src, val)

Definition at line 656 of file mips32.h.

◆ MMIPS32_B

#define MMIPS32_B ( off ) MMIPS32_BEQ(0, 0, off)

Definition at line 658 of file mips32.h.

◆ MMIPS32_BEQ

#define MMIPS32_BEQ	(	src,
		tar,
		off
	)	MIPS32_I_INST(MMIPS32_OP_BEQ, tar, src, off)

Definition at line 659 of file mips32.h.

◆ MMIPS32_BGTZ

#define MMIPS32_BGTZ	(	reg,
		off
	)	MIPS32_I_INST(MMIPS32_POOL32I, MMIPS32_OP_BGTZ, reg, off)

Definition at line 660 of file mips32.h.

◆ MMIPS32_BNE

#define MMIPS32_BNE	(	src,
		tar,
		off
	)	MIPS32_I_INST(MMIPS32_OP_BNE, tar, src, off)

Definition at line 661 of file mips32.h.

◆ MMIPS32_CACHE

#define MMIPS32_CACHE	(	op,
		off,
		base
	)	MIPS32_R_INST(MMIPS32_POOL32B, op, base, MMIPS32_OP_CACHE << 1, 0, off)

Definition at line 662 of file mips32.h.

◆ MMIPS32_CFC1

#define MMIPS32_CFC1	(	gpr,
		cpr
	)	MIPS32_R_INST(MMIPS32_POOL32F, gpr, cpr, 0, MMIPS32_OP_CFC1, MMIPS32_POOL32FXF)

Definition at line 663 of file mips32.h.

◆ MMIPS32_DRET

#define MMIPS32_DRET 0x0000E37Cu /* MIPS32_R_INST(MMIPS32_POOL32A, 0, 0, 0, 0x38D, MMIPS32_POOL32AXF) */

Definition at line 714 of file mips32.h.

◆ MMIPS32_J

#define MMIPS32_J ( tar ) MIPS32_J_INST(MMIPS32_OP_J, ((0x07FFFFFFu & ((tar) >> 1))))

Definition at line 665 of file mips32.h.

◆ MMIPS32_JR

#define MMIPS32_JR ( reg ) MIPS32_R_INST(MMIPS32_POOL32A, 0, reg, 0, MMIPS32_OP_JALR, MMIPS32_POOL32AXF)

Definition at line 666 of file mips32.h.

◆ MMIPS32_JRHB

#define MMIPS32_JRHB ( reg ) MIPS32_R_INST(MMIPS32_POOL32A, 0, reg, 0, MMIPS32_OP_JALRHB, MMIPS32_POOL32AXF)

Definition at line 667 of file mips32.h.

◆ MMIPS32_LB

#define MMIPS32_LB	(	reg,
		off,
		base
	)	MIPS32_I_INST(MMIPS32_OP_LB, reg, base, off)

Definition at line 668 of file mips32.h.

◆ MMIPS32_LBU

#define MMIPS32_LBU	(	reg,
		off,
		base
	)	MIPS32_I_INST(MMIPS32_OP_LBU, reg, base, off)

Definition at line 669 of file mips32.h.

◆ MMIPS32_LDC1

#define MMIPS32_LDC1	(	reg,
		off,
		base
	)	MIPS32_I_INST(MMIPS32_OP_LDC1, reg, base, off)

Definition at line 674 of file mips32.h.

◆ MMIPS32_LHU

#define MMIPS32_LHU	(	reg,
		off,
		base
	)	MIPS32_I_INST(MMIPS32_OP_LHU, reg, base, off)

Definition at line 670 of file mips32.h.

◆ MMIPS32_LUI

#define MMIPS32_LUI	(	reg,
		val
	)	MIPS32_I_INST(MMIPS32_POOL32I, MMIPS32_OP_LUI, reg, val)

Definition at line 671 of file mips32.h.

◆ MMIPS32_LW

#define MMIPS32_LW	(	reg,
		off,
		base
	)	MIPS32_I_INST(MMIPS32_OP_LW, reg, base, off)

Definition at line 672 of file mips32.h.

◆ MMIPS32_LWC1

#define MMIPS32_LWC1	(	reg,
		off,
		base
	)	MIPS32_I_INST(MMIPS32_OP_LWC1, reg, base, off)

Definition at line 673 of file mips32.h.

◆ MMIPS32_MFC0

#define MMIPS32_MFC0	(	gpr,
		cpr,
		sel
	)

Value:

MIPS32_R_INST(MMIPS32_POOL32A, gpr, cpr, sel,\

MMIPS32_OP_MFC0, MMIPS32_POOL32AXF)

MMIPS32_OP_MFC0

#define MMIPS32_OP_MFC0

Definition: mips32.h:626

MMIPS32_POOL32A

#define MMIPS32_POOL32A

Definition: mips32.h:600

MIPS32_R_INST

#define MIPS32_R_INST(opcode, rs, rt, rd, shamt, funct)

Definition: mips32.h:516

MMIPS32_POOL32AXF

#define MMIPS32_POOL32AXF

Definition: mips32.h:603

Definition at line 676 of file mips32.h.

◆ MMIPS32_MFC1

#define MMIPS32_MFC1	(	gpr,
		cpr
	)	MIPS32_R_INST(MMIPS32_POOL32F, gpr, cpr, 0, MMIPS32_OP_MFC1, MMIPS32_POOL32FXF)

Definition at line 678 of file mips32.h.

◆ MMIPS32_MFHC1

#define MMIPS32_MFHC1	(	gpr,
		cpr
	)	MIPS32_R_INST(MMIPS32_POOL32F, gpr, cpr, 0, MMIPS32_OP_MFHC1, MMIPS32_POOL32FXF)

Definition at line 679 of file mips32.h.

◆ MMIPS32_MFHI

#define MMIPS32_MFHI ( reg ) MIPS32_R_INST(MMIPS32_POOL32A, 0, reg, 0, MMIPS32_OP_MFHI, MMIPS32_POOL32AXF)

Definition at line 681 of file mips32.h.

◆ MMIPS32_MFLO

#define MMIPS32_MFLO ( reg ) MIPS32_R_INST(MMIPS32_POOL32A, 0, reg, 0, MMIPS32_OP_MFLO, MMIPS32_POOL32AXF)

Definition at line 680 of file mips32.h.

◆ MMIPS32_MOVN

#define MMIPS32_MOVN	(	dst,
		src,
		tar
	)	MIPS32_R_INST(MMIPS32_POOL32A, tar, src, dst, 0, MMIPS32_OP_MOVN)

Definition at line 689 of file mips32.h.

◆ MMIPS32_MTC0

#define MMIPS32_MTC0	(	gpr,
		cpr,
		sel
	)

Value:

MIPS32_R_INST(MMIPS32_POOL32A, gpr, cpr, sel,\

MMIPS32_OP_MTC0, MMIPS32_POOL32AXF)

MMIPS32_OP_MTC0

#define MMIPS32_OP_MTC0

Definition: mips32.h:629

Definition at line 682 of file mips32.h.

◆ MMIPS32_MTC1

#define MMIPS32_MTC1	(	gpr,
		cpr
	)	MIPS32_R_INST(MMIPS32_POOL32F, gpr, cpr, 0, MMIPS32_OP_MTC1, MMIPS32_POOL32FXF)

Definition at line 684 of file mips32.h.

◆ MMIPS32_MTHC1

#define MMIPS32_MTHC1	(	gpr,
		cpr
	)	MIPS32_R_INST(MMIPS32_POOL32F, gpr, cpr, 0, MMIPS32_OP_MTHC1, MMIPS32_POOL32FXF)

Definition at line 685 of file mips32.h.

◆ MMIPS32_MTHI

#define MMIPS32_MTHI ( reg ) MIPS32_R_INST(MMIPS32_POOL32A, 0, reg, 0, MMIPS32_OP_MTHI, MMIPS32_POOL32AXF)

Definition at line 687 of file mips32.h.

◆ MMIPS32_MTLO

#define MMIPS32_MTLO ( reg ) MIPS32_R_INST(MMIPS32_POOL32A, 0, reg, 0, MMIPS32_OP_MTLO, MMIPS32_POOL32AXF)

Definition at line 686 of file mips32.h.

◆ MMIPS32_NOP

#define MMIPS32_NOP 0

Definition at line 690 of file mips32.h.

◆ MMIPS32_OP_ADDI

#define MMIPS32_OP_ADDI 0x04u

Definition at line 606 of file mips32.h.

◆ MMIPS32_OP_ADDIU

#define MMIPS32_OP_ADDIU 0x0Cu

Definition at line 607 of file mips32.h.

◆ MMIPS32_OP_ADDU

#define MMIPS32_OP_ADDU 0x150u

Definition at line 608 of file mips32.h.

◆ MMIPS32_OP_AND

#define MMIPS32_OP_AND 0x250u

Definition at line 609 of file mips32.h.

◆ MMIPS32_OP_ANDI

#define MMIPS32_OP_ANDI 0x34u

Definition at line 610 of file mips32.h.

◆ MMIPS32_OP_BEQ

#define MMIPS32_OP_BEQ 0x25u

Definition at line 611 of file mips32.h.

◆ MMIPS32_OP_BGTZ

#define MMIPS32_OP_BGTZ 0x06u

Definition at line 612 of file mips32.h.

◆ MMIPS32_OP_BNE

#define MMIPS32_OP_BNE 0x2Du

Definition at line 613 of file mips32.h.

◆ MMIPS32_OP_CACHE

#define MMIPS32_OP_CACHE 0x06u

Definition at line 614 of file mips32.h.

◆ MMIPS32_OP_CFC1

#define MMIPS32_OP_CFC1 0x40u

Definition at line 615 of file mips32.h.

◆ MMIPS32_OP_J

#define MMIPS32_OP_J 0x35u

Definition at line 616 of file mips32.h.

◆ MMIPS32_OP_JALR

#define MMIPS32_OP_JALR 0x03Cu

Definition at line 617 of file mips32.h.

◆ MMIPS32_OP_JALRHB

#define MMIPS32_OP_JALRHB 0x07Cu

Definition at line 618 of file mips32.h.

◆ MMIPS32_OP_LB

#define MMIPS32_OP_LB 0x07u

Definition at line 619 of file mips32.h.

◆ MMIPS32_OP_LBU

#define MMIPS32_OP_LBU 0x05u

Definition at line 620 of file mips32.h.

◆ MMIPS32_OP_LDC1

#define MMIPS32_OP_LDC1 0x2Fu

Definition at line 625 of file mips32.h.

◆ MMIPS32_OP_LHU

#define MMIPS32_OP_LHU 0x0Du

Definition at line 621 of file mips32.h.

◆ MMIPS32_OP_LUI

#define MMIPS32_OP_LUI 0x0Du

Definition at line 622 of file mips32.h.

◆ MMIPS32_OP_LW

#define MMIPS32_OP_LW 0x3Fu

Definition at line 623 of file mips32.h.

◆ MMIPS32_OP_LWC1

#define MMIPS32_OP_LWC1 0x27u

Definition at line 624 of file mips32.h.

◆ MMIPS32_OP_MFC0

#define MMIPS32_OP_MFC0 0x03u

Definition at line 626 of file mips32.h.

◆ MMIPS32_OP_MFC1

#define MMIPS32_OP_MFC1 0x80u

Definition at line 627 of file mips32.h.

◆ MMIPS32_OP_MFHC1

#define MMIPS32_OP_MFHC1 0xC0u

Definition at line 628 of file mips32.h.

◆ MMIPS32_OP_MFHI

#define MMIPS32_OP_MFHI 0x035u

Definition at line 633 of file mips32.h.

◆ MMIPS32_OP_MFLO

#define MMIPS32_OP_MFLO 0x075u

Definition at line 632 of file mips32.h.

◆ MMIPS32_OP_MOVN

#define MMIPS32_OP_MOVN 0x018u

Definition at line 636 of file mips32.h.

◆ MMIPS32_OP_MTC0

#define MMIPS32_OP_MTC0 0x0Bu

Definition at line 629 of file mips32.h.

◆ MMIPS32_OP_MTC1

#define MMIPS32_OP_MTC1 0xA0u

Definition at line 630 of file mips32.h.

◆ MMIPS32_OP_MTHC1

#define MMIPS32_OP_MTHC1 0xE0u

Definition at line 631 of file mips32.h.

◆ MMIPS32_OP_MTHI

#define MMIPS32_OP_MTHI 0x0B5u

Definition at line 635 of file mips32.h.

◆ MMIPS32_OP_MTLO

#define MMIPS32_OP_MTLO 0x0F5u

Definition at line 634 of file mips32.h.

◆ MMIPS32_OP_ORI

#define MMIPS32_OP_ORI 0x14u

Definition at line 637 of file mips32.h.

◆ MMIPS32_OP_RDHWR

#define MMIPS32_OP_RDHWR 0x1ACu

Definition at line 638 of file mips32.h.

◆ MMIPS32_OP_SB

#define MMIPS32_OP_SB 0x06u

Definition at line 639 of file mips32.h.

◆ MMIPS32_OP_SDC1

#define MMIPS32_OP_SDC1 0x2Eu

Definition at line 643 of file mips32.h.

◆ MMIPS32_OP_SH

#define MMIPS32_OP_SH 0x0Eu

Definition at line 640 of file mips32.h.

◆ MMIPS32_OP_SLL

#define MMIPS32_OP_SLL 0x000u

Definition at line 645 of file mips32.h.

◆ MMIPS32_OP_SLTI

#define MMIPS32_OP_SLTI 0x24u

Definition at line 646 of file mips32.h.

◆ MMIPS32_OP_SLTU

#define MMIPS32_OP_SLTU 0x390u

Definition at line 644 of file mips32.h.

◆ MMIPS32_OP_SRL

#define MMIPS32_OP_SRL 0x040u

Definition at line 647 of file mips32.h.

◆ MMIPS32_OP_SW

#define MMIPS32_OP_SW 0x3Eu

Definition at line 641 of file mips32.h.

◆ MMIPS32_OP_SWC1

#define MMIPS32_OP_SWC1 0x26u

Definition at line 642 of file mips32.h.

◆ MMIPS32_OP_SYNCI

#define MMIPS32_OP_SYNCI 0x10u

Definition at line 648 of file mips32.h.

◆ MMIPS32_OP_XOR

#define MMIPS32_OP_XOR 0x310u

Definition at line 649 of file mips32.h.

◆ MMIPS32_OP_XORI

#define MMIPS32_OP_XORI 0x1Cu

Definition at line 650 of file mips32.h.

◆ MMIPS32_ORI

#define MMIPS32_ORI	(	tar,
		src,
		val
	)	MIPS32_I_INST(MMIPS32_OP_ORI, tar, src, val)

Definition at line 691 of file mips32.h.

◆ MMIPS32_POOL32A

#define MMIPS32_POOL32A 0x00u

Definition at line 600 of file mips32.h.

◆ MMIPS32_POOL32AXF

#define MMIPS32_POOL32AXF 0x3Cu

Definition at line 603 of file mips32.h.

◆ MMIPS32_POOL32B

#define MMIPS32_POOL32B 0x08u

Definition at line 604 of file mips32.h.

◆ MMIPS32_POOL32F

#define MMIPS32_POOL32F 0x15u

Definition at line 601 of file mips32.h.

◆ MMIPS32_POOL32FXF

#define MMIPS32_POOL32FXF 0x3Bu

Definition at line 602 of file mips32.h.

◆ MMIPS32_POOL32I

#define MMIPS32_POOL32I 0x10u

Definition at line 605 of file mips32.h.

◆ MMIPS32_RDHWR

#define MMIPS32_RDHWR	(	tar,
		dst
	)	MIPS32_R_INST(MMIPS32_POOL32A, dst, tar, 0, MMIPS32_OP_RDHWR, MMIPS32_POOL32AXF)

Definition at line 692 of file mips32.h.

◆ MMIPS32_SB

#define MMIPS32_SB	(	reg,
		off,
		base
	)	MIPS32_I_INST(MMIPS32_OP_SB, reg, base, off)

Definition at line 693 of file mips32.h.

◆ MMIPS32_SDBBP

#define MMIPS32_SDBBP 0x0000DB7Cu /* MIPS32_R_INST(MMIPS32_POOL32A, 0, 0, 0, 0x1BD, MMIPS32_POOL32AXF) */

Definition at line 715 of file mips32.h.

◆ MMIPS32_SDC1

#define MMIPS32_SDC1	(	reg,
		off,
		base
	)	MIPS32_I_INST(MMIPS32_OP_SDC1, reg, base, off)

Definition at line 697 of file mips32.h.

◆ MMIPS32_SH

#define MMIPS32_SH	(	reg,
		off,
		base
	)	MIPS32_I_INST(MMIPS32_OP_SH, reg, base, off)

Definition at line 694 of file mips32.h.

◆ MMIPS32_SLL

#define MMIPS32_SLL	(	dst,
		src,
		sa
	)	MIPS32_R_INST(MMIPS32_POOL32A, dst, src, sa, 0, MMIPS32_OP_SLL)

Definition at line 702 of file mips32.h.

◆ MMIPS32_SLLV

#define MMIPS32_SLLV	(	dst,
		src,
		sa
	)	MIPS32_R_INST(MMIPS32_POOL32A, dst, src, sa, 0, MMIPS32_OP_SLLV)

Definition at line 703 of file mips32.h.

◆ MMIPS32_SLTI

#define MMIPS32_SLTI	(	tar,
		src,
		val
	)	MIPS32_I_INST(MMIPS32_OP_SLTI, tar, src, val)

Definition at line 704 of file mips32.h.

◆ MMIPS32_SLTU

#define MMIPS32_SLTU	(	dst,
		src,
		tar
	)	MIPS32_R_INST(MMIPS32_POOL32A, tar, src, dst, 0, MMIPS32_OP_SLTU)

Definition at line 700 of file mips32.h.

◆ MMIPS32_SRL

#define MMIPS32_SRL	(	reg,
		src,
		off
	)	MIPS32_R_INST(MMIPS32_POOL32A, reg, src, off, 0, MMIPS32_OP_SRL)

Definition at line 699 of file mips32.h.

◆ MMIPS32_SW

#define MMIPS32_SW	(	reg,
		off,
		base
	)	MIPS32_I_INST(MMIPS32_OP_SW, reg, base, off)

Definition at line 695 of file mips32.h.

◆ MMIPS32_SWC1

#define MMIPS32_SWC1	(	reg,
		off,
		base
	)	MIPS32_I_INST(MMIPS32_OP_SWC1, reg, base, off)

Definition at line 696 of file mips32.h.

◆ MMIPS32_SYNC

#define MMIPS32_SYNC 0x00001A7Cu /* MIPS32_R_INST(MMIPS32_POOL32A, 0, 0, 0, 0x1ADu, MMIPS32_POOL32AXF) */

Definition at line 705 of file mips32.h.

◆ MMIPS32_SYNCI

#define MMIPS32_SYNCI	(	off,
		base
	)	MIPS32_I_INST(MMIPS32_POOL32I, MMIPS32_OP_SYNCI, base, off)

Definition at line 701 of file mips32.h.

◆ MMIPS32_SYNCI_STEP

#define MMIPS32_SYNCI_STEP 0x1u /* reg num od address step size to be used with synci instruction */

Definition at line 710 of file mips32.h.

◆ MMIPS32_XOR

#define MMIPS32_XOR	(	reg,
		val1,
		val2
	)	MIPS32_R_INST(MMIPS32_POOL32A, val1, val2, reg, 0, MMIPS32_OP_XOR)

Definition at line 707 of file mips32.h.

◆ MMIPS32_XORI

#define MMIPS32_XORI	(	tar,
		src,
		val
	)	MIPS32_I_INST(MMIPS32_OP_XORI, tar, src, val)

Definition at line 708 of file mips32.h.

Enumeration Type Documentation

◆ anonymous enum

anonymous enum

Enumerator
MIPS32_PC
MIPS32_FIR
MIPS32_DSPCTL
MIPS32NUMCOREREGS

Definition at line 212 of file mips32.h.

◆ mips32_dsp_imp

enum mips32_dsp_imp

Enumerator
MIPS32_DSP_IMP_NONE
MIPS32_DSP_IMP_REV1
MIPS32_DSP_IMP_REV2

Definition at line 371 of file mips32.h.

◆ mips32_fp_imp

enum mips32_fp_imp

Enumerator
MIPS32_FP_IMP_NONE
MIPS32_FP_IMP_32
MIPS32_FP_IMP_64
MIPS32_FP_IMP_UNKNOWN

Definition at line 364 of file mips32.h.

◆ mips32_isa_imp

enum mips32_isa_imp

Enumerator
MIPS32_ONLY
MMIPS32_ONLY
MIPS32_MIPS16
MIPS32_MMIPS32

Definition at line 255 of file mips32.h.

◆ mips32_isa_mode

enum mips32_isa_mode

Enumerator
MIPS32_ISA_MIPS32
MIPS32_ISA_MIPS16E
MIPS32_ISA_MMIPS32

Definition at line 249 of file mips32.h.

◆ mips32_isa_rel

enum mips32_isa_rel

Enumerator
MIPS32_RELEASE_1
MIPS32_RELEASE_2
MIPS32_RELEASE_6
MIPS32_RELEASE_UNKNOWN

Definition at line 267 of file mips32.h.

◆ mips32_isa_supported

enum mips32_isa_supported

Enumerator
MIPS16
MIPS32
MIPS64
MICROMIPS_ONLY
MIPS32_AT_RESET_AND_MICROMIPS
MICROMIPS_AT_RESET_AND_MIPS32

Definition at line 274 of file mips32.h.

Function Documentation

◆ mips32_arch_state()

int mips32_arch_state ( struct target * target )

Definition at line 484 of file mips32.c.

References buf_get_u32(), mips32_common::core_cache, debug_reason_name(), ERROR_OK, mips32_common::isa_mode, LOG_USER, MIPS32_REGLIST_C0_PC_INDEX, mips_isa_strings, reg_cache::reg_list, target_to_mips32(), and reg::value.

◆ mips32_blank_check_memory()

int mips32_blank_check_memory	(	struct target *	target,
		struct target_memory_check_block *	blocks,
		int	num_blocks,
		uint8_t	erased_value
	)

Checks whether a memory region is erased.

Definition at line 1312 of file mips32.c.

References working_area::address, ARRAY_SIZE, buf_get_u32(), buf_set_u32(), mips32_algorithm::common_magic, destroy_reg_param(), mips32_common::ejtag_info, ERROR_FAIL, ERROR_OK, ERROR_TARGET_RESOURCE_NOT_AVAILABLE, init_reg_param(), mips_ejtag::isa, mips32_algorithm::isa_mode, LOG_ERROR, MIPS32_ADDIU, MIPS32_AND, MIPS32_BNE, MIPS32_COMMON_MAGIC, MIPS32_ISA_MIPS32, MIPS32_ISA_MMIPS32, MIPS32_LB, MIPS32_SDBBP, NEG16, NULL, PARAM_IN_OUT, PARAM_OUT, pracc_swap16_array(), target_memory_check_block::result, size, target_alloc_working_area(), target_buffer_set_u32_array(), target_free_working_area(), target_run_algorithm(), target_to_mips32(), and target_write_buffer().

◆ mips32_build_reg_cache()

struct reg_cache* mips32_build_reg_cache ( struct target * target )

Definition at line 501 of file mips32.c.

References reg::arch_info, reg::caller_save, mips32_common::core_cache, reg::dirty, reg::exist, feature, reg::feature, reg::group, LOG_ERROR, mips32_core_reg::mips32_common, MIPS32_NUM_REGS, mips32_reg_type, mips32_regs, reg::name, reg_cache::name, reg_cache::next, NULL, mips32_core_reg::num, reg_cache::num_regs, reg::number, target::reg_cache, reg::reg_data_type, reg_cache::reg_list, register_get_last_cache_p(), reg::size, target, mips32_core_reg::target, target_to_mips32(), reg_data_type::type, reg::type, reg::valid, and reg::value.

Referenced by mips_m4k_init_target().

◆ mips32_checksum_memory()

int mips32_checksum_memory	(	struct target *	target,
		target_addr_t	address,
		uint32_t	count,
		uint32_t *	checksum
	)

◆ mips32_configure_break_unit()

int mips32_configure_break_unit ( struct target * target )

◆ mips32_cpu_probe()

int mips32_cpu_probe ( struct target * target )

mips32_cpu_probe - Detects processor type and applies necessary quirks.

Parameters

[in] target The target CPU to probe.

This function probes the CPU, reads its PRID (Processor ID), and determines the CPU type. It applies any quirks necessary for specific processor types.

NOTE: The proper detection of certain CPUs can become quite complicated. Please consult the following Linux kernel code when adding new CPUs: arch/mips/include/asm/cpu.h arch/mips/kernel/cpu-probe.c

Returns: ERROR_OK on success; error code on failure.

Definition at line 995 of file mips32.c.

References mips32_common::cp0_mask, mips32_common::cpu_info, cpu_entry::cpu_name, mips32_common::cpu_quirks, EJTAG_QUIRK_PAD_DRET, ERROR_OK, LOG_DEBUG, mips32_find_cpu_by_prid(), mips32_read_c0_prid(), MIPS_CP0_IAPTIV, MIPS_CP0_MAPTIV_UC, MIPS_CP0_MAPTIV_UP, MIPS_CP0_MK4, cpu_entry::prid, mips32_common::prid, PRID_COMP_INGENIC_E1, PRID_COMP_MASK, PRID_COMP_MTI, PRID_IMP_IAPTIV, PRID_IMP_IAPTIV_CM, PRID_IMP_M5150, PRID_IMP_MAPTIV_UC, PRID_IMP_MAPTIV_UP, PRID_IMP_MASK, PRID_IMP_XBURST_REV1, and target_to_mips32().

Referenced by mips_m4k_debug_entry().

◆ mips32_cpu_support_hazard_barrier()

bool mips32_cpu_support_hazard_barrier ( struct mips_ejtag * ejtag_info )

mips32_cpu_support_hazard_barrier - Checks CPU supports hazard barrier

Parameters

[in] ejtag_info MIPS EJTAG information structure.

hazard barrier instructions EHB and *.HB was introduced to MIPS from release 2.

Returns: true if current CPU supports hazard barrier(release > 1)

Definition at line 976 of file mips32.c.

References mips32_cpu_get_release(), and MIPS32_RELEASE_1.

Referenced by mips32_cp0_read(), mips32_cp0_write(), mips32_pracc_fastdata_xfer(), mips32_pracc_write_mem(), and mips32_pracc_write_regs().

◆ mips32_cpu_support_sync()

bool mips32_cpu_support_sync ( struct mips_ejtag * ejtag_info )

mips32_cpu_support_sync - Checks CPU supports ordering

Parameters

[in] ejtag_info MIPS EJTAG information structure.

MIPS ISA implemented on Lexra CPUs is MIPS-I, similar to R3000, which does not have the SYNC instruction alone with unaligned load/store instructions.

Returns: true if current CPU supports sync instruction(CPU is not Lexra)

Definition at line 963 of file mips32.c.

References mips32_cpu_is_lexra().

Referenced by mips32_pracc_fastdata_xfer(), mips32_pracc_read_mem(), mips32_pracc_read_u32(), and mips32_pracc_write_mem().

◆ mips32_enable_interrupts()

int mips32_enable_interrupts	(	struct target *	target,
		int	enable
	)

Definition at line 860 of file mips32.c.

References EJTAG_DCR, EJTAG_DCR_INTE, ERROR_OK, target_read_u32(), and target_write_u32().

Referenced by mips_m4k_internal_restore(), mips_m4k_single_step_core(), and mips_m4k_step().

◆ mips32_examine()

int mips32_examine ( struct target * target )

Definition at line 732 of file mips32.c.

References mips32_common::bp_scanned, ERROR_OK, mips32_common::num_data_bpoints, mips32_common::num_data_bpoints_avail, mips32_common::num_inst_bpoints, mips32_common::num_inst_bpoints_avail, target_set_examined(), target_to_mips32(), and target_was_examined().

Referenced by mips_m4k_examine().

◆ mips32_get_gdb_reg_list()

int mips32_get_gdb_reg_list	(	struct target *	target,
		struct reg **	reg_list[],
		int *	reg_list_size,
		enum target_register_class	reg_class
	)

Definition at line 429 of file mips32.c.

References mips32_common::core_cache, ERROR_OK, MIPS32_NUM_REGS, reg_cache::reg_list, and target_to_mips32().

◆ mips32_init_arch_info()

int mips32_init_arch_info	(	struct target *	target,
		struct mips32_common *	mips32,
		struct jtag_tap *	tap
	)

◆ mips32_read_config_regs()

int mips32_read_config_regs ( struct target * target )

◆ mips32_register_commands()

int mips32_register_commands ( struct command_context * cmd_ctx )

◆ mips32_restore_context()

int mips32_restore_context ( struct target * target )

Definition at line 468 of file mips32.c.

References mips32_common::core_cache, reg::dirty, MIPS32_NUM_REGS, mips32_pracc_write_regs(), reg_cache::reg_list, target_to_mips32(), and mips32_common::write_core_reg.

Referenced by mips_m4k_internal_restore(), and mips_m4k_step().

◆ mips32_run_algorithm()

int mips32_run_algorithm	(	struct target *	target,
		int	num_mem_params,
		struct mem_param *	mem_params,
		int	num_reg_params,
		struct reg_param *	reg_params,
		target_addr_t	entry_point,
		target_addr_t	exit_point,
		unsigned int	timeout_ms,
		void *	arch_info
	)

◆ mips32_save_context()

int mips32_save_context ( struct target * target )

Definition at line 446 of file mips32.c.

References mips32_common::core_cache, ERROR_OK, LOG_ERROR, MIPS32_NUM_REGS, mips32_pracc_read_regs(), mips32_common::read_core_reg, reg_cache::reg_list, target_to_mips32(), and reg::valid.

Referenced by mips_m4k_debug_entry().

◆ target_to_mips32()

static struct mips32_common* target_to_mips32 ( struct target * target )

inlinestatic

Definition at line 444 of file mips32.h.

References target::arch_info.

Referenced by ath79_spi_bitbang_chunk(), COMMAND_HANDLER(), mips32_arch_state(), mips32_blank_check_memory(), mips32_build_reg_cache(), mips32_checksum_memory(), mips32_configure_break_unit(), mips32_configure_dbs(), mips32_configure_ibs(), mips32_cpu_probe(), mips32_examine(), mips32_get_core_reg(), mips32_get_gdb_reg_list(), mips32_read_c0_prid(), mips32_read_config_regs(), mips32_read_core_reg(), mips32_restore_context(), mips32_run_algorithm(), mips32_save_context(), mips32_write_core_reg(), mips_m4k_add_breakpoint(), mips_m4k_add_watchpoint(), mips_m4k_bulk_read_memory(), mips_m4k_bulk_write_memory(), mips_m4k_debug_entry(), mips_m4k_examine_debug_reason(), mips_m4k_halt(), mips_m4k_internal_restore(), mips_m4k_poll(), mips_m4k_read_memory(), mips_m4k_remove_breakpoint(), mips_m4k_remove_watchpoint(), mips_m4k_set_breakpoint(), mips_m4k_set_watchpoint(), mips_m4k_single_step_core(), mips_m4k_step(), mips_m4k_unset_breakpoint(), mips_m4k_unset_watchpoint(), and mips_m4k_write_memory().

Variable Documentation

◆ mips32_command_handlers

const struct command_registration mips32_command_handlers[]

extern

Definition at line 2351 of file mips32.c.

◆ mips32_cp0_regs

const struct mips32_cp0 mips32_cp0_regs[]

static

Referenced by mips32_cp0_find_register_by_name(), and mips32_cp0_get_all_regs().

◆ mips32_cpu_entry

const struct cpu_entry mips32_cpu_entry[]

static

Referenced by COMMAND_HANDLER(), and mips32_find_cpu_by_prid().

Data Structures

Macros

Enumerations

Functions

Variables

Macro Definition Documentation

◆ EJTAG_QUIRK_PAD_DRET

◆ KSEG0

◆ KSEG1

◆ KSEG2

◆ KSEG3

◆ KSEGX

◆ KUSEG

◆ MICRO_MIPS32_SDBBP

◆ MICRO_MIPS_SDBBP

◆ MIPS16_ISA_SDBBP

◆ MIPS16_SDBBP

◆ MIPS32_ADDI

◆ MIPS32_ADDIU

◆ MIPS32_ADDU

◆ MIPS32_AND

◆ MIPS32_ANDI

◆ MIPS32_ARCH_REL1

◆ MIPS32_ARCH_REL2

◆ MIPS32_B

◆ MIPS32_BEQ

◆ MIPS32_BGTZ

◆ MIPS32_BNE

◆ MIPS32_C0_BADVADDR

◆ MIPS32_C0_CACHEERR

◆ MIPS32_C0_CAUSE

◆ MIPS32_C0_COMPARE

◆ MIPS32_C0_CONFIG

◆ MIPS32_C0_CONFIG0

◆ MIPS32_C0_CONFIG1

◆ MIPS32_C0_CONFIG2

◆ MIPS32_C0_CONFIG3

◆ MIPS32_C0_CONTEXT

◆ MIPS32_C0_COUNT

◆ MIPS32_C0_CR

◆ MIPS32_C0_CTXT

◆ MIPS32_C0_DATAHI

◆ MIPS32_C0_DATALO

◆ MIPS32_C0_DATALO2

◆ MIPS32_C0_DDATALO

◆ MIPS32_C0_DEBUG

◆ MIPS32_C0_DEPC

◆ MIPS32_C0_DESAVE

◆ MIPS32_C0_DTAGLO

◆ MIPS32_C0_EBASE

◆ MIPS32_C0_ENTRYHI

◆ MIPS32_C0_ENTRYLO0

◆ MIPS32_C0_ENTRYLO1

◆ MIPS32_C0_EPC

◆ MIPS32_C0_ERRCTL

◆ MIPS32_C0_ERRPC

◆ MIPS32_C0_GUESTCTL1

◆ MIPS32_C0_HWRENA

◆ MIPS32_C0_IDATALO

◆ MIPS32_C0_INDEX

◆ MIPS32_C0_INTCTL

◆ MIPS32_C0_INX

◆ MIPS32_C0_ITAGHI

◆ MIPS32_C0_ITAGLO

◆ MIPS32_C0_LLADDR

◆ MIPS32_C0_PAGEGRAIN

◆ MIPS32_C0_PAGEMASK

◆ MIPS32_C0_PERFCNT

◆ MIPS32_C0_PRID

◆ MIPS32_C0_RAND

◆ MIPS32_C0_RANDOM

◆ MIPS32_C0_SR

◆ MIPS32_C0_SRSCTL

◆ MIPS32_C0_SRSMAP

◆ MIPS32_C0_STATUS

◆ MIPS32_C0_TAGHI

◆ MIPS32_C0_TAGLO

◆ MIPS32_C0_TAGLO2

◆ MIPS32_C0_TLBHI

◆ MIPS32_C0_TLBLO0