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arm9tdmi.c
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1 // SPDX-License-Identifier: GPL-2.0-or-later
2 
3 /***************************************************************************
4  * Copyright (C) 2005 by Dominic Rath *
5  * Dominic.Rath@gmx.de *
6  * *
7  * Copyright (C) 2008 by Spencer Oliver *
8  * spen@spen-soft.co.uk *
9  * *
10  * Copyright (C) 2008 by Hongtao Zheng *
11  * hontor@126.com *
12  ***************************************************************************/
13 
14 #ifdef HAVE_CONFIG_H
15 #include "config.h"
16 #endif
17 
18 #include "arm9tdmi.h"
19 #include "target_type.h"
20 #include "register.h"
21 #include "arm_opcodes.h"
22 #include "arm_semihosting.h"
23 
24 /*
25  * NOTE: this holds code that's used with multiple ARM9 processors:
26  * - ARM9TDMI (ARMv4T) ... in ARM920, ARM922, and ARM940 cores
27  * - ARM9E-S (ARMv5TE) ... in ARM946, ARM966, and ARM968 cores
28  * - ARM9EJS (ARMv5TEJ) ... in ARM926 core
29  *
30  * In short, the file name is a misnomer ... it is NOT specific to
31  * that first generation ARM9 processor, or cores using it.
32  */
33 
34 #if 0
35 #define _DEBUG_INSTRUCTION_EXECUTION_
36 #endif
37 
44  /* BIT(5) reserved -- must be zero */
47 };
48 
49 static const struct arm9tdmi_vector {
50  const char *name;
51  uint32_t value;
52 } arm9tdmi_vectors[] = {
53  {"reset", ARM9TDMI_RESET_VECTOR},
54  {"undef", ARM9TDMI_UNDEF_VECTOR},
55  {"swi", ARM9TDMI_SWI_VECTOR},
56  {"pabt", ARM9TDMI_PABT_VECTOR},
57  {"dabt", ARM9TDMI_DABT_VECTOR},
58  {"irq", ARM9TDMI_IRQ_VECTOR},
59  {"fiq", ARM9TDMI_FIQ_VECTOR},
60  {0, 0},
61 };
62 
64 {
65  int retval = ERROR_OK;
66  struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
67 
68  /* only check the debug reason if we don't know it already */
71  struct scan_field fields[3];
72  uint8_t databus[4];
73  uint8_t instructionbus[4];
74  uint8_t debug_reason;
75 
76  fields[0].num_bits = 32;
77  fields[0].out_value = NULL;
78  fields[0].in_value = databus;
79 
80  fields[1].num_bits = 3;
81  fields[1].out_value = NULL;
82  fields[1].in_value = &debug_reason;
83 
84  fields[2].num_bits = 32;
85  fields[2].out_value = NULL;
86  fields[2].in_value = instructionbus;
87 
88  retval = arm_jtag_scann(&arm7_9->jtag_info, 0x1, TAP_DRPAUSE);
89  if (retval != ERROR_OK)
90  return retval;
92  if (retval != ERROR_OK)
93  return retval;
94 
95  jtag_add_dr_scan(arm7_9->jtag_info.tap, 3, fields, TAP_DRPAUSE);
96  retval = jtag_execute_queue();
97  if (retval != ERROR_OK)
98  return retval;
99 
100  fields[0].in_value = NULL;
101  fields[0].out_value = databus;
102  fields[1].in_value = NULL;
103  fields[1].out_value = &debug_reason;
104  fields[2].in_value = NULL;
105  fields[2].out_value = instructionbus;
106 
107  jtag_add_dr_scan(arm7_9->jtag_info.tap, 3, fields, TAP_DRPAUSE);
108 
109  if (debug_reason & 0x4)
110  if (debug_reason & 0x2)
112  else
114  else
116  }
117 
118  return ERROR_OK;
119 }
120 
121 /* put an instruction in the ARM9TDMI pipeline or write the data bus,
122  * and optionally read data
123  */
124 int arm9tdmi_clock_out(struct arm_jtag *jtag_info, uint32_t instr,
125  uint32_t out, uint32_t *in, int sysspeed)
126 {
127  int retval = ERROR_OK;
128  struct scan_field fields[3];
129  uint8_t out_buf[4];
130  uint8_t instr_buf[4];
131  uint8_t sysspeed_buf = 0x0;
132 
133  /* prepare buffer */
134  buf_set_u32(out_buf, 0, 32, out);
135 
136  buf_set_u32(instr_buf, 0, 32, flip_u32(instr, 32));
137 
138  if (sysspeed)
139  buf_set_u32(&sysspeed_buf, 2, 1, 1);
140 
141  retval = arm_jtag_scann(jtag_info, 0x1, TAP_DRPAUSE);
142  if (retval != ERROR_OK)
143  return retval;
144 
145  retval = arm_jtag_set_instr(jtag_info->tap, jtag_info->intest_instr, NULL, TAP_DRPAUSE);
146  if (retval != ERROR_OK)
147  return retval;
148 
149  fields[0].num_bits = 32;
150  fields[0].out_value = out_buf;
151  fields[0].in_value = NULL;
152 
153  fields[1].num_bits = 3;
154  fields[1].out_value = &sysspeed_buf;
155  fields[1].in_value = NULL;
156 
157  fields[2].num_bits = 32;
158  fields[2].out_value = instr_buf;
159  fields[2].in_value = NULL;
160 
161  if (in) {
162  fields[0].in_value = (uint8_t *)in;
163  jtag_add_dr_scan(jtag_info->tap, 3, fields, TAP_DRPAUSE);
164 
166  } else
167  jtag_add_dr_scan(jtag_info->tap, 3, fields, TAP_DRPAUSE);
168 
170 
171 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
172  {
173  retval = jtag_execute_queue();
174  if (retval != ERROR_OK)
175  return retval;
176 
177  if (in)
178  LOG_DEBUG("instr: 0x%8.8x, out: 0x%8.8x, in: 0x%8.8x", instr, out, *in);
179  else
180  LOG_DEBUG("instr: 0x%8.8x, out: 0x%8.8x", instr, out);
181  }
182 #endif
183 
184  return ERROR_OK;
185 }
186 
187 /* just read data (instruction and data-out = don't care) */
188 int arm9tdmi_clock_data_in(struct arm_jtag *jtag_info, uint32_t *in)
189 {
190  int retval = ERROR_OK;
191  struct scan_field fields[3];
192 
193  retval = arm_jtag_scann(jtag_info, 0x1, TAP_DRPAUSE);
194  if (retval != ERROR_OK)
195  return retval;
196 
197  retval = arm_jtag_set_instr(jtag_info->tap, jtag_info->intest_instr, NULL, TAP_DRPAUSE);
198  if (retval != ERROR_OK)
199  return retval;
200 
201  fields[0].num_bits = 32;
202  fields[0].out_value = NULL;
203  fields[0].in_value = (uint8_t *)in;
204 
205  fields[1].num_bits = 3;
206  fields[1].out_value = NULL;
207  fields[1].in_value = NULL;
208 
209  fields[2].num_bits = 32;
210  fields[2].out_value = NULL;
211  fields[2].in_value = NULL;
212 
213  jtag_add_dr_scan(jtag_info->tap, 3, fields, TAP_DRPAUSE);
214 
216 
218 
219 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
220  {
221  retval = jtag_execute_queue();
222  if (retval != ERROR_OK)
223  return retval;
224 
225  if (in)
226  LOG_DEBUG("in: 0x%8.8x", *in);
227  else
228  LOG_ERROR("BUG: called with in == NULL");
229  }
230 #endif
231 
232  return ERROR_OK;
233 }
234 
235 /* clock the target, and read the databus
236  * the *in pointer points to a buffer where elements of 'size' bytes
237  * are stored in big (be == 1) or little (be == 0) endianness
238  */
240  void *in, int size, int be)
241 {
242  int retval = ERROR_OK;
243  struct scan_field fields[2];
244 
245  retval = arm_jtag_scann(jtag_info, 0x1, TAP_DRPAUSE);
246  if (retval != ERROR_OK)
247  return retval;
248 
249  retval = arm_jtag_set_instr(jtag_info->tap, jtag_info->intest_instr, NULL, TAP_DRPAUSE);
250  if (retval != ERROR_OK)
251  return retval;
252 
253  if (size == 4) {
254  fields[0].num_bits = 32;
255  fields[0].out_value = NULL;
256  fields[0].in_value = in;
257 
258  fields[1].num_bits = 3 + 32;
259  fields[1].out_value = NULL;
260  fields[1].in_value = NULL;
261  } else {
262  /* Discard irrelevant bits of the scan, making sure we don't write more
263  * than size bytes to in */
264  fields[0].num_bits = size * 8;
265  fields[0].out_value = NULL;
266  fields[0].in_value = in;
267 
268  fields[1].num_bits = 3 + 32 + 32 - size * 8;
269  fields[1].out_value = NULL;
270  fields[1].in_value = NULL;
271  }
272 
273  jtag_add_dr_scan(jtag_info->tap, 2, fields, TAP_DRPAUSE);
274 
280 
282 
283 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
284  {
285  retval = jtag_execute_queue();
286  if (retval != ERROR_OK)
287  return retval;
288 
289  if (in)
290  LOG_DEBUG("in: 0x%8.8x", *(uint32_t *)in);
291  else
292  LOG_ERROR("BUG: called with in == NULL");
293  }
294 #endif
295 
296  return ERROR_OK;
297 }
298 
300  uint32_t *r0, uint32_t *pc)
301 {
302  int retval = ERROR_OK;
303  struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
304  struct arm_jtag *jtag_info = &arm7_9->jtag_info;
305 
306  /* save r0 before using it and put system in ARM state
307  * to allow common handling of ARM and THUMB debugging */
308 
309  /* fetch STR r0, [r0] */
310  arm9tdmi_clock_out(jtag_info, ARMV4_5_T_STR(0, 0), 0, NULL, 0);
311  arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
312  arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
313  /* STR r0, [r0] in Memory */
314  arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, r0, 0);
315 
316  /* MOV r0, r15 fetched, STR in Decode */
317  arm9tdmi_clock_out(jtag_info, ARMV4_5_T_MOV(0, 15), 0, NULL, 0);
318  arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
319  arm9tdmi_clock_out(jtag_info, ARMV4_5_T_STR(0, 0), 0, NULL, 0);
320  arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
321  arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
322  /* nothing fetched, STR r0, [r0] in Memory */
323  arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, pc, 0);
324 
325  /* use pc-relative LDR to clear r0[1:0] (for switch to ARM mode) */
326  arm9tdmi_clock_out(jtag_info, ARMV4_5_T_LDR_PCREL(0), 0, NULL, 0);
327  /* LDR in Decode */
328  arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
329  /* LDR in Execute */
330  arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
331  /* LDR in Memory (to account for interlock) */
332  arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
333 
334  /* fetch BX */
335  arm9tdmi_clock_out(jtag_info, ARMV4_5_T_BX(0), 0, NULL, 0);
336  /* NOP fetched, BX in Decode, MOV in Execute */
337  arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
338  /* NOP fetched, BX in Execute (1) */
339  arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
340 
341  retval = jtag_execute_queue();
342  if (retval != ERROR_OK)
343  return;
344 
345  /* fix program counter:
346  * MOV r0, r15 was the 5th instruction (+8)
347  * reading PC in Thumb state gives address of instruction + 4
348  */
349  *pc -= 0xc;
350 }
351 
353  uint32_t mask, uint32_t *core_regs[16])
354 {
355  int i;
356  struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
357  struct arm_jtag *jtag_info = &arm7_9->jtag_info;
358 
359  /* STMIA r0-15, [r0] at debug speed
360  * register values will start to appear on 4th DCLK
361  */
362  arm9tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask & 0xffff, 0, 0), 0, NULL, 0);
363 
364  /* fetch NOP, STM in DECODE stage */
365  arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
366  /* fetch NOP, STM in EXECUTE stage (1st cycle) */
367  arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
368 
369  for (i = 0; i <= 15; i++) {
370  if (mask & (1 << i))
371  /* nothing fetched, STM in MEMORY (i'th cycle) */
372  arm9tdmi_clock_data_in(jtag_info, core_regs[i]);
373  }
374 }
375 
377  uint32_t mask, void *buffer, int size)
378 {
379  int i;
380  struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
381  struct arm_jtag *jtag_info = &arm7_9->jtag_info;
382  int be = (target->endianness == TARGET_BIG_ENDIAN) ? 1 : 0;
383  uint32_t *buf_u32 = buffer;
384  uint16_t *buf_u16 = buffer;
385  uint8_t *buf_u8 = buffer;
386 
387  /* STMIA r0-15, [r0] at debug speed
388  * register values will start to appear on 4th DCLK
389  */
390  arm9tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask & 0xffff, 0, 0), 0, NULL, 0);
391 
392  /* fetch NOP, STM in DECODE stage */
393  arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
394  /* fetch NOP, STM in EXECUTE stage (1st cycle) */
395  arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
396 
397  for (i = 0; i <= 15; i++) {
398  if (mask & (1 << i))
399  /* nothing fetched, STM in MEMORY (i'th cycle) */
400  switch (size) {
401  case 4:
402  arm9tdmi_clock_data_in_endianness(jtag_info, buf_u32++, 4, be);
403  break;
404  case 2:
405  arm9tdmi_clock_data_in_endianness(jtag_info, buf_u16++, 2, be);
406  break;
407  case 1:
408  arm9tdmi_clock_data_in_endianness(jtag_info, buf_u8++, 1, be);
409  break;
410  }
411  }
412 }
413 
414 static void arm9tdmi_read_xpsr(struct target *target, uint32_t *xpsr, int spsr)
415 {
416  struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
417  struct arm_jtag *jtag_info = &arm7_9->jtag_info;
418 
419  /* MRS r0, cpsr */
420  arm9tdmi_clock_out(jtag_info, ARMV4_5_MRS(0, spsr & 1), 0, NULL, 0);
421  arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
422  arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
423  arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
424  arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
425 
426  /* STR r0, [r15] */
427  arm9tdmi_clock_out(jtag_info, ARMV4_5_STR(0, 15), 0, NULL, 0);
428  /* fetch NOP, STR in DECODE stage */
429  arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
430  /* fetch NOP, STR in EXECUTE stage (1st cycle) */
431  arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
432  /* nothing fetched, STR in MEMORY */
433  arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, xpsr, 0);
434 }
435 
436 static void arm9tdmi_write_xpsr(struct target *target, uint32_t xpsr, int spsr)
437 {
438  struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
439  struct arm_jtag *jtag_info = &arm7_9->jtag_info;
440 
441  LOG_DEBUG("xpsr: %8.8" PRIx32 ", spsr: %i", xpsr, spsr);
442 
443  /* MSR1 fetched */
444  arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM(xpsr & 0xff, 0, 1, spsr), 0, NULL, 0);
445  /* MSR2 fetched, MSR1 in DECODE */
446  arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM((xpsr & 0xff00) >> 8, 0xc, 2, spsr), 0, NULL, 0);
447  /* MSR3 fetched, MSR1 in EXECUTE (1), MSR2 in DECODE */
448  arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM((xpsr & 0xff0000) >> 16, 0x8, 4, spsr), 0, NULL, 0);
449  /* nothing fetched, MSR1 in EXECUTE (2) */
450  arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
451  /* nothing fetched, MSR1 in EXECUTE (3) */
452  arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
453  /* MSR4 fetched, MSR2 in EXECUTE (1), MSR3 in DECODE */
454  arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM((xpsr & 0xff000000) >> 24, 0x4, 8, spsr), 0, NULL, 0);
455  /* nothing fetched, MSR2 in EXECUTE (2) */
456  arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
457  /* nothing fetched, MSR2 in EXECUTE (3) */
458  arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
459  /* NOP fetched, MSR3 in EXECUTE (1), MSR4 in DECODE */
460  arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
461  /* nothing fetched, MSR3 in EXECUTE (2) */
462  arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
463  /* nothing fetched, MSR3 in EXECUTE (3) */
464  arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
465  /* NOP fetched, MSR4 in EXECUTE (1) */
466  /* last MSR writes flags, which takes only one cycle */
467  arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
468 }
469 
471  uint8_t xpsr_im, int rot, int spsr)
472 {
473  struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
474  struct arm_jtag *jtag_info = &arm7_9->jtag_info;
475 
476  LOG_DEBUG("xpsr_im: %2.2x, rot: %i, spsr: %i", xpsr_im, rot, spsr);
477 
478  /* MSR fetched */
479  arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM(xpsr_im, rot, 1, spsr), 0, NULL, 0);
480  /* NOP fetched, MSR in DECODE */
481  arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
482  /* NOP fetched, MSR in EXECUTE (1) */
483  arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
484 
485  /* rot == 4 writes flags, which takes only one cycle */
486  if (rot != 4) {
487  /* nothing fetched, MSR in EXECUTE (2) */
488  arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
489  /* nothing fetched, MSR in EXECUTE (3) */
490  arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
491  }
492 }
493 
495  uint32_t mask, uint32_t core_regs[16])
496 {
497  int i;
498  struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
499  struct arm_jtag *jtag_info = &arm7_9->jtag_info;
500 
501  /* LDMIA r0-15, [r0] at debug speed
502  * register values will start to appear on 4th DCLK
503  */
504  arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, mask & 0xffff, 0, 0), 0, NULL, 0);
505 
506  /* fetch NOP, LDM in DECODE stage */
507  arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
508  /* fetch NOP, LDM in EXECUTE stage (1st cycle) */
509  arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
510 
511  for (i = 0; i <= 15; i++) {
512  if (mask & (1 << i))
513  /* nothing fetched, LDM still in EXECUTE (1 + i cycle) */
514  arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, core_regs[i], NULL, 0);
515  }
516  arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
517 }
518 
519 void arm9tdmi_load_word_regs(struct target *target, uint32_t mask)
520 {
521  struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
522  struct arm_jtag *jtag_info = &arm7_9->jtag_info;
523 
524  /* put system-speed load-multiple into the pipeline */
525  arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, mask & 0xffff, 0, 1), 0, NULL, 0);
526  arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
527 }
528 
529 void arm9tdmi_load_hword_reg(struct target *target, int num)
530 {
531  struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
532  struct arm_jtag *jtag_info = &arm7_9->jtag_info;
533 
534  /* put system-speed load half-word into the pipeline */
535  arm9tdmi_clock_out(jtag_info, ARMV4_5_LDRH_IP(num, 0), 0, NULL, 0);
536  arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
537 }
538 
539 void arm9tdmi_load_byte_reg(struct target *target, int num)
540 {
541  struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
542  struct arm_jtag *jtag_info = &arm7_9->jtag_info;
543 
544  /* put system-speed load byte into the pipeline */
545  arm9tdmi_clock_out(jtag_info, ARMV4_5_LDRB_IP(num, 0), 0, NULL, 0);
546  arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
547 }
548 
550 {
551  struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
552  struct arm_jtag *jtag_info = &arm7_9->jtag_info;
553 
554  /* put system-speed store-multiple into the pipeline */
555  arm9tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask, 0, 1), 0, NULL, 0);
556  arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
557 }
558 
559 void arm9tdmi_store_hword_reg(struct target *target, int num)
560 {
561  struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
562  struct arm_jtag *jtag_info = &arm7_9->jtag_info;
563 
564  /* put system-speed store half-word into the pipeline */
565  arm9tdmi_clock_out(jtag_info, ARMV4_5_STRH_IP(num, 0), 0, NULL, 0);
566  arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
567 }
568 
569 void arm9tdmi_store_byte_reg(struct target *target, int num)
570 {
571  struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
572  struct arm_jtag *jtag_info = &arm7_9->jtag_info;
573 
574  /* put system-speed store byte into the pipeline */
575  arm9tdmi_clock_out(jtag_info, ARMV4_5_STRB_IP(num, 0), 0, NULL, 0);
576  arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
577 }
578 
579 static void arm9tdmi_write_pc(struct target *target, uint32_t pc)
580 {
581  struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
582  struct arm_jtag *jtag_info = &arm7_9->jtag_info;
583 
584  /* LDMIA r0-15, [r0] at debug speed
585  * register values will start to appear on 4th DCLK
586  */
587  arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, 0x8000, 0, 0), 0, NULL, 0);
588 
589  /* fetch NOP, LDM in DECODE stage */
590  arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
591  /* fetch NOP, LDM in EXECUTE stage (1st cycle) */
592  arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
593  /* nothing fetched, LDM in EXECUTE stage (2nd cycle) (output data) */
594  arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, pc, NULL, 0);
595  /* nothing fetched, LDM in EXECUTE stage (3rd cycle) */
596  arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
597  /* fetch NOP, LDM in EXECUTE stage (4th cycle) */
598  arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
599  /* fetch NOP, LDM in EXECUTE stage (5th cycle) */
600  arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
601 }
602 
604 {
605  struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
606  struct arm_jtag *jtag_info = &arm7_9->jtag_info;
607 
608  arm9tdmi_clock_out(jtag_info, ARMV4_5_B(0xfffffc, 0), 0, NULL, 0);
609  arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
610 }
611 
613 {
614  LOG_DEBUG("-");
615 
616  struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
617  struct arm *arm = &arm7_9->arm;
618  struct arm_jtag *jtag_info = &arm7_9->jtag_info;
619  struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
620 
621  /* LDMIA r0-15, [r0] at debug speed
622  * register values will start to appear on 4th DCLK
623  */
624  arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, 0x1, 0, 0), 0, NULL, 0);
625 
626  /* fetch NOP, LDM in DECODE stage */
627  arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
628  /* fetch NOP, LDM in EXECUTE stage (1st cycle) */
629  arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
630  /* nothing fetched, LDM in EXECUTE stage (2nd cycle) */
631  arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP,
632  buf_get_u32(arm->pc->value, 0, 32) | 1, NULL, 0);
633  /* nothing fetched, LDM in EXECUTE stage (3rd cycle) */
634  arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
635 
636  /* Branch and eXchange */
637  arm9tdmi_clock_out(jtag_info, ARMV4_5_BX(0), 0, NULL, 0);
638 
639  embeddedice_read_reg(dbg_stat);
640 
641  /* fetch NOP, BX in DECODE stage */
642  arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
643 
644  embeddedice_read_reg(dbg_stat);
645 
646  /* fetch NOP, BX in EXECUTE stage (1st cycle) */
647  arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
648 
649  /* target is now in Thumb state */
650  embeddedice_read_reg(dbg_stat);
651 
652  /* load r0 value, MOV_IM in Decode*/
653  arm9tdmi_clock_out(jtag_info, ARMV4_5_T_LDR_PCREL(0), 0, NULL, 0);
654  /* fetch NOP, LDR in Decode, MOV_IM in Execute */
655  arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
656  /* fetch NOP, LDR in Execute */
657  arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
658  /* nothing fetched, LDR in EXECUTE stage (2nd cycle) */
660  buf_get_u32(arm->core_cache->reg_list[0].value, 0, 32), NULL, 0);
661  /* nothing fetched, LDR in EXECUTE stage (3rd cycle) */
662  arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
663 
664  arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
665  arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
666 
667  embeddedice_read_reg(dbg_stat);
668 
669  arm9tdmi_clock_out(jtag_info, ARMV4_5_T_B(0x7f7), 0, NULL, 1);
670  arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
671 }
672 
673 void arm9tdmi_enable_single_step(struct target *target, uint32_t next_pc)
674 {
675  struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
676 
677  if (arm7_9->has_single_step) {
678  buf_set_u32(arm7_9->eice_cache->reg_list[EICE_DBG_CTRL].value, 3, 1, 1);
680  } else
682 }
683 
685 {
686  struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
687 
688  if (arm7_9->has_single_step) {
689  buf_set_u32(arm7_9->eice_cache->reg_list[EICE_DBG_CTRL].value, 3, 1, 0);
691  } else
693 }
694 
696 {
697  struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
698  struct arm *arm = target_to_arm(target);
699 
700  (*cache_p) = arm_build_reg_cache(target, arm);
701 }
702 
704  struct target *target)
705 {
708  return ERROR_OK;
709 }
710 
712  struct arm7_9_common *arm7_9, struct jtag_tap *tap)
713 {
714  /* prepare JTAG information for the new target */
715  arm7_9->jtag_info.tap = tap;
716  arm7_9->jtag_info.scann_size = 5;
717 
718  /* register arch-specific functions */
723  arm7_9->read_xpsr = arm9tdmi_read_xpsr;
724 
728 
732 
736 
737  arm7_9->write_pc = arm9tdmi_write_pc;
740 
743 
746 
747  arm7_9->post_debug_entry = NULL;
748 
749  arm7_9->pre_restore_context = NULL;
750 
751  /* initialize arch-specific breakpoint handling */
752  arm7_9->arm_bkpt = 0xdeeedeee;
753  arm7_9->thumb_bkpt = 0xdeee;
754 
755  arm7_9->dbgreq_adjust_pc = 3;
756 
757  arm7_9_init_arch_info(target, arm7_9);
758 
759  /* override use of DBGRQ, this is safe on ARM9TDMI */
760  arm7_9->use_dbgrq = 1;
761 
762  /* all ARM9s have the vector catch register */
763  arm7_9->has_vector_catch = 1;
764 
765  return ERROR_OK;
766 }
767 
768 static int arm9tdmi_target_create(struct target *target, Jim_Interp *interp)
769 {
770  struct arm7_9_common *arm7_9 = calloc(1, sizeof(struct arm7_9_common));
771 
773  arm7_9->arm.arch = ARM_ARCH_V4;
774 
775  return ERROR_OK;
776 }
777 
779 {
780  struct arm *arm = target_to_arm(target);
781  struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
782 
785  free(arm7_9);
786 }
787 
788 COMMAND_HANDLER(handle_arm9tdmi_catch_vectors_command)
789 {
791  struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
792  struct reg *vector_catch;
793  uint32_t vector_catch_value;
794 
795  if (!target_was_examined(target)) {
796  LOG_ERROR("Target not examined yet");
797  return ERROR_FAIL;
798  }
799 
800  /* it's uncommon, but some ARM7 chips can support this */
801  if (arm7_9->common_magic != ARM7_9_COMMON_MAGIC
802  || !arm7_9->has_vector_catch) {
803  command_print(CMD, "target doesn't have EmbeddedICE "
804  "with vector_catch");
805  return ERROR_TARGET_INVALID;
806  }
807 
808  vector_catch = &arm7_9->eice_cache->reg_list[EICE_VEC_CATCH];
809 
810  /* read the vector catch register if necessary */
811  if (!vector_catch->valid)
812  embeddedice_read_reg(vector_catch);
813 
814  /* get the current setting */
815  vector_catch_value = buf_get_u32(vector_catch->value, 0, 8);
816 
817  if (CMD_ARGC > 0) {
818  vector_catch_value = 0x0;
819  if (strcmp(CMD_ARGV[0], "all") == 0)
820  vector_catch_value = 0xdf;
821  else if (strcmp(CMD_ARGV[0], "none") == 0) {
822  /* do nothing */
823  } else {
824  for (unsigned i = 0; i < CMD_ARGC; i++) {
825  /* go through list of vectors */
826  unsigned j;
827  for (j = 0; arm9tdmi_vectors[j].name; j++) {
828  if (strcmp(CMD_ARGV[i], arm9tdmi_vectors[j].name) == 0) {
829  vector_catch_value |= arm9tdmi_vectors[j].value;
830  break;
831  }
832  }
833 
834  /* complain if vector wasn't found */
835  if (!arm9tdmi_vectors[j].name) {
836  command_print(CMD, "vector '%s' not found, leaving current setting unchanged", CMD_ARGV[i]);
837 
838  /* reread current setting */
839  vector_catch_value = buf_get_u32(
840  vector_catch->value,
841  0, 8);
842  break;
843  }
844  }
845  }
846 
847  /* store new settings */
848  buf_set_u32(vector_catch->value, 0, 8, vector_catch_value);
849  embeddedice_store_reg(vector_catch);
850  }
851 
852  /* output current settings */
853  for (unsigned i = 0; arm9tdmi_vectors[i].name; i++) {
854  command_print(CMD, "%s: %s", arm9tdmi_vectors[i].name,
855  (vector_catch_value & arm9tdmi_vectors[i].value)
856  ? "catch" : "don't catch");
857  }
858 
859  return ERROR_OK;
860 }
861 
863  {
864  .name = "vector_catch",
865  .handler = handle_arm9tdmi_catch_vectors_command,
866  .mode = COMMAND_EXEC,
867  .help = "Display, after optionally updating, configuration "
868  "of vector catch unit.",
869  .usage = "[all|none|(reset|undef|swi|pabt|dabt|irq|fiq)*]",
870  },
872 };
874  {
876  },
877  {
878  .name = "arm9",
879  .mode = COMMAND_ANY,
880  .help = "arm9 command group",
881  .usage = "",
883  },
885 };
886 
888 struct target_type arm9tdmi_target = {
889  .name = "arm9tdmi",
890 
891  .poll = arm7_9_poll,
892  .arch_state = arm_arch_state,
893 
894  .target_request_data = arm7_9_target_request_data,
895 
896  .halt = arm7_9_halt,
897  .resume = arm7_9_resume,
898  .step = arm7_9_step,
899 
900  .assert_reset = arm7_9_assert_reset,
901  .deassert_reset = arm7_9_deassert_reset,
902  .soft_reset_halt = arm7_9_soft_reset_halt,
903 
904  .get_gdb_arch = arm_get_gdb_arch,
905  .get_gdb_reg_list = arm_get_gdb_reg_list,
906 
907  .read_memory = arm7_9_read_memory,
908  .write_memory = arm7_9_write_memory_opt,
909 
910  .checksum_memory = arm_checksum_memory,
911  .blank_check_memory = arm_blank_check_memory,
912 
913  .run_algorithm = armv4_5_run_algorithm,
914 
915  .add_breakpoint = arm7_9_add_breakpoint,
916  .remove_breakpoint = arm7_9_remove_breakpoint,
917  .add_watchpoint = arm7_9_add_watchpoint,
918  .remove_watchpoint = arm7_9_remove_watchpoint,
919 
920  .commands = arm9tdmi_command_handlers,
921  .target_create = arm9tdmi_target_create,
922  .init_target = arm9tdmi_init_target,
923  .deinit_target = arm9tdmi_deinit_target,
924  .examine = arm7_9_examine,
925  .check_reset = arm7_9_check_reset,
926 };
int arm7_9_endianness_callback(jtag_callback_data_t pu8_in, jtag_callback_data_t i_size, jtag_callback_data_t i_be, jtag_callback_data_t i_flip)
int arm7_9_write_memory_opt(struct target *target, target_addr_t address, uint32_t size, uint32_t count, const uint8_t *buffer)
int arm7_9_examine(struct target *target)
Perform per-target setup that requires JTAG access.
void arm7_9_disable_eice_step(struct target *target)
void arm7_9_deinit(struct target *target)
int arm7_9_read_memory(struct target *target, target_addr_t address, uint32_t size, uint32_t count, uint8_t *buffer)
int arm7_9_add_breakpoint(struct target *target, struct breakpoint *breakpoint)
Add a breakpoint to an ARM7/9 target.
int arm7_9_soft_reset_halt(struct target *target)
Issue a software reset and halt to an ARM7/9 target.
const struct command_registration arm7_9_command_handlers[]
int arm7_9_assert_reset(struct target *target)
Asserts the reset (SRST) on an ARM7/9 target.
int arm7_9_poll(struct target *target)
Polls an ARM7/9 target for its current status.
int arm7_9_halt(struct target *target)
Halt an ARM7/9 target.
int arm7_9_remove_breakpoint(struct target *target, struct breakpoint *breakpoint)
Removes a breakpoint from an ARM7/9 target.
int arm7_9_remove_watchpoint(struct target *target, struct watchpoint *watchpoint)
Remove a watchpoint from an ARM7/9 target.
int arm7_9_deassert_reset(struct target *target)
Deassert the reset (SRST) signal on an ARM7/9 target.
int arm7_9_write_memory(struct target *target, target_addr_t address, uint32_t size, uint32_t count, const uint8_t *buffer)
void arm7_9_enable_eice_step(struct target *target, uint32_t next_pc)
int arm7_9_bulk_write_memory(struct target *target, target_addr_t address, uint32_t count, const uint8_t *buffer)
int arm7_9_step(struct target *target, int current, target_addr_t address, int handle_breakpoints)
int arm7_9_target_request_data(struct target *target, uint32_t size, uint8_t *buffer)
Get some data from the ARM7/9 target.
int arm7_9_add_watchpoint(struct target *target, struct watchpoint *watchpoint)
Add a watchpoint to an ARM7/9 target.
int arm7_9_check_reset(struct target *target)
int arm7_9_init_arch_info(struct target *target, struct arm7_9_common *arm7_9)
int arm7_9_resume(struct target *target, int current, target_addr_t address, int handle_breakpoints, int debug_execution)
#define ARM7_9_COMMON_MAGIC
Definition: arm7_9_common.h:23
static struct arm7_9_common * target_to_arm7_9(struct target *target)
void arm9tdmi_deinit_target(struct target *target)
Definition: arm9tdmi.c:778
static void arm9tdmi_write_pc(struct target *target, uint32_t pc)
Definition: arm9tdmi.c:579
static void arm9tdmi_write_xpsr(struct target *target, uint32_t xpsr, int spsr)
Definition: arm9tdmi.c:436
void arm9tdmi_load_hword_reg(struct target *target, int num)
Definition: arm9tdmi.c:529
void arm9tdmi_load_byte_reg(struct target *target, int num)
Definition: arm9tdmi.c:539
int arm9tdmi_init_arch_info(struct target *target, struct arm7_9_common *arm7_9, struct jtag_tap *tap)
Definition: arm9tdmi.c:711
arm9tdmi_vector_bit
Definition: arm9tdmi.c:38
@ ARM9TDMI_UNDEF_VECTOR
Definition: arm9tdmi.c:40
@ ARM9TDMI_DABT_VECTOR
Definition: arm9tdmi.c:43
@ ARM9TDMI_IRQ_VECTOR
Definition: arm9tdmi.c:45
@ ARM9TDMI_SWI_VECTOR
Definition: arm9tdmi.c:41
@ ARM9TDMI_FIQ_VECTOR
Definition: arm9tdmi.c:46
@ ARM9TDMI_PABT_VECTOR
Definition: arm9tdmi.c:42
@ ARM9TDMI_RESET_VECTOR
Definition: arm9tdmi.c:39
static void arm9tdmi_read_xpsr(struct target *target, uint32_t *xpsr, int spsr)
Definition: arm9tdmi.c:414
static const struct command_registration arm9tdmi_exec_command_handlers[]
Definition: arm9tdmi.c:862
void arm9tdmi_read_core_regs(struct target *target, uint32_t mask, uint32_t *core_regs[16])
Definition: arm9tdmi.c:352
void arm9tdmi_store_byte_reg(struct target *target, int num)
Definition: arm9tdmi.c:569
static void arm9tdmi_read_core_regs_target_buffer(struct target *target, uint32_t mask, void *buffer, int size)
Definition: arm9tdmi.c:376
void arm9tdmi_store_hword_reg(struct target *target, int num)
Definition: arm9tdmi.c:559
static void arm9tdmi_branch_resume_thumb(struct target *target)
Definition: arm9tdmi.c:612
struct target_type arm9tdmi_target
Holds methods for ARM9TDMI targets.
Definition: arm9tdmi.c:888
int arm9tdmi_init_target(struct command_context *cmd_ctx, struct target *target)
Definition: arm9tdmi.c:703
int arm9tdmi_clock_data_in_endianness(struct arm_jtag *jtag_info, void *in, int size, int be)
Definition: arm9tdmi.c:239
void arm9tdmi_enable_single_step(struct target *target, uint32_t next_pc)
Definition: arm9tdmi.c:673
const struct command_registration arm9tdmi_command_handlers[]
Definition: arm9tdmi.c:873
int arm9tdmi_clock_data_in(struct arm_jtag *jtag_info, uint32_t *in)
Definition: arm9tdmi.c:188
int arm9tdmi_examine_debug_reason(struct target *target)
Definition: arm9tdmi.c:63
void arm9tdmi_load_word_regs(struct target *target, uint32_t mask)
Definition: arm9tdmi.c:519
void arm9tdmi_write_core_regs(struct target *target, uint32_t mask, uint32_t core_regs[16])
Definition: arm9tdmi.c:494
static void arm9tdmi_change_to_arm(struct target *target, uint32_t *r0, uint32_t *pc)
Definition: arm9tdmi.c:299
COMMAND_HANDLER(handle_arm9tdmi_catch_vectors_command)
Definition: arm9tdmi.c:788
void arm9tdmi_store_word_regs(struct target *target, uint32_t mask)
Definition: arm9tdmi.c:549
void arm9tdmi_branch_resume(struct target *target)
Definition: arm9tdmi.c:603
void arm9tdmi_disable_single_step(struct target *target)
Definition: arm9tdmi.c:684
static int arm9tdmi_target_create(struct target *target, Jim_Interp *interp)
Definition: arm9tdmi.c:768
static void arm9tdmi_build_reg_cache(struct target *target)
Definition: arm9tdmi.c:695
static const struct arm9tdmi_vector arm9tdmi_vectors[]
int arm9tdmi_clock_out(struct arm_jtag *jtag_info, uint32_t instr, uint32_t out, uint32_t *in, int sysspeed)
Definition: arm9tdmi.c:124
static void arm9tdmi_write_xpsr_im8(struct target *target, uint8_t xpsr_im, int rot, int spsr)
Definition: arm9tdmi.c:470
int arm_blank_check_memory(struct target *target, struct target_memory_check_block *blocks, int num_blocks, uint8_t erased_value)
Runs ARM code in the target to check whether a memory block holds all ones.
Definition: armv4_5.c:1595
int arm_arch_state(struct target *target)
Definition: armv4_5.c:782
int arm_checksum_memory(struct target *target, target_addr_t address, uint32_t count, uint32_t *checksum)
Runs ARM code in the target to calculate a CRC32 checksum.
Definition: armv4_5.c:1522
@ ARM_ARCH_V4
Definition: arm.h:55
struct reg_cache * arm_build_reg_cache(struct target *target, struct arm *arm)
Definition: armv4_5.c:646
int arm_get_gdb_reg_list(struct target *target, struct reg **reg_list[], int *reg_list_size, enum target_register_class reg_class)
Definition: armv4_5.c:1194
int armv4_5_run_algorithm(struct target *target, int num_mem_params, struct mem_param *mem_params, int num_reg_params, struct reg_param *reg_params, target_addr_t entry_point, target_addr_t exit_point, int timeout_ms, void *arch_info)
Definition: armv4_5.c:1496
void arm_free_reg_cache(struct arm *arm)
Definition: armv4_5.c:761
const char * arm_get_gdb_arch(struct target *target)
Definition: armv4_5.c:1189
static struct arm * target_to_arm(struct target *target)
Convert target handle to generic ARM target state handle.
Definition: arm.h:243
static int arm_jtag_scann(struct arm_jtag *jtag_info, uint32_t new_scan_chain, tap_state_t end_state)
Definition: arm_jtag.h:43
static int arm_jtag_set_instr(struct jtag_tap *tap, uint32_t new_instr, void *no_verify_capture, tap_state_t end_state)
Definition: arm_jtag.h:31
static void arm_le_to_h_u32(jtag_callback_data_t arg)
Definition: arm_jtag.h:63
Macros used to generate various ARM or Thumb opcodes.
#define ARMV4_5_T_BX(rm)
Definition: arm_opcodes.h:277
#define ARMV4_5_BX(rm)
Definition: arm_opcodes.h:122
#define ARMV4_5_T_NOP
Definition: arm_opcodes.h:264
#define ARMV4_5_LDMIA(rn, list, s, w)
Definition: arm_opcodes.h:42
#define ARMV4_5_T_B(imm)
Definition: arm_opcodes.h:284
#define ARMV4_5_MRS(rn, r)
Definition: arm_opcodes.h:52
#define ARMV4_5_STRH_IP(rd, rn)
Definition: arm_opcodes.h:105
#define ARMV4_5_T_MOV(rd, rm)
Definition: arm_opcodes.h:254
#define ARMV4_5_LDRH_IP(rd, rn)
Definition: arm_opcodes.h:87
#define ARMV4_5_LDRB_IP(rd, rn)
Definition: arm_opcodes.h:93
#define ARMV4_5_T_LDR_PCREL(rd)
Definition: arm_opcodes.h:246
#define ARMV4_5_B(im, l)
Definition: arm_opcodes.h:117
#define ARMV4_5_STR(rd, rn)
Definition: arm_opcodes.h:58
#define ARMV4_5_NOP
Definition: arm_opcodes.h:46
#define ARMV4_5_STMIA(rn, list, s, w)
Definition: arm_opcodes.h:33
#define ARMV4_5_MSR_IM(im, rotate, field, r)
Definition: arm_opcodes.h:74
#define ARMV4_5_STRB_IP(rd, rn)
Definition: arm_opcodes.h:111
#define ARMV4_5_T_STR(rd, rn)
Definition: arm_opcodes.h:223
int arm_semihosting_init(struct target *target)
Initialize ARM semihosting support.
const char * name
Definition: armv4_5.c:76
uint32_t flip_u32(uint32_t value, unsigned int num)
Definition: binarybuffer.c:166
static uint32_t buf_get_u32(const uint8_t *_buffer, unsigned first, unsigned num)
Retrieves num bits from _buffer, starting at the first bit, returning the bits in a 32-bit word.
Definition: binarybuffer.h:98
static void buf_set_u32(uint8_t *_buffer, unsigned first, unsigned num, uint32_t value)
Sets num bits in _buffer, starting at the first bit, using the bits in value.
Definition: binarybuffer.h:30
void command_print(struct command_invocation *cmd, const char *format,...)
Definition: command.c:473
#define CMD
Use this macro to access the command being handled, rather than accessing the variable directly.
Definition: command.h:140
#define CMD_ARGV
Use this macro to access the arguments for the command being handled, rather than accessing the varia...
Definition: command.h:155
#define CMD_ARGC
Use this macro to access the number of arguments for the command being handled, rather than accessing...
Definition: command.h:150
#define CMD_CTX
Use this macro to access the context of the command being handled, rather than accessing the variable...
Definition: command.h:145
#define COMMAND_REGISTRATION_DONE
Use this as the last entry in an array of command_registration records.
Definition: command.h:247
@ COMMAND_ANY
Definition: command.h:42
@ COMMAND_EXEC
Definition: command.h:40
void embeddedice_store_reg(struct reg *reg)
Queue a write for an EmbeddedICE register, using cached value.
Definition: embeddedice.c:519
int embeddedice_read_reg(struct reg *reg)
Queue a read for an EmbeddedICE register into the register cache, not checking the value read.
Definition: embeddedice.c:464
@ EICE_DBG_CTRL
Definition: embeddedice.h:20
@ EICE_VEC_CATCH
Definition: embeddedice.h:36
@ EICE_DBG_STAT
Definition: embeddedice.h:21
int mask
Definition: esirisc.c:1698
int jtag_execute_queue(void)
For software FIFO implementations, the queued commands can be executed during this call or earlier.
Definition: jtag/core.c:1037
void jtag_add_runtest(int num_cycles, tap_state_t state)
Goes to TAP_IDLE (if we're not already there), cycle precisely num_cycles in the TAP_IDLE state,...
Definition: jtag/core.c:592
void jtag_add_dr_scan(struct jtag_tap *active, int in_num_fields, const struct scan_field *in_fields, tap_state_t state)
Generate a DR SCAN using the fields passed to the function.
Definition: jtag/core.c:451
void jtag_add_callback4(jtag_callback_t f, jtag_callback_data_t data0, jtag_callback_data_t data1, jtag_callback_data_t data2, jtag_callback_data_t data3)
void jtag_add_callback(jtag_callback1_t f, jtag_callback_data_t data0)
A simpler version of jtag_add_callback4().
@ TAP_DRPAUSE
Definition: jtag.h:43
intptr_t jtag_callback_data_t
Defines the type of data passed to the jtag_callback_t interface.
Definition: jtag.h:333
#define ERROR_FAIL
Definition: log.h:161
#define LOG_ERROR(expr ...)
Definition: log.h:123
#define LOG_DEBUG(expr ...)
Definition: log.h:109
#define ERROR_OK
Definition: log.h:155
struct reg_cache ** register_get_last_cache_p(struct reg_cache **first)
Definition: register.c:72
size_t size
Size of the control block search area.
Definition: rtt/rtt.c:30
Structure for items that are common between both ARM7 and ARM9 targets.
Definition: arm7_9_common.h:28
void(* enable_single_step)(struct target *target, uint32_t next_pc)
Definition: arm7_9_common.h:98
bool has_vector_catch
Specifies if the target has a reset vector catch.
Definition: arm7_9_common.h:53
struct arm arm
Definition: arm7_9_common.h:31
void(* read_xpsr)(struct target *target, uint32_t *xpsr, int spsr)
Function for reading CPSR or SPSR.
Definition: arm7_9_common.h:73
unsigned int common_magic
Definition: arm7_9_common.h:29
void(* store_hword_reg)(struct target *target, int num)
Definition: arm7_9_common.h:89
void(* write_xpsr_im8)(struct target *target, uint8_t xpsr_im, int rot, int spsr)
Function for writing an immediate value to CPSR or SPSR.
Definition: arm7_9_common.h:79
void(* write_core_regs)(struct target *target, uint32_t mask, uint32_t core_regs[16])
Definition: arm7_9_common.h:82
uint32_t arm_bkpt
ARM breakpoint instruction.
Definition: arm7_9_common.h:36
bool use_dbgrq
Specifies if DBGRQ should be used to halt the target.
Definition: arm7_9_common.h:48
int(* bulk_write_memory)(struct target *target, target_addr_t address, uint32_t count, const uint8_t *buffer)
Write target memory in multiples of 4 bytes, optimized for writing large quantities of data.
bool has_single_step
Definition: arm7_9_common.h:51
void(* branch_resume)(struct target *target)
Definition: arm7_9_common.h:95
int(* write_memory)(struct target *target, target_addr_t address, uint32_t size, uint32_t count, const uint8_t *buffer)
Variant specific memory write function that does not dispatch to bulk_write_memory.
struct arm_jtag jtag_info
JTAG information for target.
Definition: arm7_9_common.h:33
void(* read_core_regs_target_buffer)(struct target *target, uint32_t mask, void *buffer, int size)
Definition: arm7_9_common.h:71
void(* store_byte_reg)(struct target *target, int num)
Definition: arm7_9_common.h:90
struct reg_cache * eice_cache
Embedded ICE register cache.
Definition: arm7_9_common.h:34
int(* post_debug_entry)(struct target *target)
Callback function called after entering debug mode.
void(* load_word_regs)(struct target *target, uint32_t mask)
Definition: arm7_9_common.h:84
void(* load_byte_reg)(struct target *target, int num)
Definition: arm7_9_common.h:86
void(* read_core_regs)(struct target *target, uint32_t mask, uint32_t *core_regs[16])
Function for reading the core registers.
Definition: arm7_9_common.h:68
void(* load_hword_reg)(struct target *target, int num)
Definition: arm7_9_common.h:85
void(* disable_single_step)(struct target *target)
Definition: arm7_9_common.h:99
void(* write_pc)(struct target *target, uint32_t pc)
Function for writing to the program counter.
Definition: arm7_9_common.h:92
uint16_t thumb_bkpt
Thumb breakpoint instruction.
Definition: arm7_9_common.h:37
void(* store_word_regs)(struct target *target, uint32_t mask)
Definition: arm7_9_common.h:88
void(* pre_restore_context)(struct target *target)
Callback function called before restoring the processor context.
int dbgreq_adjust_pc
Amount of PC adjustment caused by a DBGREQ.
Definition: arm7_9_common.h:47
int(* examine_debug_reason)(struct target *target)
Function for determining why debug state was entered.
Definition: arm7_9_common.h:62
void(* branch_resume_thumb)(struct target *target)
Definition: arm7_9_common.h:96
void(* change_to_arm)(struct target *target, uint32_t *r0, uint32_t *pc)
Function for changing from Thumb to ARM mode.
Definition: arm7_9_common.h:65
void(* write_xpsr)(struct target *target, uint32_t xpsr, int spsr)
Function for writing to CPSR or SPSR.
Definition: arm7_9_common.h:76
const char * name
Definition: arm9tdmi.c:50
uint32_t value
Definition: arm9tdmi.c:51
uint32_t scann_size
Definition: arm_jtag.h:20
uint32_t intest_instr
Definition: arm_jtag.h:24
struct jtag_tap * tap
Definition: arm_jtag.h:18
Represents a generic ARM core, with standard application registers.
Definition: arm.h:167
enum arm_arch arch
ARM architecture version.
Definition: arm.h:194
struct reg * pc
Handle to the PC; valid in all core modes.
Definition: arm.h:173
struct reg_cache * core_cache
Definition: arm.h:170
const char * name
Definition: command.h:229
const struct command_registration * chain
If non-NULL, the commands in chain will be registered in the same context and scope of this registrat...
Definition: command.h:243
Definition: jtag.h:100
struct reg * reg_list
Definition: register.h:147
Definition: register.h:111
bool valid
Definition: register.h:126
uint8_t * value
Definition: register.h:122
This structure defines a single scan field in the scan.
Definition: jtag.h:86
int num_bits
The number of bits this field specifies.
Definition: jtag.h:88
uint8_t * in_value
A pointer to a 32-bit memory location for data scanned out.
Definition: jtag.h:92
const uint8_t * out_value
A pointer to value to be scanned into the device.
Definition: jtag.h:90
This holds methods shared between all instances of a given target type.
Definition: target_type.h:26
const char * name
Name of this type of target.
Definition: target_type.h:31
Definition: target.h:120
struct jtag_tap * tap
Definition: target.h:124
enum target_debug_reason debug_reason
Definition: target.h:159
enum target_endianness endianness
Definition: target.h:160
struct reg_cache * reg_cache
Definition: target.h:163
struct target * get_current_target(struct command_context *cmd_ctx)
Definition: target.c:536
@ DBG_REASON_WPTANDBKPT
Definition: target.h:76
@ DBG_REASON_DBGRQ
Definition: target.h:73
@ DBG_REASON_SINGLESTEP
Definition: target.h:77
@ DBG_REASON_WATCHPOINT
Definition: target.h:75
@ DBG_REASON_BREAKPOINT
Definition: target.h:74
#define ERROR_TARGET_INVALID
Definition: target.h:789
@ TARGET_BIG_ENDIAN
Definition: target.h:86
static bool target_was_examined(struct target *target)
Definition: target.h:438
#define NULL
Definition: usb.h:16