OpenOCD
arm Struct Reference

Represents a generic ARM core, with standard application registers. More...

Collaboration diagram for arm:

Data Fields

enum arm_arch arch
 ARM architecture version. More...
 
void * arch_info
 
int arm_vfp_version
 Floating point or VFP version, 0 if disabled. More...
 
unsigned int common_magic
 
struct reg_cachecore_cache
 
enum arm_mode core_mode
 Record the current core mode: SVC, USR, or some other mode. More...
 
enum arm_state core_state
 Record the current core state: ARM, Thumb, or otherwise. More...
 
enum arm_core_type core_type
 Indicates what registers are in the ARM state core register set. More...
 
struct regcpsr
 Handle to the CPSR/xPSR; valid in all core modes. More...
 
struct adiv5_dapdap
 For targets conforming to ARM Debug Interface v5, this handle references the Debug Access Port (DAP) used to make requests to the target. More...
 
struct arm_dpmdpm
 Handle for the debug module, if one is present. More...
 
struct etm_contextetm
 Handle for the Embedded Trace Module, if one is present. More...
 
int(* full_context )(struct target *target)
 Retrieve all core registers, for display. More...
 
const int * map
 Support for arm_reg_current() More...
 
int(* mcr )(struct target *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t crn, uint32_t crm, uint32_t value)
 Write coprocessor register. More...
 
int(* mrc )(struct target *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t crn, uint32_t crm, uint32_t *value)
 Read coprocessor register. More...
 
struct regpc
 Handle to the PC; valid in all core modes. More...
 
int(* read_core_reg )(struct target *target, struct reg *reg, int num, enum arm_mode mode)
 Retrieve a single core register. More...
 
int(* setup_semihosting )(struct target *target, int enable)
 
struct regspsr
 Handle to the SPSR; valid only in core modes with an SPSR. More...
 
struct targettarget
 Backpointer to the target. More...
 
int(* write_core_reg )(struct target *target, struct reg *reg, int num, enum arm_mode mode, uint8_t *value)
 

Detailed Description

Represents a generic ARM core, with standard application registers.

There are sixteen application registers (including PC, SP, LR) and a PSR. Cortex-M series cores do not support as many core states or shadowed registers as traditional ARM cores, and only support Thumb2 instructions.

Definition at line 167 of file arm.h.

Field Documentation

◆ arch

◆ arch_info

◆ arm_vfp_version

int arm::arm_vfp_version

Floating point or VFP version, 0 if disabled.

Definition at line 197 of file arm.h.

Referenced by arm_build_reg_cache(), arm_get_gdb_reg_list(), and cortex_a_target_create().

◆ common_magic

unsigned int arm::common_magic

◆ core_cache

struct reg_cache* arm::core_cache

Definition at line 170 of file arm.h.

Referenced by aarch64_assert_reset(), aarch64_restore_context(), adapter_debug_entry(), adapter_load_context(), adapter_resume(), adapter_step(), arm11_assert_reset(), arm11_debug_entry(), arm11_leave_debug_state(), arm11_read_memory_inner(), arm11_write_memory_inner(), arm7_9_assert_reset(), arm7_9_full_context(), arm7_9_restore_context(), arm7_9_resume(), arm7_9_soft_reset_halt(), arm7_9_step(), arm7tdmi_branch_resume_thumb(), arm920t_read_cp15_interpreted(), arm920t_write_cp15_interpreted(), arm9tdmi_branch_resume_thumb(), arm_build_reg_cache(), arm_dpm_full_context(), arm_dpm_read_current_registers(), arm_dpm_setup(), arm_dpm_write_dirty_registers(), arm_free_reg_cache(), arm_full_context(), arm_get_gdb_reg_list(), arm_reg_current(), arm_semihosting(), arm_set_cpsr(), armv4_5_get_reg(), armv4_5_get_reg_mode(), armv4_5_run_algorithm_inner(), armv4_5_set_reg(), armv4_5_set_reg_mode(), armv7m_arch_state(), armv7m_build_reg_cache(), armv7m_free_reg_cache(), armv7m_get_gdb_reg_list(), armv7m_read_core_reg(), armv7m_restore_context(), armv7m_start_algorithm(), armv7m_wait_algorithm(), armv7m_write_core_reg(), armv8_build_reg_cache(), armv8_dpm_full_context(), armv8_dpm_handle_exception(), armv8_dpm_read_core_reg(), armv8_dpm_read_current_registers(), armv8_dpm_setup(), armv8_dpm_write_core_reg(), armv8_dpm_write_dirty_registers(), armv8_get_core_reg32(), armv8_get_gdb_reg_list(), armv8_read_reg_simdfp_aarch32(), armv8_reg_current(), armv8_write_reg_simdfp_aarch32(), COMMAND_HANDLER(), cortex_a_assert_reset(), cortex_a_internal_restart(), cortex_a_internal_restore(), cortex_m_assert_reset(), cortex_m_debug_entry(), cortex_m_endreset_event(), cortex_m_examine(), cortex_m_fast_read_all_regs(), cortex_m_poll(), cortex_m_resume(), cortex_m_slow_read_all_regs(), cortex_m_soft_reset_halt(), cortex_m_step(), feroceon_branch_resume_thumb(), feroceon_bulk_write_memory(), hl_assert_reset(), post_result(), xscale_deassert_reset(), xscale_debug_entry(), xscale_full_context(), xscale_restore_banked(), xscale_resume(), and xscale_step_inner().

◆ core_mode

◆ core_state

◆ core_type

enum arm_core_type arm::core_type

Indicates what registers are in the ARM state core register set.

Definition at line 182 of file arm.h.

Referenced by arm11_examine(), arm11_target_create(), arm_build_reg_cache(), arm_get_gdb_reg_list(), arm_init_arch_info(), armv7m_init_arch_info(), COMMAND_HANDLER(), cortex_a_examine_first(), and xscale_init_arch_info().

◆ cpsr

◆ dap

struct adiv5_dap* arm::dap

For targets conforming to ARM Debug Interface v5, this handle references the Debug Access Port (DAP) used to make requests to the target.

Definition at line 239 of file arm.h.

Referenced by aarch64_examine_first(), aarch64_init_arch_info(), COMMAND_HANDLER(), cortex_a_examine_first(), cortex_a_init_arch_info(), cortex_m_endreset_event(), cortex_m_examine(), cortex_m_examine_exception_reason(), and cortex_m_init_arch_info().

◆ dpm

◆ etm

struct etm_context* arm::etm

Handle for the Embedded Trace Module, if one is present.

Definition at line 208 of file arm.h.

Referenced by arm11_examine(), arm7_9_examine(), COMMAND_HANDLER(), and etm_setup().

◆ full_context

int(* arm::full_context) (struct target *target)

Retrieve all core registers, for display.

Definition at line 213 of file arm.h.

Referenced by arm_dpm_setup(), arm_init_arch_info(), armv8_dpm_setup(), COMMAND_HANDLER(), and xscale_init_arch_info().

◆ map

const int* arm::map

Support for arm_reg_current()

Definition at line 182 of file arm.h.

Referenced by adapter_debug_entry(), arm_reg_current(), arm_set_cpsr(), and cortex_m_debug_entry().

◆ mcr

int(* arm::mcr) (struct target *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t crn, uint32_t crm, uint32_t value)

◆ mrc

int(* arm::mrc) (struct target *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t crn, uint32_t crm, uint32_t *value)

◆ pc

◆ read_core_reg

◆ setup_semihosting

int(* arm::setup_semihosting) (struct target *target, int enable)

◆ spsr

struct reg* arm::spsr

Handle to the SPSR; valid only in core modes with an SPSR.

Definition at line 179 of file arm.h.

Referenced by arm7_9_debug_entry(), arm7_9_write_core_reg(), arm_semihosting(), arm_set_cpsr(), cortex_a_debug_entry(), post_result(), and xscale_debug_entry().

◆ target

◆ write_core_reg

int(* arm::write_core_reg) (struct target *target, struct reg *reg, int num, enum arm_mode mode, uint8_t *value)

The documentation for this struct was generated from the following file: