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arm720t.c
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1 // SPDX-License-Identifier: GPL-2.0-or-later
2 
3 /***************************************************************************
4  * Copyright (C) 2005 by Dominic Rath *
5  * Dominic.Rath@gmx.de *
6  * *
7  * Copyright (C) 2009 by Øyvind Harboe *
8  * oyvind.harboe@zylin.com *
9  ***************************************************************************/
10 
11 #ifdef HAVE_CONFIG_H
12 #include "config.h"
13 #endif
14 
15 #include "arm720t.h"
16 #include <helper/time_support.h>
17 #include "target_type.h"
18 #include "register.h"
19 #include "arm_opcodes.h"
20 
21 
22 /*
23  * ARM720 is an ARM7TDMI-S with MMU and ETM7. For information, see
24  * ARM DDI 0229C especially Chapter 9 about debug support.
25  */
26 
27 #if 0
28 #define _DEBUG_INSTRUCTION_EXECUTION_
29 #endif
30 
31 static int arm720t_scan_cp15(struct target *target,
32  uint32_t out, uint32_t *in, int instruction, int clock_arg)
33 {
34  int retval;
35  struct arm720t_common *arm720t = target_to_arm720(target);
36  struct arm_jtag *jtag_info;
37  struct scan_field fields[2];
38  uint8_t out_buf[4];
39  uint8_t instruction_buf = instruction;
40 
41  jtag_info = &arm720t->arm7_9_common.jtag_info;
42 
43  buf_set_u32(out_buf, 0, 32, flip_u32(out, 32));
44 
45  retval = arm_jtag_scann(jtag_info, 0xf, TAP_DRPAUSE);
46  if (retval != ERROR_OK)
47  return retval;
48  retval = arm_jtag_set_instr(jtag_info->tap, jtag_info->intest_instr, NULL, TAP_DRPAUSE);
49  if (retval != ERROR_OK)
50  return retval;
51 
52  fields[0].num_bits = 1;
53  fields[0].out_value = &instruction_buf;
54  fields[0].in_value = NULL;
55 
56  fields[1].num_bits = 32;
57  fields[1].out_value = out_buf;
58  fields[1].in_value = NULL;
59 
60  if (in) {
61  fields[1].in_value = (uint8_t *)in;
62  jtag_add_dr_scan(jtag_info->tap, 2, fields, TAP_DRPAUSE);
64  } else
65  jtag_add_dr_scan(jtag_info->tap, 2, fields, TAP_DRPAUSE);
66 
67  if (clock_arg)
69 
70 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
71  retval = jtag_execute_queue();
72  if (retval != ERROR_OK)
73  return retval;
74 
75  if (in)
76  LOG_DEBUG("out: %8.8x, in: %8.8x, instruction: %i, clock: %i", out, *in, instruction, clock);
77  else
78  LOG_DEBUG("out: %8.8x, instruction: %i, clock: %i", out, instruction, clock_arg);
79 #else
80  LOG_DEBUG("out: %8.8" PRIx32 ", instruction: %i, clock: %i", out, instruction, clock_arg);
81 #endif
82 
83  return ERROR_OK;
84 }
85 
86 static int arm720t_read_cp15(struct target *target, uint32_t opcode, uint32_t *value)
87 {
88  /* fetch CP15 opcode */
89  arm720t_scan_cp15(target, opcode, NULL, 1, 1);
90  /* "DECODE" stage */
92  /* "EXECUTE" stage (1) */
94  arm720t_scan_cp15(target, 0x0, NULL, 0, 1);
95  /* "EXECUTE" stage (2) */
96  arm720t_scan_cp15(target, 0x0, NULL, 0, 1);
97  /* "EXECUTE" stage (3), CDATA is read */
98  arm720t_scan_cp15(target, ARMV4_5_NOP, value, 1, 1);
99 
100  return ERROR_OK;
101 }
102 
103 static int arm720t_write_cp15(struct target *target, uint32_t opcode, uint32_t value)
104 {
105  /* fetch CP15 opcode */
106  arm720t_scan_cp15(target, opcode, NULL, 1, 1);
107  /* "DECODE" stage */
109  /* "EXECUTE" stage (1) */
111  arm720t_scan_cp15(target, 0x0, NULL, 0, 1);
112  /* "EXECUTE" stage (2) */
113  arm720t_scan_cp15(target, value, NULL, 0, 1);
115 
116  return ERROR_OK;
117 }
118 
119 static int arm720t_get_ttb(struct target *target, uint32_t *result)
120 {
121  uint32_t ttb = 0x0;
122 
123  int retval;
124 
125  retval = arm720t_read_cp15(target, 0xee120f10, &ttb);
126  if (retval != ERROR_OK)
127  return retval;
128  retval = jtag_execute_queue();
129  if (retval != ERROR_OK)
130  return retval;
131 
132  ttb &= 0xffffc000;
133 
134  *result = ttb;
135 
136  return ERROR_OK;
137 }
138 
140  int mmu, int d_u_cache, int i_cache)
141 {
142  uint32_t cp15_control;
143  int retval;
144 
145  /* read cp15 control register */
146  retval = arm720t_read_cp15(target, 0xee110f10, &cp15_control);
147  if (retval != ERROR_OK)
148  return retval;
149  retval = jtag_execute_queue();
150  if (retval != ERROR_OK)
151  return retval;
152 
153  if (mmu)
154  cp15_control &= ~0x1U;
155 
156  if (d_u_cache || i_cache)
157  cp15_control &= ~0x4U;
158 
159  retval = arm720t_write_cp15(target, 0xee010f10, cp15_control);
160  return retval;
161 }
162 
164  int mmu, int d_u_cache, int i_cache)
165 {
166  uint32_t cp15_control;
167  int retval;
168 
169  /* read cp15 control register */
170  retval = arm720t_read_cp15(target, 0xee110f10, &cp15_control);
171  if (retval != ERROR_OK)
172  return retval;
173  retval = jtag_execute_queue();
174  if (retval != ERROR_OK)
175  return retval;
176 
177  if (mmu)
178  cp15_control |= 0x1U;
179 
180  if (d_u_cache || i_cache)
181  cp15_control |= 0x4U;
182 
183  retval = arm720t_write_cp15(target, 0xee010f10, cp15_control);
184  return retval;
185 }
186 
188 {
189  struct arm720t_common *arm720t = target_to_arm720(target);
190  int retval;
191 
192  /* examine cp15 control reg */
193  retval = arm720t_read_cp15(target, 0xee110f10, &arm720t->cp15_control_reg);
194  if (retval != ERROR_OK)
195  return retval;
196  retval = jtag_execute_queue();
197  if (retval != ERROR_OK)
198  return retval;
199  LOG_DEBUG("cp15_control_reg: %8.8" PRIx32 "", arm720t->cp15_control_reg);
200 
201  arm720t->armv4_5_mmu.mmu_enabled = (arm720t->cp15_control_reg & 0x1U) ? 1 : 0;
202  arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = (arm720t->cp15_control_reg & 0x4U) ? 1 : 0;
204 
205  /* save i/d fault status and address register */
206  retval = arm720t_read_cp15(target, 0xee150f10, &arm720t->fsr_reg);
207  if (retval != ERROR_OK)
208  return retval;
209  retval = arm720t_read_cp15(target, 0xee160f10, &arm720t->far_reg);
210  if (retval != ERROR_OK)
211  return retval;
212  retval = jtag_execute_queue();
213  return retval;
214 }
215 
217 {
218  struct arm720t_common *arm720t = target_to_arm720(target);
219 
220  /* restore i/d fault status and address register */
221  arm720t_write_cp15(target, 0xee050f10, arm720t->fsr_reg);
222  arm720t_write_cp15(target, 0xee060f10, arm720t->far_reg);
223 }
224 
225 static int arm720t_arch_state(struct target *target)
226 {
227  struct arm720t_common *arm720t = target_to_arm720(target);
228 
229  static const char *state[] = {
230  "disabled", "enabled"
231  };
232 
234  LOG_USER("MMU: %s, Cache: %s",
235  state[arm720t->armv4_5_mmu.mmu_enabled],
237 
238  return ERROR_OK;
239 }
240 
241 static int arm720_mmu(struct target *target, int *enabled)
242 {
243  if (target->state != TARGET_HALTED) {
244  LOG_ERROR("%s: target not halted", __func__);
245  return ERROR_TARGET_INVALID;
246  }
247 
249  return ERROR_OK;
250 }
251 
252 static int arm720_virt2phys(struct target *target,
253  target_addr_t virtual, target_addr_t *physical)
254 {
255  uint32_t cb;
256  struct arm720t_common *arm720t = target_to_arm720(target);
257 
258  uint32_t ret;
259  int retval = armv4_5_mmu_translate_va(target,
260  &arm720t->armv4_5_mmu, virtual, &cb, &ret);
261  if (retval != ERROR_OK)
262  return retval;
263  *physical = ret;
264  return ERROR_OK;
265 }
266 
267 static int arm720t_read_memory(struct target *target,
268  target_addr_t address, uint32_t size, uint32_t count, uint8_t *buffer)
269 {
270  int retval;
271  struct arm720t_common *arm720t = target_to_arm720(target);
272 
273  /* disable cache, but leave MMU enabled */
275  retval = arm720t_disable_mmu_caches(target, 0, 1, 0);
276  if (retval != ERROR_OK)
277  return retval;
278  }
279  retval = arm7_9_read_memory(target, address, size, count, buffer);
280 
282  retval = arm720t_enable_mmu_caches(target, 0, 1, 0);
283  if (retval != ERROR_OK)
284  return retval;
285  }
286 
287  return retval;
288 }
289 
291  target_addr_t address, uint32_t size, uint32_t count, uint8_t *buffer)
292 {
293  struct arm720t_common *arm720t = target_to_arm720(target);
294 
295  return armv4_5_mmu_read_physical(target, &arm720t->armv4_5_mmu, address, size, count, buffer);
296 }
297 
299  target_addr_t address, uint32_t size, uint32_t count, const uint8_t *buffer)
300 {
301  struct arm720t_common *arm720t = target_to_arm720(target);
302 
303  return armv4_5_mmu_write_physical(target, &arm720t->armv4_5_mmu, address, size, count, buffer);
304 }
305 
307 {
308  int retval = ERROR_OK;
309  struct arm720t_common *arm720t = target_to_arm720(target);
310  struct reg *dbg_stat = &arm720t->arm7_9_common
312  struct arm *arm = &arm720t->arm7_9_common.arm;
313 
314  retval = target_halt(target);
315  if (retval != ERROR_OK)
316  return retval;
317 
318  int64_t then = timeval_ms();
319  int timeout;
320  while (!(timeout = ((timeval_ms()-then) > 1000))) {
321  if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0) {
322  embeddedice_read_reg(dbg_stat);
323  retval = jtag_execute_queue();
324  if (retval != ERROR_OK)
325  return retval;
326  } else
327  break;
328  if (debug_level >= 3)
329  alive_sleep(100);
330  else
331  keep_alive();
332  }
333  if (timeout) {
334  LOG_ERROR("Failed to halt CPU after 1 sec");
335  return ERROR_TARGET_TIMEOUT;
336  }
337 
339 
340  /* SVC, ARM state, IRQ and FIQ disabled */
341  uint32_t cpsr;
342 
343  cpsr = buf_get_u32(arm->cpsr->value, 0, 32);
344  cpsr &= ~0xff;
345  cpsr |= 0xd3;
347  arm->cpsr->dirty = true;
348 
349  /* start fetching from 0x0 */
350  buf_set_u32(arm->pc->value, 0, 32, 0x0);
351  arm->pc->dirty = true;
352  arm->pc->valid = true;
353 
354  retval = arm720t_disable_mmu_caches(target, 1, 1, 1);
355  if (retval != ERROR_OK)
356  return retval;
357  arm720t->armv4_5_mmu.mmu_enabled = 0;
360 
362  if (retval != ERROR_OK)
363  return retval;
364 
365  return ERROR_OK;
366 }
367 
368 static int arm720t_init_target(struct command_context *cmd_ctx, struct target *target)
369 {
370  return arm7tdmi_init_target(cmd_ctx, target);
371 }
372 
373 static void arm720t_deinit_target(struct target *target)
374 {
376 }
377 
378 /* FIXME remove forward decls */
379 static int arm720t_mrc(struct target *target, int cpnum,
380  uint32_t op1, uint32_t op2,
381  uint32_t crn, uint32_t crm,
382  uint32_t *value);
383 static int arm720t_mcr(struct target *target, int cpnum,
384  uint32_t op1, uint32_t op2,
385  uint32_t crn, uint32_t crm,
386  uint32_t value);
387 
389  struct arm720t_common *arm720t, struct jtag_tap *tap)
390 {
391  struct arm7_9_common *arm7_9 = &arm720t->arm7_9_common;
392 
393  arm7_9->arm.mrc = arm720t_mrc;
394  arm7_9->arm.mcr = arm720t_mcr;
395 
396  arm7tdmi_init_arch_info(target, arm7_9, tap);
397 
399 
402 
403  arm720t->armv4_5_mmu.armv4_5_cache.ctype = -1;
409  arm720t->armv4_5_mmu.has_tiny_pages = 0;
410  arm720t->armv4_5_mmu.mmu_enabled = 0;
411 
412  return ERROR_OK;
413 }
414 
415 static int arm720t_target_create(struct target *target, Jim_Interp *interp)
416 {
417  struct arm720t_common *arm720t = calloc(1, sizeof(*arm720t));
418 
419  arm720t->arm7_9_common.arm.arch = ARM_ARCH_V4;
420  return arm720t_init_arch_info(target, arm720t, target->tap);
421 }
422 
423 static int arm720t_mrc(struct target *target, int cpnum,
424  uint32_t op1, uint32_t op2,
425  uint32_t crn, uint32_t crm,
426  uint32_t *value)
427 {
428  if (cpnum != 15) {
429  LOG_ERROR("Only cp15 is supported");
430  return ERROR_FAIL;
431  }
432 
433  /* read "to" r0 */
434  return arm720t_read_cp15(target,
435  ARMV4_5_MRC(cpnum, op1, 0, crn, crm, op2),
436  value);
437 
438 }
439 
440 static int arm720t_mcr(struct target *target, int cpnum,
441  uint32_t op1, uint32_t op2,
442  uint32_t crn, uint32_t crm,
443  uint32_t value)
444 {
445  if (cpnum != 15) {
446  LOG_ERROR("Only cp15 is supported");
447  return ERROR_FAIL;
448  }
449 
450  /* write "from" r0 */
451  return arm720t_write_cp15(target,
452  ARMV4_5_MCR(cpnum, op1, 0, crn, crm, op2),
453  value);
454 }
455 
456 static const struct command_registration arm720t_command_handlers[] = {
457  {
459  },
461 };
462 
464 struct target_type arm720t_target = {
465  .name = "arm720t",
466 
467  .poll = arm7_9_poll,
468  .arch_state = arm720t_arch_state,
469 
470  .halt = arm7_9_halt,
471  .resume = arm7_9_resume,
472  .step = arm7_9_step,
473 
474  .assert_reset = arm7_9_assert_reset,
475  .deassert_reset = arm7_9_deassert_reset,
476  .soft_reset_halt = arm720t_soft_reset_halt,
477 
478  .get_gdb_arch = arm_get_gdb_arch,
479  .get_gdb_reg_list = arm_get_gdb_reg_list,
480 
481  .read_memory = arm720t_read_memory,
482  .write_memory = arm7_9_write_memory_opt,
483  .read_phys_memory = arm720t_read_phys_memory,
484  .write_phys_memory = arm720t_write_phys_memory,
485  .mmu = arm720_mmu,
486  .virt2phys = arm720_virt2phys,
487 
488  .checksum_memory = arm_checksum_memory,
489  .blank_check_memory = arm_blank_check_memory,
490 
491  .run_algorithm = armv4_5_run_algorithm,
492 
493  .add_breakpoint = arm7_9_add_breakpoint,
494  .remove_breakpoint = arm7_9_remove_breakpoint,
495  .add_watchpoint = arm7_9_add_watchpoint,
496  .remove_watchpoint = arm7_9_remove_watchpoint,
497 
498  .commands = arm720t_command_handlers,
499  .target_create = arm720t_target_create,
500  .init_target = arm720t_init_target,
501  .deinit_target = arm720t_deinit_target,
502  .examine = arm7_9_examine,
503  .check_reset = arm7_9_check_reset,
504 };
static int arm720t_get_ttb(struct target *target, uint32_t *result)
Definition: arm720t.c:119
static int arm720t_init_target(struct command_context *cmd_ctx, struct target *target)
Definition: arm720t.c:368
static int arm720t_enable_mmu_caches(struct target *target, int mmu, int d_u_cache, int i_cache)
Definition: arm720t.c:163
static int arm720t_init_arch_info(struct target *target, struct arm720t_common *arm720t, struct jtag_tap *tap)
Definition: arm720t.c:388
static int arm720t_post_debug_entry(struct target *target)
Definition: arm720t.c:187
static int arm720t_target_create(struct target *target, Jim_Interp *interp)
Definition: arm720t.c:415
static int arm720t_write_phys_memory(struct target *target, target_addr_t address, uint32_t size, uint32_t count, const uint8_t *buffer)
Definition: arm720t.c:298
static int arm720_mmu(struct target *target, int *enabled)
Definition: arm720t.c:241
static int arm720t_write_cp15(struct target *target, uint32_t opcode, uint32_t value)
Definition: arm720t.c:103
static int arm720t_arch_state(struct target *target)
Definition: arm720t.c:225
static int arm720t_read_memory(struct target *target, target_addr_t address, uint32_t size, uint32_t count, uint8_t *buffer)
Definition: arm720t.c:267
static int arm720_virt2phys(struct target *target, target_addr_t virtual, target_addr_t *physical)
Definition: arm720t.c:252
static int arm720t_read_cp15(struct target *target, uint32_t opcode, uint32_t *value)
Definition: arm720t.c:86
static int arm720t_mcr(struct target *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t crn, uint32_t crm, uint32_t value)
Definition: arm720t.c:440
struct target_type arm720t_target
Holds methods for ARM720 targets.
Definition: arm720t.c:464
static int arm720t_mrc(struct target *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t crn, uint32_t crm, uint32_t *value)
Definition: arm720t.c:423
static void arm720t_pre_restore_context(struct target *target)
Definition: arm720t.c:216
static const struct command_registration arm720t_command_handlers[]
Definition: arm720t.c:456
static int arm720t_scan_cp15(struct target *target, uint32_t out, uint32_t *in, int instruction, int clock_arg)
Definition: arm720t.c:31
static int arm720t_soft_reset_halt(struct target *target)
Definition: arm720t.c:306
static void arm720t_deinit_target(struct target *target)
Definition: arm720t.c:373
static int arm720t_disable_mmu_caches(struct target *target, int mmu, int d_u_cache, int i_cache)
Definition: arm720t.c:139
static int arm720t_read_phys_memory(struct target *target, target_addr_t address, uint32_t size, uint32_t count, uint8_t *buffer)
Definition: arm720t.c:290
#define ARM720T_COMMON_MAGIC
Definition: arm720t.h:14
static struct arm720t_common * target_to_arm720(struct target *target)
Definition: arm720t.h:26
int arm7_9_write_memory_opt(struct target *target, target_addr_t address, uint32_t size, uint32_t count, const uint8_t *buffer)
int arm7_9_examine(struct target *target)
Perform per-target setup that requires JTAG access.
int arm7_9_read_memory(struct target *target, target_addr_t address, uint32_t size, uint32_t count, uint8_t *buffer)
int arm7_9_add_breakpoint(struct target *target, struct breakpoint *breakpoint)
Add a breakpoint to an ARM7/9 target.
const struct command_registration arm7_9_command_handlers[]
int arm7_9_assert_reset(struct target *target)
Asserts the reset (SRST) on an ARM7/9 target.
int arm7_9_poll(struct target *target)
Polls an ARM7/9 target for its current status.
int arm7_9_halt(struct target *target)
Halt an ARM7/9 target.
int arm7_9_remove_breakpoint(struct target *target, struct breakpoint *breakpoint)
Removes a breakpoint from an ARM7/9 target.
int arm7_9_remove_watchpoint(struct target *target, struct watchpoint *watchpoint)
Remove a watchpoint from an ARM7/9 target.
int arm7_9_deassert_reset(struct target *target)
Deassert the reset (SRST) signal on an ARM7/9 target.
int arm7_9_write_memory(struct target *target, target_addr_t address, uint32_t size, uint32_t count, const uint8_t *buffer)
int arm7_9_step(struct target *target, int current, target_addr_t address, int handle_breakpoints)
int arm7_9_add_watchpoint(struct target *target, struct watchpoint *watchpoint)
Add a watchpoint to an ARM7/9 target.
int arm7_9_check_reset(struct target *target)
int arm7_9_resume(struct target *target, int current, target_addr_t address, int handle_breakpoints, int debug_execution)
int arm7tdmi_init_arch_info(struct target *target, struct arm7_9_common *arm7_9, struct jtag_tap *tap)
Definition: arm7tdmi.c:621
void arm7tdmi_deinit_target(struct target *target)
Definition: arm7tdmi.c:616
int arm7tdmi_init_target(struct command_context *cmd_ctx, struct target *target)
Definition: arm7tdmi.c:609
int arm_blank_check_memory(struct target *target, struct target_memory_check_block *blocks, int num_blocks, uint8_t erased_value)
Runs ARM code in the target to check whether a memory block holds all ones.
Definition: armv4_5.c:1595
int arm_arch_state(struct target *target)
Definition: armv4_5.c:782
int arm_checksum_memory(struct target *target, target_addr_t address, uint32_t count, uint32_t *checksum)
Runs ARM code in the target to calculate a CRC32 checksum.
Definition: armv4_5.c:1522
@ ARM_ARCH_V4
Definition: arm.h:55
int arm_get_gdb_reg_list(struct target *target, struct reg **reg_list[], int *reg_list_size, enum target_register_class reg_class)
Definition: armv4_5.c:1194
int armv4_5_run_algorithm(struct target *target, int num_mem_params, struct mem_param *mem_params, int num_reg_params, struct reg_param *reg_params, target_addr_t entry_point, target_addr_t exit_point, int timeout_ms, void *arch_info)
Definition: armv4_5.c:1496
const char * arm_get_gdb_arch(struct target *target)
Definition: armv4_5.c:1189
void arm_set_cpsr(struct arm *arm, uint32_t cpsr)
Configures host-side ARM records to reflect the specified CPSR.
Definition: armv4_5.c:438
static int arm_jtag_scann(struct arm_jtag *jtag_info, uint32_t new_scan_chain, tap_state_t end_state)
Definition: arm_jtag.h:43
static int arm_jtag_set_instr(struct jtag_tap *tap, uint32_t new_instr, void *no_verify_capture, tap_state_t end_state)
Definition: arm_jtag.h:31
static void arm7flip32(jtag_callback_data_t arg)
Definition: arm_jtag.h:57
Macros used to generate various ARM or Thumb opcodes.
#define ARMV4_5_MRC(cp, op1, rd, crn, crm, op2)
Definition: arm_opcodes.h:186
#define ARMV4_5_MCR(cp, op1, rd, crn, crm, op2)
Definition: arm_opcodes.h:198
#define ARMV4_5_NOP
Definition: arm_opcodes.h:46
int armv4_5_mmu_read_physical(struct target *target, struct armv4_5_mmu_common *armv4_5_mmu, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
Definition: armv4_5_mmu.c:104
int armv4_5_mmu_write_physical(struct target *target, struct armv4_5_mmu_common *armv4_5_mmu, uint32_t address, uint32_t size, uint32_t count, const uint8_t *buffer)
Definition: armv4_5_mmu.c:132
int armv4_5_mmu_translate_va(struct target *target, struct armv4_5_mmu_common *armv4_5_mmu, uint32_t va, uint32_t *cb, uint32_t *val)
Definition: armv4_5_mmu.c:16
uint32_t flip_u32(uint32_t value, unsigned int num)
Definition: binarybuffer.c:166
static uint32_t buf_get_u32(const uint8_t *_buffer, unsigned first, unsigned num)
Retrieves num bits from _buffer, starting at the first bit, returning the bits in a 32-bit word.
Definition: binarybuffer.h:98
static void buf_set_u32(uint8_t *_buffer, unsigned first, unsigned num, uint32_t value)
Sets num bits in _buffer, starting at the first bit, using the bits in value.
Definition: binarybuffer.h:30
#define COMMAND_REGISTRATION_DONE
Use this as the last entry in an array of command_registration records.
Definition: command.h:247
int embeddedice_read_reg(struct reg *reg)
Queue a read for an EmbeddedICE register into the register cache, not checking the value read.
Definition: embeddedice.c:464
@ EICE_DBG_STAT
Definition: embeddedice.h:21
@ EICE_DBG_STATUS_DBGACK
Definition: embeddedice.h:53
int jtag_execute_queue(void)
For software FIFO implementations, the queued commands can be executed during this call or earlier.
Definition: jtag/core.c:1037
void jtag_add_runtest(int num_cycles, tap_state_t state)
Goes to TAP_IDLE (if we're not already there), cycle precisely num_cycles in the TAP_IDLE state,...
Definition: jtag/core.c:592
void jtag_add_dr_scan(struct jtag_tap *active, int in_num_fields, const struct scan_field *in_fields, tap_state_t state)
Generate a DR SCAN using the fields passed to the function.
Definition: jtag/core.c:451
void jtag_add_callback(jtag_callback1_t f, jtag_callback_data_t data0)
A simpler version of jtag_add_callback4().
@ TAP_DRPAUSE
Definition: jtag.h:43
intptr_t jtag_callback_data_t
Defines the type of data passed to the jtag_callback_t interface.
Definition: jtag.h:333
int debug_level
Definition: log.c:34
void alive_sleep(uint64_t ms)
Definition: log.c:460
void keep_alive(void)
Definition: log.c:419
#define LOG_USER(expr ...)
Definition: log.h:126
#define ERROR_FAIL
Definition: log.h:161
#define LOG_ERROR(expr ...)
Definition: log.h:123
#define LOG_DEBUG(expr ...)
Definition: log.h:109
#define ERROR_OK
Definition: log.h:155
size_t size
Size of the control block search area.
Definition: rtt/rtt.c:30
uint32_t far_reg
Definition: arm720t.h:23
uint32_t fsr_reg
Definition: arm720t.h:22
unsigned int common_magic
Definition: arm720t.h:17
uint32_t cp15_control_reg
Definition: arm720t.h:21
struct arm7_9_common arm7_9_common
Definition: arm720t.h:19
struct armv4_5_mmu_common armv4_5_mmu
Definition: arm720t.h:20
Structure for items that are common between both ARM7 and ARM9 targets.
Definition: arm7_9_common.h:28
struct arm arm
Definition: arm7_9_common.h:31
struct arm_jtag jtag_info
JTAG information for target.
Definition: arm7_9_common.h:33
struct reg_cache * eice_cache
Embedded ICE register cache.
Definition: arm7_9_common.h:34
int(* post_debug_entry)(struct target *target)
Callback function called after entering debug mode.
void(* pre_restore_context)(struct target *target)
Callback function called before restoring the processor context.
uint32_t intest_instr
Definition: arm_jtag.h:24
struct jtag_tap * tap
Definition: arm_jtag.h:18
Represents a generic ARM core, with standard application registers.
Definition: arm.h:167
enum arm_arch arch
ARM architecture version.
Definition: arm.h:194
int(* mrc)(struct target *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t crn, uint32_t crm, uint32_t *value)
Read coprocessor register.
Definition: arm.h:222
struct reg * cpsr
Handle to the CPSR/xPSR; valid in all core modes.
Definition: arm.h:176
struct reg * pc
Handle to the PC; valid in all core modes.
Definition: arm.h:173
int(* mcr)(struct target *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t crn, uint32_t crm, uint32_t value)
Write coprocessor register.
Definition: arm.h:228
int(* write_memory)(struct target *target, target_addr_t address, uint32_t size, uint32_t count, const uint8_t *buffer)
Definition: armv4_5_mmu.h:18
int(* read_memory)(struct target *target, target_addr_t address, uint32_t size, uint32_t count, uint8_t *buffer)
Definition: armv4_5_mmu.h:17
int(* get_ttb)(struct target *target, uint32_t *result)
Definition: armv4_5_mmu.h:16
int(* enable_mmu_caches)(struct target *target, int mmu, int d_u_cache, int i_cache)
Definition: armv4_5_mmu.h:21
int(* disable_mmu_caches)(struct target *target, int mmu, int d_u_cache, int i_cache)
Definition: armv4_5_mmu.h:20
struct armv4_5_cache_common armv4_5_cache
Definition: armv4_5_mmu.h:22
const struct command_registration * chain
If non-NULL, the commands in chain will be registered in the same context and scope of this registrat...
Definition: command.h:243
Definition: jtag.h:100
struct reg * reg_list
Definition: register.h:147
Definition: register.h:111
bool valid
Definition: register.h:126
uint8_t * value
Definition: register.h:122
bool dirty
Definition: register.h:124
This structure defines a single scan field in the scan.
Definition: jtag.h:86
int num_bits
The number of bits this field specifies.
Definition: jtag.h:88
uint8_t * in_value
A pointer to a 32-bit memory location for data scanned out.
Definition: jtag.h:92
const uint8_t * out_value
A pointer to value to be scanned into the device.
Definition: jtag.h:90
This holds methods shared between all instances of a given target type.
Definition: target_type.h:26
const char * name
Name of this type of target.
Definition: target_type.h:31
Definition: target.h:120
struct jtag_tap * tap
Definition: target.h:124
enum target_state state
Definition: target.h:162
Definition: psoc6.c:84
int target_call_event_callbacks(struct target *target, enum target_event event)
Definition: target.c:1833
int target_halt(struct target *target)
Definition: target.c:585
#define ERROR_TARGET_INVALID
Definition: target.h:789
@ TARGET_EVENT_HALTED
Definition: target.h:253
@ TARGET_HALTED
Definition: target.h:55
#define ERROR_TARGET_TIMEOUT
Definition: target.h:791
int64_t timeval_ms(void)
uint64_t target_addr_t
Definition: types.h:335
#define NULL
Definition: usb.h:16
uint8_t state[4]
Definition: vdebug.c:21
uint8_t count[4]
Definition: vdebug.c:22