OpenOCD
embeddedice.h
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1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 
3 /***************************************************************************
4  * Copyright (C) 2005, 2006 by Dominic Rath *
5  * Dominic.Rath@gmx.de *
6  * *
7  * Copyright (C) 2007,2008 Øyvind Harboe *
8  * oyvind.harboe@zylin.com *
9  * *
10  * Copyright (C) 2008 by Spencer Oliver *
11  * spen@spen-soft.co.uk *
12  ***************************************************************************/
13 
14 #ifndef OPENOCD_TARGET_EMBEDDEDICE_H
15 #define OPENOCD_TARGET_EMBEDDEDICE_H
16 
17 #include "arm7_9_common.h"
18 
19 enum {
36  EICE_VEC_CATCH = 16
37 };
38 
39 enum {
45 };
46 
47 enum {
54 };
55 
56 enum {
65  EICE_W_CTRL_NRW = 0x1
66 };
67 
68 enum {
71 };
72 
74  int addr;
76 };
77 
79  struct arm7_9_common *arm7_9);
81 
82 int embeddedice_setup(struct target *target);
83 
84 int embeddedice_read_reg(struct reg *reg);
86  uint8_t *check_value, uint8_t *check_mask);
87 
88 void embeddedice_write_reg(struct reg *reg, uint32_t value);
89 void embeddedice_store_reg(struct reg *reg);
90 
91 void embeddedice_set_reg(struct reg *reg, uint32_t value);
92 
93 int embeddedice_receive(struct arm_jtag *jtag_info, uint32_t *data, uint32_t size);
94 int embeddedice_send(struct arm_jtag *jtag_info, uint32_t *data, uint32_t size);
95 
96 int embeddedice_handshake(struct arm_jtag *jtag_info, int hsbit, uint32_t timeout);
97 
98 /* If many embeddedice_write_reg() follow each other, then the >1 invocations can be
99  * this faster version of embeddedice_write_reg
100  */
101 static inline void embeddedice_write_reg_inner(struct jtag_tap *tap, int reg_addr, uint32_t value)
102 {
103  uint8_t out_reg_addr = (1 << 5) | reg_addr;
104  uint8_t out_value[4];
105  buf_set_u32(out_value, 0, 32, value);
106 
107  struct scan_field fields[2] = {
108  { .num_bits = 32, .out_value = out_value },
109  { .num_bits = 6, .out_value = &out_reg_addr },
110  };
111 
112  jtag_add_dr_scan(tap, 2, fields, TAP_IDLE);
113 }
114 
115 void embeddedice_write_dcc(struct jtag_tap *tap, int reg_addr, const uint8_t *buffer,
116  int little, int count);
117 
118 #endif /* OPENOCD_TARGET_EMBEDDEDICE_H */
static void buf_set_u32(uint8_t *_buffer, unsigned first, unsigned num, uint32_t value)
Sets num bits in _buffer, starting at the first bit, using the bits in value.
Definition: binarybuffer.h:30
int embeddedice_handshake(struct arm_jtag *jtag_info, int hsbit, uint32_t timeout)
Poll DCC control register until read or write handshake completes.
Definition: embeddedice.c:577
void embeddedice_write_dcc(struct jtag_tap *tap, int reg_addr, const uint8_t *buffer, int little, int count)
This is an inner loop of the open loop DCC write of data to target.
Definition: embeddedice.c:640
@ EICE_COMM_CTRL_WBIT
Definition: embeddedice.h:69
@ EICE_COMM_CTRL_RBIT
Definition: embeddedice.h:70
@ EICE_W0_CONTROL_MASK
Definition: embeddedice.h:29
@ EICE_W1_CONTROL_VALUE
Definition: embeddedice.h:34
@ EICE_W1_DATA_VALUE
Definition: embeddedice.h:32
@ EICE_W0_CONTROL_VALUE
Definition: embeddedice.h:28
@ EICE_W0_DATA_MASK
Definition: embeddedice.h:27
@ EICE_W0_ADDR_MASK
Definition: embeddedice.h:25
@ EICE_DBG_CTRL
Definition: embeddedice.h:20
@ EICE_COMMS_DATA
Definition: embeddedice.h:23
@ EICE_W1_ADDR_VALUE
Definition: embeddedice.h:30
@ EICE_W1_ADDR_MASK
Definition: embeddedice.h:31
@ EICE_W0_ADDR_VALUE
Definition: embeddedice.h:24
@ EICE_COMMS_CTRL
Definition: embeddedice.h:22
@ EICE_W0_DATA_VALUE
Definition: embeddedice.h:26
@ EICE_W1_CONTROL_MASK
Definition: embeddedice.h:35
@ EICE_VEC_CATCH
Definition: embeddedice.h:36
@ EICE_W1_DATA_MASK
Definition: embeddedice.h:33
@ EICE_DBG_STAT
Definition: embeddedice.h:21
void embeddedice_set_reg(struct reg *reg, uint32_t value)
Queue a write for an EmbeddedICE register, updating the register cache.
Definition: embeddedice.c:473
@ EICE_W_CTRL_NOPC
Definition: embeddedice.h:62
@ EICE_W_CTRL_NTRANS
Definition: embeddedice.h:61
@ EICE_W_CTRL_MAS
Definition: embeddedice.h:63
@ EICE_W_CTRL_EXTERN
Definition: embeddedice.h:60
@ EICE_W_CTRL_CHAIN
Definition: embeddedice.h:59
@ EICE_W_CTRL_NRW
Definition: embeddedice.h:65
@ EICE_W_CTRL_ENABLE
Definition: embeddedice.h:57
@ EICE_W_CTRL_RANGE
Definition: embeddedice.h:58
@ EICE_W_CTRL_ITBIT
Definition: embeddedice.h:64
static void embeddedice_write_reg_inner(struct jtag_tap *tap, int reg_addr, uint32_t value)
Definition: embeddedice.h:101
int embeddedice_send(struct arm_jtag *jtag_info, uint32_t *data, uint32_t size)
Send a block of size 32-bit words to the DCC.
Definition: embeddedice.c:532
void embeddedice_free_reg_cache(struct reg_cache *reg_cache)
Free all memory allocated for EmbeddedICE register cache.
Definition: embeddedice.c:298
int embeddedice_setup(struct target *target)
Initialize EmbeddedICE module, if needed.
Definition: embeddedice.c:314
@ EICE_DBG_CONTROL_DBGRQ
Definition: embeddedice.h:43
@ EICE_DBG_CONTROL_DBGACK
Definition: embeddedice.h:44
@ EICE_DBG_CONTROL_ICEDIS
Definition: embeddedice.h:40
@ EICE_DBG_CONTROL_MONEN
Definition: embeddedice.h:41
@ EICE_DBG_CONTROL_INTDIS
Definition: embeddedice.h:42
struct reg_cache * embeddedice_build_reg_cache(struct target *target, struct arm7_9_common *arm7_9)
Probe EmbeddedICE module and set up local records of its registers.
Definition: embeddedice.c:162
void embeddedice_write_reg(struct reg *reg, uint32_t value)
Queue a write for an EmbeddedICE register, bypassing the register cache.
Definition: embeddedice.c:501
int embeddedice_receive(struct arm_jtag *jtag_info, uint32_t *data, uint32_t size)
Receive a block of size 32-bit words from the DCC.
Definition: embeddedice.c:412
@ EICE_DBG_STATUS_SYSCOMP
Definition: embeddedice.h:50
@ EICE_DBG_STATUS_IJBIT
Definition: embeddedice.h:48
@ EICE_DBG_STATUS_ITBIT
Definition: embeddedice.h:49
@ EICE_DBG_STATUS_IFEN
Definition: embeddedice.h:51
@ EICE_DBG_STATUS_DBGACK
Definition: embeddedice.h:53
@ EICE_DBG_STATUS_DBGRQ
Definition: embeddedice.h:52
void embeddedice_store_reg(struct reg *reg)
Queue a write for an EmbeddedICE register, using cached value.
Definition: embeddedice.c:519
int embeddedice_read_reg(struct reg *reg)
Queue a read for an EmbeddedICE register into the register cache, not checking the value read.
Definition: embeddedice.c:464
int embeddedice_read_reg_w_check(struct reg *reg, uint8_t *check_value, uint8_t *check_mask)
Queue a read for an EmbeddedICE register into the register cache, optionally checking the value read.
Definition: embeddedice.c:342
void jtag_add_dr_scan(struct jtag_tap *active, int in_num_fields, const struct scan_field *in_fields, tap_state_t state)
Generate a DR SCAN using the fields passed to the function.
Definition: jtag/core.c:451
@ TAP_IDLE
Definition: jtag.h:52
size_t size
Size of the control block search area.
Definition: rtt/rtt.c:30
Structure for items that are common between both ARM7 and ARM9 targets.
Definition: arm7_9_common.h:28
struct arm_jtag * jtag_info
Definition: embeddedice.h:75
Definition: jtag.h:100
Definition: register.h:111
This structure defines a single scan field in the scan.
Definition: jtag.h:86
int num_bits
The number of bits this field specifies.
Definition: jtag.h:88
const uint8_t * out_value
A pointer to value to be scanned into the device.
Definition: jtag.h:90
Definition: target.h:120
Definition: psoc6.c:84
uint8_t count[4]
Definition: vdebug.c:22