OpenOCD
armv4_5_mmu.h
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1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 
3 /***************************************************************************
4  * Copyright (C) 2005 by Dominic Rath *
5  * Dominic.Rath@gmx.de *
6  ***************************************************************************/
7 
8 #ifndef OPENOCD_TARGET_ARMV4_5_MMU_H
9 #define OPENOCD_TARGET_ARMV4_5_MMU_H
10 
11 #include "armv4_5_cache.h"
12 
13 struct target;
14 
16  int (*get_ttb)(struct target *target, uint32_t *result);
17  int (*read_memory)(struct target *target, target_addr_t address, uint32_t size, uint32_t count, uint8_t *buffer);
18  int (*write_memory)(struct target *target, target_addr_t address,
19  uint32_t size, uint32_t count, const uint8_t *buffer);
20  int (*disable_mmu_caches)(struct target *target, int mmu, int d_u_cache, int i_cache);
21  int (*enable_mmu_caches)(struct target *target, int mmu, int d_u_cache, int i_cache);
25 };
26 
28  struct armv4_5_mmu_common *armv4_5_mmu, uint32_t va,
29  uint32_t *cb, uint32_t *val);
30 
32  struct armv4_5_mmu_common *armv4_5_mmu,
33  uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
34 
36  struct armv4_5_mmu_common *armv4_5_mmu,
37  uint32_t address, uint32_t size, uint32_t count, const uint8_t *buffer);
38 
39 enum {
43  ARMV4_5_MMU_R_BIT = 0x200
44 };
45 
46 #endif /* OPENOCD_TARGET_ARMV4_5_MMU_H */
int armv4_5_mmu_read_physical(struct target *target, struct armv4_5_mmu_common *armv4_5_mmu, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
Definition: armv4_5_mmu.c:104
int armv4_5_mmu_write_physical(struct target *target, struct armv4_5_mmu_common *armv4_5_mmu, uint32_t address, uint32_t size, uint32_t count, const uint8_t *buffer)
Definition: armv4_5_mmu.c:132
@ ARMV4_5_ALIGNMENT_CHECK
Definition: armv4_5_mmu.h:41
@ ARMV4_5_MMU_ENABLED
Definition: armv4_5_mmu.h:40
@ ARMV4_5_MMU_S_BIT
Definition: armv4_5_mmu.h:42
@ ARMV4_5_MMU_R_BIT
Definition: armv4_5_mmu.h:43
int armv4_5_mmu_translate_va(struct target *target, struct armv4_5_mmu_common *armv4_5_mmu, uint32_t va, uint32_t *cb, uint32_t *val)
Definition: armv4_5_mmu.c:16
struct target * target
Definition: rtt/rtt.c:26
size_t size
Size of the control block search area.
Definition: rtt/rtt.c:30
int(* write_memory)(struct target *target, target_addr_t address, uint32_t size, uint32_t count, const uint8_t *buffer)
Definition: armv4_5_mmu.h:18
int(* read_memory)(struct target *target, target_addr_t address, uint32_t size, uint32_t count, uint8_t *buffer)
Definition: armv4_5_mmu.h:17
int(* get_ttb)(struct target *target, uint32_t *result)
Definition: armv4_5_mmu.h:16
int(* enable_mmu_caches)(struct target *target, int mmu, int d_u_cache, int i_cache)
Definition: armv4_5_mmu.h:21
int(* disable_mmu_caches)(struct target *target, int mmu, int d_u_cache, int i_cache)
Definition: armv4_5_mmu.h:20
struct armv4_5_cache_common armv4_5_cache
Definition: armv4_5_mmu.h:22
Definition: target.h:120
uint64_t target_addr_t
Definition: types.h:335
uint8_t count[4]
Definition: vdebug.c:22