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Holds the interface to Xtensa cores. More...
Go to the source code of this file.
Data Structures | |
struct | xtensa |
Represents a generic Xtensa core. More... | |
struct | xtensa_algorithm |
Xtensa algorithm data. More... | |
struct | xtensa_cache_config |
struct | xtensa_config |
struct | xtensa_debug_config |
struct | xtensa_high_prio_irq_config |
struct | xtensa_irq_config |
struct | xtensa_keyval_info |
struct | xtensa_local_mem_config |
struct | xtensa_local_mem_region_config |
struct | xtensa_mmu_config |
struct | xtensa_mpu_config |
struct | xtensa_sw_breakpoint |
struct | xtensa_tracing_config |
Macros | |
#define | XT_AREGS_NUM_MAX 64 |
#define | XT_IBREAKC_FB (0x80000000) |
#define | XT_IMPR_EXC_MSK (0x00000013) |
#define | XT_INS_BREAK(X, S, T) (XT_ISBE(X) ? XT_INS_BREAK_BE(S, T) : XT_INS_BREAK_LE(S, T)) |
#define | XT_INS_BREAK_BE(S, T) (0x000400 | (((S) & 0xF) << 12) | ((T) & 0xF)) |
#define | XT_INS_BREAK_LE(S, T) (0x004000 | (((S) & 0xF) << 8) | (((T) & 0xF) << 4)) |
#define | XT_INS_BREAKN(X, IMM4) (XT_ISBE(X) ? XT_INS_BREAKN_BE(IMM4) : XT_INS_BREAKN_LE(IMM4)) |
#define | XT_INS_BREAKN_BE(IMM4) (0x0FD2 | (((IMM4) & 0xF) << 12)) |
#define | XT_INS_BREAKN_LE(IMM4) (0xF02D | (((IMM4) & 0xF) << 8)) |
#define | XT_ISBE(X) ((X)->target->endianness == TARGET_BIG_ENDIAN) |
#define | XT_ISNS_SZ_MAX 3 |
#define | XT_LOCAL_MEM_REGIONS_NUM_MAX 8 |
#define | XT_MAX_TIE_REG_WIDTH (512) /* TIE register file max 4096 bits */ |
#define | XT_MEM_ACCESS_NONE 0x0 |
#define | XT_MEM_ACCESS_READ 0x1 |
#define | XT_MEM_ACCESS_WRITE 0x2 |
#define | XT_MESRCLR_IMPR_EXC_MSK (0x00000090) |
#define | XT_MS_DE_MSK BIT(5) |
#define | XT_MS_DISPST_DBG (0x10) |
#define | XT_MS_DISPST_MSK (0x1f) |
#define | XT_PS_CALLINC_MSK (0x3 << 16) |
#define | XT_PS_DIEXC_MSK BIT(2) |
#define | XT_PS_OWB_MSK (0xF << 8) |
#define | XT_PS_RING(_v_) ((uint32_t)((_v_) & 0x3) << 6) |
#define | XT_PS_RING_GET(_v_) (((_v_) >> 6) & 0x3) |
#define | XT_PS_RING_MSK (0x3 << 6) |
#define | XT_PS_WOE_MSK BIT(18) |
#define | XT_QUERYPKT_RESP_MAX (XT_MAX_TIE_REG_WIDTH * 2 + 1) |
#define | XT_USER_REGS_NUM_MAX 256 |
#define | XT_WB_C_MSK (0x7U << XT_WB_C_SHIFT) |
#define | XT_WB_C_SHIFT (4) |
#define | XT_WB_N_MSK (0x7U << XT_WB_N_SHIFT) |
#define | XT_WB_N_SHIFT (8) |
#define | XT_WB_P_MSK (0x7U << XT_WB_P_SHIFT) |
#define | XT_WB_P_SHIFT (0) |
#define | XT_WB_S_MSK (0x3U << XT_WB_S_SHIFT) |
#define | XT_WB_S_SHIFT (30) |
#define | XTENSA_COMMON_MAGIC 0x54E4E555U |
Typedefs | |
typedef uint32_t | xtensa_insn_t |
Enumerations | |
enum | xtensa_ar_scratch_set_e { XT_AR_SCRATCH_A3 = 0 , XT_AR_SCRATCH_AR3 , XT_AR_SCRATCH_A4 , XT_AR_SCRATCH_AR4 , XT_AR_SCRATCH_NUM } |
enum | xtensa_mode { XT_MODE_RING0 , XT_MODE_RING1 , XT_MODE_RING2 , XT_MODE_RING3 , XT_MODE_ANY } |
enum | xtensa_nx_reg_idx { XT_NX_REG_IDX_IBREAKC0 = 0 , XT_NX_REG_IDX_WB , XT_NX_REG_IDX_MS , XT_NX_REG_IDX_IEVEC , XT_NX_REG_IDX_IEEXTERN , XT_NX_REG_IDX_MESR , XT_NX_REG_IDX_MESRCLR , XT_NX_REG_IDX_NUM } |
enum | xtensa_qerr_e { XT_QERR_INTERNAL = 0 , XT_QERR_FAIL , XT_QERR_INVAL , XT_QERR_MEM , XT_QERR_NUM } |
enum | xtensa_stepping_isr_mode { XT_STEPPING_ISR_OFF , XT_STEPPING_ISR_ON } |
enum | xtensa_type { XT_UNDEF = 0 , XT_LX , XT_NX } |
Functions | |
COMMAND_HELPER (xtensa_cmd_mask_interrupts_do, struct xtensa *xtensa) | |
COMMAND_HELPER (xtensa_cmd_perfmon_dump_do, struct xtensa *xtensa) | |
COMMAND_HELPER (xtensa_cmd_perfmon_enable_do, struct xtensa *xtensa) | |
COMMAND_HELPER (xtensa_cmd_permissive_mode_do, struct xtensa *xtensa) | |
COMMAND_HELPER (xtensa_cmd_smpbreak_do, struct target *target) | |
COMMAND_HELPER (xtensa_cmd_tracedump_do, struct xtensa *xtensa, const char *fname) | |
COMMAND_HELPER (xtensa_cmd_tracestart_do, struct xtensa *xtensa) | |
COMMAND_HELPER (xtensa_cmd_tracestop_do, struct xtensa *xtensa) | |
COMMAND_HELPER (xtensa_cmd_xtdef_do, struct xtensa *xtensa) | |
COMMAND_HELPER (xtensa_cmd_xtmem_do, struct xtensa *xtensa) | |
COMMAND_HELPER (xtensa_cmd_xtmmu_do, struct xtensa *xtensa) | |
COMMAND_HELPER (xtensa_cmd_xtmpu_do, struct xtensa *xtensa) | |
COMMAND_HELPER (xtensa_cmd_xtopt_do, struct xtensa *xtensa) | |
COMMAND_HELPER (xtensa_cmd_xtreg_do, struct xtensa *xtensa) | |
COMMAND_HELPER (xtensa_cmd_xtregfmt_do, struct xtensa *xtensa) | |
static struct xtensa * | target_to_xtensa (struct target *target) |
static bool | xtensa_addr_in_mem (const struct xtensa_local_mem_config *mem, uint32_t addr) |
int | xtensa_assert_reset (struct target *target) |
int | xtensa_breakpoint_add (struct target *target, struct breakpoint *breakpoint) |
int | xtensa_breakpoint_remove (struct target *target, struct breakpoint *breakpoint) |
void | xtensa_cause_clear (struct target *target) |
uint32_t | xtensa_cause_get (struct target *target) |
void | xtensa_cause_reset (struct target *target) |
int | xtensa_checksum_memory (struct target *target, target_addr_t address, uint32_t count, uint32_t *checksum) |
int | xtensa_core_status_check (struct target *target) |
static int | xtensa_core_status_clear (struct target *target, uint32_t bits) |
static bool | xtensa_data_addr_valid (struct target *target, uint32_t addr) |
int | xtensa_deassert_reset (struct target *target) |
int | xtensa_do_resume (struct target *target) |
int | xtensa_do_step (struct target *target, int current, target_addr_t address, int handle_breakpoints) |
int | xtensa_examine (struct target *target) |
int | xtensa_fetch_all_regs (struct target *target) |
int | xtensa_gdb_query_custom (struct target *target, const char *packet, char **response_p) |
const char * | xtensa_get_gdb_arch (const struct target *target) |
int | xtensa_get_gdb_reg_list (struct target *target, struct reg **reg_list[], int *reg_list_size, enum target_register_class reg_class) |
int | xtensa_halt (struct target *target) |
int | xtensa_init_arch_info (struct target *target, struct xtensa *xtensa, const struct xtensa_debug_module_config *dm_cfg) |
int | xtensa_mmu_is_enabled (struct target *target, int *enabled) |
void | xtensa_on_poll (struct target *target) |
int | xtensa_poll (struct target *target) |
int | xtensa_prepare_resume (struct target *target, int current, target_addr_t address, int handle_breakpoints, int debug_execution) |
static int | xtensa_queue_dbg_reg_read (struct xtensa *xtensa, enum xtensa_dm_reg reg, uint8_t *data) |
static int | xtensa_queue_dbg_reg_write (struct xtensa *xtensa, enum xtensa_dm_reg reg, uint32_t data) |
int | xtensa_read_buffer (struct target *target, target_addr_t address, uint32_t count, uint8_t *buffer) |
int | xtensa_read_memory (struct target *target, target_addr_t address, uint32_t size, uint32_t count, uint8_t *buffer) |
xtensa_reg_val_t | xtensa_reg_get (struct target *target, enum xtensa_reg_id reg_id) |
void | xtensa_reg_set (struct target *target, enum xtensa_reg_id reg_id, xtensa_reg_val_t value) |
void | xtensa_reg_set_deep_relgen (struct target *target, enum xtensa_reg_id a_idx, xtensa_reg_val_t value) |
int | xtensa_resume (struct target *target, int current, target_addr_t address, int handle_breakpoints, int debug_execution) |
int | xtensa_run_algorithm (struct target *target, int num_mem_params, struct mem_param *mem_params, int num_reg_params, struct reg_param *reg_params, target_addr_t entry_point, target_addr_t exit_point, unsigned int timeout_ms, void *arch_info) |
void | xtensa_set_permissive_mode (struct target *target, bool state) |
int | xtensa_smpbreak_get (struct target *target, uint32_t *val) |
int | xtensa_smpbreak_read (struct xtensa *xtensa, uint32_t *val) |
int | xtensa_smpbreak_set (struct target *target, uint32_t set) |
int | xtensa_smpbreak_write (struct xtensa *xtensa, uint32_t set) |
int | xtensa_soft_reset_halt (struct target *target) |
int | xtensa_start_algorithm (struct target *target, int num_mem_params, struct mem_param *mem_params, int num_reg_params, struct reg_param *reg_params, target_addr_t entry_point, target_addr_t exit_point, void *arch_info) |
int | xtensa_step (struct target *target, int current, target_addr_t address, int handle_breakpoints) |
void | xtensa_target_deinit (struct target *target) |
int | xtensa_target_init (struct command_context *cmd_ctx, struct target *target) |
int | xtensa_wait_algorithm (struct target *target, int num_mem_params, struct mem_param *mem_params, int num_reg_params, struct reg_param *reg_params, target_addr_t exit_point, unsigned int timeout_ms, void *arch_info) |
Waits for an algorithm in the target. More... | |
int | xtensa_wakeup (struct target *target) |
int | xtensa_watchpoint_add (struct target *target, struct watchpoint *watchpoint) |
int | xtensa_watchpoint_remove (struct target *target, struct watchpoint *watchpoint) |
int | xtensa_write_buffer (struct target *target, target_addr_t address, uint32_t count, const uint8_t *buffer) |
int | xtensa_write_memory (struct target *target, target_addr_t address, uint32_t size, uint32_t count, const uint8_t *buffer) |
Variables | |
const struct command_registration | xtensa_command_handlers [] |
Holds the interface to Xtensa cores.
Definition in file xtensa.h.
#define XT_INS_BREAK | ( | X, | |
S, | |||
T | |||
) | (XT_ISBE(X) ? XT_INS_BREAK_BE(S, T) : XT_INS_BREAK_LE(S, T)) |
#define XT_INS_BREAK_BE | ( | S, | |
T | |||
) | (0x000400 | (((S) & 0xF) << 12) | ((T) & 0xF)) |
#define XT_INS_BREAK_LE | ( | S, | |
T | |||
) | (0x004000 | (((S) & 0xF) << 8) | (((T) & 0xF) << 4)) |
#define XT_INS_BREAKN | ( | X, | |
IMM4 | |||
) | (XT_ISBE(X) ? XT_INS_BREAKN_BE(IMM4) : XT_INS_BREAKN_LE(IMM4)) |
#define XT_INS_BREAKN_BE | ( | IMM4 | ) | (0x0FD2 | (((IMM4) & 0xF) << 12)) |
#define XT_INS_BREAKN_LE | ( | IMM4 | ) | (0xF02D | (((IMM4) & 0xF) << 8)) |
#define XT_ISBE | ( | X | ) | ((X)->target->endianness == TARGET_BIG_ENDIAN) |
#define XT_MAX_TIE_REG_WIDTH (512) /* TIE register file max 4096 bits */ |
#define XT_QUERYPKT_RESP_MAX (XT_MAX_TIE_REG_WIDTH * 2 + 1) |
#define XT_WB_C_MSK (0x7U << XT_WB_C_SHIFT) |
#define XT_WB_N_MSK (0x7U << XT_WB_N_SHIFT) |
#define XT_WB_P_MSK (0x7U << XT_WB_P_SHIFT) |
#define XT_WB_S_MSK (0x3U << XT_WB_S_SHIFT) |
typedef uint32_t xtensa_insn_t |
enum xtensa_mode |
enum xtensa_nx_reg_idx |
enum xtensa_qerr_e |
enum xtensa_type |
COMMAND_HELPER | ( | xtensa_cmd_mask_interrupts_do | , |
struct xtensa * | xtensa | ||
) |
Definition at line 4177 of file xtensa.c.
References CMD, CMD_ARGC, CMD_ARGV, command_print(), xtensa::core_config, xtensa_config::core_type, ERROR_FAIL, ERROR_OK, state, xtensa::stepping_isr_mode, XT_NX, XT_STEPPING_ISR_OFF, and XT_STEPPING_ISR_ON.
COMMAND_HELPER | ( | xtensa_cmd_perfmon_dump_do | , |
struct xtensa * | xtensa | ||
) |
Definition at line 4138 of file xtensa.c.
References CMD, CMD_ARGC, CMD_ARGV, command_print(), xtensa::dbg_mod, ERROR_COMMAND_ARGUMENT_INVALID, ERROR_COMMAND_SYNTAX_ERROR, ERROR_OK, NULL, xtensa_perfmon_result::overflow, xtensa_perfmon_result::value, xtensa_dm_perfmon_dump(), and XTENSA_MAX_PERF_COUNTERS.
COMMAND_HELPER | ( | xtensa_cmd_perfmon_enable_do | , |
struct xtensa * | xtensa | ||
) |
Definition at line 4078 of file xtensa.c.
References CMD, CMD_ARGC, CMD_ARGV, command_print(), config, xtensa::core_config, xtensa::dbg_mod, xtensa_config::debug, ERROR_COMMAND_ARGUMENT_INVALID, ERROR_COMMAND_SYNTAX_ERROR, xtensa_debug_config::irq_level, NULL, xtensa_dm_perfmon_enable(), XTENSA_MAX_PERF_COUNTERS, XTENSA_MAX_PERF_MASK, and XTENSA_MAX_PERF_SELECT.
COMMAND_HELPER | ( | xtensa_cmd_permissive_mode_do | , |
struct xtensa * | xtensa | ||
) |
Definition at line 4065 of file xtensa.c.
References CALL_COMMAND_HANDLER, and xtensa::permissive_mode.
COMMAND_HELPER | ( | xtensa_cmd_smpbreak_do | , |
struct target * | target | ||
) |
Definition at line 4219 of file xtensa.c.
References CMD, CMD_ARGC, CMD_ARGV, command_print(), ERROR_OK, OCDDCR_BREAKINEN, OCDDCR_BREAKOUTEN, OCDDCR_DEBUGMODEOUTEN, OCDDCR_RUNSTALLINEN, target_to_xtensa(), xtensa_smpbreak_read(), and xtensa_smpbreak_set().
COMMAND_HELPER | ( | xtensa_cmd_tracedump_do | , |
struct xtensa * | xtensa, | ||
const char * | fname | ||
) |
Definition at line 4390 of file xtensa.c.
References xtensa_trace_config::addr, CMD, command_print(), xtensa_trace_config::ctrl, xtensa::dbg_mod, ERROR_FAIL, ERROR_OK, xtensa_trace_config::memaddr_end, xtensa_trace_config::memaddr_start, TRAXADDR_TADDR_MASK, TRAXADDR_TWRAP_MASK, TRAXADDR_TWRAP_SHIFT, TRAXADDR_TWSAT, TRAXCTRL_TREN, TRAXSTAT_TRACT, xtensa_dm_trace_config_read(), xtensa_dm_trace_data_read(), and xtensa_dm_trace_status_read().
COMMAND_HELPER | ( | xtensa_cmd_tracestart_do | , |
struct xtensa * | xtensa | ||
) |
Definition at line 4305 of file xtensa.c.
References xtensa_trace_start_config::after, xtensa_trace_start_config::after_is_words, CMD, CMD_ARGC, CMD_ARGV, command_print(), xtensa::dbg_mod, ERROR_FAIL, ERROR_OK, LOG_WARNING, NULL, xtensa_trace_start_config::stopmask, xtensa_trace_start_config::stoppc, xtensa::trace_active, TRAXSTAT_TRACT, xtensa_dm_trace_start(), xtensa_dm_trace_status_read(), xtensa_dm_trace_stop(), and XTENSA_STOPMASK_DISABLED.
COMMAND_HELPER | ( | xtensa_cmd_tracestop_do | , |
struct xtensa * | xtensa | ||
) |
Definition at line 4362 of file xtensa.c.
References CMD, command_print(), xtensa::dbg_mod, ERROR_FAIL, ERROR_OK, xtensa::trace_active, TRAXSTAT_TRACT, xtensa_dm_trace_status_read(), and xtensa_dm_trace_stop().
COMMAND_HELPER | ( | xtensa_cmd_xtdef_do | , |
struct xtensa * | xtensa | ||
) |
Definition at line 3599 of file xtensa.c.
References CMD, CMD_ARGC, CMD_ARGV, command_print(), xtensa::core_config, xtensa_config::core_type, ERROR_COMMAND_ARGUMENT_INVALID, ERROR_COMMAND_SYNTAX_ERROR, ERROR_OK, XT_LX, and XT_NX.
COMMAND_HELPER | ( | xtensa_cmd_xtmem_do | , |
struct xtensa * | xtensa | ||
) |
Definition at line 3731 of file xtensa.c.
References xtensa_local_mem_region_config::access, xtensa_local_mem_region_config::base, CMD, CMD_ARGC, CMD_ARGV, command_print(), xtensa::core_config, xtensa_local_mem_config::count, xtensa_config::dcache, xtensa_config::dram, xtensa_config::drom, ERROR_COMMAND_ARGUMENT_INVALID, ERROR_COMMAND_SYNTAX_ERROR, ERROR_OK, xtensa_config::icache, xtensa_config::iram, xtensa_config::irom, xtensa_cache_config::line_size, NULL, xtensa_local_mem_config::regions, xtensa_cache_config::size, xtensa_local_mem_region_config::size, xtensa_config::sram, xtensa_config::srom, xtensa_cache_config::way_count, xtensa_cache_config::writeback, XT_MEM_ACCESS_READ, and XT_MEM_ACCESS_WRITE.
COMMAND_HELPER | ( | xtensa_cmd_xtmmu_do | , |
struct xtensa * | xtensa | ||
) |
Definition at line 3841 of file xtensa.c.
References CMD, CMD_ARGC, CMD_ARGV, command_print(), xtensa::core_config, xtensa_mmu_config::dtlb_entries_count, xtensa_mmu_config::enabled, ERROR_COMMAND_ARGUMENT_INVALID, ERROR_COMMAND_SYNTAX_ERROR, ERROR_OK, xtensa_mmu_config::itlb_entries_count, xtensa_config::mmu, and NULL.
COMMAND_HELPER | ( | xtensa_cmd_xtmpu_do | , |
struct xtensa * | xtensa | ||
) |
Definition at line 3802 of file xtensa.c.
References CMD, CMD_ARGC, CMD_ARGV, command_print(), xtensa::core_config, xtensa_mpu_config::enabled, ERROR_COMMAND_ARGUMENT_INVALID, ERROR_COMMAND_SYNTAX_ERROR, ERROR_OK, xtensa_mpu_config::execonly, xtensa_mpu_config::lockable, xtensa_mpu_config::minsegsize, xtensa_config::mpu, xtensa_mpu_config::nfgseg, and NULL.
COMMAND_HELPER | ( | xtensa_cmd_xtopt_do | , |
struct xtensa * | xtensa | ||
) |
Definition at line 3632 of file xtensa.c.
References xtensa_config::aregs_num, CMD, CMD_ARGC, CMD_ARGV, command_print(), xtensa_config::coproc, xtensa::core_config, xtensa_config::core_type, xtensa_debug_config::dbreaks_num, xtensa_config::debug, xtensa_irq_config::enabled, xtensa_high_prio_irq_config::enabled, xtensa_debug_config::enabled, xtensa_tracing_config::enabled, ERROR_COMMAND_ARGUMENT_INVALID, ERROR_COMMAND_SYNTAX_ERROR, ERROR_OK, xtensa_config::exceptions, xtensa_high_prio_irq_config::excm_level, xtensa_config::high_irq, xtensa_debug_config::ibreaks_num, xtensa_config::irq, xtensa_debug_config::irq_level, xtensa_irq_config::irq_num, xtensa_high_prio_irq_config::level_num, LOG_WARNING, xtensa_tracing_config::mem_sz, NULL, xtensa_debug_config::perfcount_num, xtensa_tracing_config::reversed_mem_access, xtensa_config::trace, xtensa_config::windowed, XT_LX, and xtensa_cmd_xtopt_legal_val().
COMMAND_HELPER | ( | xtensa_cmd_xtreg_do | , |
struct xtensa * | xtensa | ||
) |
Definition at line 3870 of file xtensa.c.
References CMD, CMD_ARGC, CMD_ARGV, command_print(), xtensa::contiguous_regs_desc, xtensa_config::coproc, xtensa::core_config, xtensa::core_regs_num, xtensa_config::core_type, xtensa_reg_desc::dbreg_num, xtensa_config::debug, xtensa::eps_dbglevel_idx, ERROR_COMMAND_ARGUMENT_INVALID, ERROR_COMMAND_SYNTAX_ERROR, ERROR_FAIL, ERROR_OK, xtensa_reg_desc::exist, xtensa_reg_desc::flags, xtensa::genpkt_regs_num, xtensa_debug_config::irq_level, LOG_DEBUG, LOG_ERROR, name, xtensa_reg_desc::name, NULL, xtensa::num_optregs, xtensa::nx_reg_idx, xtensa::optregs, xtensa_reg_desc::reg_num, xtensa::regmap_contiguous, xtensa::total_regs_num, xtensa_reg_desc::type, XT_EPS_REG_NUM_BASE, XT_LX, XT_NUM_REGS, XT_NX, XT_NX_REG_IDX_IBREAKC0, XT_NX_REG_IDX_IEEXTERN, XT_NX_REG_IDX_IEVEC, XT_NX_REG_IDX_MESR, XT_NX_REG_IDX_MESRCLR, XT_NX_REG_IDX_MS, XT_NX_REG_IDX_NUM, XT_NX_REG_IDX_WB, XT_REG_FR, XT_REG_FR_MASK, XT_REG_FR_VAL, XT_REG_GENERAL, XT_REG_GENERAL_MASK, XT_REG_GENERAL_VAL, XT_REG_IDX_ARFIRST, XT_REG_INDEX_MASK, XT_REG_OTHER, XT_REG_RELGEN, XT_REG_RELGEN_MASK, XT_REG_RELGEN_VAL, XT_REG_SPECIAL, XT_REG_SPECIAL_MASK, XT_REG_SPECIAL_VAL, XT_REG_TIE, XT_REG_TIE_MASK, XT_REG_USER, XT_REG_USER_MASK, XT_REG_USER_VAL, XT_REGF_NOREAD, xtensa_extra_debug_log, and xtensa_regs.
COMMAND_HELPER | ( | xtensa_cmd_xtregfmt_do | , |
struct xtensa * | xtensa | ||
) |
Definition at line 4035 of file xtensa.c.
References CMD, CMD_ARGC, CMD_ARGV, command_print(), ERROR_COMMAND_ARGUMENT_INVALID, ERROR_COMMAND_SYNTAX_ERROR, ERROR_OK, xtensa::genpkt_regs_num, NULL, xtensa::regmap_contiguous, and xtensa::total_regs_num.
Definition at line 290 of file xtensa.h.
References target::arch_info, xtensa::common_magic, and XTENSA_COMMON_MAGIC.
Referenced by COMMAND_HANDLER(), COMMAND_HELPER(), esp32_soc_reset(), esp32s2_deassert_reset(), esp32s2_soc_reset(), esp32s3_soc_reset(), esp_xtensa_apptrace_block_max_size_get(), esp_xtensa_apptrace_buffs_write(), esp_xtensa_apptrace_ctrl_reg_read(), esp_xtensa_apptrace_ctrl_reg_write(), esp_xtensa_apptrace_data_read(), esp_xtensa_apptrace_queue_normal_write(), esp_xtensa_apptrace_queue_reverse_write(), esp_xtensa_apptrace_status_reg_read(), esp_xtensa_apptrace_status_reg_write(), esp_xtensa_poll(), esp_xtensa_profiling(), esp_xtensa_stub_tramp_get(), esp_xtensa_swdbg_activate(), xtensa_assert_reset(), xtensa_breakpoint_add(), xtensa_breakpoint_remove(), xtensa_build_reg_cache(), xtensa_cause_clear(), xtensa_cause_get(), xtensa_cause_reset(), xtensa_chip_examine(), xtensa_chip_target_deinit(), xtensa_core_status_check(), xtensa_core_status_clear(), xtensa_data_addr_valid(), xtensa_deassert_reset(), xtensa_do_resume(), xtensa_do_step(), xtensa_examine(), xtensa_fetch_all_regs(), xtensa_fileio_detect_proc(), xtensa_free_reg_cache(), xtensa_gdb_fileio_end(), xtensa_gdb_query_custom(), xtensa_gdbqc_parse_exec_tie_ops(), xtensa_gdbqc_qxtreg(), xtensa_get_gdb_fileio_info(), xtensa_get_gdb_reg_list(), xtensa_halt(), xtensa_imprecise_exception_clear(), xtensa_imprecise_exception_occurred(), xtensa_is_stopped(), xtensa_mmu_is_enabled(), xtensa_pc_in_winexc(), xtensa_poll(), xtensa_prepare_resume(), xtensa_read_memory(), xtensa_reg_get(), xtensa_reg_set(), xtensa_reg_set_deep_relgen(), xtensa_region_ar_exec(), xtensa_set_permissive_mode(), xtensa_smpbreak_get(), xtensa_smpbreak_set(), xtensa_start_algorithm(), xtensa_sw_breakpoint_add(), xtensa_target_deinit(), xtensa_target_init(), xtensa_update_instruction(), xtensa_wait_algorithm(), xtensa_wakeup(), xtensa_watchpoint_add(), xtensa_watchpoint_remove(), xtensa_window_state_restore(), xtensa_window_state_save(), xtensa_write_dirty_registers(), and xtensa_write_memory().
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Definition at line 304 of file xtensa.h.
References addr, xtensa_local_mem_region_config::base, xtensa_local_mem_config::count, xtensa_local_mem_config::regions, and xtensa_local_mem_region_config::size.
Referenced by xtensa_data_addr_valid().
int xtensa_assert_reset | ( | struct target * | target | ) |
Definition at line 1161 of file xtensa.c.
References xtensa::core_cache, xtensa::dbg_mod, ERROR_OK, LOG_TARGET_DEBUG, PWRCTL_CORERESET, PWRCTL_COREWAKEUP, PWRCTL_DEBUGWAKEUP, PWRCTL_JTAGDEBUGUSE, PWRCTL_MEMWAKEUP, register_cache_invalidate(), xtensa::reset_asserted, target::state, TARGET_RESET, target_to_xtensa(), XDMREG_PWRCTL, xtensa_dm_queue_execute(), xtensa_dm_queue_tdi_idle(), and xtensa_queue_pwr_reg_write().
Referenced by esp32_soc_reset(), esp32s2_soc_reset(), esp32s3_soc_reset(), esp_xtensa_smp_soft_reset_halt(), and xtensa_soft_reset_halt().
int xtensa_breakpoint_add | ( | struct target * | target, |
struct breakpoint * | breakpoint | ||
) |
Definition at line 2554 of file xtensa.c.
References breakpoint::address, BKPT_SOFT, xtensa::core_config, xtensa_config::debug, ERROR_OK, ERROR_TARGET_RESOURCE_NOT_AVAILABLE, xtensa::hw_brps, xtensa_debug_config::ibreaks_num, LOG_TARGET_DEBUG, LOG_TARGET_ERROR, LOG_TARGET_WARNING, xtensa_sw_breakpoint::oocd_bp, xtensa::sw_brps, TARGET_ADDR_FMT, target_to_xtensa(), breakpoint::type, XT_SW_BREAKPOINTS_MAX_NUM, and xtensa_sw_breakpoint_add().
Referenced by esp_xtensa_breakpoint_add().
int xtensa_breakpoint_remove | ( | struct target * | target, |
struct breakpoint * | breakpoint | ||
) |
Definition at line 2598 of file xtensa.c.
References breakpoint::address, BKPT_SOFT, xtensa::core_config, xtensa_config::core_type, xtensa_config::debug, ERROR_OK, ERROR_TARGET_RESOURCE_NOT_AVAILABLE, xtensa::hw_brps, xtensa_debug_config::ibreaks_num, LOG_TARGET_DEBUG, LOG_TARGET_ERROR, LOG_TARGET_WARNING, NULL, xtensa::nx_reg_idx, xtensa_sw_breakpoint::oocd_bp, xtensa::sw_brps, TARGET_ADDR_FMT, target_to_xtensa(), breakpoint::type, XT_NX, XT_NX_REG_IDX_IBREAKC0, XT_SW_BREAKPOINTS_MAX_NUM, xtensa_reg_set(), and xtensa_sw_breakpoint_remove().
Referenced by esp_xtensa_breakpoint_remove().
void xtensa_cause_clear | ( | struct target * | target | ) |
Definition at line 1142 of file xtensa.c.
References xtensa::core_cache, xtensa::core_config, xtensa_config::core_type, DEBUGCAUSE_VALID, reg::dirty, xtensa::nx_stop_cause, reg_cache::reg_list, target_to_xtensa(), XT_LX, XT_REG_IDX_DEBUGCAUSE, and xtensa_reg_set().
Referenced by xtensa_do_step().
uint32_t xtensa_cause_get | ( | struct target * | target | ) |
Definition at line 1095 of file xtensa.c.
References xtensa::core_config, xtensa_config::core_type, xtensa::dbg_mod, DEBUGCAUSE_BI, DEBUGCAUSE_BN, DEBUGCAUSE_DB, DEBUGCAUSE_DI, DEBUGCAUSE_IB, DEBUGCAUSE_IC, DEBUGCAUSE_VALID, ERROR_OK, LOG_TARGET_ERROR, xtensa::nx_stop_cause, OCDDSR_STOPCAUSE, OCDDSR_STOPCAUSE_B, OCDDSR_STOPCAUSE_B1, OCDDSR_STOPCAUSE_BN, OCDDSR_STOPCAUSE_DB0, OCDDSR_STOPCAUSE_DB1, OCDDSR_STOPCAUSE_DI, OCDDSR_STOPCAUSE_IB, OCDDSR_STOPCAUSE_SHIFT, OCDDSR_STOPCAUSE_SS, target_to_xtensa(), XT_LX, XT_REG_IDX_DEBUGCAUSE, xtensa_dm_core_status_get(), xtensa_dm_core_status_read(), and xtensa_reg_get().
Referenced by xtensa_do_step(), xtensa_fileio_detect_proc(), xtensa_poll(), and xtensa_prepare_resume().
void xtensa_cause_reset | ( | struct target * | target | ) |
Definition at line 1154 of file xtensa.c.
References xtensa::nx_stop_cause, and target_to_xtensa().
Referenced by xtensa_do_resume().
int xtensa_checksum_memory | ( | struct target * | target, |
target_addr_t | address, | ||
uint32_t | count, | ||
uint32_t * | checksum | ||
) |
Definition at line 2298 of file xtensa.c.
References ERROR_FAIL, and LOG_WARNING.
int xtensa_core_status_check | ( | struct target * | target | ) |
Definition at line 1017 of file xtensa.c.
References xtensa::core_config, xtensa_config::core_type, xtensa::dbg_mod, ERROR_FAIL, ERROR_OK, LOG_TARGET_DEBUG, LOG_TARGET_ERROR, OCDDSR_EXECBUSY, OCDDSR_EXECEXCEPTION, OCDDSR_EXECOVERRUN, xtensa::suppress_dsr_errors, target_name(), target_to_xtensa(), XT_NX, xtensa_dm_core_status_clear(), xtensa_dm_core_status_get(), xtensa_dm_core_status_read(), xtensa_imprecise_exception_clear(), and xtensa_imprecise_exception_occurred().
Referenced by COMMAND_HELPER(), xtensa_do_resume(), xtensa_fetch_all_regs(), xtensa_gdbqc_qxtreg(), xtensa_poll(), xtensa_read_memory(), xtensa_region_ar_exec(), xtensa_update_instruction(), xtensa_window_state_save(), xtensa_write_dirty_registers(), and xtensa_write_memory().
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Definition at line 351 of file xtensa.h.
References bits, xtensa::dbg_mod, target_to_xtensa(), and xtensa_dm_core_status_clear().
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Definition at line 314 of file xtensa.h.
References addr, xtensa::core_config, xtensa_config::dram, xtensa_config::drom, xtensa_config::sram, target_to_xtensa(), and xtensa_addr_in_mem().
Referenced by esp_xtensa_dbgstubs_addr_check().
int xtensa_deassert_reset | ( | struct target * | target | ) |
Definition at line 1182 of file xtensa.c.
References xtensa::dbg_mod, ERROR_OK, LOG_TARGET_DEBUG, OCDDCR_DEBUGINTERRUPT, OCDDCR_ENABLEOCD, PWRCTL_COREWAKEUP, PWRCTL_DEBUGWAKEUP, PWRCTL_JTAGDEBUGUSE, PWRCTL_MEMWAKEUP, xtensa::reset_asserted, target::reset_halt, target::state, TARGET_RUNNING, target_to_xtensa(), XDMREG_DCRSET, XDMREG_PWRCTL, xtensa_dm_queue_execute(), xtensa_dm_queue_tdi_idle(), xtensa_queue_dbg_reg_write(), and xtensa_queue_pwr_reg_write().
Referenced by esp32_soc_reset(), esp32s2_deassert_reset(), esp32s2_soc_reset(), esp32s3_soc_reset(), and esp_xtensa_smp_deassert_reset().
int xtensa_do_resume | ( | struct target * | target | ) |
Definition at line 1656 of file xtensa.c.
References xtensa::dbg_mod, ERROR_OK, LOG_TARGET_DEBUG, LOG_TARGET_ERROR, target_to_xtensa(), XT_INS_RFDO, xtensa_cause_reset(), xtensa_core_status_check(), xtensa_dm_queue_execute(), and xtensa_queue_exec_ins().
Referenced by esp_xtensa_smp_resume(), xtensa_do_step(), and xtensa_resume().
int xtensa_do_step | ( | struct target * | target, |
int | current, | ||
target_addr_t | address, | ||
int | handle_breakpoints | ||
) |
Definition at line 1722 of file xtensa.c.
References xtensa::core_cache, xtensa::core_config, xtensa_config::core_type, xtensa::dbg_mod, DBG_REASON_NOTHALTED, DBG_REASON_SINGLESTEP, xtensa_debug_config::dbreaks_num, xtensa_config::debug, target::debug_reason, DEBUGCAUSE_BI, DEBUGCAUSE_BN, DEBUGCAUSE_DB, xtensa_high_prio_irq_config::enabled, xtensa::eps_dbglevel_idx, ERROR_FAIL, ERROR_OK, ERROR_TARGET_NOT_HALTED, xtensa_config::high_irq, xtensa_debug_config::irq_level, LOG_DEBUG, LOG_TARGET_DEBUG, LOG_TARGET_ERROR, LOG_TARGET_WARNING, MIN, reg::name, OCDDCR_STEPREQUEST, reg_cache::reg_list, start, target::state, xtensa::stepping_isr_mode, TARGET_ADDR_FMT, TARGET_HALTED, TARGET_RUNNING, target_to_xtensa(), timeval_ms(), xtensa_config::windowed, XDMREG_DCRSET, XT_LX, XT_REG_IDX_DBREAKC0, XT_REG_IDX_EXCCAUSE, XT_REG_IDX_ICOUNT, XT_REG_IDX_ICOUNTLEVEL, XT_REG_IDX_PC, XT_REG_IDX_PS, XT_STEPPING_ISR_OFF, XT_WATCHPOINTS_NUM_MAX, xtensa_cause_clear(), xtensa_cause_get(), xtensa_dm_core_status_get(), xtensa_dm_core_status_read(), xtensa_do_resume(), xtensa_fetch_all_regs(), xtensa_is_stopped(), xtensa_pc_in_winexc(), xtensa_prepare_resume(), xtensa_queue_dbg_reg_write(), xtensa_reg_get(), xtensa_reg_set(), and xtensa_write_dirty_registers().
Referenced by xtensa_prepare_resume(), and xtensa_step().
int xtensa_examine | ( | struct target * | target | ) |
Definition at line 886 of file xtensa.c.
References cmd, xtensa::core_config, xtensa_config::core_type, xtensa::dbg_mod, xtensa_debug_module::device_id, ERROR_FAIL, ERROR_OK, ERROR_TARGET_FAILURE, LOG_DEBUG, LOG_ERROR, LOG_TARGET_DEBUG, PWRCTL_COREWAKEUP, PWRCTL_DEBUGWAKEUP, PWRCTL_JTAGDEBUGUSE, PWRCTL_MEMWAKEUP, xtensa::smp_break, target_set_examined(), target_to_xtensa(), XDMREG_PWRCTL, XT_UNDEF, xtensa_dm_is_online(), xtensa_dm_queue_enable(), xtensa_dm_queue_execute(), xtensa_dm_queue_tdi_idle(), xtensa_queue_pwr_reg_write(), and xtensa_smpbreak_write().
Referenced by esp_xtensa_smp_deassert_reset(), and xtensa_chip_examine().
int xtensa_fetch_all_regs | ( | struct target * | target | ) |
Definition at line 1210 of file xtensa.c.
References a0, a3, xtensa_reg_val_u::buf, buf_cpy(), buf_get_u32(), xtensa_keyval_info::chrval, xtensa_config::coproc, xtensa::core_cache, xtensa::core_config, xtensa_config::core_type, xtensa::dbg_mod, xtensa_config::debug, reg::dirty, ERROR_FAIL, ERROR_OK, xtensa_reg_desc::exist, xtensa_reg_desc::flags, xtensa_keyval_info::intval, xtensa_debug_config::irq_level, LOG_DEBUG, LOG_ERROR, LOG_INFO, LOG_LEVEL_IS, LOG_LVL_DEBUG, LOG_TARGET_DEBUG, LOG_TARGET_ERROR, name, reg_cache::num_regs, xtensa::nx_reg_idx, OCDDSR_EXECEXCEPTION, xtensa::optregs, reg_cache::reg_list, xtensa_reg_desc::reg_num, xtensa::regs_fetched, xtensa::scratch_ars, size, target_to_xtensa(), type, xtensa_reg_desc::type, reg::valid, xtensa_config::windowed, XDMREG_DDR, XDMREG_DSR, XT_AR_SCRATCH_AR3, XT_AR_SCRATCH_AR4, XT_AR_SCRATCH_NUM, XT_AREGS_NUM_MAX, XT_EPC_REG_NUM_BASE, XT_EPS_REG_NUM_BASE, XT_INS_CALL0, XT_INS_RFR, XT_INS_ROTW, XT_INS_RSR, XT_INS_RUR, XT_INS_WSR, XT_LX, XT_MS_DISPST_DBG, XT_NUM_REGS, XT_NX, XT_NX_REG_IDX_MS, XT_NX_REG_IDX_WB, XT_PC_REG_NUM_VIRTUAL, XT_REG_A0, XT_REG_A3, XT_REG_DEBUG, XT_REG_FR, XT_REG_GENERAL, XT_REG_IDX_A0, XT_REG_IDX_A3, XT_REG_IDX_A4, XT_REG_IDX_AR0, XT_REG_IDX_CPENABLE, XT_REG_IDX_PS, XT_REG_IDX_WINDOWBASE, XT_REG_OTHER, XT_REG_RELGEN, XT_REG_SPECIAL, XT_REG_TIE, XT_REG_USER, XT_REGF_MASK, XT_REGF_NOREAD, XT_SR_DDR, XT_WB_P_MSK, XT_WB_P_SHIFT, xtensa_canonical_to_windowbase_offset(), xtensa_core_status_check(), xtensa_dm_queue_execute(), xtensa_extra_debug_log, xtensa_mark_register_dirty(), xtensa_queue_dbg_reg_read(), xtensa_queue_dbg_reg_write(), xtensa_queue_exec_ins(), xtensa_reg_is_readable(), xtensa_reg_set(), xtensa_regs, xtensa_window_state_restore(), xtensa_window_state_save(), and xtensa_windowbase_offset_to_canonical().
Referenced by COMMAND_HELPER(), xtensa_do_step(), and xtensa_poll().
int xtensa_gdb_query_custom | ( | struct target * | target, |
const char * | packet, | ||
char ** | response_p | ||
) |
Definition at line 3264 of file xtensa.c.
References xtensa_local_mem_region_config::base, xtensa::core_config, xtensa_local_mem_config::count, xtensa_config::dcache, xtensa_high_prio_irq_config::enabled, ERROR_FAIL, ERROR_OK, xtensa_high_prio_irq_config::excm_level, xtensa_config::high_irq, xtensa_config::icache, xtensa_keyval_info::intval, xtensa_config::iram, xtensa_config::irom, xtensa_cache_config::line_size, LOG_ERROR, LOG_TARGET_DEBUG, LOG_TARGET_ERROR, LOG_TARGET_WARNING, NULL, xtensa::qpkt_resp, xtensa_local_mem_config::regions, size, xtensa_cache_config::size, xtensa_local_mem_region_config::size, xtensa::spill_buf, xtensa::spill_bytes, xtensa::spill_loc, target_to_xtensa(), xtensa_cache_config::way_count, xt_qerr, XT_QERR_INVAL, XT_QERR_MEM, and xtensa_gdbqc_qxtreg().
const char* xtensa_get_gdb_arch | ( | const struct target * | target | ) |
int xtensa_get_gdb_reg_list | ( | struct target * | target, |
struct reg ** | reg_list[], | ||
int * | reg_list_size, | ||
enum target_register_class | reg_class | ||
) |
Definition at line 1489 of file xtensa.c.
References xtensa::contiguous_regs_list, xtensa::core_cache, xtensa::core_config, xtensa_config::core_type, xtensa_reg_desc::dbreg_num, xtensa::dbregs_num, xtensa_config::debug, xtensa::empty_regs, xtensa::eps_dbglevel_idx, ERROR_FAIL, ERROR_OK, reg::exist, xtensa::genpkt_regs_num, xtensa_debug_config::irq_level, LOG_DEBUG, LOG_ERROR, reg_cache::num_regs, xtensa::optregs, REG_CLASS_GENERAL, reg_cache::reg_list, xtensa::regmap_contiguous, target_to_xtensa(), xtensa::total_regs_num, type, XT_LX, XT_NUM_REGS, XT_PC_DBREG_NUM_BASE, XT_REG_IDX_ARFIRST, XT_REG_IDX_PC, XT_REG_IDX_PS, XT_REG_RELGEN, xtensa_extra_debug_log, xtensa_reg_get_value(), and xtensa_regs.
int xtensa_halt | ( | struct target * | target | ) |
Definition at line 1566 of file xtensa.c.
References xtensa::dbg_mod, ERROR_OK, LOG_TARGET_DEBUG, LOG_TARGET_ERROR, OCDDCR_DEBUGINTERRUPT, OCDDCR_ENABLEOCD, target::state, TARGET_HALTED, target_to_xtensa(), XDMREG_DCRSET, xtensa_dm_core_status_get(), xtensa_dm_core_status_read(), xtensa_dm_queue_execute(), xtensa_dm_queue_tdi_idle(), xtensa_is_stopped(), and xtensa_queue_dbg_reg_write().
Referenced by esp32_soc_reset(), esp32s2_soc_reset(), and esp32s3_soc_reset().
int xtensa_init_arch_info | ( | struct target * | target, |
struct xtensa * | xtensa, | ||
const struct xtensa_debug_module_config * | dm_cfg | ||
) |
Definition at line 3375 of file xtensa.c.
References target::arch_info, xtensa_keyval_info::chrval, xtensa::common_magic, xtensa::core_config, xtensa::dbg_mod, xtensa_config::dcache, ERROR_FAIL, xtensa_config::icache, xtensa_keyval_info::intval, LOG_ERROR, xtensa::scratch_ars, xtensa::stepping_isr_mode, target, xtensa::target, xtensa_cache_config::way_count, XT_AR_SCRATCH_A3, XT_AR_SCRATCH_A4, XT_AR_SCRATCH_AR3, XT_AR_SCRATCH_NUM, XT_STEPPING_ISR_ON, XTENSA_COMMON_MAGIC, and xtensa_dm_init().
Referenced by esp_xtensa_init_arch_info(), and xtensa_chip_init_arch_info().
int xtensa_mmu_is_enabled | ( | struct target * | target, |
int * | enabled | ||
) |
Definition at line 1558 of file xtensa.c.
References xtensa::core_config, xtensa_mmu_config::dtlb_entries_count, ERROR_OK, xtensa_mmu_config::itlb_entries_count, xtensa_config::mmu, and target_to_xtensa().
void xtensa_on_poll | ( | struct target * | target | ) |
int xtensa_poll | ( | struct target * | target | ) |
Definition at line 2304 of file xtensa.c.
References xtensa::come_online_probes_num, xtensa::core_config, xtensa_debug_module::core_status, xtensa_config::core_type, xtensa::dbg_mod, DBG_REASON_BREAKPOINT, DBG_REASON_DBGRQ, DBG_REASON_NOTHALTED, DBG_REASON_SINGLESTEP, DBG_REASON_WATCHPOINT, DBG_REASON_WPTANDBKPT, target::debug_reason, DEBUGCAUSE_BI, DEBUGCAUSE_BN, DEBUGCAUSE_DB, DEBUGCAUSE_IB, DEBUGCAUSE_IC, xtensa_core_status::dsr, ERROR_OK, ERROR_TARGET_NOT_EXAMINED, target::examined, LOG_INFO, LOG_TARGET_DEBUG, LOG_TARGET_ERROR, LOG_TARGET_INFO, OCDDSR_DEBUGINTBREAK, OCDDSR_DEBUGINTHOST, OCDDSR_DEBUGINTTRAX, OCDDSR_DEBUGPENDBREAK, OCDDSR_DEBUGPENDHOST, OCDDSR_DEBUGPENDTRAX, OCDDSR_STOPPED, xtensa_debug_module::power_status, PWRSTAT_COREWASRESET, PWRSTAT_DEBUGWASRESET, xtensa::smp_break, xtensa_power_status::stat, target::state, xtensa_power_status::stath, TARGET_DEBUG_RUNNING, TARGET_HALTED, TARGET_RESET, TARGET_RUNNING, target_to_xtensa(), TARGET_UNKNOWN, xtensa::trace_active, TRAXSTAT_CTITG, TRAXSTAT_PCMTG, TRAXSTAT_PTITG, TRAXSTAT_TRACT, XDMREG_DDR, XT_INS_RSR, XT_INS_WSR, XT_NX, XT_PS_DIEXC_MSK, XT_REG_A3, XT_REG_IDX_EXCCAUSE, XT_REG_IDX_PC, XT_REG_IDX_PS, XT_SR_DDR, XT_SR_PS, xtensa_cause_get(), xtensa_core_status_check(), xtensa_dm_core_status_clear(), xtensa_dm_core_status_read(), xtensa_dm_core_was_reset(), xtensa_dm_is_powered(), xtensa_dm_poll(), xtensa_dm_power_status_cache(), xtensa_dm_power_status_read(), xtensa_dm_queue_execute(), xtensa_dm_tap_was_reset(), xtensa_dm_trace_status_read(), xtensa_fetch_all_regs(), xtensa_is_stopped(), xtensa_mark_register_dirty(), xtensa_queue_dbg_reg_write(), xtensa_queue_exec_ins(), xtensa_reg_get(), xtensa_smpbreak_write(), and xtensa_wakeup().
Referenced by esp32_soc_reset(), esp32s2_soc_reset(), esp32s3_soc_reset(), esp_xtensa_poll(), and xtensa_chip_poll().
int xtensa_prepare_resume | ( | struct target * | target, |
int | current, | ||
target_addr_t | address, | ||
int | handle_breakpoints, | ||
int | debug_execution | ||
) |
Definition at line 1593 of file xtensa.c.
References breakpoint::address, BIT, xtensa::core_config, xtensa_config::core_type, xtensa_config::debug, DEBUGCAUSE_BI, DEBUGCAUSE_BN, DEBUGCAUSE_DB, ERROR_OK, ERROR_TARGET_NOT_HALTED, xtensa::halt_request, xtensa::hw_brps, xtensa_debug_config::ibreaks_num, LOG_TARGET_DEBUG, LOG_TARGET_ERROR, xtensa::nx_reg_idx, target::state, TARGET_ADDR_FMT, TARGET_HALTED, target_to_xtensa(), XT_IBREAKC_FB, XT_LX, XT_NX, XT_NX_REG_IDX_IBREAKC0, XT_REG_IDX_IBREAKA0, XT_REG_IDX_IBREAKENABLE, XT_REG_IDX_PC, xtensa_cause_get(), xtensa_do_step(), xtensa_reg_set(), and xtensa_write_dirty_registers().
Referenced by esp_xtensa_smp_resume(), xtensa_do_step(), and xtensa_resume().
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Definition at line 327 of file xtensa.h.
References xtensa::core_config, xtensa::dbg_mod, xtensa_debug_module::dbg_ops, xtensa_tracing_config::enabled, ERROR_FAIL, LOG_ERROR, xtensa_debug_ops::queue_reg_read, xtensa_config::trace, XDMREG_MEMADDREND, XDMREG_PMG, and XDMREG_PMSTAT7.
Referenced by esp_xtensa_apptrace_ctrl_reg_read(), esp_xtensa_apptrace_data_normal_read(), esp_xtensa_apptrace_data_reverse_read(), esp_xtensa_apptrace_status_reg_read(), esp_xtensa_profiling(), xtensa_fetch_all_regs(), xtensa_read_memory(), xtensa_region_ar_exec(), xtensa_smpbreak_read(), xtensa_window_state_save(), xtensa_write_dirty_registers(), and xtensa_write_memory().
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Definition at line 339 of file xtensa.h.
References xtensa::core_config, xtensa::dbg_mod, xtensa_debug_module::dbg_ops, xtensa_tracing_config::enabled, ERROR_FAIL, LOG_ERROR, xtensa_debug_ops::queue_reg_write, xtensa_config::trace, XDMREG_MEMADDREND, XDMREG_PMG, and XDMREG_PMSTAT7.
Referenced by COMMAND_HELPER(), esp_xtensa_apptrace_buffs_write(), esp_xtensa_apptrace_ctrl_reg_write(), esp_xtensa_apptrace_data_normal_read(), esp_xtensa_apptrace_data_read(), esp_xtensa_apptrace_data_reverse_read(), esp_xtensa_apptrace_queue_normal_write(), esp_xtensa_apptrace_queue_reverse_write(), esp_xtensa_apptrace_status_reg_write(), esp_xtensa_swdbg_activate(), xtensa_deassert_reset(), xtensa_do_step(), xtensa_fetch_all_regs(), xtensa_gdbqc_qxtreg(), xtensa_halt(), xtensa_poll(), xtensa_queue_exec_ins(), xtensa_queue_exec_ins_wide(), xtensa_read_memory(), xtensa_region_ar_exec(), xtensa_smpbreak_write(), xtensa_target_deinit(), xtensa_update_instruction(), xtensa_window_state_restore(), xtensa_window_state_save(), xtensa_write_dirty_registers(), and xtensa_write_memory().
int xtensa_read_buffer | ( | struct target * | target, |
target_addr_t | address, | ||
uint32_t | count, | ||
uint8_t * | buffer | ||
) |
Definition at line 2081 of file xtensa.c.
References buffer, count, and xtensa_read_memory().
Referenced by xtensa_pc_in_winexc().
int xtensa_read_memory | ( | struct target * | target, |
target_addr_t | address, | ||
uint32_t | size, | ||
uint32_t | count, | ||
uint8_t * | buffer | ||
) |
Definition at line 1998 of file xtensa.c.
References ALIGN_DOWN, ALIGN_UP, buf_bswap32(), buffer, count, xtensa::dbg_mod, target::endianness, ERROR_FAIL, ERROR_OK, ERROR_TARGET_NOT_HALTED, ERROR_TARGET_RESOURCE_NOT_AVAILABLE, LOG_DEBUG, LOG_TARGET_DEBUG, LOG_TARGET_ERROR, LOG_TARGET_WARNING, xtensa::permissive_mode, xtensa::probe_lsddr32p, size, target::state, xtensa::suppress_dsr_errors, xtensa::target, TARGET_ADDR_FMT, TARGET_BIG_ENDIAN, TARGET_HALTED, target_to_xtensa(), XDMREG_DDR, XDMREG_DDREXEC, XT_INS_L32I, XT_INS_LDDR32P, XT_INS_RSR, XT_INS_WSR, XT_MEM_ACCESS_READ, XT_REG_A3, XT_REG_A4, XT_REG_IDX_A3, XT_REG_IDX_A4, XT_SR_DDR, xtensa_core_status_check(), xtensa_dm_queue_execute(), xtensa_mark_register_dirty(), xtensa_memory_op_validate_range(), xtensa_queue_dbg_reg_read(), xtensa_queue_dbg_reg_write(), and xtensa_queue_exec_ins().
Referenced by xtensa_gdbqc_qxtreg(), and xtensa_read_buffer().
xtensa_reg_val_t xtensa_reg_get | ( | struct target * | target, |
enum xtensa_reg_id | reg_id | ||
) |
Definition at line 1063 of file xtensa.c.
References xtensa::core_cache, reg_cache::reg_list, target_to_xtensa(), and xtensa_reg_get_value().
Referenced by COMMAND_HELPER(), esp_xtensa_semihosting(), xtensa_cause_get(), xtensa_do_step(), xtensa_fileio_detect_proc(), xtensa_gdb_fileio_end(), xtensa_gdbqc_qxtreg(), xtensa_get_gdb_fileio_info(), xtensa_imprecise_exception_occurred(), xtensa_poll(), xtensa_reg_set_deep_relgen(), xtensa_start_algorithm(), xtensa_wait_algorithm(), and xtensa_write_dirty_registers().
void xtensa_reg_set | ( | struct target * | target, |
enum xtensa_reg_id | reg_id, | ||
xtensa_reg_val_t | value | ||
) |
Definition at line 1070 of file xtensa.c.
References xtensa::core_cache, reg_cache::reg_list, target_to_xtensa(), reg::value, xtensa_reg_get_value(), and xtensa_reg_set_value().
Referenced by COMMAND_HELPER(), esp_xtensa_semihosting_post_result(), xtensa_breakpoint_remove(), xtensa_cause_clear(), xtensa_do_step(), xtensa_fetch_all_regs(), xtensa_gdb_fileio_end(), xtensa_imprecise_exception_clear(), xtensa_prepare_resume(), xtensa_reg_set_deep_relgen(), xtensa_start_algorithm(), xtensa_wait_algorithm(), xtensa_watchpoint_add(), and xtensa_watchpoint_remove().
void xtensa_reg_set_deep_relgen | ( | struct target * | target, |
enum xtensa_reg_id | a_idx, | ||
xtensa_reg_val_t | value | ||
) |
Definition at line 1080 of file xtensa.c.
References xtensa::core_config, xtensa_config::core_type, xtensa::nx_reg_idx, target_to_xtensa(), xtensa_config::windowed, XT_LX, XT_NX, XT_NX_REG_IDX_WB, XT_REG_IDX_WINDOWBASE, XT_WB_P_MSK, XT_WB_P_SHIFT, xtensa_reg_get(), xtensa_reg_set(), and xtensa_windowbase_offset_to_canonical().
Referenced by xtensa_gdb_fileio_end().
int xtensa_resume | ( | struct target * | target, |
int | current, | ||
target_addr_t | address, | ||
int | handle_breakpoints, | ||
int | debug_execution | ||
) |
Definition at line 1673 of file xtensa.c.
References DBG_REASON_NOTHALTED, target::debug_reason, ERROR_OK, LOG_TARGET_DEBUG, LOG_TARGET_ERROR, target::state, target_call_event_callbacks(), TARGET_DEBUG_RUNNING, TARGET_EVENT_RESUMED, TARGET_RUNNING, xtensa_do_resume(), and xtensa_prepare_resume().
Referenced by esp32_soc_reset(), esp32s3_soc_reset(), and xtensa_start_algorithm().
int xtensa_run_algorithm | ( | struct target * | target, |
int | num_mem_params, | ||
struct mem_param * | mem_params, | ||
int | num_reg_params, | ||
struct reg_param * | reg_params, | ||
target_addr_t | entry_point, | ||
target_addr_t | exit_point, | ||
unsigned int | timeout_ms, | ||
void * | arch_info | ||
) |
Definition at line 2911 of file xtensa.c.
References reg::arch_info, ERROR_OK, xtensa_start_algorithm(), and xtensa_wait_algorithm().
void xtensa_set_permissive_mode | ( | struct target * | target, |
bool | state | ||
) |
Definition at line 3414 of file xtensa.c.
References xtensa::permissive_mode, state, and target_to_xtensa().
int xtensa_smpbreak_get | ( | struct target * | target, |
uint32_t * | val | ||
) |
Definition at line 968 of file xtensa.c.
References ERROR_OK, xtensa::smp_break, and target_to_xtensa().
Referenced by esp_xtensa_smp_resume(), and esp_xtensa_smp_smpbreak_disable().
int xtensa_smpbreak_read | ( | struct xtensa * | xtensa, |
uint32_t * | val | ||
) |
Definition at line 956 of file xtensa.c.
References buf_get_u32(), xtensa::dbg_mod, XDMREG_DCRSET, xtensa_dm_queue_execute(), xtensa_dm_queue_tdi_idle(), and xtensa_queue_dbg_reg_read().
Referenced by COMMAND_HELPER().
int xtensa_smpbreak_set | ( | struct target * | target, |
uint32_t | set | ||
) |
Definition at line 944 of file xtensa.c.
References ERROR_OK, LOG_TARGET_DEBUG, xtensa::smp_break, target::state, target_to_xtensa(), target_was_examined(), and xtensa_smpbreak_write().
Referenced by COMMAND_HELPER(), esp_xtensa_smp_smpbreak_disable(), and esp_xtensa_smp_smpbreak_restore().
int xtensa_smpbreak_write | ( | struct xtensa * | xtensa, |
uint32_t | set | ||
) |
Definition at line 929 of file xtensa.c.
References xtensa::dbg_mod, LOG_TARGET_DEBUG, OCDDCR_BREAKINEN, OCDDCR_BREAKOUTEN, OCDDCR_DEBUGMODEOUTEN, OCDDCR_ENABLEOCD, OCDDCR_RUNSTALLINEN, xtensa::target, XDMREG_DCRCLR, XDMREG_DCRSET, XDMREG_DSR, xtensa_dm_queue_execute(), xtensa_dm_queue_tdi_idle(), and xtensa_queue_dbg_reg_write().
Referenced by esp32s2_deassert_reset(), esp32s2_soc_reset(), xtensa_examine(), xtensa_poll(), and xtensa_smpbreak_set().
int xtensa_soft_reset_halt | ( | struct target * | target | ) |
Definition at line 1204 of file xtensa.c.
References LOG_TARGET_DEBUG, and xtensa_assert_reset().
Referenced by esp32s2_soft_reset_halt().
int xtensa_start_algorithm | ( | struct target * | target, |
int | num_mem_params, | ||
struct mem_param * | mem_params, | ||
int | num_reg_params, | ||
struct reg_param * | reg_params, | ||
target_addr_t | entry_point, | ||
target_addr_t | exit_point, | ||
void * | arch_info | ||
) |
Definition at line 2712 of file xtensa.c.
References xtensa::algo_context_backup, buf_cpy(), buf_get_u32(), xtensa::core_cache, xtensa::core_config, xtensa_algorithm::core_mode, xtensa_config::core_type, xtensa_algorithm::ctx_debug_reason, xtensa_algorithm::ctx_ps, xtensa_config::debug, target::debug_reason, direction, xtensa::eps_dbglevel_idx, ERROR_FAIL, ERROR_OK, ERROR_TARGET_NOT_HALTED, xtensa_debug_config::irq_level, LOG_DEBUG, LOG_ERROR, LOG_WARNING, reg_cache::num_regs, PARAM_IN, reg_cache::reg_list, reg_param::reg_name, register_get_by_name(), size, reg_param::size, reg::size, target::state, TARGET_HALTED, target_to_xtensa(), target_write_buffer(), reg::valid, reg::value, XT_LX, XT_MODE_ANY, XT_PS_RING, XT_PS_RING_GET, XT_PS_RING_MSK, xtensa_reg_get(), xtensa_reg_set(), xtensa_reg_set_value(), and xtensa_resume().
Referenced by xtensa_run_algorithm().
int xtensa_step | ( | struct target * | target, |
int | current, | ||
target_addr_t | address, | ||
int | handle_breakpoints | ||
) |
Definition at line 1934 of file xtensa.c.
References ERROR_OK, target_call_event_callbacks(), TARGET_EVENT_HALTED, and xtensa_do_step().
Referenced by esp32s2_step(), and esp_xtensa_smp_step().
void xtensa_target_deinit | ( | struct target * | target | ) |
Definition at line 3485 of file xtensa.c.
References xtensa_keyval_info::chrval, xtensa::core_config, xtensa::dbg_mod, ERROR_OK, xtensa::hw_brps, xtensa::hw_wps, LOG_DEBUG, LOG_ERROR, NULL, OCDDCR_ENABLEOCD, xtensa::scratch_ars, xtensa::spill_buf, xtensa::sw_brps, target_to_xtensa(), target_was_examined(), XDMREG_DCRCLR, XT_AR_SCRATCH_NUM, xtensa_dm_deinit(), xtensa_dm_queue_execute(), xtensa_dm_queue_tdi_idle(), xtensa_free_reg_cache(), and xtensa_queue_dbg_reg_write().
Referenced by esp_xtensa_target_deinit(), and xtensa_chip_target_deinit().
int xtensa_target_init | ( | struct command_context * | cmd_ctx, |
struct target * | target | ||
) |
Definition at line 3419 of file xtensa.c.
References xtensa::come_online_probes_num, ERROR_FAIL, xtensa::hw_brps, xtensa::hw_wps, LOG_ERROR, NULL, xtensa::probe_lsddr32p, xtensa::spill_buf, xtensa::spill_bytes, xtensa::spill_loc, xtensa::sw_brps, target_to_xtensa(), XT_HW_DBREAK_MAX_NUM, XT_HW_IBREAK_MAX_NUM, XT_SW_BREAKPOINTS_MAX_NUM, and xtensa_build_reg_cache().
Referenced by esp_xtensa_target_init(), and xtensa_chip_target_init().
int xtensa_wait_algorithm | ( | struct target * | target, |
int | num_mem_params, | ||
struct mem_param * | mem_params, | ||
int | num_reg_params, | ||
struct reg_param * | reg_params, | ||
target_addr_t | exit_point, | ||
unsigned int | timeout_ms, | ||
void * | arch_info | ||
) |
Waits for an algorithm in the target.
Definition at line 2803 of file xtensa.c.
References xtensa::algo_context_backup, buf_cpy(), buf_get_u32(), buf_get_u64(), buf_set_u32(), xtensa::core_cache, xtensa::core_config, xtensa_config::core_type, xtensa_algorithm::ctx_debug_reason, xtensa_algorithm::ctx_ps, target::debug_reason, direction, reg::dirty, xtensa::eps_dbglevel_idx, ERROR_FAIL, ERROR_OK, ERROR_TARGET_TIMEOUT, keep_alive(), LOG_DEBUG, LOG_ERROR, LOG_TARGET_ERROR, reg::name, reg_cache::num_regs, PARAM_OUT, reg_cache::reg_list, reg_param::reg_name, register_get_by_name(), size, reg_param::size, reg::size, target::state, TARGET_ADDR_FMT, target_halt(), TARGET_HALTED, target_read_buffer(), target_to_xtensa(), target_wait_state(), reg::valid, reg::value, XT_LX, XT_REG_IDX_DEBUGCAUSE, XT_REG_IDX_PC, XT_REG_IDX_PS, xtensa_reg_get(), xtensa_reg_get_value(), xtensa_reg_set(), and xtensa_write_dirty_registers().
Referenced by xtensa_run_algorithm().
int xtensa_wakeup | ( | struct target * | target | ) |
Definition at line 915 of file xtensa.c.
References cmd, xtensa::dbg_mod, PWRCTL_CORERESET, PWRCTL_COREWAKEUP, PWRCTL_DEBUGWAKEUP, PWRCTL_JTAGDEBUGUSE, PWRCTL_MEMWAKEUP, xtensa::reset_asserted, target_to_xtensa(), XDMREG_PWRCTL, xtensa_dm_queue_execute(), xtensa_dm_queue_tdi_idle(), and xtensa_queue_pwr_reg_write().
Referenced by xtensa_poll().
int xtensa_watchpoint_add | ( | struct target * | target, |
struct watchpoint * | watchpoint | ||
) |
Definition at line 2636 of file xtensa.c.
References watchpoint::address, ALIGN_DOWN, BIT, xtensa::core_config, xtensa_debug_config::dbreaks_num, xtensa_config::debug, ERROR_OK, ERROR_TARGET_NOT_HALTED, ERROR_TARGET_RESOURCE_NOT_AVAILABLE, xtensa::hw_wps, IS_ALIGNED, IS_PWR_OF_2, watchpoint::length, LOG_TARGET_DEBUG, LOG_TARGET_ERROR, LOG_TARGET_WARNING, watchpoint::mask, watchpoint::rw, target::state, TARGET_ADDR_FMT, TARGET_HALTED, target_to_xtensa(), WATCHPOINT_IGNORE_DATA_VALUE_MASK, WPT_ACCESS, WPT_READ, WPT_WRITE, XT_REG_IDX_DBREAKA0, XT_REG_IDX_DBREAKC0, and xtensa_reg_set().
Referenced by esp_xtensa_smp_watchpoint_add().
int xtensa_watchpoint_remove | ( | struct target * | target, |
struct watchpoint * | watchpoint | ||
) |
Definition at line 2692 of file xtensa.c.
References watchpoint::address, xtensa::core_config, xtensa_debug_config::dbreaks_num, xtensa_config::debug, ERROR_OK, ERROR_TARGET_RESOURCE_NOT_AVAILABLE, xtensa::hw_wps, LOG_TARGET_DEBUG, LOG_TARGET_WARNING, NULL, TARGET_ADDR_FMT, target_to_xtensa(), XT_REG_IDX_DBREAKC0, and xtensa_reg_set().
Referenced by esp_xtensa_smp_watchpoint_remove().
int xtensa_write_buffer | ( | struct target * | target, |
target_addr_t | address, | ||
uint32_t | count, | ||
const uint8_t * | buffer | ||
) |
Definition at line 2292 of file xtensa.c.
References buffer, count, and xtensa_write_memory().
int xtensa_write_memory | ( | struct target * | target, |
target_addr_t | address, | ||
uint32_t | size, | ||
uint32_t | count, | ||
const uint8_t * | buffer | ||
) |
Definition at line 2087 of file xtensa.c.
References ALIGN_DOWN, ALIGN_UP, buf_bswap32(), buf_get_u32(), buffer, xtensa::core_config, count, xtensa::dbg_mod, xtensa_config::dcache, target::endianness, ERROR_COMMAND_SYNTAX_ERROR, ERROR_FAIL, ERROR_OK, ERROR_TARGET_NOT_HALTED, ERROR_TARGET_RESOURCE_NOT_AVAILABLE, xtensa_config::icache, xtensa_cache_config::line_size, LOG_ERROR, LOG_TARGET_DEBUG, LOG_TARGET_ERROR, LOG_TARGET_INFO, LOG_TARGET_WARNING, LOG_WARNING, MIN, xtensa::permissive_mode, xtensa::probe_lsddr32p, size, target::state, xtensa::suppress_dsr_errors, xtensa::target, TARGET_ADDR_FMT, TARGET_BIG_ENDIAN, TARGET_HALTED, target_to_xtensa(), XDMREG_DDR, XDMREG_DDREXEC, XT_INS_DHWBI, XT_INS_IHI, XT_INS_L32I, XT_INS_LDDR32P, XT_INS_RSR, XT_INS_S32I, XT_INS_SDDR32P, XT_INS_WSR, XT_MEM_ACCESS_WRITE, XT_REG_A3, XT_REG_A4, XT_REG_IDX_A3, XT_REG_IDX_A4, XT_SR_DDR, xtensa_core_status_check(), xtensa_dm_queue_execute(), xtensa_is_dcacheable(), xtensa_is_icacheable(), xtensa_mark_register_dirty(), xtensa_memory_op_validate_range(), xtensa_queue_dbg_reg_read(), xtensa_queue_dbg_reg_write(), xtensa_queue_exec_ins(), and xtensa_region_ar_exec().
Referenced by xtensa_gdbqc_qxtreg(), and xtensa_write_buffer().
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