20 #define ESP32_S2_RTC_DATA_LOW 0x50000000
21 #define ESP32_S2_RTC_DATA_HIGH 0x50002000
22 #define ESP32_S2_DR_REG_LOW 0x3f400000
23 #define ESP32_S2_DR_REG_HIGH 0x3f4d3FFC
24 #define ESP32_S2_SYS_RAM_LOW 0x60000000UL
25 #define ESP32_S2_SYS_RAM_HIGH (ESP32_S2_SYS_RAM_LOW + 0x20000000UL)
28 #define ESP32_S2_WDT_WKEY_VALUE 0x50d83aa1
29 #define ESP32_S2_TIMG0_BASE 0x3f41F000
30 #define ESP32_S2_TIMG1_BASE 0x3f420000
31 #define ESP32_S2_TIMGWDT_CFG0_OFF 0x48
32 #define ESP32_S2_TIMGWDT_PROTECT_OFF 0x64
33 #define ESP32_S2_TIMG0WDT_CFG0 (ESP32_S2_TIMG0_BASE + ESP32_S2_TIMGWDT_CFG0_OFF)
34 #define ESP32_S2_TIMG1WDT_CFG0 (ESP32_S2_TIMG1_BASE + ESP32_S2_TIMGWDT_CFG0_OFF)
35 #define ESP32_S2_TIMG0WDT_PROTECT (ESP32_S2_TIMG0_BASE + ESP32_S2_TIMGWDT_PROTECT_OFF)
36 #define ESP32_S2_TIMG1WDT_PROTECT (ESP32_S2_TIMG1_BASE + ESP32_S2_TIMGWDT_PROTECT_OFF)
37 #define ESP32_S2_RTCCNTL_BASE 0x3f408000
38 #define ESP32_S2_RTCWDT_CFG_OFF 0x94
39 #define ESP32_S2_RTCWDT_PROTECT_OFF 0xAC
40 #define ESP32_S2_SWD_CONF_OFF 0xB0
41 #define ESP32_S2_SWD_WPROTECT_OFF 0xB4
42 #define ESP32_S2_RTC_CNTL_DIG_PWC_REG_OFF 0x8C
43 #define ESP32_S2_RTC_CNTL_DIG_PWC_REG (ESP32_S2_RTCCNTL_BASE + ESP32_S2_RTC_CNTL_DIG_PWC_REG_OFF)
44 #define ESP32_S2_RTCWDT_CFG (ESP32_S2_RTCCNTL_BASE + ESP32_S2_RTCWDT_CFG_OFF)
45 #define ESP32_S2_RTCWDT_PROTECT (ESP32_S2_RTCCNTL_BASE + ESP32_S2_RTCWDT_PROTECT_OFF)
46 #define ESP32_S2_SWD_CONF_REG (ESP32_S2_RTCCNTL_BASE + ESP32_S2_SWD_CONF_OFF)
47 #define ESP32_S2_SWD_WPROTECT_REG (ESP32_S2_RTCCNTL_BASE + ESP32_S2_SWD_WPROTECT_OFF)
48 #define ESP32_S2_SWD_AUTO_FEED_EN_M BIT(31)
49 #define ESP32_S2_SWD_WKEY_VALUE 0x8F1D312AU
50 #define ESP32_S2_OPTIONS0 (ESP32_S2_RTCCNTL_BASE + 0x0000)
51 #define ESP32_S2_SW_SYS_RST_M 0x80000000
52 #define ESP32_S2_SW_SYS_RST_V 0x1
53 #define ESP32_S2_SW_SYS_RST_S 31
54 #define ESP32_S2_SW_STALL_PROCPU_C0_M ((ESP32_S2_SW_STALL_PROCPU_C0_V) << (ESP32_S2_SW_STALL_PROCPU_C0_S))
55 #define ESP32_S2_SW_STALL_PROCPU_C0_V 0x3
56 #define ESP32_S2_SW_STALL_PROCPU_C0_S 2
57 #define ESP32_S2_SW_CPU_STALL (ESP32_S2_RTCCNTL_BASE + 0x00B8)
58 #define ESP32_S2_SW_STALL_PROCPU_C1_M ((ESP32_S2_SW_STALL_PROCPU_C1_V) << (ESP32_S2_SW_STALL_PROCPU_C1_S))
59 #define ESP32_S2_SW_STALL_PROCPU_C1_V 0x3FU
60 #define ESP32_S2_SW_STALL_PROCPU_C1_S 26
61 #define ESP32_S2_CLK_CONF (ESP32_S2_RTCCNTL_BASE + 0x0074)
62 #define ESP32_S2_CLK_CONF_DEF 0x1583218
63 #define ESP32_S2_STORE4 (ESP32_S2_RTCCNTL_BASE + 0x00BC)
64 #define ESP32_S2_STORE5 (ESP32_S2_RTCCNTL_BASE + 0x00C0)
65 #define ESP32_S2_DPORT_PMS_OCCUPY_3 0x3F4C10E0
67 #define ESP32_S2_TRACEMEM_BLOCK_SZ 0x4000
69 #define ESP32_S2_DR_REG_UART_BASE 0x3f400000
70 #define ESP32_S2_REG_UART_BASE(i) (ESP32_S2_DR_REG_UART_BASE + (i) * 0x10000)
71 #define ESP32_S2_UART_DATE_REG(i) (ESP32_S2_REG_UART_BASE(i) + 0x74)
98 LOG_ERROR(
"Failed to restore smpbreak (%d)!", res);
124 reg_val = (reg_val & (~
mask)) | val;
141 LOG_ERROR(
"Failed to write ESP32_S2_SW_CPU_STALL (%d)!", res);
149 LOG_ERROR(
"Failed to write ESP32_S2_OPTIONS0 (%d)!", res);
196 "Couldn't halt target before SoC reset! (xtensa_assert_reset returned %d)",
209 "Couldn't halt target before SoC reset! (xtensa_deassert_reset returned %d)",
229 LOG_ERROR(
"Failed to write ESP32_S2_STORE4 (%d)!", res);
234 LOG_ERROR(
"Failed to write ESP32_S2_STORE5 (%d)!", res);
239 LOG_ERROR(
"Failed to write ESP32_S2_RTC_CNTL_DIG_PWC_REG (%d)!", res);
244 LOG_ERROR(
"Failed to write ESP32_S2_CLK_CONF (%d)!", res);
254 LOG_ERROR(
"Failed to set smpbreak (%d)!", res);
265 LOG_ERROR(
"Failed to write ESP32_S2_OPTIONS0 (%d)!", res);
298 LOG_ERROR(
"Failed to write ESP32_S2_DPORT_PMS_OCCUPY_3 (%d)!", res);
309 LOG_ERROR(
"Failed to write ESP32_S2_TIMG0WDT_PROTECT (%d)!", res);
314 LOG_ERROR(
"Failed to write ESP32_S2_TIMG0WDT_CFG0 (%d)!", res);
320 LOG_ERROR(
"Failed to write ESP32_S2_TIMG1WDT_PROTECT (%d)!", res);
325 LOG_ERROR(
"Failed to write ESP32_S2_TIMG1WDT_CFG0 (%d)!", res);
331 LOG_ERROR(
"Failed to write ESP32_S2_RTCWDT_PROTECT (%d)!", res);
336 LOG_ERROR(
"Failed to write ESP32_S2_RTCWDT_CFG (%d)!", res);
342 LOG_ERROR(
"Failed to write ESP32_S2_SWD_WPROTECT_REG (%d)!", res);
345 uint32_t swd_conf_reg = 0;
348 LOG_ERROR(
"Failed to read ESP32_S2_SWD_CONF_REG (%d)!", res);
354 LOG_ERROR(
"Failed to write ESP32_S2_SWD_CONF_REG (%d)!", res);
453 .queue_tdi_idle =
NULL,
454 .queue_tdi_idle_arg =
NULL
460 LOG_ERROR(
"Failed to alloc memory for arch info!");
489 .help =
"ARM Command Group",
#define COMMAND_REGISTRATION_DONE
Use this as the last entry in an array of command_registration records.
const struct command_registration esp32_apptrace_command_handlers[]
#define ESP32_S2_SWD_AUTO_FEED_EN_M
static int esp32s2_deassert_reset(struct target *target)
static const struct command_registration esp32s2_command_handlers[]
#define ESP32_S2_OPTIONS0
#define ESP32_S2_SW_STALL_PROCPU_C1_M
#define ESP32_S2_CLK_CONF
static const struct esp_semihost_ops esp32s2_semihost_ops
static int esp32s2_stall_set(struct target *target, bool stall)
#define ESP32_S2_RTCWDT_CFG
static const struct xtensa_power_ops esp32s2_pwr_ops
#define ESP32_S2_TIMG0WDT_CFG0
static int esp32s2_set_peri_reg_mask(struct target *target, target_addr_t addr, uint32_t mask, uint32_t val)
#define ESP32_S2_RTCWDT_PROTECT
static int esp32s2_disable_wdts(struct target *target)
#define ESP32_S2_SWD_WPROTECT_REG
#define ESP32_S2_SW_STALL_PROCPU_C1_S
#define ESP32_S2_RTC_CNTL_DIG_PWC_REG
#define ESP32_S2_TIMG1WDT_PROTECT
#define ESP32_S2_SW_CPU_STALL
static int esp32s2_arch_state(struct target *target)
static int esp32s2_soft_reset_halt(struct target *target)
static int esp32s2_target_create(struct target *target, Jim_Interp *interp)
static int esp32s2_poll(struct target *target)
struct target_type esp32s2_target
static const struct xtensa_debug_ops esp32s2_dbg_ops
#define ESP32_S2_SWD_WKEY_VALUE
static int esp32s2_step(struct target *target, int current, target_addr_t address, int handle_breakpoints)
#define ESP32_S2_SW_STALL_PROCPU_C0_M
#define ESP32_S2_SW_SYS_RST_M
static int esp32s2_stall(struct target *target)
#define ESP32_S2_TIMG1WDT_CFG0
static int esp32s2_target_init(struct command_context *cmd_ctx, struct target *target)
#define ESP32_S2_DPORT_PMS_OCCUPY_3
#define ESP32_S2_SW_STALL_PROCPU_C0_S
#define ESP32_S2_SW_SYS_RST_S
static int esp32s2_soc_reset(struct target *target)
#define ESP32_S2_WDT_WKEY_VALUE
#define ESP32_S2_SWD_CONF_REG
#define ESP32_S2_CLK_CONF_DEF
static int esp32s2_unstall(struct target *target)
#define ESP32_S2_TIMG0WDT_PROTECT
static int esp32s2_virt2phys(struct target *target, target_addr_t virtual, target_addr_t *physical)
static int esp32s2_assert_reset(struct target *target)
static int esp32s2_on_halt(struct target *target)
int esp_xtensa_init_arch_info(struct target *target, struct esp_xtensa_common *esp_xtensa, struct xtensa_debug_module_config *dm_cfg, const struct esp_semihost_ops *semihost_ops)
int esp_xtensa_poll(struct target *target)
void esp_xtensa_target_deinit(struct target *target)
int esp_xtensa_target_init(struct command_context *cmd_ctx, struct target *target)
int esp_xtensa_breakpoint_remove(struct target *target, struct breakpoint *breakpoint)
int esp_xtensa_breakpoint_add(struct target *target, struct breakpoint *breakpoint)
int esp_xtensa_on_halt(struct target *target)
static struct esp_xtensa_common * target_to_esp_xtensa(struct target *target)
int esp_xtensa_semihosting_init(struct target *target)
int esp_xtensa_semihosting(struct target *target, int *retval)
Checks and processes an ESP Xtensa semihosting request.
void alive_sleep(uint64_t ms)
#define LOG_TARGET_ERROR(target, fmt_str,...)
#define LOG_TARGET_DEBUG(target, fmt_str,...)
#define LOG_ERROR(expr ...)
#define LOG_DEBUG(expr ...)
target_addr_t addr
Start address to search for the control block.
const struct command_registration semihosting_common_handlers[]
const struct command_registration * chain
If non-NULL, the commands in chain will be registered in the same context and scope of this registrat...
struct esp_xtensa_common esp_xtensa
Semihost calls handling operations.
int(* prepare)(struct target *target)
Callback called before handling semihost call.
struct esp_semihost_data semihost
This holds methods shared between all instances of a given target type.
const char * name
Name of this type of target.
enum target_debug_reason debug_reason
const struct xtensa_debug_ops * dbg_ops
int(* queue_enable)(struct xtensa_debug_module *dm)
enable operation
int(* queue_reg_read)(struct xtensa_debug_module *dm, enum xtensa_dm_pwr_reg reg, uint8_t *data, uint32_t clear)
register read.
Represents a generic Xtensa core.
int target_call_event_callbacks(struct target *target, enum target_event event)
int target_write_u32(struct target *target, target_addr_t address, uint32_t value)
int target_read_u32(struct target *target, target_addr_t address, uint32_t *value)
int target_wait_state(struct target *target, enum target_state state, unsigned int ms)
int target_resume(struct target *target, int current, target_addr_t address, int handle_breakpoints, int debug_execution)
Make the target (re)start executing using its saved execution context (possibly with some modificatio...
@ TARGET_EVENT_DEBUG_HALTED
#define ERROR_TARGET_TIMEOUT
int xtensa_watchpoint_add(struct target *target, struct watchpoint *watchpoint)
const char * xtensa_get_gdb_arch(const struct target *target)
int xtensa_poll(struct target *target)
int xtensa_halt(struct target *target)
int xtensa_read_buffer(struct target *target, target_addr_t address, uint32_t count, uint8_t *buffer)
int xtensa_get_gdb_reg_list(struct target *target, struct reg **reg_list[], int *reg_list_size, enum target_register_class reg_class)
int xtensa_step(struct target *target, int current, target_addr_t address, int handle_breakpoints)
int xtensa_checksum_memory(struct target *target, target_addr_t address, uint32_t count, uint32_t *checksum)
const struct command_registration xtensa_command_handlers[]
int xtensa_examine(struct target *target)
int xtensa_start_algorithm(struct target *target, int num_mem_params, struct mem_param *mem_params, int num_reg_params, struct reg_param *reg_params, target_addr_t entry_point, target_addr_t exit_point, void *arch_info)
int xtensa_resume(struct target *target, int current, target_addr_t address, int handle_breakpoints, int debug_execution)
int xtensa_watchpoint_remove(struct target *target, struct watchpoint *watchpoint)
int xtensa_write_buffer(struct target *target, target_addr_t address, uint32_t count, const uint8_t *buffer)
int xtensa_smpbreak_write(struct xtensa *xtensa, uint32_t set)
int xtensa_write_memory(struct target *target, target_addr_t address, uint32_t size, uint32_t count, const uint8_t *buffer)
int xtensa_mmu_is_enabled(struct target *target, int *enabled)
int xtensa_deassert_reset(struct target *target)
int xtensa_read_memory(struct target *target, target_addr_t address, uint32_t size, uint32_t count, uint8_t *buffer)
int xtensa_soft_reset_halt(struct target *target)
int xtensa_assert_reset(struct target *target)
int xtensa_run_algorithm(struct target *target, int num_mem_params, struct mem_param *mem_params, int num_reg_params, struct reg_param *reg_params, target_addr_t entry_point, target_addr_t exit_point, unsigned int timeout_ms, void *arch_info)
int xtensa_wait_algorithm(struct target *target, int num_mem_params, struct mem_param *mem_params, int num_reg_params, struct reg_param *reg_params, target_addr_t exit_point, unsigned int timeout_ms, void *arch_info)
Waits for an algorithm in the target.
static struct xtensa * target_to_xtensa(struct target *target)
int xtensa_dm_queue_reg_read(struct xtensa_debug_module *dm, enum xtensa_dm_reg reg, uint8_t *value)
int xtensa_dm_queue_pwr_reg_write(struct xtensa_debug_module *dm, enum xtensa_dm_pwr_reg reg, uint32_t data)
int xtensa_dm_queue_pwr_reg_read(struct xtensa_debug_module *dm, enum xtensa_dm_pwr_reg reg, uint8_t *data, uint32_t clear)
int xtensa_dm_queue_reg_write(struct xtensa_debug_module *dm, enum xtensa_dm_reg reg, uint32_t value)
int xtensa_dm_queue_enable(struct xtensa_debug_module *dm)
#define OCDDCR_RUNSTALLINEN