xtensa_debug_module.h File Reference

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Data Structures
struct	xtensa_core_status
struct	xtensa_debug_module
struct	xtensa_debug_module_config
struct	xtensa_debug_ops
struct	xtensa_dm_pwr_reg_offsets
struct	xtensa_dm_reg_offsets
struct	xtensa_perfmon_config
struct	xtensa_perfmon_result
struct	xtensa_power_ops
struct	xtensa_power_status
struct	xtensa_trace_config
struct	xtensa_trace_start_config
struct	xtensa_trace_status

Macros
#define	DEBUGCAUSE_BI   BIT(3) /* BREAK instruction encountered */
#define	DEBUGCAUSE_BN   BIT(4) /* BREAK.N instruction encountered */
#define	DEBUGCAUSE_DB   BIT(2) /* DBREAK exception */
#define	DEBUGCAUSE_DI   BIT(5) /* Debug Interrupt */
#define	DEBUGCAUSE_IB   BIT(1) /* IBREAK exception */
#define	DEBUGCAUSE_IC   BIT(0) /* ICOUNT exception */
#define	DEBUGCAUSE_VALID   BIT(31) /* Pseudo-value to trigger reread (NX only) */
#define	OCDDCR_BREAKACKITO   BIT(25)
#define	OCDDCR_BREAKINEN   BIT(16)
#define	OCDDCR_BREAKOUTEN   BIT(17)
#define	OCDDCR_BREAKOUTITO   BIT(24)
#define	OCDDCR_DEBUGINTERRUPT   BIT(1)
#define	OCDDCR_DEBUGMODEOUTEN   BIT(22)
#define	OCDDCR_DEBUGSWACTIVE   BIT(20)
#define	OCDDCR_ENABLEOCD   BIT(0)
#define	OCDDCR_INTERRUPTALLCONDS   BIT(2)
#define	OCDDCR_RUNSTALLINEN   BIT(21)
#define	OCDDCR_STEPREQUEST   BIT(3) /* NX only */
#define	OCDDSR_BREACKOUTACKITI   BIT(25)
#define	OCDDSR_BREAKINITI   BIT(26)
#define	OCDDSR_COREREADDDR   BIT(11)
#define	OCDDSR_COREWROTEDDR   BIT(10)
#define	OCDDSR_DBGMODPOWERON   BIT(31)
#define	OCDDSR_DEBUGINTBREAK   BIT(20)
#define	OCDDSR_DEBUGINTHOST   BIT(21)
#define	OCDDSR_DEBUGINTTRAX   BIT(22)
#define	OCDDSR_DEBUGPENDBREAK   BIT(16)
#define	OCDDSR_DEBUGPENDHOST   BIT(17)
#define	OCDDSR_DEBUGPENDTRAX   BIT(18)
#define	OCDDSR_EXECBUSY   BIT(2)
#define	OCDDSR_EXECDONE   BIT(0)
#define	OCDDSR_EXECEXCEPTION   BIT(1)
#define	OCDDSR_EXECOVERRUN   BIT(3)
#define	OCDDSR_HOSTREADDDR   BIT(15)
#define	OCDDSR_HOSTWROTEDDR   BIT(14)
#define	OCDDSR_RUNSTALLSAMPLE   BIT(24)
#define	OCDDSR_RUNSTALLTOGGLE   BIT(23)
#define	OCDDSR_STOPCAUSE   (0xF << 5) /* NX only */
#define	OCDDSR_STOPCAUSE_B   (6) /* SW breakpoint (BREAK instruction) */
#define	OCDDSR_STOPCAUSE_B1   (4) /* SW breakpoint (BREAK.1 instruction) */
#define	OCDDSR_STOPCAUSE_BN   (5) /* SW breakpoint (BREAK.N instruction) */
#define	OCDDSR_STOPCAUSE_DB0   (8) /* HW watchpoint (DBREAK0 match) */
#define	OCDDSR_STOPCAUSE_DB1   (9) /* HW watchpoint (DBREAK0 match) */
#define	OCDDSR_STOPCAUSE_DI   (0) /* Debug Interrupt */
#define	OCDDSR_STOPCAUSE_IB   (2) /* HW breakpoint (IBREAKn match) */
#define	OCDDSR_STOPCAUSE_SHIFT   (5) /* NX only */
#define	OCDDSR_STOPCAUSE_SS   (1) /* Single-step completed */
#define	OCDDSR_STOPPED   BIT(4)
#define	PCMATCHCTRL_PCML_MASK   0x1F
#define	PCMATCHCTRL_PCML_SHIFT   0 /* Amount of lower bits to ignore in pc trigger register */
#define	PCMATCHCTRL_PCMS
#define	PWRCTL_CORERESET(x)   (((x)->dbg_mod.dap) ? BIT(16) : BIT(4))
#define	PWRCTL_COREWAKEUP(x)   (((x)->dbg_mod.dap) ? BIT(0) : BIT(0))
#define	PWRCTL_DEBUGRESET(x)   (((x)->dbg_mod.dap) ? BIT(28) : BIT(6))
#define	PWRCTL_DEBUGWAKEUP(x)   (((x)->dbg_mod.dap) ? BIT(12) : BIT(2))
#define	PWRCTL_JTAGDEBUGUSE(x)   (((x)->dbg_mod.dap) ? (0) : BIT(7))
#define	PWRCTL_MEMWAKEUP(x)   (((x)->dbg_mod.dap) ? BIT(8) : BIT(1))
#define	PWRSTAT_COREDOMAINON(x)   (((x)->dbg_mod.dap) ? BIT(0) : BIT(0))
#define	PWRSTAT_CORESTILLNEEDED(x)   (((x)->dbg_mod.dap) ? BIT(4) : BIT(3))
#define	PWRSTAT_COREWASRESET(x)   (PWRSTAT_COREWASRESET_DM(&((x)->dbg_mod)))
#define	PWRSTAT_COREWASRESET_DM(d)   (((d)->dap) ? BIT(16) : BIT(4))
#define	PWRSTAT_DEBUGDOMAINON(x)   (((x)->dbg_mod.dap) ? BIT(12) : BIT(2))
#define	PWRSTAT_DEBUGWASRESET(x)   (PWRSTAT_DEBUGWASRESET_DM(&((x)->dbg_mod)))
#define	PWRSTAT_DEBUGWASRESET_DM(d)   (((d)->dap) ? BIT(28) : BIT(6))
#define	PWRSTAT_MEMDOMAINON(x)   (((x)->dbg_mod.dap) ? BIT(8) : BIT(1))
#define	TRAXADDR_TADDR_MASK   0x1FFFFF /* Actually is only as big as the trace buffer size max addr. */
#define	TRAXADDR_TADDR_SHIFT   0 /* Trax memory address, in 32-bit words. */
#define	TRAXADDR_TWRAP_MASK   0x3FF
#define	TRAXADDR_TWRAP_SHIFT   21 /* Amount of times TADDR has overflown */
#define	TRAXADDR_TWSAT   BIT(31) /* 1 if TWRAP has overflown, clear by disabling tren.*/
#define	TRAXCTRL_ATEN   BIT(31) /* ATB interface enable */
#define	TRAXCTRL_ATID_MASK   0x7F /* ARB source ID */
#define	TRAXCTRL_ATID_SHIFT   24
#define	TRAXCTRL_CNTU
#define	TRAXCTRL_CTIEN   BIT(5) /* Cross-trigger enable */
#define	TRAXCTRL_CTOWS   BIT(21) /* Cross-trigger Out enabled when trace stop completes */
#define	TRAXCTRL_CTOWT   BIT(20) /* Cross-trigger Out enabled when stop triggered */
#define	TRAXCTRL_ITATV   BIT(24) /* replaces ATID when in integration mode: ATVALID output */
#define	TRAXCTRL_ITCTIA   BIT(23) /* Integration mode: cross-trigger ack */
#define	TRAXCTRL_ITCTO   BIT(22) /* Integration mode: cross-trigger output */
#define	TRAXCTRL_PCMEN   BIT(2) /* PC match enable */
#define	TRAXCTRL_PTIEN   BIT(4) /* Processor-trigger enable */
#define	TRAXCTRL_PTOWS   BIT(17) /* Processor Trigger Out (OCD halt) enabled when trace stop completes */
#define	TRAXCTRL_PTOWT   BIT(16) /* Processor Trigger Out (OCD halt) enabled when stop triggered */
#define	TRAXCTRL_SMPER_MASK   0x07 /* Synchronization message period */
#define	TRAXCTRL_SMPER_SHIFT   12 /* Send sync every 2^(9-smper) messages. 7=reserved, 0=no sync msg */
#define	TRAXCTRL_TMEN   BIT(7) /* Tracemem Enable. Always set. */
#define	TRAXCTRL_TREN   BIT(0) /* Trace enable. Tracing starts on 0->1 */
#define	TRAXCTRL_TRSTP   BIT(1) /* Trace Stop. Make 1 to stop trace. */
#define	TRAXCTRL_TSEN   BIT(11) /* Undocumented/deprecated? */
#define	TRAXID_PRODNO_MASK   0xf
#define	TRAXID_PRODNO_SHIFT   28
#define	TRAXID_PRODNO_TRAX   0 /* TRAXID.PRODNO value for TRAX module */
#define	TRAXSTAT_CTITG   BIT(5) /* Stop trigger caused by Cross-Trigger Input. Clears on TREN 1->0 */
#define	TRAXSTAT_CTO   BIT(17) /* Cross-Trigger Output: current value */
#define	TRAXSTAT_ITATR   BIT(24) /* ATREADY Input: current value */
#define	TRAXSTAT_ITCTI   BIT(23) /* Cross-Trigger Input: current value */
#define	TRAXSTAT_ITCTOA   BIT(22) /* Cross-Trigger Out Ack: current value */
#define	TRAXSTAT_MEMSZ_MASK   0x1F
#define	TRAXSTAT_MEMSZ_SHIFT   8 /* Traceram size inducator. Usable trace ram is 2^MEMSZ bytes. */
#define	TRAXSTAT_PCMTG   BIT(2) /* Stop trigger caused by PC match. Clears on TREN 1->0 */
#define	TRAXSTAT_PJTR   BIT(3) /* JTAG transaction result. 1=err in preceding jtag transaction. */
#define	TRAXSTAT_PTITG   BIT(4) /* Stop trigger caused by Processor Trigger Input.Clears on TREN 1->0 */
#define	TRAXSTAT_PTO   BIT(16) /* Processor Trigger Output: current value */
#define	TRAXSTAT_TRACT   BIT(0) /* Trace active flag. */
#define	TRAXSTAT_TRIG   BIT(1) /* Trace stop trigger. Clears on TREN 1->0 */
#define	XTENSA_DM_APB_ALIGN   0x4000
#define	XTENSA_DM_PWR_REG_OFFSETS
#define	XTENSA_DM_REG_OFFSETS
#define	XTENSA_MAX_PERF_COUNTERS   2
#define	XTENSA_MAX_PERF_MASK   0xffff
#define	XTENSA_MAX_PERF_SELECT   32
#define	XTENSA_STOPMASK_DISABLED   UINT32_MAX

Typedefs
typedef uint32_t	xtensa_dsr_t
typedef uint32_t	xtensa_ocdid_t
typedef uint32_t	xtensa_pwrstat_t
typedef uint32_t	xtensa_traxstat_t

Enumerations
enum	xtensa_dm_pwr_reg { XDMREG_PWRCTL = 0x00 , XDMREG_PWRSTAT , XDMREG_PWRNUM }
enum	xtensa_dm_reg {   XDMREG_TRAXID = 0x00 , XDMREG_TRAXCTRL , XDMREG_TRAXSTAT , XDMREG_TRAXDATA ,   XDMREG_TRAXADDR , XDMREG_TRIGGERPC , XDMREG_PCMATCHCTRL , XDMREG_DELAYCNT ,   XDMREG_MEMADDRSTART , XDMREG_MEMADDREND , XDMREG_DEBUGPC , XDMREG_EXTTIMELO ,   XDMREG_EXTTIMEHI , XDMREG_TRAXRSVD48 , XDMREG_TRAXRSVD4C , XDMREG_TRAXRSVD50 ,   XDMREG_TRAXRSVD54 , XDMREG_TRAXRSVD58 , XDMREG_TRAXRSVD5C , XDMREG_TRAXRSVD60 ,   XDMREG_TRAXRSVD64 , XDMREG_TRAXRSVD68 , XDMREG_TRAXRSVD6C , XDMREG_TRAXRSVD70 ,   XDMREG_TRAXRSVD74 , XDMREG_CONFIGID0 , XDMREG_CONFIGID1 , XDMREG_PMG ,   XDMREG_INTPC , XDMREG_PM0 , XDMREG_PM1 , XDMREG_PM2 ,   XDMREG_PM3 , XDMREG_PM4 , XDMREG_PM5 , XDMREG_PM6 ,   XDMREG_PM7 , XDMREG_PMCTRL0 , XDMREG_PMCTRL1 , XDMREG_PMCTRL2 ,   XDMREG_PMCTRL3 , XDMREG_PMCTRL4 , XDMREG_PMCTRL5 , XDMREG_PMCTRL6 ,   XDMREG_PMCTRL7 , XDMREG_PMSTAT0 , XDMREG_PMSTAT1 , XDMREG_PMSTAT2 ,   XDMREG_PMSTAT3 , XDMREG_PMSTAT4 , XDMREG_PMSTAT5 , XDMREG_PMSTAT6 ,   XDMREG_PMSTAT7 , XDMREG_OCDID , XDMREG_DCRCLR , XDMREG_DCRSET ,   XDMREG_DSR , XDMREG_DDR , XDMREG_DDREXEC , XDMREG_DIR0EXEC ,   XDMREG_DIR0 , XDMREG_DIR1 , XDMREG_DIR2 , XDMREG_DIR3 ,   XDMREG_DIR4 , XDMREG_DIR5 , XDMREG_DIR6 , XDMREG_DIR7 ,   XDMREG_ERISTAT , XDMREG_ITCTRL , XDMREG_CLAIMSET , XDMREG_CLAIMCLR ,   XDMREG_LOCKACCESS , XDMREG_LOCKSTATUS , XDMREG_AUTHSTATUS , XDMREG_DEVID ,   XDMREG_DEVTYPE , XDMREG_PERID4 , XDMREG_PERID5 , XDMREG_PERID6 ,   XDMREG_PERID7 , XDMREG_PERID0 , XDMREG_PERID1 , XDMREG_PERID2 ,   XDMREG_PERID3 , XDMREG_COMPID0 , XDMREG_COMPID1 , XDMREG_COMPID2 ,   XDMREG_COMPID3 , XDMREG_NUM }

Functions
static bool	xtensa_dm_core_is_stalled (struct xtensa_debug_module *dm)
int	xtensa_dm_core_status_check (struct xtensa_debug_module *dm)
int	xtensa_dm_core_status_clear (struct xtensa_debug_module *dm, xtensa_dsr_t bits)
static xtensa_dsr_t	xtensa_dm_core_status_get (struct xtensa_debug_module *dm)
int	xtensa_dm_core_status_read (struct xtensa_debug_module *dm)
static bool	xtensa_dm_core_was_reset (struct xtensa_debug_module *dm)
void	xtensa_dm_deinit (struct xtensa_debug_module *dm)
static xtensa_ocdid_t	xtensa_dm_device_id_get (struct xtensa_debug_module *dm)
int	xtensa_dm_device_id_read (struct xtensa_debug_module *dm)
int	xtensa_dm_examine (struct xtensa_debug_module *dm)
int	xtensa_dm_init (struct xtensa_debug_module *dm, const struct xtensa_debug_module_config *cfg)
static bool	xtensa_dm_is_online (struct xtensa_debug_module *dm)
static bool	xtensa_dm_is_powered (struct xtensa_debug_module *dm)
int	xtensa_dm_perfmon_dump (struct xtensa_debug_module *dm, int counter_id, struct xtensa_perfmon_result *out_result)
int	xtensa_dm_perfmon_enable (struct xtensa_debug_module *dm, int counter_id, const struct xtensa_perfmon_config *config)
int	xtensa_dm_poll (struct xtensa_debug_module *dm)
static void	xtensa_dm_power_status_cache (struct xtensa_debug_module *dm)
static void	xtensa_dm_power_status_cache_reset (struct xtensa_debug_module *dm)
static xtensa_pwrstat_t	xtensa_dm_power_status_get (struct xtensa_debug_module *dm)
int	xtensa_dm_power_status_read (struct xtensa_debug_module *dm, uint32_t clear)
int	xtensa_dm_queue_enable (struct xtensa_debug_module *dm)
static int	xtensa_dm_queue_execute (struct xtensa_debug_module *dm)
int	xtensa_dm_queue_pwr_reg_read (struct xtensa_debug_module *dm, enum xtensa_dm_pwr_reg reg, uint8_t *data, uint32_t clear)
int	xtensa_dm_queue_pwr_reg_write (struct xtensa_debug_module *dm, enum xtensa_dm_pwr_reg reg, uint32_t data)
int	xtensa_dm_queue_reg_read (struct xtensa_debug_module *dm, enum xtensa_dm_reg reg, uint8_t *value)
int	xtensa_dm_queue_reg_write (struct xtensa_debug_module *dm, enum xtensa_dm_reg reg, uint32_t value)
static void	xtensa_dm_queue_tdi_idle (struct xtensa_debug_module *dm)
int	xtensa_dm_read (struct xtensa_debug_module *dm, uint32_t addr, uint32_t *val)
static bool	xtensa_dm_tap_was_reset (struct xtensa_debug_module *dm)
int	xtensa_dm_trace_config_read (struct xtensa_debug_module *dm, struct xtensa_trace_config *config)
int	xtensa_dm_trace_data_read (struct xtensa_debug_module *dm, uint8_t *dest, uint32_t size)
int	xtensa_dm_trace_start (struct xtensa_debug_module *dm, struct xtensa_trace_start_config *cfg)
int	xtensa_dm_trace_status_read (struct xtensa_debug_module *dm, struct xtensa_trace_status *status)
int	xtensa_dm_trace_stop (struct xtensa_debug_module *dm, bool pto_enable)
int	xtensa_dm_write (struct xtensa_debug_module *dm, uint32_t addr, uint32_t val)

Macro Definition Documentation

DEBUGCAUSE_BI

#define DEBUGCAUSE_BI   BIT(3) /* BREAK instruction encountered */

Definition at line 329 of file xtensa_debug_module.h.

DEBUGCAUSE_BN

#define DEBUGCAUSE_BN   BIT(4) /* BREAK.N instruction encountered */

Definition at line 330 of file xtensa_debug_module.h.

DEBUGCAUSE_DB

#define DEBUGCAUSE_DB   BIT(2) /* DBREAK exception */

Definition at line 328 of file xtensa_debug_module.h.

DEBUGCAUSE_DI

#define DEBUGCAUSE_DI   BIT(5) /* Debug Interrupt */

Definition at line 331 of file xtensa_debug_module.h.

DEBUGCAUSE_IB

#define DEBUGCAUSE_IB   BIT(1) /* IBREAK exception */

Definition at line 327 of file xtensa_debug_module.h.

DEBUGCAUSE_IC

#define DEBUGCAUSE_IC   BIT(0) /* ICOUNT exception */

Definition at line 326 of file xtensa_debug_module.h.

DEBUGCAUSE_VALID

#define DEBUGCAUSE_VALID   BIT(31) /* Pseudo-value to trigger reread (NX only) */

Definition at line 332 of file xtensa_debug_module.h.

OCDDCR_BREAKACKITO

#define OCDDCR_BREAKACKITO   BIT(25)

Definition at line 290 of file xtensa_debug_module.h.

OCDDCR_BREAKINEN

#define OCDDCR_BREAKINEN   BIT(16)

Definition at line 284 of file xtensa_debug_module.h.

OCDDCR_BREAKOUTEN

#define OCDDCR_BREAKOUTEN   BIT(17)

Definition at line 285 of file xtensa_debug_module.h.

OCDDCR_BREAKOUTITO

#define OCDDCR_BREAKOUTITO   BIT(24)

Definition at line 289 of file xtensa_debug_module.h.

OCDDCR_DEBUGINTERRUPT

#define OCDDCR_DEBUGINTERRUPT   BIT(1)

Definition at line 281 of file xtensa_debug_module.h.

OCDDCR_DEBUGMODEOUTEN

#define OCDDCR_DEBUGMODEOUTEN   BIT(22)

Definition at line 288 of file xtensa_debug_module.h.

OCDDCR_DEBUGSWACTIVE

#define OCDDCR_DEBUGSWACTIVE   BIT(20)

Definition at line 286 of file xtensa_debug_module.h.

OCDDCR_ENABLEOCD

#define OCDDCR_ENABLEOCD   BIT(0)

Definition at line 280 of file xtensa_debug_module.h.

OCDDCR_INTERRUPTALLCONDS

#define OCDDCR_INTERRUPTALLCONDS   BIT(2)

Definition at line 282 of file xtensa_debug_module.h.

OCDDCR_RUNSTALLINEN

#define OCDDCR_RUNSTALLINEN   BIT(21)

Definition at line 287 of file xtensa_debug_module.h.

OCDDCR_STEPREQUEST

#define OCDDCR_STEPREQUEST   BIT(3) /* NX only */

Definition at line 283 of file xtensa_debug_module.h.

OCDDSR_BREACKOUTACKITI

#define OCDDSR_BREACKOUTACKITI   BIT(25)

Definition at line 311 of file xtensa_debug_module.h.

OCDDSR_BREAKINITI

#define OCDDSR_BREAKINITI   BIT(26)

Definition at line 312 of file xtensa_debug_module.h.

OCDDSR_COREREADDDR

#define OCDDSR_COREREADDDR   BIT(11)

Definition at line 300 of file xtensa_debug_module.h.

OCDDSR_COREWROTEDDR

#define OCDDSR_COREWROTEDDR   BIT(10)

Definition at line 299 of file xtensa_debug_module.h.

OCDDSR_DBGMODPOWERON

#define OCDDSR_DBGMODPOWERON   BIT(31)

Definition at line 313 of file xtensa_debug_module.h.

OCDDSR_DEBUGINTBREAK

#define OCDDSR_DEBUGINTBREAK   BIT(20)

Definition at line 306 of file xtensa_debug_module.h.

OCDDSR_DEBUGINTHOST

#define OCDDSR_DEBUGINTHOST   BIT(21)

Definition at line 307 of file xtensa_debug_module.h.

OCDDSR_DEBUGINTTRAX

#define OCDDSR_DEBUGINTTRAX   BIT(22)

Definition at line 308 of file xtensa_debug_module.h.

OCDDSR_DEBUGPENDBREAK

#define OCDDSR_DEBUGPENDBREAK   BIT(16)

Definition at line 303 of file xtensa_debug_module.h.

OCDDSR_DEBUGPENDHOST

#define OCDDSR_DEBUGPENDHOST   BIT(17)

Definition at line 304 of file xtensa_debug_module.h.

OCDDSR_DEBUGPENDTRAX

#define OCDDSR_DEBUGPENDTRAX   BIT(18)

Definition at line 305 of file xtensa_debug_module.h.

OCDDSR_EXECBUSY

#define OCDDSR_EXECBUSY   BIT(2)

Definition at line 294 of file xtensa_debug_module.h.

OCDDSR_EXECDONE

#define OCDDSR_EXECDONE   BIT(0)

Definition at line 292 of file xtensa_debug_module.h.

OCDDSR_EXECEXCEPTION

#define OCDDSR_EXECEXCEPTION   BIT(1)

Definition at line 293 of file xtensa_debug_module.h.

OCDDSR_EXECOVERRUN

#define OCDDSR_EXECOVERRUN   BIT(3)

Definition at line 295 of file xtensa_debug_module.h.

OCDDSR_HOSTREADDDR

#define OCDDSR_HOSTREADDDR   BIT(15)

Definition at line 302 of file xtensa_debug_module.h.

OCDDSR_HOSTWROTEDDR

#define OCDDSR_HOSTWROTEDDR   BIT(14)

Definition at line 301 of file xtensa_debug_module.h.

OCDDSR_RUNSTALLSAMPLE

#define OCDDSR_RUNSTALLSAMPLE   BIT(24)

Definition at line 310 of file xtensa_debug_module.h.

OCDDSR_RUNSTALLTOGGLE

#define OCDDSR_RUNSTALLTOGGLE   BIT(23)

Definition at line 309 of file xtensa_debug_module.h.

OCDDSR_STOPCAUSE

#define OCDDSR_STOPCAUSE   (0xF << 5) /* NX only */

Definition at line 297 of file xtensa_debug_module.h.

OCDDSR_STOPCAUSE_B

#define OCDDSR_STOPCAUSE_B   (6) /* SW breakpoint (BREAK instruction) */

Definition at line 321 of file xtensa_debug_module.h.

OCDDSR_STOPCAUSE_B1

#define OCDDSR_STOPCAUSE_B1   (4) /* SW breakpoint (BREAK.1 instruction) */

Definition at line 319 of file xtensa_debug_module.h.

OCDDSR_STOPCAUSE_BN

#define OCDDSR_STOPCAUSE_BN   (5) /* SW breakpoint (BREAK.N instruction) */

Definition at line 320 of file xtensa_debug_module.h.

OCDDSR_STOPCAUSE_DB0

#define OCDDSR_STOPCAUSE_DB0   (8) /* HW watchpoint (DBREAK0 match) */

Definition at line 322 of file xtensa_debug_module.h.

OCDDSR_STOPCAUSE_DB1

#define OCDDSR_STOPCAUSE_DB1   (9) /* HW watchpoint (DBREAK0 match) */

Definition at line 323 of file xtensa_debug_module.h.

OCDDSR_STOPCAUSE_DI

#define OCDDSR_STOPCAUSE_DI   (0) /* Debug Interrupt */

Definition at line 316 of file xtensa_debug_module.h.

OCDDSR_STOPCAUSE_IB

#define OCDDSR_STOPCAUSE_IB   (2) /* HW breakpoint (IBREAKn match) */

Definition at line 318 of file xtensa_debug_module.h.

OCDDSR_STOPCAUSE_SHIFT

#define OCDDSR_STOPCAUSE_SHIFT   (5) /* NX only */

Definition at line 298 of file xtensa_debug_module.h.

OCDDSR_STOPCAUSE_SS

#define OCDDSR_STOPCAUSE_SS   (1) /* Single-step completed */

Definition at line 317 of file xtensa_debug_module.h.

OCDDSR_STOPPED

#define OCDDSR_STOPPED   BIT(4)

Definition at line 296 of file xtensa_debug_module.h.

PCMATCHCTRL_PCML_MASK

#define PCMATCHCTRL_PCML_MASK   0x1F

Definition at line 381 of file xtensa_debug_module.h.

PCMATCHCTRL_PCML_SHIFT

#define PCMATCHCTRL_PCML_SHIFT   0 /* Amount of lower bits to ignore in pc trigger register */

Definition at line 380 of file xtensa_debug_module.h.

PCMATCHCTRL_PCMS

#define PCMATCHCTRL_PCMS

Value:

                                             BIT(31)    /* PC Match Sense, 0-match when procs PC is in-range, 1-match when
                                             * out-of-range */

Definition at line 382 of file xtensa_debug_module.h.

PWRCTL_CORERESET

#define PWRCTL_CORERESET

(

x

)

(((x)->dbg_mod.dap) ? BIT(16) : BIT(4))

Definition at line 51 of file xtensa_debug_module.h.

PWRCTL_COREWAKEUP

#define PWRCTL_COREWAKEUP

(

x

)

(((x)->dbg_mod.dap) ? BIT(0) : BIT(0))

Definition at line 54 of file xtensa_debug_module.h.

PWRCTL_DEBUGRESET

#define PWRCTL_DEBUGRESET

(

x

)

(((x)->dbg_mod.dap) ? BIT(28) : BIT(6))

Definition at line 50 of file xtensa_debug_module.h.

PWRCTL_DEBUGWAKEUP

#define PWRCTL_DEBUGWAKEUP

(

x

)

(((x)->dbg_mod.dap) ? BIT(12) : BIT(2))

Definition at line 52 of file xtensa_debug_module.h.

PWRCTL_JTAGDEBUGUSE

#define PWRCTL_JTAGDEBUGUSE

(

x

)

(((x)->dbg_mod.dap) ? (0) : BIT(7))

Definition at line 49 of file xtensa_debug_module.h.

PWRCTL_MEMWAKEUP

#define PWRCTL_MEMWAKEUP

(

x

)

(((x)->dbg_mod.dap) ? BIT(8) : BIT(1))

Definition at line 53 of file xtensa_debug_module.h.

PWRSTAT_COREDOMAINON

#define PWRSTAT_COREDOMAINON

(

x

)

(((x)->dbg_mod.dap) ? BIT(0) : BIT(0))

Definition at line 63 of file xtensa_debug_module.h.

PWRSTAT_CORESTILLNEEDED

#define PWRSTAT_CORESTILLNEEDED

(

x

)

(((x)->dbg_mod.dap) ? BIT(4) : BIT(3))

Definition at line 60 of file xtensa_debug_module.h.

PWRSTAT_COREWASRESET

#define PWRSTAT_COREWASRESET

(

x

)

(PWRSTAT_COREWASRESET_DM(&((x)->dbg_mod)))

Definition at line 59 of file xtensa_debug_module.h.

PWRSTAT_COREWASRESET_DM

#define PWRSTAT_COREWASRESET_DM

(

d

)

(((d)->dap) ? BIT(16) : BIT(4))

Definition at line 57 of file xtensa_debug_module.h.

PWRSTAT_DEBUGDOMAINON

#define PWRSTAT_DEBUGDOMAINON

(

x

)

(((x)->dbg_mod.dap) ? BIT(12) : BIT(2))

Definition at line 61 of file xtensa_debug_module.h.

PWRSTAT_DEBUGWASRESET

#define PWRSTAT_DEBUGWASRESET

(

x

)

(PWRSTAT_DEBUGWASRESET_DM(&((x)->dbg_mod)))

Definition at line 58 of file xtensa_debug_module.h.

PWRSTAT_DEBUGWASRESET_DM

#define PWRSTAT_DEBUGWASRESET_DM

(

d

)

(((d)->dap) ? BIT(28) : BIT(6))

Definition at line 56 of file xtensa_debug_module.h.

PWRSTAT_MEMDOMAINON

#define PWRSTAT_MEMDOMAINON

(

x

)

(((x)->dbg_mod.dap) ? BIT(8) : BIT(1))

Definition at line 62 of file xtensa_debug_module.h.

TRAXADDR_TADDR_MASK

#define TRAXADDR_TADDR_MASK   0x1FFFFF /* Actually is only as big as the trace buffer size max addr. */

Definition at line 375 of file xtensa_debug_module.h.

TRAXADDR_TADDR_SHIFT

#define TRAXADDR_TADDR_SHIFT   0 /* Trax memory address, in 32-bit words. */

Definition at line 374 of file xtensa_debug_module.h.

TRAXADDR_TWRAP_MASK

#define TRAXADDR_TWRAP_MASK   0x3FF

Definition at line 377 of file xtensa_debug_module.h.

TRAXADDR_TWRAP_SHIFT

#define TRAXADDR_TWRAP_SHIFT   21 /* Amount of times TADDR has overflown */

Definition at line 376 of file xtensa_debug_module.h.

TRAXADDR_TWSAT

#define TRAXADDR_TWSAT   BIT(31) /* 1 if TWRAP has overflown, clear by disabling tren.*/

Definition at line 378 of file xtensa_debug_module.h.

TRAXCTRL_ATEN

#define TRAXCTRL_ATEN   BIT(31) /* ATB interface enable */

Definition at line 358 of file xtensa_debug_module.h.

TRAXCTRL_ATID_MASK

#define TRAXCTRL_ATID_MASK   0x7F /* ARB source ID */

Definition at line 356 of file xtensa_debug_module.h.

TRAXCTRL_ATID_SHIFT

#define TRAXCTRL_ATID_SHIFT   24

Definition at line 357 of file xtensa_debug_module.h.

TRAXCTRL_CNTU

#define TRAXCTRL_CNTU

Value:

                                             BIT(9) /* Post-stop-trigger countdown units; selects when DelayCount-- happens.
                                             * 0 - every 32-bit word written to tracemem, 1 - every cpu instruction */

Definition at line 345 of file xtensa_debug_module.h.

TRAXCTRL_CTIEN

#define TRAXCTRL_CTIEN   BIT(5) /* Cross-trigger enable */

Definition at line 343 of file xtensa_debug_module.h.

TRAXCTRL_CTOWS

#define TRAXCTRL_CTOWS   BIT(21) /* Cross-trigger Out enabled when trace stop completes */

Definition at line 352 of file xtensa_debug_module.h.

TRAXCTRL_CTOWT

#define TRAXCTRL_CTOWT   BIT(20) /* Cross-trigger Out enabled when stop triggered */

Definition at line 351 of file xtensa_debug_module.h.

TRAXCTRL_ITATV

#define TRAXCTRL_ITATV   BIT(24) /* replaces ATID when in integration mode: ATVALID output */

Definition at line 355 of file xtensa_debug_module.h.

TRAXCTRL_ITCTIA

#define TRAXCTRL_ITCTIA   BIT(23) /* Integration mode: cross-trigger ack */

Definition at line 354 of file xtensa_debug_module.h.

TRAXCTRL_ITCTO

#define TRAXCTRL_ITCTO   BIT(22) /* Integration mode: cross-trigger output */

Definition at line 353 of file xtensa_debug_module.h.

TRAXCTRL_PCMEN

#define TRAXCTRL_PCMEN   BIT(2) /* PC match enable */

Definition at line 341 of file xtensa_debug_module.h.

TRAXCTRL_PTIEN

#define TRAXCTRL_PTIEN   BIT(4) /* Processor-trigger enable */

Definition at line 342 of file xtensa_debug_module.h.

TRAXCTRL_PTOWS

#define TRAXCTRL_PTOWS   BIT(17) /* Processor Trigger Out (OCD halt) enabled when trace stop completes */

Definition at line 350 of file xtensa_debug_module.h.

TRAXCTRL_PTOWT

#define TRAXCTRL_PTOWT   BIT(16) /* Processor Trigger Out (OCD halt) enabled when stop triggered */

Definition at line 349 of file xtensa_debug_module.h.

TRAXCTRL_SMPER_MASK

#define TRAXCTRL_SMPER_MASK   0x07 /* Synchronization message period */

Definition at line 348 of file xtensa_debug_module.h.

TRAXCTRL_SMPER_SHIFT

#define TRAXCTRL_SMPER_SHIFT   12 /* Send sync every 2^(9-smper) messages. 7=reserved, 0=no sync msg */

Definition at line 347 of file xtensa_debug_module.h.

TRAXCTRL_TMEN

#define TRAXCTRL_TMEN   BIT(7) /* Tracemem Enable. Always set. */

Definition at line 344 of file xtensa_debug_module.h.

TRAXCTRL_TREN

#define TRAXCTRL_TREN   BIT(0) /* Trace enable. Tracing starts on 0->1 */

Definition at line 339 of file xtensa_debug_module.h.

TRAXCTRL_TRSTP

#define TRAXCTRL_TRSTP   BIT(1) /* Trace Stop. Make 1 to stop trace. */

Definition at line 340 of file xtensa_debug_module.h.

TRAXCTRL_TSEN

#define TRAXCTRL_TSEN   BIT(11) /* Undocumented/deprecated? */

Definition at line 346 of file xtensa_debug_module.h.

TRAXID_PRODNO_MASK

#define TRAXID_PRODNO_MASK   0xf

Definition at line 337 of file xtensa_debug_module.h.

TRAXID_PRODNO_SHIFT

#define TRAXID_PRODNO_SHIFT   28

Definition at line 336 of file xtensa_debug_module.h.

TRAXID_PRODNO_TRAX

#define TRAXID_PRODNO_TRAX   0 /* TRAXID.PRODNO value for TRAX module */

Definition at line 335 of file xtensa_debug_module.h.

TRAXSTAT_CTITG

#define TRAXSTAT_CTITG   BIT(5) /* Stop trigger caused by Cross-Trigger Input. Clears on TREN 1->0 */

Definition at line 365 of file xtensa_debug_module.h.

TRAXSTAT_CTO

#define TRAXSTAT_CTO   BIT(17) /* Cross-Trigger Output: current value */

Definition at line 369 of file xtensa_debug_module.h.

TRAXSTAT_ITATR

#define TRAXSTAT_ITATR   BIT(24) /* ATREADY Input: current value */

Definition at line 372 of file xtensa_debug_module.h.

TRAXSTAT_ITCTI

#define TRAXSTAT_ITCTI   BIT(23) /* Cross-Trigger Input: current value */

Definition at line 371 of file xtensa_debug_module.h.

TRAXSTAT_ITCTOA

#define TRAXSTAT_ITCTOA   BIT(22) /* Cross-Trigger Out Ack: current value */

Definition at line 370 of file xtensa_debug_module.h.

TRAXSTAT_MEMSZ_MASK

#define TRAXSTAT_MEMSZ_MASK   0x1F

Definition at line 367 of file xtensa_debug_module.h.

TRAXSTAT_MEMSZ_SHIFT

#define TRAXSTAT_MEMSZ_SHIFT   8 /* Traceram size inducator. Usable trace ram is 2^MEMSZ bytes. */

Definition at line 366 of file xtensa_debug_module.h.

TRAXSTAT_PCMTG

#define TRAXSTAT_PCMTG   BIT(2) /* Stop trigger caused by PC match. Clears on TREN 1->0 */

Definition at line 362 of file xtensa_debug_module.h.

TRAXSTAT_PJTR

#define TRAXSTAT_PJTR   BIT(3) /* JTAG transaction result. 1=err in preceding jtag transaction. */

Definition at line 363 of file xtensa_debug_module.h.

TRAXSTAT_PTITG

#define TRAXSTAT_PTITG   BIT(4) /* Stop trigger caused by Processor Trigger Input.Clears on TREN 1->0 */

Definition at line 364 of file xtensa_debug_module.h.

TRAXSTAT_PTO

#define TRAXSTAT_PTO   BIT(16) /* Processor Trigger Output: current value */

Definition at line 368 of file xtensa_debug_module.h.

TRAXSTAT_TRACT

#define TRAXSTAT_TRACT   BIT(0) /* Trace active flag. */

Definition at line 360 of file xtensa_debug_module.h.

TRAXSTAT_TRIG

#define TRAXSTAT_TRIG   BIT(1) /* Trace stop trigger. Clears on TREN 1->0 */

Definition at line 361 of file xtensa_debug_module.h.

XTENSA_DM_APB_ALIGN

#define XTENSA_DM_APB_ALIGN   0x4000

Definition at line 277 of file xtensa_debug_module.h.

XTENSA_DM_PWR_REG_OFFSETS

#define XTENSA_DM_PWR_REG_OFFSETS

Value:

    {               \
    /* Power/Reset Registers */                     \
    { .apb = 0x3020 },      /* XDMREG_PWRCTL */     \
    { .apb = 0x3024 },      /* XDMREG_PWRSTAT */    \
}

Definition at line 32 of file xtensa_debug_module.h.

XTENSA_DM_REG_OFFSETS

#define XTENSA_DM_REG_OFFSETS

Definition at line 176 of file xtensa_debug_module.h.

XTENSA_MAX_PERF_COUNTERS

#define XTENSA_MAX_PERF_COUNTERS   2

Definition at line 384 of file xtensa_debug_module.h.

XTENSA_MAX_PERF_MASK

#define XTENSA_MAX_PERF_MASK   0xffff

Definition at line 386 of file xtensa_debug_module.h.

XTENSA_MAX_PERF_SELECT

#define XTENSA_MAX_PERF_SELECT   32

Definition at line 385 of file xtensa_debug_module.h.

XTENSA_STOPMASK_DISABLED

#define XTENSA_STOPMASK_DISABLED   UINT32_MAX

Definition at line 388 of file xtensa_debug_module.h.

Typedef Documentation

xtensa_dsr_t

typedef uint32_t xtensa_dsr_t

Definition at line 415 of file xtensa_debug_module.h.

xtensa_ocdid_t

typedef uint32_t xtensa_ocdid_t

Definition at line 414 of file xtensa_debug_module.h.

xtensa_pwrstat_t

typedef uint32_t xtensa_pwrstat_t

Definition at line 413 of file xtensa_debug_module.h.

xtensa_traxstat_t

typedef uint32_t xtensa_traxstat_t

Definition at line 416 of file xtensa_debug_module.h.

Enumeration Type Documentation

xtensa_dm_pwr_reg

enum xtensa_dm_pwr_reg

Enumerator
XDMREG_PWRCTL
XDMREG_PWRSTAT
XDMREG_PWRNUM

Definition at line 20 of file xtensa_debug_module.h.

xtensa_dm_reg

enum xtensa_dm_reg

Enumerator
XDMREG_TRAXID
XDMREG_TRAXCTRL
XDMREG_TRAXSTAT
XDMREG_TRAXDATA
XDMREG_TRAXADDR
XDMREG_TRIGGERPC
XDMREG_PCMATCHCTRL
XDMREG_DELAYCNT
XDMREG_MEMADDRSTART
XDMREG_MEMADDREND
XDMREG_DEBUGPC
XDMREG_EXTTIMELO
XDMREG_EXTTIMEHI
XDMREG_TRAXRSVD48
XDMREG_TRAXRSVD4C
XDMREG_TRAXRSVD50
XDMREG_TRAXRSVD54
XDMREG_TRAXRSVD58
XDMREG_TRAXRSVD5C
XDMREG_TRAXRSVD60
XDMREG_TRAXRSVD64
XDMREG_TRAXRSVD68
XDMREG_TRAXRSVD6C
XDMREG_TRAXRSVD70
XDMREG_TRAXRSVD74
XDMREG_CONFIGID0
XDMREG_CONFIGID1
XDMREG_PMG
XDMREG_INTPC
XDMREG_PM0
XDMREG_PM1
XDMREG_PM2
XDMREG_PM3
XDMREG_PM4
XDMREG_PM5
XDMREG_PM6
XDMREG_PM7
XDMREG_PMCTRL0
XDMREG_PMCTRL1
XDMREG_PMCTRL2
XDMREG_PMCTRL3
XDMREG_PMCTRL4
XDMREG_PMCTRL5
XDMREG_PMCTRL6
XDMREG_PMCTRL7
XDMREG_PMSTAT0
XDMREG_PMSTAT1
XDMREG_PMSTAT2
XDMREG_PMSTAT3
XDMREG_PMSTAT4
XDMREG_PMSTAT5
XDMREG_PMSTAT6
XDMREG_PMSTAT7
XDMREG_OCDID
XDMREG_DCRCLR
XDMREG_DCRSET
XDMREG_DSR
XDMREG_DDR
XDMREG_DDREXEC
XDMREG_DIR0EXEC
XDMREG_DIR0
XDMREG_DIR1
XDMREG_DIR2
XDMREG_DIR3
XDMREG_DIR4
XDMREG_DIR5
XDMREG_DIR6
XDMREG_DIR7
XDMREG_ERISTAT
XDMREG_ITCTRL
XDMREG_CLAIMSET
XDMREG_CLAIMCLR
XDMREG_LOCKACCESS
XDMREG_LOCKSTATUS
XDMREG_AUTHSTATUS
XDMREG_DEVID
XDMREG_DEVTYPE
XDMREG_PERID4
XDMREG_PERID5
XDMREG_PERID6
XDMREG_PERID7
XDMREG_PERID0
XDMREG_PERID1
XDMREG_PERID2
XDMREG_PERID3
XDMREG_COMPID0
XDMREG_COMPID1
XDMREG_COMPID2
XDMREG_COMPID3
XDMREG_NUM

Definition at line 66 of file xtensa_debug_module.h.

Function Documentation

xtensa_dm_core_is_stalled()

static bool xtensa_dm_core_is_stalled ( struct xtensa_debug_module *  dm )

inlinestatic

Definition at line 587 of file xtensa_debug_module.h.

Referenced by esp32_soc_reset(), and esp32s3_soc_reset().

xtensa_dm_core_status_check()

int xtensa_dm_core_status_check

(

struct xtensa_debug_module *

dm

)

xtensa_dm_core_status_clear()

int xtensa_dm_core_status_clear	(	struct xtensa_debug_module *	dm,
		xtensa_dsr_t	bits
	)

Definition at line 291 of file xtensa_debug_module.c.

References bits, xtensa_debug_module::dbg_ops, xtensa_debug_ops::queue_reg_write, XDMREG_DSR, xtensa_dm_queue_execute(), and xtensa_dm_queue_tdi_idle().

Referenced by xtensa_core_status_check(), xtensa_core_status_clear(), and xtensa_poll().

xtensa_dm_core_status_get()

static xtensa_dsr_t xtensa_dm_core_status_get ( struct xtensa_debug_module *  dm )

inlinestatic

Definition at line 547 of file xtensa_debug_module.h.

Referenced by xtensa_cause_get(), xtensa_core_status_check(), xtensa_do_step(), and xtensa_halt().

xtensa_dm_core_status_read()

int xtensa_dm_core_status_read

(

struct xtensa_debug_module *

dm

)

Definition at line 277 of file xtensa_debug_module.c.

References buf_get_u32(), xtensa_debug_module::core_status, xtensa_debug_module::dbg_ops, xtensa_core_status::dsr, ERROR_OK, xtensa_debug_ops::queue_reg_read, XDMREG_DSR, xtensa_dm_queue_enable(), xtensa_dm_queue_execute(), and xtensa_dm_queue_tdi_idle().

Referenced by xtensa_cause_get(), xtensa_core_status_check(), xtensa_do_step(), xtensa_halt(), and xtensa_poll().

xtensa_dm_core_was_reset()

static bool xtensa_dm_core_was_reset ( struct xtensa_debug_module *  dm )

inlinestatic

Definition at line 581 of file xtensa_debug_module.h.

Referenced by xtensa_poll().

xtensa_dm_deinit()

void xtensa_dm_deinit

(

struct xtensa_debug_module *

dm

)

Definition at line 96 of file xtensa_debug_module.c.

References dap_put_ap(), xtensa_debug_module::debug_ap, and NULL.

Referenced by xtensa_target_deinit().

xtensa_dm_device_id_get()

static xtensa_ocdid_t xtensa_dm_device_id_get ( struct xtensa_debug_module *  dm )

inlinestatic

Definition at line 556 of file xtensa_debug_module.h.

xtensa_dm_device_id_read()

int xtensa_dm_device_id_read

(

struct xtensa_debug_module *

dm

)

Definition at line 244 of file xtensa_debug_module.c.

References buf_get_u32(), xtensa_debug_module::dbg_ops, xtensa_debug_module::device_id, ERROR_OK, xtensa_debug_ops::queue_reg_read, XDMREG_OCDID, xtensa_dm_queue_execute(), and xtensa_dm_queue_tdi_idle().

xtensa_dm_examine()

int xtensa_dm_examine

(

struct xtensa_debug_module *

dm

)

Definition at line 114 of file xtensa_debug_module.c.

References adiv5_ap::ap_num, AP_TYPE_APB_AP, xtensa_debug_module::dap, dap_find_get_ap(), dap_get_ap(), dap_put_ap(), xtensa_debug_module::debug_ap, xtensa_debug_module::debug_apsel, DP_APSEL_INVALID, ERROR_OK, LOG_DEBUG, LOG_ERROR, mem_ap_init(), adiv5_ap::memaccess_tck, NULL, and adiv5_ap::tar_autoincr_block.

Referenced by xtensa_chip_examine().

xtensa_dm_init()

int xtensa_dm_init	(	struct xtensa_debug_module *	dm,
		const struct xtensa_debug_module_config *	cfg
	)

Definition at line 74 of file xtensa_debug_module.c.

References xtensa_debug_module_config::ap_offset, xtensa_debug_module::ap_offset, xtensa_debug_module_config::dap, xtensa_debug_module::dap, xtensa_debug_module_config::dbg_ops, xtensa_debug_module::dbg_ops, xtensa_debug_module_config::debug_ap, xtensa_debug_module::debug_ap, xtensa_debug_module_config::debug_apsel, xtensa_debug_module::debug_apsel, ERROR_FAIL, ERROR_OK, IS_ALIGNED, LOG_ERROR, xtensa_debug_module_config::pwr_ops, xtensa_debug_module::pwr_ops, xtensa_debug_module_config::queue_tdi_idle, xtensa_debug_module::queue_tdi_idle, xtensa_debug_module_config::queue_tdi_idle_arg, xtensa_debug_module::queue_tdi_idle_arg, xtensa_debug_module_config::tap, xtensa_debug_module::tap, and XTENSA_DM_APB_ALIGN.

Referenced by xtensa_init_arch_info().

xtensa_dm_is_online()

static bool xtensa_dm_is_online ( struct xtensa_debug_module *  dm )

inlinestatic

Definition at line 567 of file xtensa_debug_module.h.

Referenced by xtensa_examine().

xtensa_dm_is_powered()

static bool xtensa_dm_is_powered ( struct xtensa_debug_module *  dm )

inlinestatic

Definition at line 592 of file xtensa_debug_module.h.

Referenced by xtensa_poll().

xtensa_dm_perfmon_dump()

int xtensa_dm_perfmon_dump	(	struct xtensa_debug_module *	dm,
		int	counter_id,
		struct xtensa_perfmon_result *	out_result
	)

Definition at line 458 of file xtensa_debug_module.c.

References buf_get_u32(), xtensa_debug_module::dbg_ops, ERROR_OK, xtensa_perfmon_result::overflow, xtensa_debug_ops::queue_reg_read, xtensa_trace_status::stat, xtensa_perfmon_result::value, XDMREG_PM0, XDMREG_PMSTAT0, xtensa_dm_queue_execute(), and xtensa_dm_queue_tdi_idle().

Referenced by COMMAND_HELPER().

xtensa_dm_perfmon_enable()

int xtensa_dm_perfmon_enable	(	struct xtensa_debug_module *	dm,
		int	counter_id,
		const struct xtensa_perfmon_config *	config
	)

Definition at line 436 of file xtensa_debug_module.c.

References config, xtensa_debug_module::dbg_ops, ERROR_FAIL, xtensa_debug_ops::queue_reg_read, xtensa_debug_ops::queue_reg_write, XDMREG_PM0, XDMREG_PMCTRL0, XDMREG_PMG, XDMREG_PMSTAT0, xtensa_dm_queue_execute(), and xtensa_dm_queue_tdi_idle().

Referenced by COMMAND_HELPER().

xtensa_dm_poll()

int xtensa_dm_poll

(

struct xtensa_debug_module *

dm

)

Definition at line 104 of file xtensa_debug_module.c.

References xtensa_debug_module::dap, xtensa_debug_module::debug_ap, ERROR_FAIL, and ERROR_OK.

Referenced by xtensa_poll().

xtensa_dm_power_status_cache()

static void xtensa_dm_power_status_cache ( struct xtensa_debug_module *  dm )

inlinestatic

Definition at line 535 of file xtensa_debug_module.h.

Referenced by xtensa_poll().

xtensa_dm_power_status_cache_reset()

static void xtensa_dm_power_status_cache_reset ( struct xtensa_debug_module *  dm )

inlinestatic

Definition at line 531 of file xtensa_debug_module.h.

xtensa_dm_power_status_get()

static xtensa_pwrstat_t xtensa_dm_power_status_get ( struct xtensa_debug_module *  dm )

inlinestatic

Definition at line 539 of file xtensa_debug_module.h.

Referenced by esp_xtensa_poll().

xtensa_dm_power_status_read()

int xtensa_dm_power_status_read	(	struct xtensa_debug_module *	dm,
		uint32_t	clear
	)

Definition at line 257 of file xtensa_debug_module.c.

References buf_get_u32(), ERROR_OK, xtensa_debug_module::power_status, xtensa_debug_module::pwr_ops, xtensa_power_ops::queue_reg_read, xtensa_power_status::stat, xtensa_power_status::stath, XDMREG_PWRSTAT, xtensa_dm_queue_execute(), and xtensa_dm_queue_tdi_idle().

Referenced by xtensa_poll().

xtensa_dm_queue_enable()

int xtensa_dm_queue_enable

(

struct xtensa_debug_module *

dm

)

Definition at line 157 of file xtensa_debug_module.c.

References xtensa_debug_module::dbg_ops, OCDDCR_ENABLEOCD, xtensa_debug_ops::queue_reg_write, and XDMREG_DCRSET.

Referenced by xtensa_dm_core_status_read(), xtensa_dm_read(), xtensa_dm_write(), and xtensa_examine().

xtensa_dm_queue_execute()

static int xtensa_dm_queue_execute ( struct xtensa_debug_module *  dm )

inlinestatic

Definition at line 519 of file xtensa_debug_module.h.

Referenced by COMMAND_HELPER(), esp_xtensa_apptrace_buffs_write(), esp_xtensa_apptrace_ctrl_reg_read(), esp_xtensa_apptrace_ctrl_reg_write(), esp_xtensa_apptrace_data_read(), esp_xtensa_apptrace_status_reg_read(), esp_xtensa_apptrace_status_reg_write(), esp_xtensa_profiling(), esp_xtensa_swdbg_activate(), xtensa_assert_reset(), xtensa_deassert_reset(), xtensa_dm_core_status_clear(), xtensa_dm_core_status_read(), xtensa_dm_device_id_read(), xtensa_dm_perfmon_dump(), xtensa_dm_perfmon_enable(), xtensa_dm_power_status_read(), xtensa_dm_read(), xtensa_dm_trace_config_read(), xtensa_dm_trace_data_read(), xtensa_dm_trace_start(), xtensa_dm_trace_status_read(), xtensa_dm_trace_stop(), xtensa_dm_write(), xtensa_do_resume(), xtensa_examine(), xtensa_fetch_all_regs(), xtensa_gdbqc_qxtreg(), xtensa_halt(), xtensa_poll(), xtensa_read_memory(), xtensa_region_ar_exec(), xtensa_smpbreak_read(), xtensa_smpbreak_write(), xtensa_target_deinit(), xtensa_update_instruction(), xtensa_wakeup(), xtensa_window_state_save(), xtensa_write_dirty_registers(), and xtensa_write_memory().

xtensa_dm_queue_pwr_reg_read()

int xtensa_dm_queue_pwr_reg_read	(	struct xtensa_debug_module *	dm,
		enum xtensa_dm_pwr_reg	reg,
		uint8_t *	data,
		uint32_t	clear
	)

Definition at line 197 of file xtensa_debug_module.c.

References xtensa_debug_module::ap_offset, xtensa_dm_pwr_reg_offsets::apb, xtensa_debug_module::dap, xtensa_debug_module::debug_ap, ERROR_FAIL, ERROR_OK, LOG_ERROR, mem_ap_read_buf(), mem_ap_write_u32(), TAP_IDLE, TAPINS_PWRCTL, TAPINS_PWRCTL_LEN, TAPINS_PWRSTAT, TAPINS_PWRSTAT_LEN, xdm_pwr_regs, XDMREG_PWRCTL, XDMREG_PWRNUM, xtensa_dm_add_dr_scan(), and xtensa_dm_add_set_ir().

xtensa_dm_queue_pwr_reg_write()

int xtensa_dm_queue_pwr_reg_write	(	struct xtensa_debug_module *	dm,
		enum xtensa_dm_pwr_reg	reg,
		uint32_t	data
	)

Definition at line 224 of file xtensa_debug_module.c.

References xtensa_debug_module::ap_offset, xtensa_dm_pwr_reg_offsets::apb, xtensa_debug_module::dap, xtensa_debug_module::debug_ap, ERROR_FAIL, ERROR_OK, LOG_ERROR, mem_ap_write_u32(), NULL, TAP_IDLE, TAPINS_PWRCTL, TAPINS_PWRCTL_LEN, TAPINS_PWRSTAT, TAPINS_PWRSTAT_LEN, xdm_pwr_regs, XDMREG_PWRCTL, XDMREG_PWRNUM, xtensa_dm_add_dr_scan(), and xtensa_dm_add_set_ir().

xtensa_dm_queue_reg_read()

int xtensa_dm_queue_reg_read	(	struct xtensa_debug_module *	dm,
		enum xtensa_dm_reg	reg,
		uint8_t *	value
	)

Definition at line 162 of file xtensa_debug_module.c.

References xtensa_debug_module::ap_offset, xtensa_dm_reg_offsets::apb, xtensa_debug_module::dap, xtensa_debug_module::debug_ap, dummy, ERROR_FAIL, ERROR_OK, LOG_ERROR, mem_ap_read_buf(), xtensa_dm_reg_offsets::nar, NULL, TAP_IDLE, TAPINS_NARSEL, TAPINS_NARSEL_ADRLEN, TAPINS_NARSEL_DATALEN, xdm_regs, XDMREG_NUM, xtensa_dm_add_dr_scan(), and xtensa_dm_add_set_ir().

xtensa_dm_queue_reg_write()

int xtensa_dm_queue_reg_write	(	struct xtensa_debug_module *	dm,
		enum xtensa_dm_reg	reg,
		uint32_t	value
	)

Definition at line 181 of file xtensa_debug_module.c.

References xtensa_debug_module::ap_offset, xtensa_dm_reg_offsets::apb, xtensa_debug_module::dap, xtensa_debug_module::debug_ap, ERROR_FAIL, ERROR_OK, LOG_ERROR, mem_ap_write_u32(), xtensa_dm_reg_offsets::nar, NULL, TAP_IDLE, TAPINS_NARSEL, TAPINS_NARSEL_ADRLEN, TAPINS_NARSEL_DATALEN, xdm_regs, XDMREG_NUM, xtensa_dm_add_dr_scan(), and xtensa_dm_add_set_ir().

xtensa_dm_queue_tdi_idle()

static void xtensa_dm_queue_tdi_idle ( struct xtensa_debug_module *  dm )

inlinestatic

Definition at line 524 of file xtensa_debug_module.h.

Referenced by esp_xtensa_apptrace_buffs_write(), esp_xtensa_apptrace_ctrl_reg_read(), esp_xtensa_apptrace_ctrl_reg_write(), esp_xtensa_apptrace_data_read(), esp_xtensa_apptrace_status_reg_read(), esp_xtensa_apptrace_status_reg_write(), esp_xtensa_swdbg_activate(), xtensa_assert_reset(), xtensa_deassert_reset(), xtensa_dm_core_status_clear(), xtensa_dm_core_status_read(), xtensa_dm_device_id_read(), xtensa_dm_perfmon_dump(), xtensa_dm_perfmon_enable(), xtensa_dm_power_status_read(), xtensa_dm_read(), xtensa_dm_trace_config_read(), xtensa_dm_trace_data_read(), xtensa_dm_trace_start(), xtensa_dm_trace_status_read(), xtensa_dm_trace_stop(), xtensa_dm_write(), xtensa_examine(), xtensa_halt(), xtensa_smpbreak_read(), xtensa_smpbreak_write(), xtensa_target_deinit(), and xtensa_wakeup().

xtensa_dm_read()

int xtensa_dm_read	(	struct xtensa_debug_module *	dm,
		uint32_t	addr,
		uint32_t *	val
	)

Definition at line 298 of file xtensa_debug_module.c.

References addr, buf_get_u32(), xtensa_debug_module::dbg_ops, ERROR_FAIL, ERROR_OK, xtensa_debug_ops::queue_reg_read, XDMREG_NUM, xtensa_dm_queue_enable(), xtensa_dm_queue_execute(), xtensa_dm_queue_tdi_idle(), and xtensa_dm_regaddr_to_id().

Referenced by COMMAND_HELPER().

xtensa_dm_tap_was_reset()

static bool xtensa_dm_tap_was_reset ( struct xtensa_debug_module *  dm )

inlinestatic

Definition at line 575 of file xtensa_debug_module.h.

Referenced by xtensa_poll().

xtensa_dm_trace_config_read()

int xtensa_dm_trace_config_read	(	struct xtensa_debug_module *	dm,
		struct xtensa_trace_config *	config
	)

Definition at line 400 of file xtensa_debug_module.c.

References buf_get_u32(), config, xtensa_debug_module::dbg_ops, ERROR_FAIL, ERROR_OK, xtensa_debug_ops::queue_reg_read, XDMREG_MEMADDREND, XDMREG_MEMADDRSTART, XDMREG_TRAXADDR, XDMREG_TRAXCTRL, xtensa_dm_queue_execute(), and xtensa_dm_queue_tdi_idle().

Referenced by COMMAND_HELPER(), and esp_xtensa_apptrace_block_max_size_get().

xtensa_dm_trace_data_read()

int xtensa_dm_trace_data_read	(	struct xtensa_debug_module *	dm,
		uint8_t *	dest,
		uint32_t	size
	)

Definition at line 425 of file xtensa_debug_module.c.

References xtensa_debug_module::dbg_ops, ERROR_FAIL, xtensa_debug_ops::queue_reg_read, size, XDMREG_TRAXDATA, xtensa_dm_queue_execute(), and xtensa_dm_queue_tdi_idle().

Referenced by COMMAND_HELPER().

xtensa_dm_trace_start()

int xtensa_dm_trace_start	(	struct xtensa_debug_module *	dm,
		struct xtensa_trace_start_config *	cfg
	)

Definition at line 326 of file xtensa_debug_module.c.

References xtensa_trace_start_config::after, xtensa_trace_start_config::after_is_words, xtensa_debug_module::dbg_ops, ERROR_OK, PCMATCHCTRL_PCML_SHIFT, xtensa_debug_ops::queue_reg_write, xtensa_trace_start_config::stopmask, xtensa_trace_start_config::stoppc, TRAXCTRL_CNTU, TRAXCTRL_PCMEN, TRAXCTRL_PTOWS, TRAXCTRL_SMPER_SHIFT, TRAXCTRL_TMEN, TRAXCTRL_TREN, XDMREG_DELAYCNT, XDMREG_PCMATCHCTRL, XDMREG_TRAXADDR, XDMREG_TRAXCTRL, XDMREG_TRIGGERPC, xtensa_dm_queue_execute(), xtensa_dm_queue_tdi_idle(), and XTENSA_STOPMASK_DISABLED.

Referenced by COMMAND_HELPER().

xtensa_dm_trace_status_read()

int xtensa_dm_trace_status_read	(	struct xtensa_debug_module *	dm,
		struct xtensa_trace_status *	status
	)

Definition at line 388 of file xtensa_debug_module.c.

References buf_get_u32(), xtensa_debug_module::dbg_ops, ERROR_OK, xtensa_debug_ops::queue_reg_read, status, XDMREG_TRAXSTAT, xtensa_dm_queue_execute(), and xtensa_dm_queue_tdi_idle().

Referenced by COMMAND_HELPER(), esp_xtensa_apptrace_block_max_size_get(), xtensa_dm_trace_stop(), and xtensa_poll().

xtensa_dm_trace_stop()

int xtensa_dm_trace_stop	(	struct xtensa_debug_module *	dm,
		bool	pto_enable
	)

Definition at line 354 of file xtensa_debug_module.c.

References buf_get_u32(), xtensa_debug_module::dbg_ops, ERROR_FAIL, ERROR_OK, LOG_ERROR, xtensa_debug_ops::queue_reg_read, xtensa_debug_ops::queue_reg_write, TRAXCTRL_PTOWS, TRAXCTRL_PTOWT, TRAXCTRL_TRSTP, TRAXSTAT_TRACT, XDMREG_TRAXCTRL, xtensa_dm_queue_execute(), xtensa_dm_queue_tdi_idle(), and xtensa_dm_trace_status_read().

Referenced by COMMAND_HELPER().

xtensa_dm_write()

int xtensa_dm_write	(	struct xtensa_debug_module *	dm,
		uint32_t	addr,
		uint32_t	val
	)

Definition at line 314 of file xtensa_debug_module.c.

References addr, xtensa_debug_module::dbg_ops, ERROR_FAIL, xtensa_debug_ops::queue_reg_write, XDMREG_NUM, xtensa_dm_queue_enable(), xtensa_dm_queue_execute(), xtensa_dm_queue_tdi_idle(), and xtensa_dm_regaddr_to_id().

Referenced by COMMAND_HELPER().