OpenOCD
esp32s3.c
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1 // SPDX-License-Identifier: GPL-2.0-or-later
2 
3 /***************************************************************************
4  * ESP32-S3 target API for OpenOCD *
5  * Copyright (C) 2020 Espressif Systems Ltd. *
6  ***************************************************************************/
7 
8 #ifdef HAVE_CONFIG_H
9 #include "config.h"
10 #endif
11 
12 #include <helper/time_support.h>
13 #include <target/target.h>
14 #include <target/target_type.h>
15 #include <target/smp.h>
17 #include "assert.h"
18 #include "esp_xtensa_smp.h"
19 
20 /*
21 This is a JTAG driver for the ESP32_S3, the are two Tensilica cores inside
22 the ESP32_S3 chip. For more information please have a look into ESP32_S3 target
23 implementation.
24 */
25 
26 /* ESP32_S3 memory map */
27 #define ESP32_S3_RTC_DATA_LOW 0x50000000
28 #define ESP32_S3_RTC_DATA_HIGH 0x50002000
29 #define ESP32_S3_EXTRAM_DATA_LOW 0x3D000000
30 #define ESP32_S3_EXTRAM_DATA_HIGH 0x3E000000
31 #define ESP32_S3_SYS_RAM_LOW 0x60000000UL
32 #define ESP32_S3_SYS_RAM_HIGH (ESP32_S3_SYS_RAM_LOW + 0x10000000UL)
33 #define ESP32_S3_RTC_SLOW_MEM_BASE ESP32_S3_RTC_DATA_LOW
34 
35 /* ESP32_S3 WDT */
36 #define ESP32_S3_WDT_WKEY_VALUE 0x50D83AA1
37 #define ESP32_S3_TIMG0_BASE 0x6001F000
38 #define ESP32_S3_TIMG1_BASE 0x60020000
39 #define ESP32_S3_TIMGWDT_CFG0_OFF 0x48
40 #define ESP32_S3_TIMGWDT_PROTECT_OFF 0x64
41 #define ESP32_S3_TIMG0WDT_CFG0 (ESP32_S3_TIMG0_BASE + ESP32_S3_TIMGWDT_CFG0_OFF)
42 #define ESP32_S3_TIMG1WDT_CFG0 (ESP32_S3_TIMG1_BASE + ESP32_S3_TIMGWDT_CFG0_OFF)
43 #define ESP32_S3_TIMG0WDT_PROTECT (ESP32_S3_TIMG0_BASE + ESP32_S3_TIMGWDT_PROTECT_OFF)
44 #define ESP32_S3_TIMG1WDT_PROTECT (ESP32_S3_TIMG1_BASE + ESP32_S3_TIMGWDT_PROTECT_OFF)
45 #define ESP32_S3_RTCCNTL_BASE 0x60008000
46 #define ESP32_S3_RTCWDT_CFG_OFF 0x98
47 #define ESP32_S3_RTCWDT_PROTECT_OFF 0xB0
48 #define ESP32_S3_SWD_CONF_OFF 0xB0
49 #define ESP32_S3_SWD_WPROTECT_OFF 0xB4
50 #define ESP32_S3_RTCWDT_CFG (ESP32_S3_RTCCNTL_BASE + ESP32_S3_RTCWDT_CFG_OFF)
51 #define ESP32_S3_RTCWDT_PROTECT (ESP32_S3_RTCCNTL_BASE + ESP32_S3_RTCWDT_PROTECT_OFF)
52 #define ESP32_S3_SWD_CONF_REG (ESP32_S3_RTCCNTL_BASE + ESP32_S3_SWD_CONF_OFF)
53 #define ESP32_S3_SWD_WPROTECT_REG (ESP32_S3_RTCCNTL_BASE + ESP32_S3_SWD_WPROTECT_OFF)
54 #define ESP32_S3_SWD_AUTO_FEED_EN_M BIT(31)
55 #define ESP32_S3_SWD_WKEY_VALUE 0x8F1D312AU
56 
57 #define ESP32_S3_TRACEMEM_BLOCK_SZ 0x4000
58 
59 /* ESP32_S3 dport regs */
60 #define ESP32_S3_DR_REG_SYSTEM_BASE 0x600c0000
61 #define ESP32_S3_SYSTEM_CORE_1_CONTROL_0_REG (ESP32_S3_DR_REG_SYSTEM_BASE + 0x014)
62 #define ESP32_S3_SYSTEM_CONTROL_CORE_1_CLKGATE_EN BIT(1)
63 
64 /* ESP32_S3 RTC regs */
65 #define ESP32_S3_RTC_CNTL_SW_CPU_STALL_REG (ESP32_S3_RTCCNTL_BASE + 0xBC)
66 #define ESP32_S3_RTC_CNTL_SW_CPU_STALL_DEF 0x0
67 
70 };
71 
72 /* Reset ESP32-S3's peripherals.
73  * 1. OpenOCD makes sure the target is halted; if not, tries to halt it.
74  * If that fails, tries to reset it (via OCD) and then halt.
75  * 2. OpenOCD loads the stub code into RTC_SLOW_MEM.
76  * 3. Executes the stub code from address 0x50000004.
77  * 4. The stub code changes the reset vector to 0x50000000, and triggers
78  * a system reset using RTC_CNTL_SW_SYS_RST bit.
79  * 5. Once the PRO CPU is out of reset, it executes the stub code from address 0x50000000.
80  * The stub code disables the watchdog, re-enables JTAG and the APP CPU,
81  * restores the reset vector, and enters an infinite loop.
82  * 6. OpenOCD waits until it can talk to the OCD module again, then halts the target.
83  * 7. OpenOCD restores the contents of RTC_SLOW_MEM.
84  *
85  * End result: all the peripherals except RTC_CNTL are reset, CPU's PC is undefined,
86  * PRO CPU is halted, APP CPU is in reset.
87  */
88 
89 static const uint8_t esp32s3_reset_stub_code[] = {
90 #include "../../../contrib/loaders/reset/espressif/esp32s3/cpu_reset_handler_code.inc"
91 };
92 
93 static int esp32s3_soc_reset(struct target *target)
94 {
95  int res;
96  struct target_list *head;
97  struct xtensa *xtensa;
98 
99  LOG_DEBUG("start");
100  /* In order to write to peripheral registers, target must be halted first */
101  if (target->state != TARGET_HALTED) {
102  LOG_DEBUG("Target not halted before SoC reset, trying to halt it first");
104  res = target_wait_state(target, TARGET_HALTED, 1000);
105  if (res != ERROR_OK) {
106  LOG_DEBUG("Couldn't halt target before SoC reset, trying to do reset-halt");
108  if (res != ERROR_OK) {
109  LOG_ERROR(
110  "Couldn't halt target before SoC reset! (xtensa_assert_reset returned %d)",
111  res);
112  return res;
113  }
114  alive_sleep(10);
116  bool reset_halt_save = target->reset_halt;
117  target->reset_halt = true;
119  target->reset_halt = reset_halt_save;
120  if (res != ERROR_OK) {
121  LOG_ERROR(
122  "Couldn't halt target before SoC reset! (xtensa_deassert_reset returned %d)",
123  res);
124  return res;
125  }
126  alive_sleep(10);
129  res = target_wait_state(target, TARGET_HALTED, 1000);
130  if (res != ERROR_OK) {
131  LOG_ERROR("Couldn't halt target before SoC reset");
132  return res;
133  }
134  }
135  }
136 
137  if (target->smp) {
139  xtensa = target_to_xtensa(head->target);
140  /* if any of the cores is stalled unstall them */
142  LOG_TARGET_DEBUG(head->target, "Unstall CPUs before SW reset!");
143  res = target_write_u32(target,
146  if (res != ERROR_OK) {
147  LOG_TARGET_ERROR(head->target, "Failed to unstall CPUs before SW reset!");
148  return res;
149  }
150  break; /* both cores are unstalled now, so exit the loop */
151  }
152  }
153  }
154 
155  LOG_DEBUG("Loading stub code into RTC RAM");
156  uint8_t slow_mem_save[sizeof(esp32s3_reset_stub_code)];
157 
158  /* Save contents of RTC_SLOW_MEM which we are about to overwrite */
159  res = target_read_buffer(target, ESP32_S3_RTC_SLOW_MEM_BASE, sizeof(slow_mem_save), slow_mem_save);
160  if (res != ERROR_OK) {
161  LOG_ERROR("Failed to save contents of RTC_SLOW_MEM (%d)!", res);
162  return res;
163  }
164 
165  /* Write stub code into RTC_SLOW_MEM */
168  sizeof(esp32s3_reset_stub_code),
170  if (res != ERROR_OK) {
171  LOG_ERROR("Failed to write stub (%d)!", res);
172  return res;
173  }
174 
175  LOG_DEBUG("Resuming the target");
177  xtensa->suppress_dsr_errors = true;
178  res = xtensa_resume(target, 0, ESP32_S3_RTC_SLOW_MEM_BASE + 4, 0, 0);
179  xtensa->suppress_dsr_errors = false;
180  if (res != ERROR_OK) {
181  LOG_ERROR("Failed to run stub (%d)!", res);
182  return res;
183  }
184  LOG_DEBUG("resume done, waiting for the target to come alive");
185 
186  /* Wait for SoC to reset */
187  alive_sleep(100);
188  int64_t timeout = timeval_ms() + 100;
189  bool get_timeout = false;
190  while (target->state != TARGET_RESET && target->state != TARGET_RUNNING) {
191  alive_sleep(10);
193  if (timeval_ms() >= timeout) {
195  "Timed out waiting for CPU to be reset, target state=%d",
196  target->state);
197  get_timeout = true;
198  break;
199  }
200  }
201 
202  /* Halt the CPU again */
203  LOG_DEBUG("halting the target");
205  res = target_wait_state(target, TARGET_HALTED, 1000);
206  if (res == ERROR_OK) {
207  LOG_DEBUG("restoring RTC_SLOW_MEM");
208  res = target_write_buffer(target, ESP32_S3_RTC_SLOW_MEM_BASE, sizeof(slow_mem_save), slow_mem_save);
209  if (res != ERROR_OK)
210  LOG_TARGET_ERROR(target, "Failed to restore contents of RTC_SLOW_MEM (%d)!", res);
211  } else {
212  LOG_TARGET_ERROR(target, "Timed out waiting for CPU to be halted after SoC reset");
213  }
214 
215  return get_timeout ? ERROR_TARGET_TIMEOUT : res;
216 }
217 
218 static int esp32s3_disable_wdts(struct target *target)
219 {
220  /* TIMG1 WDT */
222  if (res != ERROR_OK) {
223  LOG_ERROR("Failed to write ESP32_S3_TIMG0WDT_PROTECT (%d)!", res);
224  return res;
225  }
227  if (res != ERROR_OK) {
228  LOG_ERROR("Failed to write ESP32_S3_TIMG0WDT_CFG0 (%d)!", res);
229  return res;
230  }
231  /* TIMG2 WDT */
233  if (res != ERROR_OK) {
234  LOG_ERROR("Failed to write ESP32_S3_TIMG1WDT_PROTECT (%d)!", res);
235  return res;
236  }
238  if (res != ERROR_OK) {
239  LOG_ERROR("Failed to write ESP32_S3_TIMG1WDT_CFG0 (%d)!", res);
240  return res;
241  }
242  /* RTC WDT */
244  if (res != ERROR_OK) {
245  LOG_ERROR("Failed to write ESP32_S3_RTCWDT_PROTECT (%d)!", res);
246  return res;
247  }
249  if (res != ERROR_OK) {
250  LOG_ERROR("Failed to write ESP32_S3_RTCWDT_CFG (%d)!", res);
251  return res;
252  }
253  /* Enable SWD auto-feed */
255  if (res != ERROR_OK) {
256  LOG_ERROR("Failed to write ESP32_S3_SWD_WPROTECT_REG (%d)!", res);
257  return res;
258  }
259  uint32_t swd_conf_reg = 0;
260  res = target_read_u32(target, ESP32_S3_SWD_CONF_REG, &swd_conf_reg);
261  if (res != ERROR_OK) {
262  LOG_ERROR("Failed to read ESP32_S3_SWD_CONF_REG (%d)!", res);
263  return res;
264  }
265  swd_conf_reg |= ESP32_S3_SWD_AUTO_FEED_EN_M;
266  res = target_write_u32(target, ESP32_S3_SWD_CONF_REG, swd_conf_reg);
267  if (res != ERROR_OK) {
268  LOG_ERROR("Failed to write ESP32_S3_SWD_CONF_REG (%d)!", res);
269  return res;
270  }
271  return ERROR_OK;
272 }
273 
274 static int esp32s3_on_halt(struct target *target)
275 {
276  int ret = esp32s3_disable_wdts(target);
277  if (ret == ERROR_OK)
279  return ret;
280 }
281 
282 static int esp32s3_arch_state(struct target *target)
283 {
284  return ERROR_OK;
285 }
286 
287 static int esp32s3_virt2phys(struct target *target,
288  target_addr_t virtual, target_addr_t *physical)
289 {
290  if (physical) {
291  *physical = virtual;
292  return ERROR_OK;
293  }
294  return ERROR_FAIL;
295 }
296 
297 static int esp32s3_target_init(struct command_context *cmd_ctx, struct target *target)
298 {
299  return esp_xtensa_smp_target_init(cmd_ctx, target);
300 }
301 
302 static const struct xtensa_debug_ops esp32s3_dbg_ops = {
304  .queue_reg_read = xtensa_dm_queue_reg_read,
305  .queue_reg_write = xtensa_dm_queue_reg_write
306 };
307 
308 static const struct xtensa_power_ops esp32s3_pwr_ops = {
310  .queue_reg_write = xtensa_dm_queue_pwr_reg_write
311 };
312 
313 static const struct esp_xtensa_smp_chip_ops esp32s3_chip_ops = {
315  .on_halt = esp32s3_on_halt
316 };
317 
318 static const struct esp_semihost_ops esp32s3_semihost_ops = {
320 };
321 
322 static int esp32s3_target_create(struct target *target, Jim_Interp *interp)
323 {
324  struct xtensa_debug_module_config esp32s3_dm_cfg = {
326  .pwr_ops = &esp32s3_pwr_ops,
327  .tap = target->tap,
328  .queue_tdi_idle = NULL,
329  .queue_tdi_idle_arg = NULL
330  };
331 
332  struct esp32s3_common *esp32s3 = calloc(1, sizeof(struct esp32s3_common));
333  if (!esp32s3) {
334  LOG_ERROR("Failed to alloc memory for arch info!");
335  return ERROR_FAIL;
336  }
337 
339  &esp32s3->esp_xtensa_smp,
340  &esp32s3_dm_cfg,
343  if (ret != ERROR_OK) {
344  LOG_ERROR("Failed to init arch info!");
345  free(esp32s3);
346  return ret;
347  }
348 
349  /* Assume running target. If different, the first poll will fix this. */
352  return ERROR_OK;
353 }
354 
355 static const struct command_registration esp32s3_command_handlers[] = {
356  {
357  .usage = "",
359  },
360  {
361  .name = "esp",
362  .usage = "",
364  },
365  {
366  .name = "esp32",
367  .usage = "",
368  .chain = smp_command_handlers,
369  },
370  {
371  .name = "arm",
372  .mode = COMMAND_ANY,
373  .help = "ARM Command Group",
374  .usage = "",
376  },
378 };
379 
381 struct target_type esp32s3_target = {
382  .name = "esp32s3",
383 
384  .poll = esp_xtensa_smp_poll,
385  .arch_state = esp32s3_arch_state,
386 
387  .halt = xtensa_halt,
388  .resume = esp_xtensa_smp_resume,
389  .step = esp_xtensa_smp_step,
390 
391  .assert_reset = esp_xtensa_smp_assert_reset,
392  .deassert_reset = esp_xtensa_smp_deassert_reset,
393  .soft_reset_halt = esp_xtensa_smp_soft_reset_halt,
394 
395  .virt2phys = esp32s3_virt2phys,
396  .mmu = xtensa_mmu_is_enabled,
397  .read_memory = xtensa_read_memory,
398  .write_memory = xtensa_write_memory,
399 
400  .read_buffer = xtensa_read_buffer,
401  .write_buffer = xtensa_write_buffer,
402 
403  .checksum_memory = xtensa_checksum_memory,
404 
405  .get_gdb_arch = xtensa_get_gdb_arch,
406  .get_gdb_reg_list = xtensa_get_gdb_reg_list,
407 
408  .run_algorithm = xtensa_run_algorithm,
409  .start_algorithm = xtensa_start_algorithm,
410  .wait_algorithm = xtensa_wait_algorithm,
411 
412  .add_breakpoint = esp_xtensa_breakpoint_add,
413  .remove_breakpoint = esp_xtensa_breakpoint_remove,
414 
415  .add_watchpoint = esp_xtensa_smp_watchpoint_add,
416  .remove_watchpoint = esp_xtensa_smp_watchpoint_remove,
417 
418  .target_create = esp32s3_target_create,
419  .init_target = esp32s3_target_init,
420  .examine = xtensa_examine,
421  .deinit_target = esp_xtensa_target_deinit,
422 
423  .commands = esp32s3_command_handlers,
424  .profiling = esp_xtensa_profiling,
425 };
#define COMMAND_REGISTRATION_DONE
Use this as the last entry in an array of command_registration records.
Definition: command.h:253
@ COMMAND_ANY
Definition: command.h:42
const struct command_registration esp32_apptrace_command_handlers[]
static int esp32s3_target_init(struct command_context *cmd_ctx, struct target *target)
Definition: esp32s3.c:297
#define ESP32_S3_SWD_CONF_REG
Definition: esp32s3.c:52
struct target_type esp32s3_target
Holds methods for Xtensa targets.
Definition: esp32s3.c:381
static const struct esp_semihost_ops esp32s3_semihost_ops
Definition: esp32s3.c:318
static int esp32s3_soc_reset(struct target *target)
Definition: esp32s3.c:93
static const struct xtensa_debug_ops esp32s3_dbg_ops
Definition: esp32s3.c:302
#define ESP32_S3_SWD_AUTO_FEED_EN_M
Definition: esp32s3.c:54
static int esp32s3_target_create(struct target *target, Jim_Interp *interp)
Definition: esp32s3.c:322
#define ESP32_S3_WDT_WKEY_VALUE
Definition: esp32s3.c:36
#define ESP32_S3_RTC_CNTL_SW_CPU_STALL_DEF
Definition: esp32s3.c:66
static const struct xtensa_power_ops esp32s3_pwr_ops
Definition: esp32s3.c:308
#define ESP32_S3_SWD_WKEY_VALUE
Definition: esp32s3.c:55
#define ESP32_S3_RTC_CNTL_SW_CPU_STALL_REG
Definition: esp32s3.c:65
#define ESP32_S3_RTC_SLOW_MEM_BASE
Definition: esp32s3.c:33
#define ESP32_S3_SWD_WPROTECT_REG
Definition: esp32s3.c:53
static int esp32s3_virt2phys(struct target *target, target_addr_t virtual, target_addr_t *physical)
Definition: esp32s3.c:287
#define ESP32_S3_TIMG0WDT_PROTECT
Definition: esp32s3.c:43
static const struct command_registration esp32s3_command_handlers[]
Definition: esp32s3.c:355
#define ESP32_S3_RTCWDT_PROTECT
Definition: esp32s3.c:51
static const uint8_t esp32s3_reset_stub_code[]
Definition: esp32s3.c:89
static int esp32s3_disable_wdts(struct target *target)
Definition: esp32s3.c:218
#define ESP32_S3_TIMG1WDT_CFG0
Definition: esp32s3.c:42
#define ESP32_S3_RTCWDT_CFG
Definition: esp32s3.c:50
#define ESP32_S3_TIMG1WDT_PROTECT
Definition: esp32s3.c:44
static int esp32s3_on_halt(struct target *target)
Definition: esp32s3.c:274
#define ESP32_S3_TIMG0WDT_CFG0
Definition: esp32s3.c:41
static int esp32s3_arch_state(struct target *target)
Definition: esp32s3.c:282
static const struct esp_xtensa_smp_chip_ops esp32s3_chip_ops
Definition: esp32s3.c:313
void esp_xtensa_target_deinit(struct target *target)
Definition: esp_xtensa.c:87
int esp_xtensa_breakpoint_remove(struct target *target, struct breakpoint *breakpoint)
Definition: esp_xtensa.c:177
int esp_xtensa_breakpoint_add(struct target *target, struct breakpoint *breakpoint)
Definition: esp_xtensa.c:171
int esp_xtensa_profiling(struct target *target, uint32_t *samples, uint32_t max_num_samples, uint32_t *num_samples, uint32_t seconds)
Definition: esp_xtensa.c:183
int esp_xtensa_smp_init_arch_info(struct target *target, struct esp_xtensa_smp_common *esp_xtensa_smp, struct xtensa_debug_module_config *dm_cfg, const struct esp_xtensa_smp_chip_ops *chip_ops, const struct esp_semihost_ops *semihost_ops)
const struct command_registration esp_xtensa_smp_command_handlers[]
int esp_xtensa_smp_soft_reset_halt(struct target *target)
int esp_xtensa_smp_deassert_reset(struct target *target)
int esp_xtensa_smp_step(struct target *target, int current, target_addr_t address, int handle_breakpoints)
int esp_xtensa_smp_watchpoint_remove(struct target *target, struct watchpoint *watchpoint)
int esp_xtensa_smp_target_init(struct command_context *cmd_ctx, struct target *target)
int esp_xtensa_smp_on_halt(struct target *target)
int esp_xtensa_smp_watchpoint_add(struct target *target, struct watchpoint *watchpoint)
int esp_xtensa_smp_assert_reset(struct target *target)
int esp_xtensa_smp_poll(struct target *target)
int esp_xtensa_smp_resume(struct target *target, int current, target_addr_t address, int handle_breakpoints, int debug_execution)
void alive_sleep(uint64_t ms)
Definition: log.c:456
#define ERROR_FAIL
Definition: log.h:170
#define LOG_TARGET_ERROR(target, fmt_str,...)
Definition: log.h:158
#define LOG_TARGET_DEBUG(target, fmt_str,...)
Definition: log.h:149
#define LOG_ERROR(expr ...)
Definition: log.h:132
#define LOG_DEBUG(expr ...)
Definition: log.h:109
#define ERROR_OK
Definition: log.h:164
const struct command_registration semihosting_common_handlers[]
const struct command_registration smp_command_handlers[]
Definition: smp.c:153
#define foreach_smp_target(pos, head)
Definition: smp.h:15
const char * name
Definition: command.h:235
const char * usage
a string listing the options and arguments, required or optional
Definition: command.h:241
struct esp_xtensa_smp_common esp_xtensa_smp
Definition: esp32s3.c:69
Semihost calls handling operations.
int(* prepare)(struct target *target)
Callback called before handling semihost call.
int(* reset)(struct target *target)
struct target * target
Definition: target.h:214
This holds methods shared between all instances of a given target type.
Definition: target_type.h:26
const char * name
Name of this type of target.
Definition: target_type.h:31
Definition: target.h:116
struct jtag_tap * tap
Definition: target.h:119
enum target_debug_reason debug_reason
Definition: target.h:154
enum target_state state
Definition: target.h:157
struct list_head * smp_targets
Definition: target.h:188
unsigned int smp
Definition: target.h:187
bool reset_halt
Definition: target.h:144
Definition: psoc6.c:83
const struct xtensa_debug_ops * dbg_ops
int(* queue_enable)(struct xtensa_debug_module *dm)
enable operation
int(* queue_reg_read)(struct xtensa_debug_module *dm, enum xtensa_dm_pwr_reg reg, uint8_t *data, uint32_t clear)
register read.
Represents a generic Xtensa core.
Definition: xtensa.h:241
struct xtensa_debug_module dbg_mod
Definition: xtensa.h:245
bool suppress_dsr_errors
Definition: xtensa.h:271
int target_write_buffer(struct target *target, target_addr_t address, uint32_t size, const uint8_t *buffer)
Definition: target.c:2342
int target_read_buffer(struct target *target, target_addr_t address, uint32_t size, uint8_t *buffer)
Definition: target.c:2407
int target_write_u32(struct target *target, target_addr_t address, uint32_t value)
Definition: target.c:2641
int target_read_u32(struct target *target, target_addr_t address, uint32_t *value)
Definition: target.c:2550
int target_wait_state(struct target *target, enum target_state state, unsigned int ms)
Definition: target.c:3214
@ DBG_REASON_NOTHALTED
Definition: target.h:74
@ TARGET_RESET
Definition: target.h:57
@ TARGET_HALTED
Definition: target.h:56
@ TARGET_RUNNING
Definition: target.h:55
#define ERROR_TARGET_TIMEOUT
Definition: target.h:789
int64_t timeval_ms(void)
uint64_t target_addr_t
Definition: types.h:335
#define NULL
Definition: usb.h:16
const char * xtensa_get_gdb_arch(const struct target *target)
Definition: xtensa.c:3518
int xtensa_poll(struct target *target)
Definition: xtensa.c:2304
int xtensa_halt(struct target *target)
Definition: xtensa.c:1566
int xtensa_read_buffer(struct target *target, target_addr_t address, uint32_t count, uint8_t *buffer)
Definition: xtensa.c:2081
int xtensa_get_gdb_reg_list(struct target *target, struct reg **reg_list[], int *reg_list_size, enum target_register_class reg_class)
Definition: xtensa.c:1489
int xtensa_checksum_memory(struct target *target, target_addr_t address, uint32_t count, uint32_t *checksum)
Definition: xtensa.c:2298
int xtensa_examine(struct target *target)
Definition: xtensa.c:886
int xtensa_start_algorithm(struct target *target, int num_mem_params, struct mem_param *mem_params, int num_reg_params, struct reg_param *reg_params, target_addr_t entry_point, target_addr_t exit_point, void *arch_info)
Definition: xtensa.c:2712
int xtensa_resume(struct target *target, int current, target_addr_t address, int handle_breakpoints, int debug_execution)
Definition: xtensa.c:1673
int xtensa_write_buffer(struct target *target, target_addr_t address, uint32_t count, const uint8_t *buffer)
Definition: xtensa.c:2292
int xtensa_write_memory(struct target *target, target_addr_t address, uint32_t size, uint32_t count, const uint8_t *buffer)
Definition: xtensa.c:2087
int xtensa_mmu_is_enabled(struct target *target, int *enabled)
Definition: xtensa.c:1558
int xtensa_deassert_reset(struct target *target)
Definition: xtensa.c:1182
int xtensa_read_memory(struct target *target, target_addr_t address, uint32_t size, uint32_t count, uint8_t *buffer)
Definition: xtensa.c:1998
int xtensa_assert_reset(struct target *target)
Definition: xtensa.c:1161
int xtensa_run_algorithm(struct target *target, int num_mem_params, struct mem_param *mem_params, int num_reg_params, struct reg_param *reg_params, target_addr_t entry_point, target_addr_t exit_point, unsigned int timeout_ms, void *arch_info)
Definition: xtensa.c:2911
int xtensa_wait_algorithm(struct target *target, int num_mem_params, struct mem_param *mem_params, int num_reg_params, struct reg_param *reg_params, target_addr_t exit_point, unsigned int timeout_ms, void *arch_info)
Waits for an algorithm in the target.
Definition: xtensa.c:2803
static struct xtensa * target_to_xtensa(struct target *target)
Definition: xtensa.h:290
int xtensa_dm_queue_reg_read(struct xtensa_debug_module *dm, enum xtensa_dm_reg reg, uint8_t *value)
int xtensa_dm_queue_pwr_reg_write(struct xtensa_debug_module *dm, enum xtensa_dm_pwr_reg reg, uint32_t data)
int xtensa_dm_queue_pwr_reg_read(struct xtensa_debug_module *dm, enum xtensa_dm_pwr_reg reg, uint8_t *data, uint32_t clear)
int xtensa_dm_queue_reg_write(struct xtensa_debug_module *dm, enum xtensa_dm_reg reg, uint32_t value)
int xtensa_dm_queue_enable(struct xtensa_debug_module *dm)
static bool xtensa_dm_core_is_stalled(struct xtensa_debug_module *dm)