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esp32s3.c File Reference
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Data Structures

struct  esp32s3_common
 

Macros

#define ESP32_S3_DR_REG_SYSTEM_BASE   0x600c0000
 
#define ESP32_S3_EXTRAM_DATA_HIGH   0x3E000000
 
#define ESP32_S3_EXTRAM_DATA_LOW   0x3D000000
 
#define ESP32_S3_RTC_CNTL_SW_CPU_STALL_DEF   0x0
 
#define ESP32_S3_RTC_CNTL_SW_CPU_STALL_REG   (ESP32_S3_RTCCNTL_BASE + 0xBC)
 
#define ESP32_S3_RTC_DATA_HIGH   0x50002000
 
#define ESP32_S3_RTC_DATA_LOW   0x50000000
 
#define ESP32_S3_RTC_SLOW_MEM_BASE   ESP32_S3_RTC_DATA_LOW
 
#define ESP32_S3_RTCCNTL_BASE   0x60008000
 
#define ESP32_S3_RTCWDT_CFG   (ESP32_S3_RTCCNTL_BASE + ESP32_S3_RTCWDT_CFG_OFF)
 
#define ESP32_S3_RTCWDT_CFG_OFF   0x98
 
#define ESP32_S3_RTCWDT_PROTECT   (ESP32_S3_RTCCNTL_BASE + ESP32_S3_RTCWDT_PROTECT_OFF)
 
#define ESP32_S3_RTCWDT_PROTECT_OFF   0xB0
 
#define ESP32_S3_SWD_AUTO_FEED_EN_M   BIT(31)
 
#define ESP32_S3_SWD_CONF_OFF   0xB0
 
#define ESP32_S3_SWD_CONF_REG   (ESP32_S3_RTCCNTL_BASE + ESP32_S3_SWD_CONF_OFF)
 
#define ESP32_S3_SWD_WKEY_VALUE   0x8F1D312AU
 
#define ESP32_S3_SWD_WPROTECT_OFF   0xB4
 
#define ESP32_S3_SWD_WPROTECT_REG   (ESP32_S3_RTCCNTL_BASE + ESP32_S3_SWD_WPROTECT_OFF)
 
#define ESP32_S3_SYS_RAM_HIGH   (ESP32_S3_SYS_RAM_LOW + 0x10000000UL)
 
#define ESP32_S3_SYS_RAM_LOW   0x60000000UL
 
#define ESP32_S3_SYSTEM_CONTROL_CORE_1_CLKGATE_EN   BIT(1)
 
#define ESP32_S3_SYSTEM_CORE_1_CONTROL_0_REG   (ESP32_S3_DR_REG_SYSTEM_BASE + 0x014)
 
#define ESP32_S3_TIMG0_BASE   0x6001F000
 
#define ESP32_S3_TIMG0WDT_CFG0   (ESP32_S3_TIMG0_BASE + ESP32_S3_TIMGWDT_CFG0_OFF)
 
#define ESP32_S3_TIMG0WDT_PROTECT   (ESP32_S3_TIMG0_BASE + ESP32_S3_TIMGWDT_PROTECT_OFF)
 
#define ESP32_S3_TIMG1_BASE   0x60020000
 
#define ESP32_S3_TIMG1WDT_CFG0   (ESP32_S3_TIMG1_BASE + ESP32_S3_TIMGWDT_CFG0_OFF)
 
#define ESP32_S3_TIMG1WDT_PROTECT   (ESP32_S3_TIMG1_BASE + ESP32_S3_TIMGWDT_PROTECT_OFF)
 
#define ESP32_S3_TIMGWDT_CFG0_OFF   0x48
 
#define ESP32_S3_TIMGWDT_PROTECT_OFF   0x64
 
#define ESP32_S3_TRACEMEM_BLOCK_SZ   0x4000
 
#define ESP32_S3_WDT_WKEY_VALUE   0x50D83AA1
 

Functions

static int esp32s3_arch_state (struct target *target)
 
static int esp32s3_disable_wdts (struct target *target)
 
static int esp32s3_on_halt (struct target *target)
 
static int esp32s3_soc_reset (struct target *target)
 
static int esp32s3_target_create (struct target *target, Jim_Interp *interp)
 
static int esp32s3_target_init (struct command_context *cmd_ctx, struct target *target)
 
static int esp32s3_virt2phys (struct target *target, target_addr_t virtual, target_addr_t *physical)
 

Variables

static const struct esp_xtensa_smp_chip_ops esp32s3_chip_ops
 
static const struct command_registration esp32s3_command_handlers []
 
static const struct xtensa_debug_ops esp32s3_dbg_ops
 
static const struct xtensa_power_ops esp32s3_pwr_ops
 
static const uint8_t esp32s3_reset_stub_code []
 
static const struct esp_semihost_ops esp32s3_semihost_ops
 
struct target_type esp32s3_target
 Holds methods for Xtensa targets. More...
 

Macro Definition Documentation

◆ ESP32_S3_DR_REG_SYSTEM_BASE

#define ESP32_S3_DR_REG_SYSTEM_BASE   0x600c0000

Definition at line 60 of file esp32s3.c.

◆ ESP32_S3_EXTRAM_DATA_HIGH

#define ESP32_S3_EXTRAM_DATA_HIGH   0x3E000000

Definition at line 30 of file esp32s3.c.

◆ ESP32_S3_EXTRAM_DATA_LOW

#define ESP32_S3_EXTRAM_DATA_LOW   0x3D000000

Definition at line 29 of file esp32s3.c.

◆ ESP32_S3_RTC_CNTL_SW_CPU_STALL_DEF

#define ESP32_S3_RTC_CNTL_SW_CPU_STALL_DEF   0x0

Definition at line 66 of file esp32s3.c.

◆ ESP32_S3_RTC_CNTL_SW_CPU_STALL_REG

#define ESP32_S3_RTC_CNTL_SW_CPU_STALL_REG   (ESP32_S3_RTCCNTL_BASE + 0xBC)

Definition at line 65 of file esp32s3.c.

◆ ESP32_S3_RTC_DATA_HIGH

#define ESP32_S3_RTC_DATA_HIGH   0x50002000

Definition at line 28 of file esp32s3.c.

◆ ESP32_S3_RTC_DATA_LOW

#define ESP32_S3_RTC_DATA_LOW   0x50000000

Definition at line 27 of file esp32s3.c.

◆ ESP32_S3_RTC_SLOW_MEM_BASE

#define ESP32_S3_RTC_SLOW_MEM_BASE   ESP32_S3_RTC_DATA_LOW

Definition at line 33 of file esp32s3.c.

◆ ESP32_S3_RTCCNTL_BASE

#define ESP32_S3_RTCCNTL_BASE   0x60008000

Definition at line 45 of file esp32s3.c.

◆ ESP32_S3_RTCWDT_CFG

#define ESP32_S3_RTCWDT_CFG   (ESP32_S3_RTCCNTL_BASE + ESP32_S3_RTCWDT_CFG_OFF)

Definition at line 50 of file esp32s3.c.

◆ ESP32_S3_RTCWDT_CFG_OFF

#define ESP32_S3_RTCWDT_CFG_OFF   0x98

Definition at line 46 of file esp32s3.c.

◆ ESP32_S3_RTCWDT_PROTECT

#define ESP32_S3_RTCWDT_PROTECT   (ESP32_S3_RTCCNTL_BASE + ESP32_S3_RTCWDT_PROTECT_OFF)

Definition at line 51 of file esp32s3.c.

◆ ESP32_S3_RTCWDT_PROTECT_OFF

#define ESP32_S3_RTCWDT_PROTECT_OFF   0xB0

Definition at line 47 of file esp32s3.c.

◆ ESP32_S3_SWD_AUTO_FEED_EN_M

#define ESP32_S3_SWD_AUTO_FEED_EN_M   BIT(31)

Definition at line 54 of file esp32s3.c.

◆ ESP32_S3_SWD_CONF_OFF

#define ESP32_S3_SWD_CONF_OFF   0xB0

Definition at line 48 of file esp32s3.c.

◆ ESP32_S3_SWD_CONF_REG

#define ESP32_S3_SWD_CONF_REG   (ESP32_S3_RTCCNTL_BASE + ESP32_S3_SWD_CONF_OFF)

Definition at line 52 of file esp32s3.c.

◆ ESP32_S3_SWD_WKEY_VALUE

#define ESP32_S3_SWD_WKEY_VALUE   0x8F1D312AU

Definition at line 55 of file esp32s3.c.

◆ ESP32_S3_SWD_WPROTECT_OFF

#define ESP32_S3_SWD_WPROTECT_OFF   0xB4

Definition at line 49 of file esp32s3.c.

◆ ESP32_S3_SWD_WPROTECT_REG

#define ESP32_S3_SWD_WPROTECT_REG   (ESP32_S3_RTCCNTL_BASE + ESP32_S3_SWD_WPROTECT_OFF)

Definition at line 53 of file esp32s3.c.

◆ ESP32_S3_SYS_RAM_HIGH

#define ESP32_S3_SYS_RAM_HIGH   (ESP32_S3_SYS_RAM_LOW + 0x10000000UL)

Definition at line 32 of file esp32s3.c.

◆ ESP32_S3_SYS_RAM_LOW

#define ESP32_S3_SYS_RAM_LOW   0x60000000UL

Definition at line 31 of file esp32s3.c.

◆ ESP32_S3_SYSTEM_CONTROL_CORE_1_CLKGATE_EN

#define ESP32_S3_SYSTEM_CONTROL_CORE_1_CLKGATE_EN   BIT(1)

Definition at line 62 of file esp32s3.c.

◆ ESP32_S3_SYSTEM_CORE_1_CONTROL_0_REG

#define ESP32_S3_SYSTEM_CORE_1_CONTROL_0_REG   (ESP32_S3_DR_REG_SYSTEM_BASE + 0x014)

Definition at line 61 of file esp32s3.c.

◆ ESP32_S3_TIMG0_BASE

#define ESP32_S3_TIMG0_BASE   0x6001F000

Definition at line 37 of file esp32s3.c.

◆ ESP32_S3_TIMG0WDT_CFG0

#define ESP32_S3_TIMG0WDT_CFG0   (ESP32_S3_TIMG0_BASE + ESP32_S3_TIMGWDT_CFG0_OFF)

Definition at line 41 of file esp32s3.c.

◆ ESP32_S3_TIMG0WDT_PROTECT

#define ESP32_S3_TIMG0WDT_PROTECT   (ESP32_S3_TIMG0_BASE + ESP32_S3_TIMGWDT_PROTECT_OFF)

Definition at line 43 of file esp32s3.c.

◆ ESP32_S3_TIMG1_BASE

#define ESP32_S3_TIMG1_BASE   0x60020000

Definition at line 38 of file esp32s3.c.

◆ ESP32_S3_TIMG1WDT_CFG0

#define ESP32_S3_TIMG1WDT_CFG0   (ESP32_S3_TIMG1_BASE + ESP32_S3_TIMGWDT_CFG0_OFF)

Definition at line 42 of file esp32s3.c.

◆ ESP32_S3_TIMG1WDT_PROTECT

#define ESP32_S3_TIMG1WDT_PROTECT   (ESP32_S3_TIMG1_BASE + ESP32_S3_TIMGWDT_PROTECT_OFF)

Definition at line 44 of file esp32s3.c.

◆ ESP32_S3_TIMGWDT_CFG0_OFF

#define ESP32_S3_TIMGWDT_CFG0_OFF   0x48

Definition at line 39 of file esp32s3.c.

◆ ESP32_S3_TIMGWDT_PROTECT_OFF

#define ESP32_S3_TIMGWDT_PROTECT_OFF   0x64

Definition at line 40 of file esp32s3.c.

◆ ESP32_S3_TRACEMEM_BLOCK_SZ

#define ESP32_S3_TRACEMEM_BLOCK_SZ   0x4000

Definition at line 57 of file esp32s3.c.

◆ ESP32_S3_WDT_WKEY_VALUE

#define ESP32_S3_WDT_WKEY_VALUE   0x50D83AA1

Definition at line 36 of file esp32s3.c.

Function Documentation

◆ esp32s3_arch_state()

static int esp32s3_arch_state ( struct target *  target)
static

Definition at line 282 of file esp32s3.c.

References ERROR_OK.

◆ esp32s3_disable_wdts()

static int esp32s3_disable_wdts ( struct target *  target)
static

Definition at line 218 of file esp32s3.c.

References ERROR_OK, ESP32_S3_RTCWDT_CFG, ESP32_S3_RTCWDT_PROTECT, ESP32_S3_SWD_AUTO_FEED_EN_M, ESP32_S3_SWD_CONF_REG, ESP32_S3_SWD_WKEY_VALUE, ESP32_S3_SWD_WPROTECT_REG, ESP32_S3_TIMG0WDT_CFG0, ESP32_S3_TIMG0WDT_PROTECT, ESP32_S3_TIMG1WDT_CFG0, ESP32_S3_TIMG1WDT_PROTECT, ESP32_S3_WDT_WKEY_VALUE, LOG_ERROR, target_read_u32(), and target_write_u32().

Referenced by esp32s3_on_halt().

◆ esp32s3_on_halt()

static int esp32s3_on_halt ( struct target *  target)
static

Definition at line 274 of file esp32s3.c.

References ERROR_OK, esp32s3_disable_wdts(), and esp_xtensa_smp_on_halt().

◆ esp32s3_soc_reset()

static int esp32s3_soc_reset ( struct target *  target)
static

Definition at line 93 of file esp32s3.c.

References alive_sleep(), xtensa::dbg_mod, ERROR_OK, ERROR_TARGET_TIMEOUT, ESP32_S3_RTC_CNTL_SW_CPU_STALL_DEF, ESP32_S3_RTC_CNTL_SW_CPU_STALL_REG, ESP32_S3_RTC_SLOW_MEM_BASE, esp32s3_reset_stub_code, foreach_smp_target, LOG_DEBUG, LOG_ERROR, LOG_TARGET_DEBUG, LOG_TARGET_ERROR, target::reset_halt, target::smp, target::smp_targets, target::state, xtensa::suppress_dsr_errors, target_list::target, TARGET_HALTED, target_read_buffer(), TARGET_RESET, TARGET_RUNNING, target_to_xtensa(), target_wait_state(), target_write_buffer(), target_write_u32(), timeval_ms(), xtensa_assert_reset(), xtensa_deassert_reset(), xtensa_dm_core_is_stalled(), xtensa_halt(), xtensa_poll(), and xtensa_resume().

◆ esp32s3_target_create()

static int esp32s3_target_create ( struct target *  target,
Jim_Interp *  interp 
)
static

Definition at line 322 of file esp32s3.c.

◆ esp32s3_target_init()

static int esp32s3_target_init ( struct command_context *  cmd_ctx,
struct target *  target 
)
static

Definition at line 297 of file esp32s3.c.

◆ esp32s3_virt2phys()

static int esp32s3_virt2phys ( struct target *  target,
target_addr_t  virtual,
target_addr_t *  physical 
)
static

Definition at line 287 of file esp32s3.c.

References ERROR_FAIL, and ERROR_OK.

Variable Documentation

◆ esp32s3_chip_ops

const struct esp_xtensa_smp_chip_ops esp32s3_chip_ops
static
Initial value:
= {
.reset = esp32s3_soc_reset,
.on_halt = esp32s3_on_halt
}
esp32s3_soc_reset
static int esp32s3_soc_reset(struct target *target)
Definition: esp32s3.c:93
esp32s3_on_halt
static int esp32s3_on_halt(struct target *target)
Definition: esp32s3.c:274

Definition at line 297 of file esp32s3.c.

◆ esp32s3_command_handlers

const struct command_registration esp32s3_command_handlers[]
static
Initial value:
= {
{
.usage = "",
.chain = esp_xtensa_smp_command_handlers,
},
{
.name = "esp",
.usage = "",
.chain = esp32_apptrace_command_handlers,
},
{
.name = "esp32",
.usage = "",
.chain = smp_command_handlers,
},
{
.name = "arm",
.mode = COMMAND_ANY,
.help = "ARM Command Group",
.usage = "",
.chain = semihosting_common_handlers
},
COMMAND_REGISTRATION_DONE
}
COMMAND_REGISTRATION_DONE
#define COMMAND_REGISTRATION_DONE
Use this as the last entry in an array of command_registration records.
Definition: command.h:253
COMMAND_ANY
@ COMMAND_ANY
Definition: command.h:42
esp32_apptrace_command_handlers
const struct command_registration esp32_apptrace_command_handlers[]
Definition: esp32_apptrace.c:1606
esp_xtensa_smp_command_handlers
const struct command_registration esp_xtensa_smp_command_handlers[]
Definition: esp_xtensa_smp.c:1031
semihosting_common_handlers
const struct command_registration semihosting_common_handlers[]
Definition: semihosting_common.c:2115
smp_command_handlers
const struct command_registration smp_command_handlers[]
Definition: smp.c:153
command_registration::name
const char * name
Definition: command.h:235

Definition at line 322 of file esp32s3.c.

◆ esp32s3_dbg_ops

const struct xtensa_debug_ops esp32s3_dbg_ops
static
Initial value:
= {
.queue_enable = xtensa_dm_queue_enable,
.queue_reg_read = xtensa_dm_queue_reg_read,
.queue_reg_write = xtensa_dm_queue_reg_write
}
xtensa_dm_queue_reg_read
int xtensa_dm_queue_reg_read(struct xtensa_debug_module *dm, enum xtensa_dm_reg reg, uint8_t *value)
Definition: xtensa_debug_module.c:162
xtensa_dm_queue_reg_write
int xtensa_dm_queue_reg_write(struct xtensa_debug_module *dm, enum xtensa_dm_reg reg, uint32_t value)
Definition: xtensa_debug_module.c:181
xtensa_dm_queue_enable
int xtensa_dm_queue_enable(struct xtensa_debug_module *dm)
Definition: xtensa_debug_module.c:157

Definition at line 297 of file esp32s3.c.

◆ esp32s3_pwr_ops

const struct xtensa_power_ops esp32s3_pwr_ops
static
Initial value:
= {
.queue_reg_read = xtensa_dm_queue_pwr_reg_read,
.queue_reg_write = xtensa_dm_queue_pwr_reg_write
}
xtensa_dm_queue_pwr_reg_write
int xtensa_dm_queue_pwr_reg_write(struct xtensa_debug_module *dm, enum xtensa_dm_pwr_reg reg, uint32_t data)
Definition: xtensa_debug_module.c:224
xtensa_dm_queue_pwr_reg_read
int xtensa_dm_queue_pwr_reg_read(struct xtensa_debug_module *dm, enum xtensa_dm_pwr_reg reg, uint8_t *data, uint32_t clear)
Definition: xtensa_debug_module.c:197

Definition at line 297 of file esp32s3.c.

◆ esp32s3_reset_stub_code

const uint8_t esp32s3_reset_stub_code[]
static
Initial value:
= {
}

Definition at line 89 of file esp32s3.c.

Referenced by esp32s3_soc_reset().

◆ esp32s3_semihost_ops

const struct esp_semihost_ops esp32s3_semihost_ops
static
Initial value:
= {
.prepare = esp32s3_disable_wdts
}
esp32s3_disable_wdts
static int esp32s3_disable_wdts(struct target *target)
Definition: esp32s3.c:218

Definition at line 297 of file esp32s3.c.

◆ esp32s3_target

struct target_type esp32s3_target

Holds methods for Xtensa targets.

Definition at line 322 of file esp32s3.c.