OpenOCD
xtensa_debug_module.h
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1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 
3 /***************************************************************************
4  * Xtensa Debug Module (XDM) Support for OpenOCD *
5  * Copyright (C) 2020-2022 Cadence Design Systems, Inc. *
6  * Copyright (C) 2019 Espressif Systems Ltd. *
7  * Derived from original ESP8266 target. *
8  * Author: Angus Gratton gus@projectgus.com *
9  ***************************************************************************/
10 
11 #ifndef OPENOCD_TARGET_XTENSA_DEBUG_MODULE_H
12 #define OPENOCD_TARGET_XTENSA_DEBUG_MODULE_H
13 
14 #include <jtag/jtag.h>
15 #include <target/arm_adi_v5.h>
16 #include <helper/bits.h>
17 #include <target/target.h>
18 
19 /* Virtual IDs for using with xtensa_power_ops API */
21  XDMREG_PWRCTL = 0x00,
24 };
25 
26 /* Debug Module Power Register offsets within APB */
28  uint16_t apb;
29 };
30 
31 /* Debug Module Power Register offset structure; must include XDMREG_PWRNUM entries */
32 #define XTENSA_DM_PWR_REG_OFFSETS { \
33  /* Power/Reset Registers */ \
34  { .apb = 0x3020 }, /* XDMREG_PWRCTL */ \
35  { .apb = 0x3024 }, /* XDMREG_PWRSTAT */ \
36 }
37 
38 /*
39  From the manual:
40  To properly use Debug registers through JTAG, software must ensure that:
41  - Tap is out of reset
42  - Xtensa Debug Module is out of reset
43  - Other bits of PWRCTL are set to their desired values, and finally
44  - JtagDebugUse transitions from 0 to 1
45  The bit must continue to be 1 in order for JTAG accesses to the Debug
46  Module to happen correctly. When it is set, any write to this bit clears it.
47  Either don't access it, or re-write it to 1 so JTAG accesses continue.
48 */
49 #define PWRCTL_JTAGDEBUGUSE(x) (((x)->dbg_mod.dap) ? (0) : BIT(7))
50 #define PWRCTL_DEBUGRESET(x) (((x)->dbg_mod.dap) ? BIT(28) : BIT(6))
51 #define PWRCTL_CORERESET(x) (((x)->dbg_mod.dap) ? BIT(16) : BIT(4))
52 #define PWRCTL_DEBUGWAKEUP(x) (((x)->dbg_mod.dap) ? BIT(12) : BIT(2))
53 #define PWRCTL_MEMWAKEUP(x) (((x)->dbg_mod.dap) ? BIT(8) : BIT(1))
54 #define PWRCTL_COREWAKEUP(x) (((x)->dbg_mod.dap) ? BIT(0) : BIT(0))
55 
56 #define PWRSTAT_DEBUGWASRESET_DM(d) (((d)->dap) ? BIT(28) : BIT(6))
57 #define PWRSTAT_COREWASRESET_DM(d) (((d)->dap) ? BIT(16) : BIT(4))
58 #define PWRSTAT_DEBUGWASRESET(x) (PWRSTAT_DEBUGWASRESET_DM(&((x)->dbg_mod)))
59 #define PWRSTAT_COREWASRESET(x) (PWRSTAT_COREWASRESET_DM(&((x)->dbg_mod)))
60 #define PWRSTAT_CORESTILLNEEDED(x) (((x)->dbg_mod.dap) ? BIT(4) : BIT(3))
61 #define PWRSTAT_DEBUGDOMAINON(x) (((x)->dbg_mod.dap) ? BIT(12) : BIT(2))
62 #define PWRSTAT_MEMDOMAINON(x) (((x)->dbg_mod.dap) ? BIT(8) : BIT(1))
63 #define PWRSTAT_COREDOMAINON(x) (((x)->dbg_mod.dap) ? BIT(0) : BIT(0))
64 
65 /* Virtual IDs for using with xtensa_debug_ops API */
67  /* TRAX Registers */
68  XDMREG_TRAXID = 0x00,
78  XDMREG_DEBUGPC,/*Unsupported, undocumented, may not be present*/
95 
96  /* Performance Monitor Registers */
123 
124  /* OCD Registers */
140 
141  /* Misc Registers */
143 
144  /* CoreSight Registers */
165 
166  XDMREG_NUM
167 };
168 
169 /* Debug Module Register offsets within Nexus (NAR) or APB */
171  uint8_t nar;
172  uint16_t apb;
173 };
174 
175 /* Debug Module Register offset structure; must include XDMREG_NUM entries */
176 #define XTENSA_DM_REG_OFFSETS { \
177  /* TRAX Registers */ \
178  { .nar = 0x00, .apb = 0x0000 }, /* XDMREG_TRAXID */ \
179  { .nar = 0x01, .apb = 0x0004 }, /* XDMREG_TRAXCTRL */ \
180  { .nar = 0x02, .apb = 0x0008 }, /* XDMREG_TRAXSTAT */ \
181  { .nar = 0x03, .apb = 0x000c }, /* XDMREG_TRAXDATA */ \
182  { .nar = 0x04, .apb = 0x0010 }, /* XDMREG_TRAXADDR */ \
183  { .nar = 0x05, .apb = 0x0014 }, /* XDMREG_TRIGGERPC */ \
184  { .nar = 0x06, .apb = 0x0018 }, /* XDMREG_PCMATCHCTRL */ \
185  { .nar = 0x07, .apb = 0x001c }, /* XDMREG_DELAYCNT */ \
186  { .nar = 0x08, .apb = 0x0020 }, /* XDMREG_MEMADDRSTART */ \
187  { .nar = 0x09, .apb = 0x0024 }, /* XDMREG_MEMADDREND */ \
188  { .nar = 0x0f, .apb = 0x003c }, /* XDMREG_DEBUGPC */ \
189  { .nar = 0x10, .apb = 0x0040 }, /* XDMREG_EXTTIMELO */ \
190  { .nar = 0x11, .apb = 0x0044 }, /* XDMREG_EXTTIMEHI */ \
191  { .nar = 0x12, .apb = 0x0048 }, /* XDMREG_TRAXRSVD48 */ \
192  { .nar = 0x13, .apb = 0x004c }, /* XDMREG_TRAXRSVD4C */ \
193  { .nar = 0x14, .apb = 0x0050 }, /* XDMREG_TRAXRSVD50 */ \
194  { .nar = 0x15, .apb = 0x0054 }, /* XDMREG_TRAXRSVD54 */ \
195  { .nar = 0x16, .apb = 0x0058 }, /* XDMREG_TRAXRSVD58 */ \
196  { .nar = 0x17, .apb = 0x005c }, /* XDMREG_TRAXRSVD5C */ \
197  { .nar = 0x18, .apb = 0x0060 }, /* XDMREG_TRAXRSVD60 */ \
198  { .nar = 0x19, .apb = 0x0064 }, /* XDMREG_TRAXRSVD64 */ \
199  { .nar = 0x1a, .apb = 0x0068 }, /* XDMREG_TRAXRSVD68 */ \
200  { .nar = 0x1b, .apb = 0x006c }, /* XDMREG_TRAXRSVD6C */ \
201  { .nar = 0x1c, .apb = 0x0070 }, /* XDMREG_TRAXRSVD70 */ \
202  { .nar = 0x1d, .apb = 0x0074 }, /* XDMREG_TRAXRSVD74 */ \
203  { .nar = 0x1e, .apb = 0x0078 }, /* XDMREG_CONFIGID0 */ \
204  { .nar = 0x1f, .apb = 0x007c }, /* XDMREG_CONFIGID1 */ \
205  \
206  /* Performance Monitor Registers */ \
207  { .nar = 0x20, .apb = 0x1000 }, /* XDMREG_PMG */ \
208  { .nar = 0x24, .apb = 0x1010 }, /* XDMREG_INTPC */ \
209  { .nar = 0x28, .apb = 0x1080 }, /* XDMREG_PM0 */ \
210  { .nar = 0x29, .apb = 0x1084 }, /* XDMREG_PM1 */ \
211  { .nar = 0x2a, .apb = 0x1088 }, /* XDMREG_PM2 */ \
212  { .nar = 0x2b, .apb = 0x108c }, /* XDMREG_PM3 */ \
213  { .nar = 0x2c, .apb = 0x1090 }, /* XDMREG_PM4 */ \
214  { .nar = 0x2d, .apb = 0x1094 }, /* XDMREG_PM5 */ \
215  { .nar = 0x2e, .apb = 0x1098 }, /* XDMREG_PM6 */ \
216  { .nar = 0x2f, .apb = 0x109c }, /* XDMREG_PM7 */ \
217  { .nar = 0x30, .apb = 0x1100 }, /* XDMREG_PMCTRL0 */ \
218  { .nar = 0x31, .apb = 0x1104 }, /* XDMREG_PMCTRL1 */ \
219  { .nar = 0x32, .apb = 0x1108 }, /* XDMREG_PMCTRL2 */ \
220  { .nar = 0x33, .apb = 0x110c }, /* XDMREG_PMCTRL3 */ \
221  { .nar = 0x34, .apb = 0x1110 }, /* XDMREG_PMCTRL4 */ \
222  { .nar = 0x35, .apb = 0x1114 }, /* XDMREG_PMCTRL5 */ \
223  { .nar = 0x36, .apb = 0x1118 }, /* XDMREG_PMCTRL6 */ \
224  { .nar = 0x37, .apb = 0x111c }, /* XDMREG_PMCTRL7 */ \
225  { .nar = 0x38, .apb = 0x1180 }, /* XDMREG_PMSTAT0 */ \
226  { .nar = 0x39, .apb = 0x1184 }, /* XDMREG_PMSTAT1 */ \
227  { .nar = 0x3a, .apb = 0x1188 }, /* XDMREG_PMSTAT2 */ \
228  { .nar = 0x3b, .apb = 0x118c }, /* XDMREG_PMSTAT3 */ \
229  { .nar = 0x3c, .apb = 0x1190 }, /* XDMREG_PMSTAT4 */ \
230  { .nar = 0x3d, .apb = 0x1194 }, /* XDMREG_PMSTAT5 */ \
231  { .nar = 0x3e, .apb = 0x1198 }, /* XDMREG_PMSTAT6 */ \
232  { .nar = 0x3f, .apb = 0x119c }, /* XDMREG_PMSTAT7 */ \
233  \
234  /* OCD Registers */ \
235  { .nar = 0x40, .apb = 0x2000 }, /* XDMREG_OCDID */ \
236  { .nar = 0x42, .apb = 0x2008 }, /* XDMREG_DCRCLR */ \
237  { .nar = 0x43, .apb = 0x200c }, /* XDMREG_DCRSET */ \
238  { .nar = 0x44, .apb = 0x2010 }, /* XDMREG_DSR */ \
239  { .nar = 0x45, .apb = 0x2014 }, /* XDMREG_DDR */ \
240  { .nar = 0x46, .apb = 0x2018 }, /* XDMREG_DDREXEC */ \
241  { .nar = 0x47, .apb = 0x201c }, /* XDMREG_DIR0EXEC */ \
242  { .nar = 0x48, .apb = 0x2020 }, /* XDMREG_DIR0 */ \
243  { .nar = 0x49, .apb = 0x2024 }, /* XDMREG_DIR1 */ \
244  { .nar = 0x4a, .apb = 0x2028 }, /* XDMREG_DIR2 */ \
245  { .nar = 0x4b, .apb = 0x202c }, /* XDMREG_DIR3 */ \
246  { .nar = 0x4c, .apb = 0x2030 }, /* XDMREG_DIR4 */ \
247  { .nar = 0x4d, .apb = 0x2034 }, /* XDMREG_DIR5 */ \
248  { .nar = 0x4e, .apb = 0x2038 }, /* XDMREG_DIR6 */ \
249  { .nar = 0x4f, .apb = 0x203c }, /* XDMREG_DIR7 */ \
250  \
251  /* Misc Registers */ \
252  { .nar = 0x5a, .apb = 0x3028 }, /* XDMREG_ERISTAT */ \
253  \
254  /* CoreSight Registers */ \
255  { .nar = 0x60, .apb = 0x3f00 }, /* XDMREG_ITCTRL */ \
256  { .nar = 0x68, .apb = 0x3fa0 }, /* XDMREG_CLAIMSET */ \
257  { .nar = 0x69, .apb = 0x3fa4 }, /* XDMREG_CLAIMCLR */ \
258  { .nar = 0x6c, .apb = 0x3fb0 }, /* XDMREG_LOCKACCESS */ \
259  { .nar = 0x6d, .apb = 0x3fb4 }, /* XDMREG_LOCKSTATUS */ \
260  { .nar = 0x6e, .apb = 0x3fb8 }, /* XDMREG_AUTHSTATUS */ \
261  { .nar = 0x72, .apb = 0x3fc8 }, /* XDMREG_DEVID */ \
262  { .nar = 0x73, .apb = 0x3fcc }, /* XDMREG_DEVTYPE */ \
263  { .nar = 0x74, .apb = 0x3fd0 }, /* XDMREG_PERID4 */ \
264  { .nar = 0x75, .apb = 0x3fd4 }, /* XDMREG_PERID5 */ \
265  { .nar = 0x76, .apb = 0x3fd8 }, /* XDMREG_PERID6 */ \
266  { .nar = 0x77, .apb = 0x3fdc }, /* XDMREG_PERID7 */ \
267  { .nar = 0x78, .apb = 0x3fe0 }, /* XDMREG_PERID0 */ \
268  { .nar = 0x79, .apb = 0x3fe4 }, /* XDMREG_PERID1 */ \
269  { .nar = 0x7a, .apb = 0x3fe8 }, /* XDMREG_PERID2 */ \
270  { .nar = 0x7b, .apb = 0x3fec }, /* XDMREG_PERID3 */ \
271  { .nar = 0x7c, .apb = 0x3ff0 }, /* XDMREG_COMPID0 */ \
272  { .nar = 0x7d, .apb = 0x3ff4 }, /* XDMREG_COMPID1 */ \
273  { .nar = 0x7e, .apb = 0x3ff8 }, /* XDMREG_COMPID2 */ \
274  { .nar = 0x7f, .apb = 0x3ffc }, /* XDMREG_COMPID3 */ \
275 }
276 
277 #define XTENSA_DM_APB_ALIGN 0x4000
278 
279 /* OCD registers, bit definitions */
280 #define OCDDCR_ENABLEOCD BIT(0)
281 #define OCDDCR_DEBUGINTERRUPT BIT(1)
282 #define OCDDCR_INTERRUPTALLCONDS BIT(2)
283 #define OCDDCR_STEPREQUEST BIT(3) /* NX only */
284 #define OCDDCR_BREAKINEN BIT(16)
285 #define OCDDCR_BREAKOUTEN BIT(17)
286 #define OCDDCR_DEBUGSWACTIVE BIT(20)
287 #define OCDDCR_RUNSTALLINEN BIT(21)
288 #define OCDDCR_DEBUGMODEOUTEN BIT(22)
289 #define OCDDCR_BREAKOUTITO BIT(24)
290 #define OCDDCR_BREAKACKITO BIT(25)
291 
292 #define OCDDSR_EXECDONE BIT(0)
293 #define OCDDSR_EXECEXCEPTION BIT(1)
294 #define OCDDSR_EXECBUSY BIT(2)
295 #define OCDDSR_EXECOVERRUN BIT(3)
296 #define OCDDSR_STOPPED BIT(4)
297 #define OCDDSR_STOPCAUSE (0xF << 5) /* NX only */
298 #define OCDDSR_STOPCAUSE_SHIFT (5) /* NX only */
299 #define OCDDSR_COREWROTEDDR BIT(10)
300 #define OCDDSR_COREREADDDR BIT(11)
301 #define OCDDSR_HOSTWROTEDDR BIT(14)
302 #define OCDDSR_HOSTREADDDR BIT(15)
303 #define OCDDSR_DEBUGPENDBREAK BIT(16)
304 #define OCDDSR_DEBUGPENDHOST BIT(17)
305 #define OCDDSR_DEBUGPENDTRAX BIT(18)
306 #define OCDDSR_DEBUGINTBREAK BIT(20)
307 #define OCDDSR_DEBUGINTHOST BIT(21)
308 #define OCDDSR_DEBUGINTTRAX BIT(22)
309 #define OCDDSR_RUNSTALLTOGGLE BIT(23)
310 #define OCDDSR_RUNSTALLSAMPLE BIT(24)
311 #define OCDDSR_BREACKOUTACKITI BIT(25)
312 #define OCDDSR_BREAKINITI BIT(26)
313 #define OCDDSR_DBGMODPOWERON BIT(31)
314 
315 /* NX stop cause */
316 #define OCDDSR_STOPCAUSE_DI (0) /* Debug Interrupt */
317 #define OCDDSR_STOPCAUSE_SS (1) /* Single-step completed */
318 #define OCDDSR_STOPCAUSE_IB (2) /* HW breakpoint (IBREAKn match) */
319 #define OCDDSR_STOPCAUSE_B1 (4) /* SW breakpoint (BREAK.1 instruction) */
320 #define OCDDSR_STOPCAUSE_BN (5) /* SW breakpoint (BREAK.N instruction) */
321 #define OCDDSR_STOPCAUSE_B (6) /* SW breakpoint (BREAK instruction) */
322 #define OCDDSR_STOPCAUSE_DB0 (8) /* HW watchpoint (DBREAK0 match) */
323 #define OCDDSR_STOPCAUSE_DB1 (9) /* HW watchpoint (DBREAK0 match) */
324 
325 /* LX stop cause */
326 #define DEBUGCAUSE_IC BIT(0) /* ICOUNT exception */
327 #define DEBUGCAUSE_IB BIT(1) /* IBREAK exception */
328 #define DEBUGCAUSE_DB BIT(2) /* DBREAK exception */
329 #define DEBUGCAUSE_BI BIT(3) /* BREAK instruction encountered */
330 #define DEBUGCAUSE_BN BIT(4) /* BREAK.N instruction encountered */
331 #define DEBUGCAUSE_DI BIT(5) /* Debug Interrupt */
332 #define DEBUGCAUSE_VALID BIT(31) /* Pseudo-value to trigger reread (NX only) */
333 
334 /* TRAXID */
335 #define TRAXID_PRODNO_TRAX 0 /* TRAXID.PRODNO value for TRAX module */
336 #define TRAXID_PRODNO_SHIFT 28
337 #define TRAXID_PRODNO_MASK 0xf
338 
339 #define TRAXCTRL_TREN BIT(0) /* Trace enable. Tracing starts on 0->1 */
340 #define TRAXCTRL_TRSTP BIT(1) /* Trace Stop. Make 1 to stop trace. */
341 #define TRAXCTRL_PCMEN BIT(2) /* PC match enable */
342 #define TRAXCTRL_PTIEN BIT(4) /* Processor-trigger enable */
343 #define TRAXCTRL_CTIEN BIT(5) /* Cross-trigger enable */
344 #define TRAXCTRL_TMEN BIT(7) /* Tracemem Enable. Always set. */
345 #define TRAXCTRL_CNTU BIT(9) /* Post-stop-trigger countdown units; selects when DelayCount-- happens.
346  * 0 - every 32-bit word written to tracemem, 1 - every cpu instruction */
347 #define TRAXCTRL_TSEN BIT(11) /* Undocumented/deprecated? */
348 #define TRAXCTRL_SMPER_SHIFT 12 /* Send sync every 2^(9-smper) messages. 7=reserved, 0=no sync msg */
349 #define TRAXCTRL_SMPER_MASK 0x07 /* Synchronization message period */
350 #define TRAXCTRL_PTOWT BIT(16) /* Processor Trigger Out (OCD halt) enabled when stop triggered */
351 #define TRAXCTRL_PTOWS BIT(17) /* Processor Trigger Out (OCD halt) enabled when trace stop completes */
352 #define TRAXCTRL_CTOWT BIT(20) /* Cross-trigger Out enabled when stop triggered */
353 #define TRAXCTRL_CTOWS BIT(21) /* Cross-trigger Out enabled when trace stop completes */
354 #define TRAXCTRL_ITCTO BIT(22) /* Integration mode: cross-trigger output */
355 #define TRAXCTRL_ITCTIA BIT(23) /* Integration mode: cross-trigger ack */
356 #define TRAXCTRL_ITATV BIT(24) /* replaces ATID when in integration mode: ATVALID output */
357 #define TRAXCTRL_ATID_MASK 0x7F /* ARB source ID */
358 #define TRAXCTRL_ATID_SHIFT 24
359 #define TRAXCTRL_ATEN BIT(31) /* ATB interface enable */
360 
361 #define TRAXSTAT_TRACT BIT(0) /* Trace active flag. */
362 #define TRAXSTAT_TRIG BIT(1) /* Trace stop trigger. Clears on TREN 1->0 */
363 #define TRAXSTAT_PCMTG BIT(2) /* Stop trigger caused by PC match. Clears on TREN 1->0 */
364 #define TRAXSTAT_PJTR BIT(3) /* JTAG transaction result. 1=err in preceding jtag transaction. */
365 #define TRAXSTAT_PTITG BIT(4) /* Stop trigger caused by Processor Trigger Input.Clears on TREN 1->0 */
366 #define TRAXSTAT_CTITG BIT(5) /* Stop trigger caused by Cross-Trigger Input. Clears on TREN 1->0 */
367 #define TRAXSTAT_MEMSZ_SHIFT 8 /* Traceram size inducator. Usable trace ram is 2^MEMSZ bytes. */
368 #define TRAXSTAT_MEMSZ_MASK 0x1F
369 #define TRAXSTAT_PTO BIT(16) /* Processor Trigger Output: current value */
370 #define TRAXSTAT_CTO BIT(17) /* Cross-Trigger Output: current value */
371 #define TRAXSTAT_ITCTOA BIT(22) /* Cross-Trigger Out Ack: current value */
372 #define TRAXSTAT_ITCTI BIT(23) /* Cross-Trigger Input: current value */
373 #define TRAXSTAT_ITATR BIT(24) /* ATREADY Input: current value */
374 
375 #define TRAXADDR_TADDR_SHIFT 0 /* Trax memory address, in 32-bit words. */
376 #define TRAXADDR_TADDR_MASK 0x1FFFFF /* Actually is only as big as the trace buffer size max addr. */
377 #define TRAXADDR_TWRAP_SHIFT 21 /* Amount of times TADDR has overflown */
378 #define TRAXADDR_TWRAP_MASK 0x3FF
379 #define TRAXADDR_TWSAT BIT(31) /* 1 if TWRAP has overflown, clear by disabling tren.*/
380 
381 #define PCMATCHCTRL_PCML_SHIFT 0 /* Amount of lower bits to ignore in pc trigger register */
382 #define PCMATCHCTRL_PCML_MASK 0x1F
383 #define PCMATCHCTRL_PCMS BIT(31) /* PC Match Sense, 0-match when procs PC is in-range, 1-match when
384  * out-of-range */
385 
386 #define XTENSA_MAX_PERF_COUNTERS 2
387 #define XTENSA_MAX_PERF_SELECT 32
388 #define XTENSA_MAX_PERF_MASK 0xffff
389 
390 #define XTENSA_STOPMASK_DISABLED UINT32_MAX
391 
393 
396  int (*queue_enable)(struct xtensa_debug_module *dm);
398  int (*queue_reg_read)(struct xtensa_debug_module *dm, enum xtensa_dm_reg reg, uint8_t *data);
400  int (*queue_reg_write)(struct xtensa_debug_module *dm, enum xtensa_dm_reg reg, uint32_t data);
401 };
402 
403 /* Xtensa power registers are 8 bits wide on JTAG interfaces but 32 bits wide
404  * when accessed via APB/DAP. In order to use DAP queuing APIs (for optimal
405  * performance), the XDM power register APIs take 32-bit register params.
406  */
409  int (*queue_reg_read)(struct xtensa_debug_module *dm, enum xtensa_dm_pwr_reg reg, uint8_t *data,
410  uint32_t clear);
412  int (*queue_reg_write)(struct xtensa_debug_module *dm, enum xtensa_dm_pwr_reg reg, uint32_t data);
413 };
414 
415 typedef uint32_t xtensa_pwrstat_t;
416 typedef uint32_t xtensa_ocdid_t;
417 typedef uint32_t xtensa_dsr_t;
418 typedef uint32_t xtensa_traxstat_t;
419 
423  /* TODO: do not need to keep previous status to detect that core or debug module has been
424  * reset, */
425  /* we can clear PWRSTAT_DEBUGWASRESET and PWRSTAT_COREWASRESET after reading will do
426  * the job; */
427  /* upon next reet those bits will be set again. So we can get rid of
428  * xtensa_dm_power_status_cache_reset() and xtensa_dm_power_status_cache(). */
430 };
431 
432 struct xtensa_core_status {
434 };
435 
437  uint32_t ctrl;
438  uint32_t memaddr_start;
439  uint32_t memaddr_end;
440  uint32_t addr;
441 };
442 
443 struct xtensa_trace_status {
445 };
446 
448  uint32_t stoppc;
450  uint32_t after;
451  uint32_t stopmask; /* UINT32_MAX: disable PC match option */
452 };
453 
455  int select;
456  uint32_t mask;
457  int kernelcnt;
458  int tracelevel;
459 };
460 
462  uint64_t value;
463  bool overflow;
464 };
465 
467  const struct xtensa_power_ops *pwr_ops;
468  const struct xtensa_debug_ops *dbg_ops;
469 
470  /* Either JTAG or DAP structures will be populated */
471  struct jtag_tap *tap;
472  void (*queue_tdi_idle)(struct target *target);
473  void *queue_tdi_idle_arg;
474 
475  /* For targets conforming to ARM Debug Interface v5,
476  * "dap" references the Debug Access Port (DAP)
477  * used to make requests to the target;
478  * "debug_ap" is AP instance connected to processor
479  */
480  struct adiv5_dap *dap;
482  int debug_apsel;
483  uint32_t ap_offset;
484 };
485 
487  const struct xtensa_power_ops *pwr_ops;
488  const struct xtensa_debug_ops *dbg_ops;
489 
490  /* Either JTAG or DAP structures will be populated */
491  struct jtag_tap *tap;
492  void (*queue_tdi_idle)(struct target *target);
493  void *queue_tdi_idle_arg;
494 
495  /* DAP struct; AP instance connected to processor */
496  struct adiv5_dap *dap;
497  struct adiv5_ap *debug_ap;
498  int debug_apsel;
499 
503  uint32_t ap_offset;
504 };
505 
506 int xtensa_dm_init(struct xtensa_debug_module *dm, const struct xtensa_debug_module_config *cfg);
507 void xtensa_dm_deinit(struct xtensa_debug_module *dm);
508 int xtensa_dm_poll(struct xtensa_debug_module *dm);
509 int xtensa_dm_examine(struct xtensa_debug_module *dm);
511 int xtensa_dm_queue_reg_read(struct xtensa_debug_module *dm, enum xtensa_dm_reg reg, uint8_t *value);
512 int xtensa_dm_queue_reg_write(struct xtensa_debug_module *dm, enum xtensa_dm_reg reg, uint32_t value);
514  enum xtensa_dm_pwr_reg reg,
515  uint8_t *data,
516  uint32_t clear);
518  enum xtensa_dm_pwr_reg reg,
519  uint32_t data);
520 
521 static inline int xtensa_dm_queue_execute(struct xtensa_debug_module *dm)
522 {
523  return dm->dap ? dap_run(dm->dap) : jtag_execute_queue();
524 }
525 
526 static inline void xtensa_dm_queue_tdi_idle(struct xtensa_debug_module *dm)
527 {
528  if (dm->queue_tdi_idle)
530 }
531 
532 int xtensa_dm_power_status_read(struct xtensa_debug_module *dm, uint32_t clear);
533 static inline void xtensa_dm_power_status_cache_reset(struct xtensa_debug_module *dm)
534 {
536 }
537 static inline void xtensa_dm_power_status_cache(struct xtensa_debug_module *dm)
538 {
540 }
542 {
543  return dm->power_status.stat;
544 }
545 
550 {
551  return dm->core_status.dsr;
552 }
553 
554 int xtensa_dm_read(struct xtensa_debug_module *dm, uint32_t addr, uint32_t *val);
555 int xtensa_dm_write(struct xtensa_debug_module *dm, uint32_t addr, uint32_t val);
556 
559 {
560  return dm->device_id;
561 }
562 
564 int xtensa_dm_trace_stop(struct xtensa_debug_module *dm, bool pto_enable);
567 int xtensa_dm_trace_data_read(struct xtensa_debug_module *dm, uint8_t *dest, uint32_t size);
568 
569 static inline bool xtensa_dm_is_online(struct xtensa_debug_module *dm)
570 {
571  int res = xtensa_dm_device_id_read(dm);
572  if (res != ERROR_OK)
573  return false;
574  return dm->device_id != 0xffffffff && dm->device_id != 0;
575 }
576 
577 static inline bool xtensa_dm_tap_was_reset(struct xtensa_debug_module *dm)
578 {
579  return !(dm->power_status.prev_stat & PWRSTAT_DEBUGWASRESET_DM(dm)) &&
581 }
582 
583 static inline bool xtensa_dm_core_was_reset(struct xtensa_debug_module *dm)
584 {
585  return !(dm->power_status.prev_stat & PWRSTAT_COREWASRESET_DM(dm)) &&
587 }
588 
589 static inline bool xtensa_dm_core_is_stalled(struct xtensa_debug_module *dm)
590 {
592 }
593 
594 static inline bool xtensa_dm_is_powered(struct xtensa_debug_module *dm)
595 {
596  return dm->core_status.dsr & OCDDSR_DBGMODPOWERON;
597 }
598 
599 int xtensa_dm_perfmon_enable(struct xtensa_debug_module *dm, int counter_id,
600  const struct xtensa_perfmon_config *config);
601 int xtensa_dm_perfmon_dump(struct xtensa_debug_module *dm, int counter_id,
602  struct xtensa_perfmon_result *out_result);
603 
604 #endif /* OPENOCD_TARGET_XTENSA_DEBUG_MODULE_H */
This defines formats and data structures used to talk to ADIv5 entities.
static int dap_run(struct adiv5_dap *dap)
Perform all queued DAP operations, and clear any errors posted in the CTRL_STAT register when they ar...
Definition: arm_adi_v5.h:648
int jtag_execute_queue(void)
For software FIFO implementations, the queued commands can be executed during this call or earlier.
Definition: jtag/core.c:1037
The JTAG interface can be implemented with a software or hardware fifo.
#define ERROR_OK
Definition: log.h:164
uint8_t bits[QN908X_FLASH_MAX_BLOCKS *QN908X_FLASH_PAGES_PER_BLOCK/8]
Definition: qn908x.c:0
target_addr_t addr
Start address to search for the control block.
Definition: rtt/rtt.c:28
struct target * target
Definition: rtt/rtt.c:26
size_t size
Size of the control block search area.
Definition: rtt/rtt.c:30
This represents an ARM Debug Interface (v5) Access Port (AP).
Definition: arm_adi_v5.h:250
This represents an ARM Debug Interface (v5) Debug Access Port (DAP).
Definition: arm_adi_v5.h:348
Definition: jtag.h:101
Definition: register.h:111
Definition: target.h:116
void(* queue_tdi_idle)(struct target *target)
const struct xtensa_debug_ops * dbg_ops
const struct xtensa_power_ops * pwr_ops
struct xtensa_power_status power_status
void(* queue_tdi_idle)(struct target *target)
const struct xtensa_power_ops * pwr_ops
struct jtag_tap * tap
struct xtensa_core_status core_status
struct adiv5_dap * dap
const struct xtensa_debug_ops * dbg_ops
struct adiv5_ap * debug_ap
int(* queue_reg_write)(struct xtensa_debug_module *dm, enum xtensa_dm_reg reg, uint32_t data)
register write.
int(* queue_reg_read)(struct xtensa_debug_module *dm, enum xtensa_dm_reg reg, uint8_t *data)
register read.
int(* queue_enable)(struct xtensa_debug_module *dm)
enable operation
int(* queue_reg_read)(struct xtensa_debug_module *dm, enum xtensa_dm_pwr_reg reg, uint8_t *data, uint32_t clear)
register read.
int(* queue_reg_write)(struct xtensa_debug_module *dm, enum xtensa_dm_pwr_reg reg, uint32_t data)
register write.
xtensa_pwrstat_t stath
xtensa_pwrstat_t prev_stat
xtensa_traxstat_t stat
uint8_t status[4]
Definition: vdebug.c:17
static void xtensa_dm_power_status_cache(struct xtensa_debug_module *dm)
int xtensa_dm_trace_status_read(struct xtensa_debug_module *dm, struct xtensa_trace_status *status)
int xtensa_dm_queue_reg_read(struct xtensa_debug_module *dm, enum xtensa_dm_reg reg, uint8_t *value)
int xtensa_dm_queue_pwr_reg_write(struct xtensa_debug_module *dm, enum xtensa_dm_pwr_reg reg, uint32_t data)
static xtensa_ocdid_t xtensa_dm_device_id_get(struct xtensa_debug_module *dm)
int xtensa_dm_trace_start(struct xtensa_debug_module *dm, struct xtensa_trace_start_config *cfg)
int xtensa_dm_trace_stop(struct xtensa_debug_module *dm, bool pto_enable)
int xtensa_dm_device_id_read(struct xtensa_debug_module *dm)
int xtensa_dm_queue_pwr_reg_read(struct xtensa_debug_module *dm, enum xtensa_dm_pwr_reg reg, uint8_t *data, uint32_t clear)
int xtensa_dm_write(struct xtensa_debug_module *dm, uint32_t addr, uint32_t val)
int xtensa_dm_queue_reg_write(struct xtensa_debug_module *dm, enum xtensa_dm_reg reg, uint32_t value)
#define OCDDSR_DBGMODPOWERON
static void xtensa_dm_power_status_cache_reset(struct xtensa_debug_module *dm)
uint32_t xtensa_dsr_t
uint32_t xtensa_pwrstat_t
static void xtensa_dm_queue_tdi_idle(struct xtensa_debug_module *dm)
static bool xtensa_dm_core_was_reset(struct xtensa_debug_module *dm)
#define PWRSTAT_COREWASRESET_DM(d)
static xtensa_dsr_t xtensa_dm_core_status_get(struct xtensa_debug_module *dm)
xtensa_dm_pwr_reg
@ XDMREG_PWRNUM
@ XDMREG_PWRSTAT
@ XDMREG_PWRCTL
static bool xtensa_dm_is_powered(struct xtensa_debug_module *dm)
int xtensa_dm_power_status_read(struct xtensa_debug_module *dm, uint32_t clear)
int xtensa_dm_poll(struct xtensa_debug_module *dm)
static bool xtensa_dm_tap_was_reset(struct xtensa_debug_module *dm)
int xtensa_dm_perfmon_enable(struct xtensa_debug_module *dm, int counter_id, const struct xtensa_perfmon_config *config)
int xtensa_dm_core_status_check(struct xtensa_debug_module *dm)
void xtensa_dm_deinit(struct xtensa_debug_module *dm)
static int xtensa_dm_queue_execute(struct xtensa_debug_module *dm)
static bool xtensa_dm_core_is_stalled(struct xtensa_debug_module *dm)
int xtensa_dm_trace_config_read(struct xtensa_debug_module *dm, struct xtensa_trace_config *config)
#define OCDDSR_RUNSTALLSAMPLE
int xtensa_dm_trace_data_read(struct xtensa_debug_module *dm, uint8_t *dest, uint32_t size)
int xtensa_dm_core_status_clear(struct xtensa_debug_module *dm, xtensa_dsr_t bits)
#define PWRSTAT_DEBUGWASRESET_DM(d)
xtensa_dm_reg
@ XDMREG_LOCKSTATUS
@ XDMREG_DCRSET
@ XDMREG_DIR7
@ XDMREG_PERID5
@ XDMREG_EXTTIMELO
@ XDMREG_PMCTRL5
@ XDMREG_PMSTAT6
@ XDMREG_PMSTAT1
@ XDMREG_PCMATCHCTRL
@ XDMREG_TRAXDATA
@ XDMREG_PM4
@ XDMREG_CLAIMCLR
@ XDMREG_DIR1
@ XDMREG_TRAXADDR
@ XDMREG_PMSTAT3
@ XDMREG_DEBUGPC
@ XDMREG_TRAXSTAT
@ XDMREG_COMPID1
@ XDMREG_DIR4
@ XDMREG_DELAYCNT
@ XDMREG_INTPC
@ XDMREG_PERID0
@ XDMREG_MEMADDREND
@ XDMREG_TRAXRSVD68
@ XDMREG_TRAXRSVD48
@ XDMREG_DDREXEC
@ XDMREG_PMCTRL4
@ XDMREG_PMSTAT5
@ XDMREG_DIR5
@ XDMREG_PMCTRL0
@ XDMREG_DSR
@ XDMREG_ITCTRL
@ XDMREG_PMSTAT2
@ XDMREG_EXTTIMEHI
@ XDMREG_TRAXID
@ XDMREG_TRAXRSVD60
@ XDMREG_LOCKACCESS
@ XDMREG_TRAXRSVD58
@ XDMREG_PM1
@ XDMREG_PERID6
@ XDMREG_PM3
@ XDMREG_PM5
@ XDMREG_PMSTAT4
@ XDMREG_TRAXRSVD70
@ XDMREG_NUM
@ XDMREG_PERID7
@ XDMREG_PM6
@ XDMREG_PERID1
@ XDMREG_DIR2
@ XDMREG_DIR6
@ XDMREG_PM2
@ XDMREG_TRAXRSVD54
@ XDMREG_PM0
@ XDMREG_DIR3
@ XDMREG_CLAIMSET
@ XDMREG_PMCTRL2
@ XDMREG_PM7
@ XDMREG_TRAXRSVD5C
@ XDMREG_PMCTRL1
@ XDMREG_PERID4
@ XDMREG_TRIGGERPC
@ XDMREG_TRAXRSVD50
@ XDMREG_TRAXCTRL
@ XDMREG_DEVID
@ XDMREG_DEVTYPE
@ XDMREG_DIR0
@ XDMREG_PMSTAT0
@ XDMREG_COMPID2
@ XDMREG_OCDID
@ XDMREG_TRAXRSVD64
@ XDMREG_PMCTRL7
@ XDMREG_CONFIGID0
@ XDMREG_CONFIGID1
@ XDMREG_PMCTRL6
@ XDMREG_MEMADDRSTART
@ XDMREG_TRAXRSVD6C
@ XDMREG_DDR
@ XDMREG_TRAXRSVD4C
@ XDMREG_COMPID3
@ XDMREG_PERID2
@ XDMREG_DCRCLR
@ XDMREG_TRAXRSVD74
@ XDMREG_DIR0EXEC
@ XDMREG_AUTHSTATUS
@ XDMREG_PMSTAT7
@ XDMREG_COMPID0
@ XDMREG_PMCTRL3
@ XDMREG_ERISTAT
@ XDMREG_PERID3
@ XDMREG_PMG
int xtensa_dm_core_status_read(struct xtensa_debug_module *dm)
static bool xtensa_dm_is_online(struct xtensa_debug_module *dm)
static xtensa_pwrstat_t xtensa_dm_power_status_get(struct xtensa_debug_module *dm)
int xtensa_dm_queue_enable(struct xtensa_debug_module *dm)
int xtensa_dm_init(struct xtensa_debug_module *dm, const struct xtensa_debug_module_config *cfg)
int xtensa_dm_examine(struct xtensa_debug_module *dm)
uint32_t xtensa_traxstat_t
int xtensa_dm_read(struct xtensa_debug_module *dm, uint32_t addr, uint32_t *val)
int xtensa_dm_perfmon_dump(struct xtensa_debug_module *dm, int counter_id, struct xtensa_perfmon_result *out_result)
uint32_t xtensa_ocdid_t