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Data Structures | Macros | Functions | Variables
esp32s2.c File Reference
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Data Structures

struct  esp32s2_common
 

Macros

#define ESP32_S2_CLK_CONF   (ESP32_S2_RTCCNTL_BASE + 0x0074)
 
#define ESP32_S2_CLK_CONF_DEF   0x1583218
 
#define ESP32_S2_DPORT_PMS_OCCUPY_3   0x3F4C10E0
 
#define ESP32_S2_DR_REG_HIGH   0x3f4d3FFC
 
#define ESP32_S2_DR_REG_LOW   0x3f400000
 
#define ESP32_S2_DR_REG_UART_BASE   0x3f400000
 
#define ESP32_S2_OPTIONS0   (ESP32_S2_RTCCNTL_BASE + 0x0000)
 
#define ESP32_S2_REG_UART_BASE(i)   (ESP32_S2_DR_REG_UART_BASE + (i) * 0x10000)
 
#define ESP32_S2_RTC_CNTL_DIG_PWC_REG   (ESP32_S2_RTCCNTL_BASE + ESP32_S2_RTC_CNTL_DIG_PWC_REG_OFF)
 
#define ESP32_S2_RTC_CNTL_DIG_PWC_REG_OFF   0x8C
 
#define ESP32_S2_RTC_DATA_HIGH   0x50002000
 
#define ESP32_S2_RTC_DATA_LOW   0x50000000
 
#define ESP32_S2_RTCCNTL_BASE   0x3f408000
 
#define ESP32_S2_RTCWDT_CFG   (ESP32_S2_RTCCNTL_BASE + ESP32_S2_RTCWDT_CFG_OFF)
 
#define ESP32_S2_RTCWDT_CFG_OFF   0x94
 
#define ESP32_S2_RTCWDT_PROTECT   (ESP32_S2_RTCCNTL_BASE + ESP32_S2_RTCWDT_PROTECT_OFF)
 
#define ESP32_S2_RTCWDT_PROTECT_OFF   0xAC
 
#define ESP32_S2_STORE4   (ESP32_S2_RTCCNTL_BASE + 0x00BC)
 
#define ESP32_S2_STORE5   (ESP32_S2_RTCCNTL_BASE + 0x00C0)
 
#define ESP32_S2_SW_CPU_STALL   (ESP32_S2_RTCCNTL_BASE + 0x00B8)
 
#define ESP32_S2_SW_STALL_PROCPU_C0_M   ((ESP32_S2_SW_STALL_PROCPU_C0_V) << (ESP32_S2_SW_STALL_PROCPU_C0_S))
 
#define ESP32_S2_SW_STALL_PROCPU_C0_S   2
 
#define ESP32_S2_SW_STALL_PROCPU_C0_V   0x3
 
#define ESP32_S2_SW_STALL_PROCPU_C1_M   ((ESP32_S2_SW_STALL_PROCPU_C1_V) << (ESP32_S2_SW_STALL_PROCPU_C1_S))
 
#define ESP32_S2_SW_STALL_PROCPU_C1_S   26
 
#define ESP32_S2_SW_STALL_PROCPU_C1_V   0x3FU
 
#define ESP32_S2_SW_SYS_RST_M   0x80000000
 
#define ESP32_S2_SW_SYS_RST_S   31
 
#define ESP32_S2_SW_SYS_RST_V   0x1
 
#define ESP32_S2_SWD_AUTO_FEED_EN_M   BIT(31)
 
#define ESP32_S2_SWD_CONF_OFF   0xB0
 
#define ESP32_S2_SWD_CONF_REG   (ESP32_S2_RTCCNTL_BASE + ESP32_S2_SWD_CONF_OFF)
 
#define ESP32_S2_SWD_WKEY_VALUE   0x8F1D312AU
 
#define ESP32_S2_SWD_WPROTECT_OFF   0xB4
 
#define ESP32_S2_SWD_WPROTECT_REG   (ESP32_S2_RTCCNTL_BASE + ESP32_S2_SWD_WPROTECT_OFF)
 
#define ESP32_S2_SYS_RAM_HIGH   (ESP32_S2_SYS_RAM_LOW + 0x20000000UL)
 
#define ESP32_S2_SYS_RAM_LOW   0x60000000UL
 
#define ESP32_S2_TIMG0_BASE   0x3f41F000
 
#define ESP32_S2_TIMG0WDT_CFG0   (ESP32_S2_TIMG0_BASE + ESP32_S2_TIMGWDT_CFG0_OFF)
 
#define ESP32_S2_TIMG0WDT_PROTECT   (ESP32_S2_TIMG0_BASE + ESP32_S2_TIMGWDT_PROTECT_OFF)
 
#define ESP32_S2_TIMG1_BASE   0x3f420000
 
#define ESP32_S2_TIMG1WDT_CFG0   (ESP32_S2_TIMG1_BASE + ESP32_S2_TIMGWDT_CFG0_OFF)
 
#define ESP32_S2_TIMG1WDT_PROTECT   (ESP32_S2_TIMG1_BASE + ESP32_S2_TIMGWDT_PROTECT_OFF)
 
#define ESP32_S2_TIMGWDT_CFG0_OFF   0x48
 
#define ESP32_S2_TIMGWDT_PROTECT_OFF   0x64
 
#define ESP32_S2_TRACEMEM_BLOCK_SZ   0x4000
 
#define ESP32_S2_UART_DATE_REG(i)   (ESP32_S2_REG_UART_BASE(i) + 0x74)
 
#define ESP32_S2_WDT_WKEY_VALUE   0x50d83aa1
 

Functions

static int esp32s2_arch_state (struct target *target)
 
static int esp32s2_assert_reset (struct target *target)
 
static int esp32s2_deassert_reset (struct target *target)
 
static int esp32s2_disable_wdts (struct target *target)
 
static int esp32s2_on_halt (struct target *target)
 
static int esp32s2_poll (struct target *target)
 
static int esp32s2_set_peri_reg_mask (struct target *target, target_addr_t addr, uint32_t mask, uint32_t val)
 
static int esp32s2_soc_reset (struct target *target)
 
static int esp32s2_soft_reset_halt (struct target *target)
 
static int esp32s2_stall (struct target *target)
 
static int esp32s2_stall_set (struct target *target, bool stall)
 
static int esp32s2_step (struct target *target, bool current, target_addr_t address, bool handle_breakpoints)
 
static int esp32s2_target_create (struct target *target)
 
static int esp32s2_target_init (struct command_context *cmd_ctx, struct target *target)
 
static int esp32s2_unstall (struct target *target)
 
static int esp32s2_virt2phys (struct target *target, target_addr_t virtual, target_addr_t *physical)
 

Variables

static const struct command_registration esp32s2_command_handlers []
 
static const struct xtensa_debug_ops esp32s2_dbg_ops
 
static const struct xtensa_power_ops esp32s2_pwr_ops
 
static const struct esp_semihost_ops esp32s2_semihost_ops
 
struct target_type esp32s2_target
 

Macro Definition Documentation

◆ ESP32_S2_CLK_CONF

#define ESP32_S2_CLK_CONF   (ESP32_S2_RTCCNTL_BASE + 0x0074)

Definition at line 61 of file esp32s2.c.

◆ ESP32_S2_CLK_CONF_DEF

#define ESP32_S2_CLK_CONF_DEF   0x1583218

Definition at line 62 of file esp32s2.c.

◆ ESP32_S2_DPORT_PMS_OCCUPY_3

#define ESP32_S2_DPORT_PMS_OCCUPY_3   0x3F4C10E0

Definition at line 65 of file esp32s2.c.

◆ ESP32_S2_DR_REG_HIGH

#define ESP32_S2_DR_REG_HIGH   0x3f4d3FFC

Definition at line 23 of file esp32s2.c.

◆ ESP32_S2_DR_REG_LOW

#define ESP32_S2_DR_REG_LOW   0x3f400000

Definition at line 22 of file esp32s2.c.

◆ ESP32_S2_DR_REG_UART_BASE

#define ESP32_S2_DR_REG_UART_BASE   0x3f400000

Definition at line 69 of file esp32s2.c.

◆ ESP32_S2_OPTIONS0

#define ESP32_S2_OPTIONS0   (ESP32_S2_RTCCNTL_BASE + 0x0000)

Definition at line 50 of file esp32s2.c.

◆ ESP32_S2_REG_UART_BASE

#define ESP32_S2_REG_UART_BASE (   i)    (ESP32_S2_DR_REG_UART_BASE + (i) * 0x10000)

Definition at line 70 of file esp32s2.c.

◆ ESP32_S2_RTC_CNTL_DIG_PWC_REG

#define ESP32_S2_RTC_CNTL_DIG_PWC_REG   (ESP32_S2_RTCCNTL_BASE + ESP32_S2_RTC_CNTL_DIG_PWC_REG_OFF)

Definition at line 43 of file esp32s2.c.

◆ ESP32_S2_RTC_CNTL_DIG_PWC_REG_OFF

#define ESP32_S2_RTC_CNTL_DIG_PWC_REG_OFF   0x8C

Definition at line 42 of file esp32s2.c.

◆ ESP32_S2_RTC_DATA_HIGH

#define ESP32_S2_RTC_DATA_HIGH   0x50002000

Definition at line 21 of file esp32s2.c.

◆ ESP32_S2_RTC_DATA_LOW

#define ESP32_S2_RTC_DATA_LOW   0x50000000

Definition at line 20 of file esp32s2.c.

◆ ESP32_S2_RTCCNTL_BASE

#define ESP32_S2_RTCCNTL_BASE   0x3f408000

Definition at line 37 of file esp32s2.c.

◆ ESP32_S2_RTCWDT_CFG

#define ESP32_S2_RTCWDT_CFG   (ESP32_S2_RTCCNTL_BASE + ESP32_S2_RTCWDT_CFG_OFF)

Definition at line 44 of file esp32s2.c.

◆ ESP32_S2_RTCWDT_CFG_OFF

#define ESP32_S2_RTCWDT_CFG_OFF   0x94

Definition at line 38 of file esp32s2.c.

◆ ESP32_S2_RTCWDT_PROTECT

#define ESP32_S2_RTCWDT_PROTECT   (ESP32_S2_RTCCNTL_BASE + ESP32_S2_RTCWDT_PROTECT_OFF)

Definition at line 45 of file esp32s2.c.

◆ ESP32_S2_RTCWDT_PROTECT_OFF

#define ESP32_S2_RTCWDT_PROTECT_OFF   0xAC

Definition at line 39 of file esp32s2.c.

◆ ESP32_S2_STORE4

#define ESP32_S2_STORE4   (ESP32_S2_RTCCNTL_BASE + 0x00BC)

Definition at line 63 of file esp32s2.c.

◆ ESP32_S2_STORE5

#define ESP32_S2_STORE5   (ESP32_S2_RTCCNTL_BASE + 0x00C0)

Definition at line 64 of file esp32s2.c.

◆ ESP32_S2_SW_CPU_STALL

#define ESP32_S2_SW_CPU_STALL   (ESP32_S2_RTCCNTL_BASE + 0x00B8)

Definition at line 57 of file esp32s2.c.

◆ ESP32_S2_SW_STALL_PROCPU_C0_M

#define ESP32_S2_SW_STALL_PROCPU_C0_M   ((ESP32_S2_SW_STALL_PROCPU_C0_V) << (ESP32_S2_SW_STALL_PROCPU_C0_S))

Definition at line 54 of file esp32s2.c.

◆ ESP32_S2_SW_STALL_PROCPU_C0_S

#define ESP32_S2_SW_STALL_PROCPU_C0_S   2

Definition at line 56 of file esp32s2.c.

◆ ESP32_S2_SW_STALL_PROCPU_C0_V

#define ESP32_S2_SW_STALL_PROCPU_C0_V   0x3

Definition at line 55 of file esp32s2.c.

◆ ESP32_S2_SW_STALL_PROCPU_C1_M

#define ESP32_S2_SW_STALL_PROCPU_C1_M   ((ESP32_S2_SW_STALL_PROCPU_C1_V) << (ESP32_S2_SW_STALL_PROCPU_C1_S))

Definition at line 58 of file esp32s2.c.

◆ ESP32_S2_SW_STALL_PROCPU_C1_S

#define ESP32_S2_SW_STALL_PROCPU_C1_S   26

Definition at line 60 of file esp32s2.c.

◆ ESP32_S2_SW_STALL_PROCPU_C1_V

#define ESP32_S2_SW_STALL_PROCPU_C1_V   0x3FU

Definition at line 59 of file esp32s2.c.

◆ ESP32_S2_SW_SYS_RST_M

#define ESP32_S2_SW_SYS_RST_M   0x80000000

Definition at line 51 of file esp32s2.c.

◆ ESP32_S2_SW_SYS_RST_S

#define ESP32_S2_SW_SYS_RST_S   31

Definition at line 53 of file esp32s2.c.

◆ ESP32_S2_SW_SYS_RST_V

#define ESP32_S2_SW_SYS_RST_V   0x1

Definition at line 52 of file esp32s2.c.

◆ ESP32_S2_SWD_AUTO_FEED_EN_M

#define ESP32_S2_SWD_AUTO_FEED_EN_M   BIT(31)

Definition at line 48 of file esp32s2.c.

◆ ESP32_S2_SWD_CONF_OFF

#define ESP32_S2_SWD_CONF_OFF   0xB0

Definition at line 40 of file esp32s2.c.

◆ ESP32_S2_SWD_CONF_REG

#define ESP32_S2_SWD_CONF_REG   (ESP32_S2_RTCCNTL_BASE + ESP32_S2_SWD_CONF_OFF)

Definition at line 46 of file esp32s2.c.

◆ ESP32_S2_SWD_WKEY_VALUE

#define ESP32_S2_SWD_WKEY_VALUE   0x8F1D312AU

Definition at line 49 of file esp32s2.c.

◆ ESP32_S2_SWD_WPROTECT_OFF

#define ESP32_S2_SWD_WPROTECT_OFF   0xB4

Definition at line 41 of file esp32s2.c.

◆ ESP32_S2_SWD_WPROTECT_REG

#define ESP32_S2_SWD_WPROTECT_REG   (ESP32_S2_RTCCNTL_BASE + ESP32_S2_SWD_WPROTECT_OFF)

Definition at line 47 of file esp32s2.c.

◆ ESP32_S2_SYS_RAM_HIGH

#define ESP32_S2_SYS_RAM_HIGH   (ESP32_S2_SYS_RAM_LOW + 0x20000000UL)

Definition at line 25 of file esp32s2.c.

◆ ESP32_S2_SYS_RAM_LOW

#define ESP32_S2_SYS_RAM_LOW   0x60000000UL

Definition at line 24 of file esp32s2.c.

◆ ESP32_S2_TIMG0_BASE

#define ESP32_S2_TIMG0_BASE   0x3f41F000

Definition at line 29 of file esp32s2.c.

◆ ESP32_S2_TIMG0WDT_CFG0

#define ESP32_S2_TIMG0WDT_CFG0   (ESP32_S2_TIMG0_BASE + ESP32_S2_TIMGWDT_CFG0_OFF)

Definition at line 33 of file esp32s2.c.

◆ ESP32_S2_TIMG0WDT_PROTECT

#define ESP32_S2_TIMG0WDT_PROTECT   (ESP32_S2_TIMG0_BASE + ESP32_S2_TIMGWDT_PROTECT_OFF)

Definition at line 35 of file esp32s2.c.

◆ ESP32_S2_TIMG1_BASE

#define ESP32_S2_TIMG1_BASE   0x3f420000

Definition at line 30 of file esp32s2.c.

◆ ESP32_S2_TIMG1WDT_CFG0

#define ESP32_S2_TIMG1WDT_CFG0   (ESP32_S2_TIMG1_BASE + ESP32_S2_TIMGWDT_CFG0_OFF)

Definition at line 34 of file esp32s2.c.

◆ ESP32_S2_TIMG1WDT_PROTECT

#define ESP32_S2_TIMG1WDT_PROTECT   (ESP32_S2_TIMG1_BASE + ESP32_S2_TIMGWDT_PROTECT_OFF)

Definition at line 36 of file esp32s2.c.

◆ ESP32_S2_TIMGWDT_CFG0_OFF

#define ESP32_S2_TIMGWDT_CFG0_OFF   0x48

Definition at line 31 of file esp32s2.c.

◆ ESP32_S2_TIMGWDT_PROTECT_OFF

#define ESP32_S2_TIMGWDT_PROTECT_OFF   0x64

Definition at line 32 of file esp32s2.c.

◆ ESP32_S2_TRACEMEM_BLOCK_SZ

#define ESP32_S2_TRACEMEM_BLOCK_SZ   0x4000

Definition at line 67 of file esp32s2.c.

◆ ESP32_S2_UART_DATE_REG

#define ESP32_S2_UART_DATE_REG (   i)    (ESP32_S2_REG_UART_BASE(i) + 0x74)

Definition at line 71 of file esp32s2.c.

◆ ESP32_S2_WDT_WKEY_VALUE

#define ESP32_S2_WDT_WKEY_VALUE   0x50d83aa1

Definition at line 28 of file esp32s2.c.

Function Documentation

◆ esp32s2_arch_state()

static int esp32s2_arch_state ( struct target *  target)
static

Definition at line 360 of file esp32s2.c.

References ERROR_OK.

◆ esp32s2_assert_reset()

static int esp32s2_assert_reset ( struct target *  target)
static

Definition at line 79 of file esp32s2.c.

References ERROR_OK.

◆ esp32s2_deassert_reset()

static int esp32s2_deassert_reset ( struct target *  target)
static

Definition at line 84 of file esp32s2.c.

References ERROR_OK, LOG_ERROR, LOG_TARGET_DEBUG, xtensa::smp_break, target_to_xtensa(), xtensa_deassert_reset(), and xtensa_smpbreak_write().

◆ esp32s2_disable_wdts()

static int esp32s2_disable_wdts ( struct target *  target)
static

Definition at line 304 of file esp32s2.c.

References ERROR_OK, ESP32_S2_RTCWDT_CFG, ESP32_S2_RTCWDT_PROTECT, ESP32_S2_SWD_AUTO_FEED_EN_M, ESP32_S2_SWD_CONF_REG, ESP32_S2_SWD_WKEY_VALUE, ESP32_S2_SWD_WPROTECT_REG, ESP32_S2_TIMG0WDT_CFG0, ESP32_S2_TIMG0WDT_PROTECT, ESP32_S2_TIMG1WDT_CFG0, ESP32_S2_TIMG1WDT_PROTECT, ESP32_S2_WDT_WKEY_VALUE, LOG_ERROR, target_read_u32(), and target_write_u32().

Referenced by esp32s2_on_halt(), and esp32s2_soc_reset().

◆ esp32s2_on_halt()

static int esp32s2_on_halt ( struct target *  target)
static

Definition at line 365 of file esp32s2.c.

References ERROR_OK, esp32s2_disable_wdts(), and esp_xtensa_on_halt().

Referenced by esp32s2_poll(), and esp32s2_step().

◆ esp32s2_poll()

static int esp32s2_poll ( struct target *  target)
static

Definition at line 384 of file esp32s2.c.

References ERROR_OK, esp32s2_on_halt(), esp_xtensa_poll(), esp_xtensa_semihosting(), LOG_ERROR, esp_semihost_data::need_resume, esp_xtensa_common::semihost, SEMIHOSTING_HANDLED, target::state, target_call_event_callbacks(), TARGET_DEBUG_RUNNING, TARGET_EVENT_DEBUG_HALTED, TARGET_EVENT_HALTED, TARGET_HALTED, target_resume(), and target_to_esp_xtensa().

◆ esp32s2_set_peri_reg_mask()

static int esp32s2_set_peri_reg_mask ( struct target *  target,
target_addr_t  addr,
uint32_t  mask,
uint32_t  val 
)
static

Definition at line 115 of file esp32s2.c.

References addr, ERROR_OK, mask, target_read_u32(), and target_write_u32().

Referenced by esp32s2_soc_reset(), and esp32s2_stall_set().

◆ esp32s2_soc_reset()

static int esp32s2_soc_reset ( struct target *  target)
static

Definition at line 178 of file esp32s2.c.

References alive_sleep(), BIT, ERROR_OK, ERROR_TARGET_TIMEOUT, ESP32_S2_CLK_CONF, ESP32_S2_CLK_CONF_DEF, ESP32_S2_DPORT_PMS_OCCUPY_3, ESP32_S2_OPTIONS0, ESP32_S2_RTC_CNTL_DIG_PWC_REG, ESP32_S2_STORE4, ESP32_S2_STORE5, ESP32_S2_SW_SYS_RST_M, ESP32_S2_SW_SYS_RST_S, esp32s2_disable_wdts(), esp32s2_set_peri_reg_mask(), esp32s2_stall(), esp32s2_unstall(), LOG_DEBUG, LOG_ERROR, LOG_TARGET_DEBUG, LOG_TARGET_ERROR, OCDDCR_RUNSTALLINEN, target::reset_halt, target::state, xtensa::suppress_dsr_errors, TARGET_HALTED, TARGET_RESET, TARGET_RUNNING, target_state_name(), target_to_xtensa(), target_wait_state(), target_write_u32(), timeval_ms(), xtensa_assert_reset(), xtensa_deassert_reset(), xtensa_halt(), xtensa_poll(), and xtensa_smpbreak_write().

Referenced by esp32s2_soft_reset_halt().

◆ esp32s2_soft_reset_halt()

static int esp32s2_soft_reset_halt ( struct target *  target)
static

Definition at line 104 of file esp32s2.c.

References ERROR_OK, esp32s2_soc_reset(), LOG_TARGET_DEBUG, and xtensa_soft_reset_halt().

◆ esp32s2_stall()

static int esp32s2_stall ( struct target *  target)
inlinestatic

Definition at line 155 of file esp32s2.c.

References esp32s2_stall_set().

Referenced by esp32s2_soc_reset().

◆ esp32s2_stall_set()

static int esp32s2_stall_set ( struct target *  target,
bool  stall 
)
static

Definition at line 132 of file esp32s2.c.

References ERROR_OK, ESP32_S2_OPTIONS0, ESP32_S2_SW_CPU_STALL, ESP32_S2_SW_STALL_PROCPU_C0_M, ESP32_S2_SW_STALL_PROCPU_C0_S, ESP32_S2_SW_STALL_PROCPU_C1_M, ESP32_S2_SW_STALL_PROCPU_C1_S, esp32s2_set_peri_reg_mask(), LOG_ERROR, and LOG_TARGET_DEBUG.

Referenced by esp32s2_stall(), and esp32s2_unstall().

◆ esp32s2_step()

static int esp32s2_step ( struct target *  target,
bool  current,
target_addr_t  address,
bool  handle_breakpoints 
)
static

Definition at line 373 of file esp32s2.c.

References address, ERROR_OK, esp32s2_on_halt(), target_call_event_callbacks(), TARGET_EVENT_HALTED, and xtensa_step().

◆ esp32s2_target_create()

static int esp32s2_target_create ( struct target *  target)
static

Definition at line 448 of file esp32s2.c.

◆ esp32s2_target_init()

static int esp32s2_target_init ( struct command_context *  cmd_ctx,
struct target *  target 
)
static

Definition at line 424 of file esp32s2.c.

◆ esp32s2_unstall()

static int esp32s2_unstall ( struct target *  target)
inlinestatic

Definition at line 160 of file esp32s2.c.

References esp32s2_stall_set().

Referenced by esp32s2_soc_reset().

◆ esp32s2_virt2phys()

static int esp32s2_virt2phys ( struct target *  target,
target_addr_t  virtual,
target_addr_t *  physical 
)
static

Definition at line 417 of file esp32s2.c.

References ERROR_OK.

Variable Documentation

◆ esp32s2_command_handlers

const struct command_registration esp32s2_command_handlers[]
static
Initial value:
= {
{
.chain = xtensa_command_handlers,
},
{
.name = "esp",
.usage = "",
.chain = esp32_apptrace_command_handlers,
},
{
.name = "arm",
.mode = COMMAND_ANY,
.help = "ARM Command Group",
.usage = "",
.chain = semihosting_common_handlers
},
COMMAND_REGISTRATION_DONE
}
COMMAND_REGISTRATION_DONE
#define COMMAND_REGISTRATION_DONE
Use this as the last entry in an array of command_registration records.
Definition: command.h:251
COMMAND_ANY
@ COMMAND_ANY
Definition: command.h:42
esp32_apptrace_command_handlers
const struct command_registration esp32_apptrace_command_handlers[]
Definition: esp32_apptrace.c:1606
semihosting_common_handlers
const struct command_registration semihosting_common_handlers[]
Definition: semihosting_common.c:2114
command_registration::name
const char * name
Definition: command.h:234
xtensa_command_handlers
const struct command_registration xtensa_command_handlers[]
Definition: xtensa.c:4622

Definition at line 448 of file esp32s2.c.

◆ esp32s2_dbg_ops

const struct xtensa_debug_ops esp32s2_dbg_ops
static
Initial value:
= {
.queue_enable = xtensa_dm_queue_enable,
.queue_reg_read = xtensa_dm_queue_reg_read,
.queue_reg_write = xtensa_dm_queue_reg_write
}
xtensa_dm_queue_reg_read
int xtensa_dm_queue_reg_read(struct xtensa_debug_module *dm, enum xtensa_dm_reg reg, uint8_t *value)
Definition: xtensa_debug_module.c:162
xtensa_dm_queue_reg_write
int xtensa_dm_queue_reg_write(struct xtensa_debug_module *dm, enum xtensa_dm_reg reg, uint32_t value)
Definition: xtensa_debug_module.c:181
xtensa_dm_queue_enable
int xtensa_dm_queue_enable(struct xtensa_debug_module *dm)
Definition: xtensa_debug_module.c:157

Definition at line 424 of file esp32s2.c.

◆ esp32s2_pwr_ops

const struct xtensa_power_ops esp32s2_pwr_ops
static
Initial value:
= {
.queue_reg_read = xtensa_dm_queue_pwr_reg_read,
.queue_reg_write = xtensa_dm_queue_pwr_reg_write
}
xtensa_dm_queue_pwr_reg_write
int xtensa_dm_queue_pwr_reg_write(struct xtensa_debug_module *dm, enum xtensa_dm_pwr_reg reg, uint32_t data)
Definition: xtensa_debug_module.c:224
xtensa_dm_queue_pwr_reg_read
int xtensa_dm_queue_pwr_reg_read(struct xtensa_debug_module *dm, enum xtensa_dm_pwr_reg reg, uint8_t *data, uint32_t clear)
Definition: xtensa_debug_module.c:197

Definition at line 424 of file esp32s2.c.

◆ esp32s2_semihost_ops

const struct esp_semihost_ops esp32s2_semihost_ops
static
Initial value:
= {
.prepare = esp32s2_disable_wdts
}
esp32s2_disable_wdts
static int esp32s2_disable_wdts(struct target *target)
Definition: esp32s2.c:304

Definition at line 424 of file esp32s2.c.

◆ esp32s2_target

struct target_type esp32s2_target

Definition at line 448 of file esp32s2.c.