OpenOCD
|
Go to the source code of this file.
Data Structures | |
struct | esp32s2_common |
Variables | |
static const struct command_registration | esp32s2_command_handlers [] |
static const struct xtensa_debug_ops | esp32s2_dbg_ops |
static const struct xtensa_power_ops | esp32s2_pwr_ops |
static const struct esp_semihost_ops | esp32s2_semihost_ops |
struct target_type | esp32s2_target |
#define ESP32_S2_CLK_CONF (ESP32_S2_RTCCNTL_BASE + 0x0074) |
#define ESP32_S2_DROM0_HIGH ESP32_S2_DR_REG_LOW |
#define ESP32_S2_DROM1_LOW ESP32_S2_DR_REG_HIGH |
#define ESP32_S2_OPTIONS0 (ESP32_S2_RTCCNTL_BASE + 0x0000) |
#define ESP32_S2_REG_UART_BASE | ( | i | ) | (ESP32_S2_DR_REG_UART_BASE + (i) * 0x10000) |
#define ESP32_S2_RTC_CNTL_DIG_PWC_REG (ESP32_S2_RTCCNTL_BASE + ESP32_S2_RTC_CNTL_DIG_PWC_REG_OFF) |
#define ESP32_S2_RTCWDT_CFG (ESP32_S2_RTCCNTL_BASE + ESP32_S2_RTCWDT_CFG_OFF) |
#define ESP32_S2_RTCWDT_PROTECT (ESP32_S2_RTCCNTL_BASE + ESP32_S2_RTCWDT_PROTECT_OFF) |
#define ESP32_S2_STORE4 (ESP32_S2_RTCCNTL_BASE + 0x00BC) |
#define ESP32_S2_STORE5 (ESP32_S2_RTCCNTL_BASE + 0x00C0) |
#define ESP32_S2_SW_CPU_STALL (ESP32_S2_RTCCNTL_BASE + 0x00B8) |
#define ESP32_S2_SW_STALL_PROCPU_C0_M ((ESP32_S2_SW_STALL_PROCPU_C0_V) << (ESP32_S2_SW_STALL_PROCPU_C0_S)) |
#define ESP32_S2_SW_STALL_PROCPU_C1_M ((ESP32_S2_SW_STALL_PROCPU_C1_V) << (ESP32_S2_SW_STALL_PROCPU_C1_S)) |
#define ESP32_S2_SWD_CONF_REG (ESP32_S2_RTCCNTL_BASE + ESP32_S2_SWD_CONF_OFF) |
#define ESP32_S2_SWD_WPROTECT_REG (ESP32_S2_RTCCNTL_BASE + ESP32_S2_SWD_WPROTECT_OFF) |
#define ESP32_S2_SYS_RAM_HIGH (ESP32_S2_SYS_RAM_LOW + 0x20000000UL) |
#define ESP32_S2_TIMG0WDT_CFG0 (ESP32_S2_TIMG0_BASE + ESP32_S2_TIMGWDT_CFG0_OFF) |
#define ESP32_S2_TIMG0WDT_PROTECT (ESP32_S2_TIMG0_BASE + ESP32_S2_TIMGWDT_PROTECT_OFF) |
#define ESP32_S2_TIMG1WDT_CFG0 (ESP32_S2_TIMG1_BASE + ESP32_S2_TIMGWDT_CFG0_OFF) |
#define ESP32_S2_TIMG1WDT_PROTECT (ESP32_S2_TIMG1_BASE + ESP32_S2_TIMGWDT_PROTECT_OFF) |
#define ESP32_S2_UART_DATE_REG | ( | i | ) | (ESP32_S2_REG_UART_BASE(i) + 0x74) |
|
static |
|
static |
|
static |
Definition at line 105 of file esp32s2.c.
References ERROR_OK, LOG_ERROR, LOG_TARGET_DEBUG, xtensa::smp_break, target_to_xtensa(), xtensa_deassert_reset(), and xtensa_smpbreak_write().
|
static |
Definition at line 325 of file esp32s2.c.
References ERROR_OK, ESP32_S2_RTCWDT_CFG, ESP32_S2_RTCWDT_PROTECT, ESP32_S2_SWD_AUTO_FEED_EN_M, ESP32_S2_SWD_CONF_REG, ESP32_S2_SWD_WKEY_VALUE, ESP32_S2_SWD_WPROTECT_REG, ESP32_S2_TIMG0WDT_CFG0, ESP32_S2_TIMG0WDT_PROTECT, ESP32_S2_TIMG1WDT_CFG0, ESP32_S2_TIMG1WDT_PROTECT, ESP32_S2_WDT_WKEY_VALUE, LOG_ERROR, target_read_u32(), and target_write_u32().
Referenced by esp32s2_on_halt(), and esp32s2_soc_reset().
|
static |
Definition at line 386 of file esp32s2.c.
References esp32s2_disable_wdts().
Referenced by esp32s2_poll(), and esp32s2_step().
|
static |
Definition at line 401 of file esp32s2.c.
References ERROR_OK, esp32s2_on_halt(), esp_xtensa_poll(), esp_xtensa_semihosting(), LOG_ERROR, esp_semihost_data::need_resume, esp_xtensa_common::semihost, SEMIHOSTING_HANDLED, target::state, target_call_event_callbacks(), TARGET_DEBUG_RUNNING, TARGET_EVENT_DEBUG_HALTED, TARGET_EVENT_HALTED, TARGET_HALTED, target_resume(), and target_to_esp_xtensa().
|
static |
Definition at line 136 of file esp32s2.c.
References addr, ERROR_OK, mask, target_read_u32(), and target_write_u32().
Referenced by esp32s2_soc_reset(), and esp32s2_stall_set().
|
static |
Definition at line 199 of file esp32s2.c.
References alive_sleep(), BIT, ERROR_OK, ERROR_TARGET_TIMEOUT, ESP32_S2_CLK_CONF, ESP32_S2_CLK_CONF_DEF, ESP32_S2_DPORT_PMS_OCCUPY_3, ESP32_S2_OPTIONS0, ESP32_S2_RTC_CNTL_DIG_PWC_REG, ESP32_S2_STORE4, ESP32_S2_STORE5, ESP32_S2_SW_SYS_RST_M, ESP32_S2_SW_SYS_RST_S, esp32s2_disable_wdts(), esp32s2_set_peri_reg_mask(), esp32s2_stall(), esp32s2_unstall(), LOG_DEBUG, LOG_ERROR, LOG_TARGET_DEBUG, LOG_TARGET_ERROR, OCDDCR_RUNSTALLINEN, target::reset_halt, target::state, xtensa::suppress_dsr_errors, TARGET_HALTED, TARGET_RESET, TARGET_RUNNING, target_to_xtensa(), target_wait_state(), target_write_u32(), timeval_ms(), xtensa_assert_reset(), xtensa_deassert_reset(), xtensa_halt(), xtensa_poll(), and xtensa_smpbreak_write().
Referenced by esp32s2_soft_reset_halt().
|
static |
Definition at line 125 of file esp32s2.c.
References ERROR_OK, esp32s2_soc_reset(), LOG_TARGET_DEBUG, and xtensa_soft_reset_halt().
|
inlinestatic |
Definition at line 176 of file esp32s2.c.
References esp32s2_stall_set().
Referenced by esp32s2_soc_reset().
|
static |
Definition at line 153 of file esp32s2.c.
References ERROR_OK, ESP32_S2_OPTIONS0, ESP32_S2_SW_CPU_STALL, ESP32_S2_SW_STALL_PROCPU_C0_M, ESP32_S2_SW_STALL_PROCPU_C0_S, ESP32_S2_SW_STALL_PROCPU_C1_M, ESP32_S2_SW_STALL_PROCPU_C1_S, esp32s2_set_peri_reg_mask(), LOG_ERROR, and LOG_TARGET_DEBUG.
Referenced by esp32s2_stall(), and esp32s2_unstall().
|
static |
Definition at line 391 of file esp32s2.c.
References ERROR_OK, esp32s2_on_halt(), target_call_event_callbacks(), TARGET_EVENT_HALTED, and xtensa_step().
|
static |
|
static |
|
inlinestatic |
Definition at line 181 of file esp32s2.c.
References esp32s2_stall_set().
Referenced by esp32s2_soc_reset().
|
static |
|
static |
|
static |
|
static |
|
static |
struct target_type esp32s2_target |