28 #define JSP_BANNER "\n\r" \
29 "******************************\n\r" \
30 "** JTAG Serial Port **\n\r" \
31 "******************************\n\r" \
41 #define ADBG_USE_HISPEED 1
47 #define ENABLE_JSP_SERVER 2
52 #define ENABLE_JSP_MULTI 4
57 #define DBG_MODULE_SELECT_REG_SIZE 2
58 #define DBG_MAX_MODULES 4
67 #define DBG_CPU_CR_STALL 0x01
68 #define DBG_CPU_CR_RESET 0x02
75 #define ADBG_CRC_POLY 0xedb88320
81 #define DBG_WB_REG_SEL_LEN 1
82 #define DBG_WB_REG_ERROR 0
85 #define DBG_WB_OPCODE_LEN 4
86 #define DBG_WB_CMD_NOP 0x0
87 #define DBG_WB_CMD_BWRITE8 0x1
88 #define DBG_WB_CMD_BWRITE16 0x2
89 #define DBG_WB_CMD_BWRITE32 0x3
90 #define DBG_WB_CMD_BREAD8 0x5
91 #define DBG_WB_CMD_BREAD16 0x6
92 #define DBG_WB_CMD_BREAD32 0x7
93 #define DBG_WB_CMD_IREG_WR 0x9
94 #define DBG_WB_CMD_IREG_SEL 0xd
97 #define DBG_CPU0_REG_SEL_LEN 1
98 #define DBG_CPU0_REG_STATUS 0
101 #define DBG_CPU0_OPCODE_LEN 4
102 #define DBG_CPU0_CMD_NOP 0x0
103 #define DBG_CPU0_CMD_BWRITE32 0x3
104 #define DBG_CPU0_CMD_BREAD32 0x7
105 #define DBG_CPU0_CMD_IREG_WR 0x9
106 #define DBG_CPU0_CMD_IREG_SEL 0xd
109 #define DBG_CPU1_REG_SEL_LEN 1
110 #define DBG_CPU1_REG_STATUS 0
113 #define DBG_CPU1_OPCODE_LEN 4
114 #define DBG_CPU1_CMD_NOP 0x0
115 #define DBG_CPU1_CMD_BWRITE32 0x3
116 #define DBG_CPU1_CMD_BREAD32 0x7
117 #define DBG_CPU1_CMD_IREG_WR 0x9
118 #define DBG_CPU1_CMD_IREG_SEL 0xd
120 #define MAX_READ_STATUS_WAIT 10
121 #define MAX_READ_BUSY_RETRY 2
122 #define MAX_READ_CRC_RETRY 2
123 #define MAX_WRITE_CRC_RETRY 2
124 #define BURST_READ_READY 1
125 #define MAX_BUS_ERRORS 2
127 #define MAX_BURST_SIZE (4 * 1024)
129 #define STATUS_BYTES 1
134 static const char *
const chain_name[] = {
"WISHBONE",
"CPU0",
"CPU1",
"JSP"};
139 for (
int i = 0; i < length_bits; i++) {
141 d = ((data_in >> i) & 0x1) ? 0xffffffff : 0;
142 c = (crc & 0x1) ? 0xffffffff : 0;
157 while (!(buf[i] & (1 <<
count++)) && (i < len)) {
165 ret = (i * 8) +
count;
174 int retval = tap_ip->
init(jtag_info);
190 LOG_INFO(
"adv debug unit is configured with option ADBG_USE_HISPEED");
194 LOG_INFO(
"adv debug unit is configured with option ENABLE_JSP_MULTI");
195 LOG_INFO(
"adv debug unit is configured with option ENABLE_JSP_SERVER");
198 LOG_ERROR(
"Couldn't start the JSP server");
272 LOG_ERROR(
"Illegal debug chain selected (%i) while selecting control register",
278 uint32_t data = (opcode & ~(1 << opcode_len)) << index_len;
283 field.
num_bits = (opcode_len + 1) + index_len;
299 uint32_t *cmd_data,
int length_bits)
305 LOG_DEBUG(
"Write control register %" PRId8
": 0x%08" PRIx32, regidx, cmd_data[0]);
309 LOG_ERROR(
"Error while calling adbg_select_ctrl_reg");
330 LOG_ERROR(
"Illegal debug chain selected (%i) while doing control write",
338 uint32_t data = (opcode & ~(1 << opcode_len)) << index_len;
342 field[0].
out_value = (uint8_t *)cmd_data;
345 field[1].
num_bits = (opcode_len + 1) + index_len;
356 uint32_t *data,
int length_bits)
361 LOG_ERROR(
"Error while calling adbg_select_ctrl_reg");
383 LOG_ERROR(
"Illegal debug chain selected (%i) while doing control read",
389 uint32_t outdata = opcode & ~(0x1 << opcode_len);
395 field[0].
in_value = (uint8_t *)data;
398 field[1].
out_value = (uint8_t *)&outdata;
413 uint32_t address, uint16_t length_words)
418 data[0] = length_words | (address << 16);
420 data[1] = ((address >> 16) | ((opcode & 0xf) << 16)) & ~(0x1 << 20);
434 int count, uint32_t start_address, uint8_t *data)
436 int retry_full_crc = 0;
437 int retry_full_busy = 0;
441 LOG_DEBUG(
"Doing burst read, word size %d, word count %d, start address 0x%08" PRIx32,
454 LOG_WARNING(
"Tried burst read with invalid word size (%d),"
455 "defaulting to 4-byte words",
size);
463 LOG_WARNING(
"Tried burst read with invalid word size (%d),"
464 "defaulting to 4-byte words",
size);
472 LOG_WARNING(
"Tried burst read with invalid word size (%d),"
473 "defaulting to 4-byte words",
size);
478 LOG_ERROR(
"Illegal debug chain selected (%i) while doing burst read",
511 goto retry_read_full;
522 memcpy(data, in_buffer, total_size_bytes);
523 memcpy(&crc_read, &in_buffer[total_size_bytes], 4);
525 uint32_t crc_calc = 0xffffffff;
526 for (
int i = 0; i < total_size_bytes; i++)
529 if (crc_calc != crc_read) {
530 LOG_WARNING(
"CRC ERROR! Computed 0x%08" PRIx32
", read CRC 0x%08" PRIx32, crc_calc, crc_read);
532 goto retry_read_full;
545 uint32_t err_data[2] = {0, 0};
547 int bus_error_retries = 0;
555 if (err_data[0] & 0x1) {
561 addr = (err_data[0] >> 1) | (err_data[1] << 31);
562 LOG_WARNING(
"WB bus error during burst read, address 0x%08" PRIx32
", retrying!",
addr);
566 LOG_ERROR(
"Max WB bus errors reached during burst read");
578 goto retry_read_full;
590 int count,
unsigned long start_address)
592 int retry_full_crc = 0;
596 LOG_DEBUG(
"Doing burst write, word size %d, word count %d,"
597 "start address 0x%08lx",
size,
count, start_address);
609 LOG_DEBUG(
"Tried WB burst write with invalid word size (%d),"
610 "defaulting to 4-byte words",
size);
618 LOG_DEBUG(
"Tried CPU0 burst write with invalid word size (%d),"
619 "defaulting to 4-byte words",
size);
627 LOG_DEBUG(
"Tried CPU1 burst write with invalid word size (%d),"
628 "defaulting to 4-byte words",
size);
633 LOG_ERROR(
"Illegal debug chain selected (%i) while doing burst write",
653 uint32_t crc_calc = 0xffffffff;
662 field[2].
out_value = (uint8_t *)&crc_calc;
678 LOG_WARNING(
"CRC ERROR! match bit after write is %" PRIi8
" (computed CRC 0x%08" PRIx32
")", value, crc_calc);
680 goto retry_full_write;
690 int bus_error_retries = 0;
691 uint32_t err_data[2] = {0, 0};
699 if (err_data[0] & 0x1) {
705 addr = (err_data[0] >> 1) | (err_data[1] << 31);
706 LOG_WARNING(
"WB bus error during burst write, address 0x%08" PRIx32
", retrying!",
addr);
710 LOG_ERROR(
"Max WB bus errors reached during burst read");
722 goto retry_full_write;
731 uint32_t
addr,
int count, uint32_t *value)
748 uint32_t
addr,
int count,
const uint32_t *value)
874 int block_count_left =
count;
875 uint32_t block_count_address =
addr;
876 uint8_t *block_count_buffer =
buffer;
878 while (block_count_left) {
884 block_count_address, block_count_buffer);
888 block_count_left -= blocks_this_round;
937 t = calloc(
count *
size,
sizeof(uint8_t));
957 int block_count_left =
count;
958 uint32_t block_count_address =
addr;
959 uint8_t *block_count_buffer = (uint8_t *)
buffer;
961 while (block_count_left) {
967 size, blocks_this_round,
968 block_count_address);
974 block_count_left -= blocks_this_round;
984 int *out_len,
unsigned char *out_buffer,
985 int *in_len,
unsigned char *in_buffer)
1002 xmitsize = *out_len;
1004 uint8_t out_data[10];
1005 uint8_t in_data[10];
1007 int startbit, stopbit, wrapbit;
1009 memset(out_data, 0, 10);
1014 wrapbit = (xmitsize >> 3) & 0x1;
1015 out_data[0] = (xmitsize << 5) | 0x1;
1019 for (i = 0; i < xmitsize; i++) {
1020 out_data[i + 1] = (out_buffer[i] << 1) | wrapbit;
1021 wrapbit = (out_buffer[i] >> 7) & 0x1;
1025 out_data[i + 1] = wrapbit;
1027 out_data[9] = wrapbit;
1032 stopbit = !!(out_data[9] & 0x01);
1037 out_data[0] = 0x0 | (xmitsize << 4);
1039 memcpy(&out_data[1], out_buffer, xmitsize);
1044 stopbit = !!(out_data[8] & 0x80);
1047 field.
num_bits = 72 + startbit + stopbit;
1058 *in_len = (in_data[0] >> 4) & 0xF;
1059 memcpy(in_buffer, &in_data[1], *in_len);
1061 int bytes_free = in_data[0] & 0x0F;
1062 *out_len = (bytes_free < xmitsize) ? bytes_free : xmitsize;
void buffer_shr(void *_buf, unsigned buf_len, unsigned count)
int jsp_init(struct or1k_jtag *jtag_info, char *banner)
int jtag_execute_queue(void)
For software FIFO implementations, the queued commands can be executed during this call or earlier.
void jtag_add_dr_scan(struct jtag_tap *active, int in_num_fields, const struct scan_field *in_fields, tap_state_t state)
Generate a DR SCAN using the fields passed to the function.
The JTAG interface can be implemented with a software or hardware fifo.
static void list_add_tail(struct list_head *new, struct list_head *head)
list_add_tail - add a new entry
#define LOG_WARNING(expr ...)
#define LOG_ERROR(expr ...)
#define LOG_INFO(expr ...)
#define LOG_DEBUG(expr ...)
#define DBG_WB_CMD_BREAD8
#define DBG_WB_OPCODE_LEN
static int or1k_adv_jtag_read_cpu(struct or1k_jtag *jtag_info, uint32_t addr, int count, uint32_t *value)
#define DBG_CPU0_CMD_BWRITE32
static uint32_t adbg_compute_crc(uint32_t crc, uint32_t data_in, int length_bits)
#define DBG_CPU1_CMD_IREG_SEL
#define DBG_CPU1_CMD_IREG_WR
#define DBG_CPU1_CMD_BREAD32
#define DBG_WB_CMD_BREAD32
int or1k_du_adv_register(void)
int or1k_adv_jtag_jsp_xfer(struct or1k_jtag *jtag_info, int *out_len, unsigned char *out_buffer, int *in_len, unsigned char *in_buffer)
#define DBG_WB_CMD_BWRITE16
#define DBG_CPU0_OPCODE_LEN
static int adbg_wb_burst_read(struct or1k_jtag *jtag_info, int size, int count, uint32_t start_address, uint8_t *data)
static int adbg_ctrl_write(struct or1k_jtag *jtag_info, uint8_t regidx, uint32_t *cmd_data, int length_bits)
#define DBG_CPU0_REG_SEL_LEN
static int adbg_select_module(struct or1k_jtag *jtag_info, int chain)
static int or1k_adv_is_cpu_running(struct or1k_jtag *jtag_info, int *running)
static int or1k_adv_jtag_read_memory(struct or1k_jtag *jtag_info, uint32_t addr, uint32_t size, int count, uint8_t *buffer)
#define DBG_CPU0_CMD_IREG_SEL
static int or1k_adv_cpu_reset(struct or1k_jtag *jtag_info, int action)
#define DBG_WB_CMD_BWRITE32
#define MAX_WRITE_CRC_RETRY
static int or1k_adv_jtag_write_cpu(struct or1k_jtag *jtag_info, uint32_t addr, int count, const uint32_t *value)
static int adbg_burst_command(struct or1k_jtag *jtag_info, uint32_t opcode, uint32_t address, uint16_t length_words)
#define DBG_WB_REG_SEL_LEN
static int find_status_bit(void *_buf, int len)
static struct or1k_du or1k_du_adv
static int or1k_adv_jtag_write_memory(struct or1k_jtag *jtag_info, uint32_t addr, uint32_t size, int count, const uint8_t *buffer)
#define DBG_CPU1_REG_SEL_LEN
#define DBG_WB_CMD_IREG_WR
#define DBG_WB_CMD_BREAD16
#define DBG_MODULE_SELECT_REG_SIZE
static int adbg_ctrl_read(struct or1k_jtag *jtag_info, uint32_t regidx, uint32_t *data, int length_bits)
#define DBG_CPU1_CMD_BWRITE32
#define MAX_READ_CRC_RETRY
static int or1k_adv_jtag_init(struct or1k_jtag *jtag_info)
#define DBG_WB_CMD_BWRITE8
static int adbg_select_ctrl_reg(struct or1k_jtag *jtag_info, uint8_t regidx)
static const char *const chain_name[]
#define DBG_CPU0_REG_STATUS
#define ENABLE_JSP_SERVER
#define DBG_CPU1_OPCODE_LEN
#define DBG_WB_CMD_IREG_SEL
static int adbg_wb_burst_write(struct or1k_jtag *jtag_info, const uint8_t *data, int size, int count, unsigned long start_address)
#define DBG_CPU0_CMD_BREAD32
#define DBG_CPU0_CMD_IREG_WR
#define MAX_READ_BUSY_RETRY
static int or1k_adv_cpu_stall(struct or1k_jtag *jtag_info, int action)
size_t size
Size of the control block search area.
uint8_t * current_reg_idx
int or1k_jtag_module_selected
struct or1k_tap_ip * tap_ip
int(* init)(struct or1k_jtag *jtag_info)
This structure defines a single scan field in the scan.
int num_bits
The number of bits this field specifies.
uint8_t * in_value
A pointer to a 32-bit memory location for data scanned out.
const uint8_t * out_value
A pointer to value to be scanned into the device.
enum target_endianness endianness
#define ERROR_TARGET_FAILURE
static void buf_bswap16(uint8_t *dst, const uint8_t *src, size_t len)
Byte-swap buffer 16-bit.
static void buf_bswap32(uint8_t *dst, const uint8_t *src, size_t len)
Byte-swap buffer 32-bit.
#define CPU_RESET
Value to write into CPUCS to put EZ-USB into reset.