22 #define ASM_REG_W_R0 0x60F400
23 #define ASM_REG_W_R1 0x61F400
24 #define ASM_REG_W_R2 0x62F400
25 #define ASM_REG_W_R3 0x63F400
26 #define ASM_REG_W_R4 0x64F400
27 #define ASM_REG_W_R5 0x65F400
28 #define ASM_REG_W_R6 0x66F400
29 #define ASM_REG_W_R7 0x67F400
31 #define ASM_REG_W_N0 0x70F400
32 #define ASM_REG_W_N1 0x71F400
33 #define ASM_REG_W_N2 0x72F400
34 #define ASM_REG_W_N3 0x73F400
35 #define ASM_REG_W_N4 0x74F400
36 #define ASM_REG_W_N5 0x75F400
37 #define ASM_REG_W_N6 0x76F400
38 #define ASM_REG_W_N7 0x77F400
40 #define ASM_REG_W_M0 0x05F420
41 #define ASM_REG_W_M1 0x05F421
42 #define ASM_REG_W_M2 0x05F422
43 #define ASM_REG_W_M3 0x05F423
44 #define ASM_REG_W_M4 0x05F424
45 #define ASM_REG_W_M5 0x05F425
46 #define ASM_REG_W_M6 0x05F426
47 #define ASM_REG_W_M7 0x05F427
49 #define ASM_REG_W_X0 0x44F400
50 #define ASM_REG_W_X1 0x45F400
52 #define ASM_REG_W_Y0 0x46F400
53 #define ASM_REG_W_Y1 0x47F400
55 #define ASM_REG_W_A0 0x50F400
56 #define ASM_REG_W_A1 0x54F400
57 #define ASM_REG_W_A2 0x52F400
59 #define ASM_REG_W_B0 0x51F400
60 #define ASM_REG_W_B1 0x55F400
61 #define ASM_REG_W_B2 0x53F400
63 #define ASM_REG_W_VBA 0x05F430
64 #define ASM_REG_W_OMR 0x05F43A
65 #define ASM_REG_W_EP 0x05F42A
66 #define ASM_REG_W_SC 0x05F431
67 #define ASM_REG_W_SZ 0x05F438
68 #define ASM_REG_W_SR 0x05F439
69 #define ASM_REG_W_SP 0x05F43B
70 #define ASM_REG_W_SSH 0x05F43C
71 #define ASM_REG_W_SSL 0x05F43D
72 #define ASM_REG_W_LA 0x05F43E
73 #define ASM_REG_W_LC 0x05F43F
74 #define ASM_REG_W_PC 0x000000
75 #define ASM_REG_W_IPRC 0xFFFFFF
76 #define ASM_REG_W_IPRP 0xFFFFFE
78 #define ASM_REG_W_BCR 0xFFFFFB
79 #define ASM_REG_W_DCR 0xFFFFFA
80 #define ASM_REG_W_AAR0 0xFFFFF9
81 #define ASM_REG_W_AAR1 0xFFFFF8
82 #define ASM_REG_W_AAR2 0xFFFFF7
83 #define ASM_REG_W_AAR3 0xFFFFF6
88 #define OBCR_B0_AND_B1 ((0x0) << 10)
89 #define OBCR_B0_OR_B1 ((0x1) << 10)
90 #define OBCR_B1_AFTER_B0 ((0x2) << 10)
91 #define OBCR_B0_AFTER_B1 ((0x3) << 10)
93 #define OBCR_BP_DISABLED (0x0)
94 #define OBCR_BP_MEM_P (0x1)
95 #define OBCR_BP_MEM_X (0x2)
96 #define OBCR_BP_MEM_Y (0x3)
97 #define OBCR_BP_ON_READ ((0x2) << 0)
98 #define OBCR_BP_ON_WRITE ((0x1) << 0)
99 #define OBCR_BP_CC_NOT_EQUAL ((0x0) << 2)
100 #define OBCR_BP_CC_EQUAL ((0x1) << 2)
101 #define OBCR_BP_CC_LESS_THAN ((0x2) << 2)
102 #define OBCR_BP_CC_GREATER_THAN ((0x3) << 2)
104 #define OBCR_BP_0(x) ((x)<<2)
105 #define OBCR_BP_1(x) ((x)<<6)
222 static const struct {
311 #define INSTR_JUMP 0x0AF080
321 #define INSTR_MOVEP_REG_HIO(s, w, d, p) (0x084000 | \
322 ((s & 1) << 16) | ((w & 1) << 15) | ((d & 0x3f) << 8) | (p & 0x3f))
343 struct reg **reg_list[],
354 *reg_list = malloc(
sizeof(
struct reg *) * (*reg_list_size));
447 cache->
name =
"dsp563xx registers";
463 reg_list[i].
size = 32;
464 reg_list[i].
value = calloc(1, 4);
465 reg_list[i].
dirty =
false;
466 reg_list[i].
valid =
false;
467 reg_list[i].
exist =
true;
571 LOG_DEBUG(
"%s conditional branch not supported yet (0x%" PRIx32
" 0x%" PRIx32
" 0x%" PRIx32
")",
743 switch (arch_info->
num) {
795 switch (arch_info->
num) {
916 LOG_ERROR(
"no IDCODE present on device");
926 if (((chip>>5)&0x1f) == 0)
929 LOG_INFO(
"DSP56%03" PRIu32
" device found", chip);
944 #define DSP563XX_SR_SA (1<<17)
945 #define DSP563XX_SR_SC (1<<13)
1042 uint32_t once_status = 0;
1049 LOG_ERROR(
"jtag status contains invalid mode value - communication failure");
1106 LOG_WARNING(
"target was in unknown state when halt was requested");
1120 int handle_breakpoints,
1121 int debug_execution)
1138 LOG_DEBUG(
"%s %08X %08X", __func__, current, (
unsigned) address);
1177 int handle_breakpoints,
1181 uint32_t once_status;
1182 uint32_t dr_in, cnt;
1202 LOG_DEBUG(
"%s %08X %08X", __func__, current, (
unsigned) address);
1263 LOG_DEBUG(
"fetch: %08X", (
unsigned) dr_in&0x00ffffff);
1267 LOG_DEBUG(
"decode: %08X", (
unsigned) dr_in&0x00ffffff);
1271 LOG_DEBUG(
"execute: %08X", (
unsigned) dr_in&0x00ffffff);
1293 int handle_breakpoints)
1374 int num_mem_params,
struct mem_param *mem_params,
1375 int num_reg_params,
struct reg_param *reg_params,
1377 int timeout_ms,
void *arch_info)
1388 for (i = 0; i < num_mem_params; i++) {
1392 mem_params[i].
size, mem_params[i].value);
1397 for (i = 0; i < num_reg_params; i++) {
1406 LOG_ERROR(
"BUG: register '%s' not found", reg_params[i].reg_name);
1411 LOG_ERROR(
"BUG: register '%s' size doesn't match reg_params[i].size",
1412 reg_params[i].reg_name);
1430 for (i = 0; i < num_mem_params; i++) {
1433 mem_params[i].address,
1435 mem_params[i].
value);
1440 for (i = 0; i < num_reg_params; i++) {
1447 LOG_ERROR(
"BUG: register '%s' not found", reg_params[i].reg_name);
1453 "BUG: register '%s' size doesn't match reg_params[i].size",
1454 reg_params[i].reg_name);
1482 memspace = Jim_GetGlobalVariableStr(
interp,
"memspace", JIM_NONE);
1487 c = (
char *)Jim_GetString(memspace,
NULL);
1516 uint32_t data, move_cmd = 0;
1520 "memtype: %d address: 0x%8.8" PRIx32
", size: 0x%8.8" PRIx32
", count: 0x%8.8" PRIx32
"",
1534 move_cmd = 0x61d800;
1537 move_cmd = 0x69d800;
1540 move_cmd = 0x07d891;
1565 for (i = 0; i < x; i++) {
1587 for (i = 0; i < x; i++) {
1606 uint8_t *buffer_y, *buffer_x;
1614 LOG_DEBUG(
"size is not aligned to 4 byte");
1653 for (i = 0, i1 = 0; i <
count; i += 2, i1++) {
1655 buf_get_u32(buffer_y + i1 *
sizeof(uint32_t), 0, 32));
1657 buf_get_u32(buffer_x + i1 *
sizeof(uint32_t), 0, 32));
1697 uint32_t data, move_cmd = 0;
1701 "memtype: %d address: 0x%8.8" TARGET_PRIxADDR ", size: 0x%8.8" PRIx32
", count: 0x%8.8" PRIx32
"",
1716 move_cmd = 0x615800;
1719 move_cmd = 0x695800;
1722 move_cmd = 0x075891;
1747 for (i = 0; i < x; i++) {
1780 uint8_t *buffer_y, *buffer_x;
1788 LOG_DEBUG(
"size is not aligned to 4 byte");
1811 for (i = 0, i1 = 0; i <
count; i += 2, i1++) {
1812 buf_set_u32(buffer_y + i1 *
sizeof(uint32_t), 0, 32,
1814 buf_set_u32(buffer_x + i1 *
sizeof(uint32_t), 0, 32,
1883 bool was_running =
false;
1891 LOG_ERROR(
"Cannot add watchpoint. Hardware resource already used.");
1895 uint32_t obcr_value = 0;
1926 LOG_ERROR(
"Unsupported write mode (%d)", rw);
1946 LOG_ERROR(
"Unsupported condition code (%d)", cond);
1973 if (err ==
ERROR_OK && was_running) {
1987 LOG_ERROR(
"Cannot remove watchpoint, as no watchpoint is currently configured!");
2025 uint32_t address = 0;
2093 uint32_t address = 0;
2094 uint32_t
count = 1, i;
2095 uint32_t pattern = 0;
2154 for (i = 0; i <
count; i++) {
2175 .handler = dsp563xx_mem_command,
2177 .help =
"write x memory words",
2178 .usage =
"address value [count]",
2182 .handler = dsp563xx_mem_command,
2184 .help =
"write y memory words",
2185 .usage =
"address value [count]",
2189 .handler = dsp563xx_mem_command,
2191 .help =
"write p memory words",
2192 .usage =
"address value [count]",
2196 .handler = dsp563xx_mem_command,
2198 .help =
"display x memory words",
2199 .usage =
"address [count]",
2203 .handler = dsp563xx_mem_command,
2205 .help =
"display y memory words",
2206 .usage =
"address [count]",
2210 .handler = dsp563xx_mem_command,
2212 .help =
"display p memory words",
2213 .usage =
"address [count]",
2220 .handler = dsp563xx_add_watchpoint_command,
2222 .help =
"Create p memspace watchpoint",
2223 .usage =
"(>|<|=|!) (r|w|a) address",
2227 .handler = dsp563xx_add_watchpoint_command,
2229 .help =
"Create x memspace watchpoint",
2230 .usage =
"(>|<|=|!) (r|w|a) address",
2234 .handler = dsp563xx_add_watchpoint_command,
2236 .help =
"Create y memspace watchpoint",
2237 .usage =
"(>|<|=|!) (r|w|a) address",
2241 .handler = dsp563xx_remove_watchpoint_command,
2243 .help =
"remove watchpoint custom",
static uint32_t buf_get_u32(const uint8_t *_buffer, unsigned first, unsigned num)
Retrieves num bits from _buffer, starting at the first bit, returning the bits in a 32-bit word.
static void buf_set_u32(uint8_t *_buffer, unsigned first, unsigned num, uint32_t value)
Sets num bits in _buffer, starting at the first bit, using the bits in value.
#define CMD
Use this macro to access the command being handled, rather than accessing the variable directly.
#define CMD_NAME
Use this macro to access the name of the command being handled, rather than accessing the variable di...
#define CMD_ARGV
Use this macro to access the arguments for the command being handled, rather than accessing the varia...
#define ERROR_COMMAND_SYNTAX_ERROR
#define CMD_ARGC
Use this macro to access the number of arguments for the command being handled, rather than accessing...
#define COMMAND_PARSE_NUMBER(type, in, out)
parses the string in into out as a type, or prints a command error and passes the error code to the c...
#define CMD_CTX
Use this macro to access the context of the command being handled, rather than accessing the variable...
#define COMMAND_REGISTRATION_DONE
Use this as the last entry in an array of command_registration records.
static const struct reg_arch_type dsp563xx_reg_type
static int dsp563xx_deassert_reset(struct target *target)
static int dsp563xx_write_memory(struct target *target, int mem_type, target_addr_t address, uint32_t size, uint32_t count, const uint8_t *buffer)
static int dsp563xx_add_custom_watchpoint(struct target *target, uint32_t address, uint32_t mem_type, enum watchpoint_rw rw, enum watchpoint_condition cond)
#define OBCR_BP_CC_NOT_EQUAL
static int dsp563xx_remove_watchpoint(struct target *target, struct watchpoint *watchpoint)
static int dsp563xx_reg_read(struct target *target, uint32_t eame, uint32_t *data)
struct command_context * global_cmd_ctx
static int dsp563xx_read_memory(struct target *target, int mem_type, target_addr_t address, uint32_t size, uint32_t count, uint8_t *buffer)
static int dsp563xx_debug_once_init(struct target *target)
static int dsp563xx_reg_read_high_io(struct target *target, uint32_t instr_mask, uint32_t *data)
static struct once_reg once_regs[]
static int dsp563xx_remove_breakpoint(struct target *target, struct breakpoint *breakpoint)
static int dsp563xx_arch_state(struct target *target)
static int dsp563xx_reg_ssh_read(struct target *target)
static int dsp563xx_add_breakpoint(struct target *target, struct breakpoint *breakpoint)
static int dsp563xx_examine(struct target *target)
static int dsp563xx_write_memory_default(struct target *target, target_addr_t address, uint32_t size, uint32_t count, const uint8_t *buffer)
static int dsp563xx_jtag_debug_request(struct target *target)
COMMAND_HANDLER(dsp563xx_add_watchpoint_command)
static int dsp563xx_read_core_reg(struct target *target, int num)
static int dsp563xx_remove_custom_watchpoint(struct target *target)
static int dsp563xx_write_core_reg(struct target *target, int num)
static int dsp563xx_write_memory_core(struct target *target, int mem_type, target_addr_t address, uint32_t size, uint32_t count, const uint8_t *buffer)
static int dsp563xx_target_create(struct target *target, Jim_Interp *interp)
static int dsp563xx_init_target(struct command_context *cmd_ctx, struct target *target)
static int dsp563xx_run_algorithm(struct target *target, int num_mem_params, struct mem_param *mem_params, int num_reg_params, struct reg_param *reg_params, target_addr_t entry_point, target_addr_t exit_point, int timeout_ms, void *arch_info)
static int dsp563xx_read_memory_core(struct target *target, int mem_type, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
static int dsp563xx_reg_write_high_io(struct target *target, uint32_t instr_mask, uint32_t data)
static int dsp563xx_halt(struct target *target)
static const struct @82 dsp563xx_regs[]
static void dsp563xx_build_reg_cache(struct target *target)
#define OBCR_BP_CC_GREATER_THAN
static int dsp563xx_get_default_memory(void)
static int dsp563xx_write_buffer_default(struct target *target, target_addr_t address, uint32_t size, const uint8_t *buffer)
static const uint8_t gdb_reg_list_idx[]
static int dsp563xx_read_memory_default(struct target *target, target_addr_t address, uint32_t size, uint32_t count, uint8_t *buffer)
static int dsp563xx_reg_write(struct target *target, uint32_t instr_mask, uint32_t data)
static int dsp563xx_step(struct target *target, int current, target_addr_t address, int handle_breakpoints)
static void dsp563xx_invalidate_x_context(struct target *target, uint32_t addr_start, uint32_t addr_end)
static int dsp563xx_write_register(struct target *target, int num, int force)
static int dsp563xx_poll(struct target *target)
static int dsp563xx_reg_ssh_write(struct target *target)
static int dsp563xx_get_gdb_reg_list(struct target *target, struct reg **reg_list[], int *reg_list_size, enum target_register_class reg_class)
static int dsp563xx_debug_init(struct target *target)
static int dsp563xx_resume(struct target *target, int current, target_addr_t address, int handle_breakpoints, int debug_execution)
static int dsp563xx_set_core_reg(struct reg *reg, uint8_t *buf)
static int dsp563xx_reg_ssl_read(struct target *target)
#define OBCR_BP_CC_LESS_THAN
static const struct command_registration dsp563xx_command_handlers[]
static int dsp563xx_step_ex(struct target *target, int current, uint32_t address, int handle_breakpoints, int steps)
static int dsp563xx_save_context(struct target *target)
static int dsp563xx_get_core_reg(struct reg *reg)
static int dsp563xx_restore_context(struct target *target)
static int dsp563xx_read_buffer_default(struct target *target, target_addr_t address, uint32_t size, uint8_t *buffer)
static int dsp563xx_read_register(struct target *target, int num, int force)
struct target_type dsp563xx_target
Holds methods for DSP563XX targets.
static int dsp563xx_reg_pc_read(struct target *target)
static int dsp563xx_assert_reset(struct target *target)
static int dsp563xx_add_watchpoint(struct target *target, struct watchpoint *watchpoint)
#define INSTR_MOVEP_REG_HIO(s, w, d, p)
#define DSP563XX_NUMONCEREGS
#define DSP563XX_NUMCOREREGS
static struct dsp563xx_common * target_to_dsp563xx(struct target *target)
int dsp563xx_once_execute_sw_ir(struct jtag_tap *tap, int flush, uint32_t opcode)
single word instruction
int dsp563xx_once_reg_write(struct jtag_tap *tap, int flush, uint8_t reg, uint32_t data)
once write register
int dsp563xx_once_execute_dw_ir(struct jtag_tap *tap, int flush, uint32_t opcode, uint32_t operand)
double word instruction
int dsp563xx_once_target_status(struct jtag_tap *tap)
int dsp563xx_once_reg_read(struct jtag_tap *tap, int flush, uint8_t reg, uint32_t *data)
once read register
int dsp563xx_once_read_register(struct jtag_tap *tap, int flush, struct once_reg *regs, int len)
once read registers
int dsp563xx_once_request_debug(struct jtag_tap *tap, int reset_state)
#define DSP563XX_ONCE_PDBGOTO
#define DSP563XX_ONCE_OBCR
#define DSP563XX_ONCE_OSCR_DEBUG_M
#define DSP563XX_ONCE_OSCR_MBO
#define DSP563XX_ONCE_OPABFR
#define DSP563XX_ONCE_OPABF11
#define DSP563XX_ONCE_OSCR_TME
#define DSP563XX_ONCE_OPDBR
#define DSP563XX_ONCE_OCR_EX
#define DSP563XX_ONCE_OPABEX
#define DSP563XX_ONCE_OGDBR
#define DSP563XX_ONCE_OSCR_TO
#define DSP563XX_ONCE_OTC
#define DSP563XX_ONCE_OPILR
#define DSP563XX_ONCE_OMLR0
#define DSP563XX_ONCE_OCR_GO
#define DSP563XX_ONCE_OMLR1
#define DSP563XX_ONCE_OPABDR
#define DSP563XX_ONCE_OSCR
#define DSP563XX_ONCE_OSCR_SWO
#define DSP563XX_ONCE_OMBC
static uint16_t direction
void jtag_add_reset(int req_tlr_or_trst, int req_srst)
A reset of the TAP state machine can be requested.
int jtag_execute_queue(void)
For software FIFO implementations, the queued commands can be executed during this call or earlier.
static enum reset_types jtag_reset_config
void jtag_add_sleep(uint32_t us)
enum reset_types jtag_get_reset_config(void)
#define LOG_WARNING(expr ...)
#define LOG_ERROR(expr ...)
#define LOG_INFO(expr ...)
#define LOG_DEBUG(expr ...)
struct reg * register_get_by_name(struct reg_cache *first, const char *name, bool search_all)
struct reg_cache ** register_get_last_cache_p(struct reg_cache **first)
void register_cache_invalidate(struct reg_cache *cache)
Marks the contents of the register cache as invalid (and clean).
size_t size
Size of the control block search area.
uint32_t core_regs[DSP563XX_NUMCOREREGS]
int(* read_core_reg)(struct target *target, int num)
bool hardware_breakpoints_cleared
struct mcu_jtag jtag_info
struct hardware_breakpoint hardware_breakpoint[1]
int(* write_core_reg)(struct target *target, int num)
struct reg_cache * core_cache
struct dsp563xx_common * dsp563xx_common
enum breakpoint_usage used
bool hasidcode
not all devices have idcode, we'll discover this during chain examination
uint32_t idcode
device identification code
int(* get)(struct reg *reg)
const struct reg_arch_type * type
This holds methods shared between all instances of a given target type.
const char * name
Name of this type of target.
enum target_debug_reason debug_reason
struct reg_cache * reg_cache
int target_call_event_callbacks(struct target *target, enum target_event event)
const char * target_state_name(struct target *t)
Return the name of this targets current state.
int target_halt(struct target *target)
void target_buffer_set_u32(struct target *target, uint8_t *buffer, uint32_t value)
int target_write_buffer(struct target *target, target_addr_t address, uint32_t size, const uint8_t *buffer)
int target_read_buffer(struct target *target, target_addr_t address, uint32_t size, uint8_t *buffer)
void target_handle_md_output(struct command_invocation *cmd, struct target *target, target_addr_t address, unsigned size, unsigned count, const uint8_t *buffer)
struct target * get_current_target(struct command_context *cmd_ctx)
uint32_t target_buffer_get_u32(struct target *target, const uint8_t *buffer)
int target_resume(struct target *target, int current, target_addr_t address, int handle_breakpoints, int debug_execution)
Make the target (re)start executing using its saved execution context (possibly with some modificatio...
int target_wait_state(struct target *target, enum target_state state, int ms)
#define ERROR_TARGET_NOT_HALTED
#define ERROR_TARGET_INVALID
@ TARGET_EVENT_DEBUG_RESUMED
@ TARGET_EVENT_DEBUG_HALTED
#define ERROR_TARGET_RESOURCE_NOT_AVAILABLE
static void target_set_examined(struct target *target)
Sets the examined flag for the given target.
static bool target_was_examined(struct target *target)
#define ERROR_TARGET_FAILURE
static int read_mem(struct target *t, uint32_t size, uint32_t addr, uint8_t *buf)