26 #define FLASH_ACR 0x00
27 #define FLASH_PECR 0x04
28 #define FLASH_PDKEYR 0x08
29 #define FLASH_PEKEYR 0x0C
30 #define FLASH_PRGKEYR 0x10
31 #define FLASH_OPTKEYR 0x14
33 #define FLASH_OBR 0x1C
34 #define FLASH_WRPR 0x20
37 #define FLASH_ACR__LATENCY (1<<0)
38 #define FLASH_ACR__PRFTEN (1<<1)
39 #define FLASH_ACR__ACC64 (1<<2)
40 #define FLASH_ACR__SLEEP_PD (1<<3)
41 #define FLASH_ACR__RUN_PD (1<<4)
44 #define FLASH_PECR__PELOCK (1<<0)
45 #define FLASH_PECR__PRGLOCK (1<<1)
46 #define FLASH_PECR__OPTLOCK (1<<2)
47 #define FLASH_PECR__PROG (1<<3)
48 #define FLASH_PECR__DATA (1<<4)
49 #define FLASH_PECR__FTDW (1<<8)
50 #define FLASH_PECR__ERASE (1<<9)
51 #define FLASH_PECR__FPRG (1<<10)
52 #define FLASH_PECR__EOPIE (1<<16)
53 #define FLASH_PECR__ERRIE (1<<17)
54 #define FLASH_PECR__OBL_LAUNCH (1<<18)
57 #define FLASH_SR__BSY (1<<0)
58 #define FLASH_SR__EOP (1<<1)
59 #define FLASH_SR__ENDHV (1<<2)
60 #define FLASH_SR__READY (1<<3)
61 #define FLASH_SR__WRPERR (1<<8)
62 #define FLASH_SR__PGAERR (1<<9)
63 #define FLASH_SR__SIZERR (1<<10)
64 #define FLASH_SR__OPTVERR (1<<11)
67 #define PEKEY1 0x89ABCDEF
68 #define PEKEY2 0x02030405
69 #define PRGKEY1 0x8C9DAEBF
70 #define PRGKEY2 0x13141516
71 #define OPTKEY1 0xFBEAD9C8
72 #define OPTKEY2 0x24252627
75 #define DBGMCU_IDCODE 0xE0042000
76 #define DBGMCU_IDCODE_L0 0x40015800
79 #define FLASH_SECTOR_SIZE 4096
80 #define FLASH_BANK0_ADDRESS 0x08000000
83 #define OPTION_BYTES_ADDRESS 0x1FF80000
85 #define OPTION_BYTE_0_PR1 0xFFFF0000
86 #define OPTION_BYTE_0_PR0 0xFF5500AA
129 { 0x1000,
"A" }, { 0x1008,
"Y" }, { 0x1038,
"W" }, { 0x1078,
"V" },
132 { 0x1000,
"A" }, { 0x1008,
"Z" }, { 0x1018,
"Y" }, { 0x1038,
"X" }
135 { 0x1000,
"A" }, { 0x2000,
"B" }, { 0x2008,
"Y" }, { 0x2018,
"1, X" },
138 { 0x1000,
"A" }, { 0x1018,
"Y" }, { 0x1038,
"X" }, { 0x10f8,
"V" },
141 { 0x1000,
"A" }, { 0x1018,
"Z" },
144 { 0x1000,
"A" }, { 0x1008,
"Z" }, { 0x1018,
"Y" }, { 0x1038,
"X" },
150 { 0x1000,
"A" }, { 0x2000,
"B" }, { 0x2008,
"Z" },
153 { 0x1000,
"A" }, { 0x1008,
"Z" },
161 .device_str =
"STM32L1xx (Cat.1 - Low/Medium Density)",
163 .pages_per_sector = 16,
164 .max_flash_size_kb = 128,
165 .has_dual_banks =
false,
166 .flash_base = 0x40023C00,
167 .fsize_base = 0x1FF8004C,
173 .device_str =
"STM32L0xx (Cat. 3)",
175 .pages_per_sector = 32,
176 .max_flash_size_kb = 64,
177 .has_dual_banks =
false,
178 .flash_base = 0x40022000,
179 .fsize_base = 0x1FF8007C,
185 .device_str =
"STM32L0xx (Cat. 2)",
187 .pages_per_sector = 32,
188 .max_flash_size_kb = 32,
189 .has_dual_banks =
false,
190 .flash_base = 0x40022000,
191 .fsize_base = 0x1FF8007C,
197 .device_str =
"STM32L1xx (Cat.3 - Medium+ Density)",
199 .pages_per_sector = 16,
200 .max_flash_size_kb = 256,
201 .has_dual_banks =
false,
202 .flash_base = 0x40023C00,
203 .fsize_base = 0x1FF800CC,
209 .device_str =
"STM32L1xx (Cat.2)",
211 .pages_per_sector = 16,
212 .max_flash_size_kb = 128,
213 .has_dual_banks =
false,
214 .flash_base = 0x40023C00,
215 .fsize_base = 0x1FF8004C,
221 .device_str =
"STM32L1xx (Cat.4/Cat.3 - Medium+/High Density)",
223 .pages_per_sector = 16,
224 .max_flash_size_kb = 384,
225 .first_bank_size_kb = 192,
226 .has_dual_banks =
true,
227 .flash_base = 0x40023C00,
228 .fsize_base = 0x1FF800CC,
234 .device_str =
"STM32L1xx (Cat.5/Cat.6)",
236 .pages_per_sector = 16,
237 .max_flash_size_kb = 512,
238 .first_bank_size_kb = 0,
239 .has_dual_banks =
true,
240 .flash_base = 0x40023C00,
241 .fsize_base = 0x1FF800CC,
247 .device_str =
"STM32L0xx (Cat.5)",
249 .pages_per_sector = 32,
250 .max_flash_size_kb = 192,
251 .first_bank_size_kb = 0,
252 .has_dual_banks =
false,
253 .flash_base = 0x40022000,
254 .fsize_base = 0x1FF8007C,
260 .device_str =
"STM32L0xx (Cat.1)",
262 .pages_per_sector = 32,
263 .max_flash_size_kb = 16,
264 .has_dual_banks =
false,
265 .flash_base = 0x40022000,
266 .fsize_base = 0x1FF8007C,
279 stm32lx_info = calloc(1,
sizeof(*stm32lx_info));
283 LOG_ERROR(
"failed to allocate bank structure");
287 bank->driver_priv = stm32lx_info;
289 stm32lx_info->
probed =
false;
293 bank->default_padded_value =
bank->erased_value = 0x00;
374 for (
unsigned int i = 0; i <
bank->num_sectors; i++) {
376 bank->sectors[i].is_protected = 1;
378 bank->sectors[i].is_protected = 0;
401 for (
unsigned int i = first; i <= last; i++) {
405 bank->sectors[i].is_erased = 1;
417 uint32_t buffer_size = (16384 / hp_nb) * hp_nb;
427 static const uint8_t stm32lx_flash_write_code[] = {
428 #include "../../../contrib/loaders/flash/stm32/stm32lx.inc"
433 LOG_ERROR(
"The offset must be %" PRIu32
"B-aligned but it is %" PRIi32
"B)", hp_nb,
offset);
437 LOG_ERROR(
"The byte count must be %" PRIu32
"B-aligned but count is %" PRIu32
"B)", hp_nb,
count);
444 LOG_DEBUG(
"no working area for block memory writes");
451 sizeof(stm32lx_flash_write_code),
452 stm32lx_flash_write_code);
460 if (buffer_size > 1024)
465 if (buffer_size <= stm32lx_info->part_info.page_size) {
470 LOG_WARNING(
"no large enough working area available, can't do block memory writes");
474 buffer_size -= buffer_size % hp_nb;
504 LOG_ERROR(
"unable to get armv7m target");
509 uint32_t demcr_save = armv7m->
demcr;
515 this_count = (
count > buffer_size) ? buffer_size :
count;
528 buf_set_u32(reg_params[2].value, 0, 32, this_count / hp_nb);
537 write_algorithm->
address, 0, 10000, &armv7m_info);
551 address += this_count;
556 armv7m->
demcr = demcr_save;
569 LOG_WARNING(
"Couldn't use loader, falling back to page memory writes");
586 address += this_count;
613 uint32_t halfpages_number;
614 uint32_t bytes_remaining = 0;
616 uint32_t bytes_written = 0;
625 LOG_ERROR(
"offset 0x%" PRIx32
" breaks required 4-byte alignment",
offset);
639 while (bytes_remaining > 0) {
640 uint8_t value[4] = {0xff, 0xff, 0xff, 0xff};
643 uint32_t bytes_to_write =
MIN(4, bytes_remaining);
644 memcpy(value,
buffer + bytes_written, bytes_to_write);
648 goto reset_pg_and_lock;
650 bytes_written += bytes_to_write;
651 bytes_remaining -= bytes_to_write;
656 goto reset_pg_and_lock;
660 count -= bytes_written;
663 assert((
offset % hp_nb) == 0);
666 halfpages_number =
count / hp_nb;
668 if (halfpages_number) {
672 LOG_WARNING(
"couldn't use block writes, falling back to single memory accesses");
673 halfpages_number = 0;
681 uint32_t page_bytes_written = hp_nb * halfpages_number;
682 bytes_written += page_bytes_written;
683 address += page_bytes_written;
684 bytes_remaining =
count - page_bytes_written;
690 while (bytes_remaining > 0) {
691 uint8_t value[4] = {0xff, 0xff, 0xff, 0xff};
694 uint32_t bytes_to_write =
MIN(4, bytes_remaining);
695 memcpy(value,
buffer + bytes_written, bytes_to_write);
699 goto reset_pg_and_lock;
701 bytes_written += bytes_to_write;
702 bytes_remaining -= bytes_to_write;
707 goto reset_pg_and_lock;
734 uint16_t flash_size_in_kb;
737 uint32_t second_bank_base;
740 stm32lx_info->
probed =
false;
746 stm32lx_info->
idcode = device_id;
748 LOG_DEBUG(
"device id = 0x%08" PRIx32
"", device_id);
758 LOG_ERROR(
"Cannot identify target as an STM32 L0 or L1 family device.");
773 if (retval ==
ERROR_OK && (device_id & 0xfff) == 0x436) {
774 if (flash_size_in_kb == 0)
775 flash_size_in_kb = 384;
776 else if (flash_size_in_kb == 1)
777 flash_size_in_kb = 256;
781 if (retval ==
ERROR_OK && (device_id & 0xfff) == 0x429) {
782 flash_size_in_kb &= 0xff;
787 if (retval !=
ERROR_OK || flash_size_in_kb == 0xffff || flash_size_in_kb == 0) {
788 LOG_WARNING(
"STM32L flash size failed, probe inaccurate - assuming %dk flash",
792 LOG_WARNING(
"STM32L probed flash size assumed incorrect since FLASH_SIZE=%dk > %dk, - assuming %dk flash",
807 second_bank_base = base_address +
809 if (
bank->base == second_bank_base || !
bank->base) {
811 base_address = second_bank_base;
812 flash_size_in_kb = flash_size_in_kb -
814 }
else if (
bank->base == base_address) {
818 LOG_WARNING(
"STM32L flash bank base address config is incorrect. "
821 bank->base, base_address, second_bank_base);
824 LOG_INFO(
"STM32L flash has dual banks. Bank (%u) size is %dkb, base address is 0x%" PRIx32,
825 bank->bank_number, flash_size_in_kb, base_address);
827 LOG_INFO(
"STM32L flash size is %dkb, base address is 0x%" PRIx32, flash_size_in_kb, base_address);
834 LOG_INFO(
"ignoring flash probed value, using configured bank size: %dkbytes", flash_size_in_kb);
842 bank->size = flash_size_in_kb * 1024;
843 bank->base = base_address;
844 bank->num_sectors = num_sectors;
846 if (!
bank->sectors) {
847 LOG_ERROR(
"failed to allocate bank sectors");
851 for (
unsigned int i = 0; i < num_sectors; i++) {
854 bank->sectors[i].is_erased = -1;
855 bank->sectors[i].is_protected = -1;
858 stm32lx_info->
probed =
true;
878 uint16_t rev_id = stm32lx_info->
idcode >> 16;
879 const char *rev_str =
NULL;
881 if (!stm32lx_info->
probed) {
889 for (
unsigned int i = 0; i <
info->num_revs; i++)
890 if (rev_id ==
info->revs[i].rev)
891 rev_str =
info->revs[i].str;
904 .
name =
"mass_erase",
905 .handler = stm32lx_handle_mass_erase_command,
908 .help =
"Erase entire flash device. including available EEPROM",
912 .handler = stm32lx_handle_lock_command,
915 .help =
"Increase the readout protection to Level 1.",
919 .handler = stm32lx_handle_unlock_command,
922 .help =
"Lower the readout protection from Level 1 to 0.",
931 .help =
"stm32lx flash command group",
941 .flash_bank_command = stm32lx_flash_bank_command,
1120 uint32_t
addr =
bank->base +
bank->sectors[sector].offset + (page
1212 LOG_ERROR(
"timed out waiting for flash");
1219 LOG_ERROR(
"access denied / write protected");
1251 }
while (--tries > 0 &&
1317 stm32lx_info =
bank->driver_priv;
1352 if (flash_size_in_kb == 192 || flash_size_in_kb == 128) {
void init_reg_param(struct reg_param *param, char *reg_name, uint32_t size, enum param_direction direction)
void destroy_reg_param(struct reg_param *param)
static struct armv7m_common * target_to_armv7m(struct target *target)
#define ARMV7M_COMMON_MAGIC
Support functions to access arbitrary bits in a byte array.
static void buf_set_u32(uint8_t *_buffer, unsigned first, unsigned num, uint32_t value)
Sets num bits in _buffer, starting at the first bit, using the bits in value.
void command_print_sameline(struct command_invocation *cmd, const char *format,...)
void command_print(struct command_invocation *cmd, const char *format,...)
#define CMD
Use this macro to access the command being handled, rather than accessing the variable directly.
#define CALL_COMMAND_HANDLER(name, extra ...)
Use this to macro to call a command helper (or a nested handler).
#define ERROR_COMMAND_SYNTAX_ERROR
#define CMD_ARGC
Use this macro to access the number of arguments for the command being handled, rather than accessing...
#define COMMAND_REGISTRATION_DONE
Use this as the last entry in an array of command_registration records.
#define ERROR_FLASH_OPERATION_FAILED
#define ERROR_FLASH_DST_BREAKS_ALIGNMENT
int default_flash_blank_check(struct flash_bank *bank)
Provides default erased-bank check handling.
int default_flash_read(struct flash_bank *bank, uint8_t *buffer, uint32_t offset, uint32_t count)
Provides default read implementation for flash memory.
void default_flash_free_driver_priv(struct flash_bank *bank)
Deallocates bank->driver_priv.
void alive_sleep(uint64_t ms)
#define LOG_WARNING(expr ...)
#define LOG_ERROR(expr ...)
#define LOG_INFO(expr ...)
#define LOG_DEBUG(expr ...)
#define FLASH_SR__OPTVERR
static const struct stm32lx_rev stm32_425_revs[]
static int stm32lx_protect_check(struct flash_bank *bank)
static int stm32lx_lock_program_memory(struct flash_bank *bank)
static const struct stm32lx_rev stm32_447_revs[]
static const struct stm32lx_rev stm32_436_revs[]
static const struct stm32lx_rev stm32_437_revs[]
#define OPTION_BYTES_ADDRESS
static int stm32lx_update_part_info(struct flash_bank *bank, uint16_t flash_size_in_kb)
static int stm32lx_auto_probe(struct flash_bank *bank)
#define OPTION_BYTE_0_PR0
#define FLASH_PECR__OPTLOCK
#define FLASH_PECR__ERASE
static int stm32lx_read_id_code(struct target *target, uint32_t *id)
#define FLASH_BANK0_ADDRESS
static const struct stm32lx_rev stm32_416_revs[]
static int stm32lx_unlock_program_memory(struct flash_bank *bank)
static int stm32lx_probe(struct flash_bank *bank)
static const struct stm32lx_rev stm32_457_revs[]
static int stm32lx_erase_sector(struct flash_bank *bank, int sector)
static int stm32lx_mass_erase(struct flash_bank *bank)
static const struct command_registration stm32lx_exec_command_handlers[]
static const struct stm32lx_rev stm32_427_revs[]
static int stm32lx_write_half_pages(struct flash_bank *bank, const uint8_t *buffer, uint32_t offset, uint32_t count)
static const struct stm32lx_rev stm32_429_revs[]
#define FLASH_PECR__OBL_LAUNCH
static const struct command_registration stm32lx_command_handlers[]
FLASH_BANK_COMMAND_HANDLER(stm32lx_flash_bank_command)
static int stm32lx_wait_until_bsy_clear(struct flash_bank *bank)
static const struct stm32lx_rev stm32_417_revs[]
static int stm32lx_erase(struct flash_bank *bank, unsigned int first, unsigned int last)
static const struct stm32lx_part_info stm32lx_parts[]
static int stm32lx_unlock(struct flash_bank *bank)
#define FLASH_PECR__PELOCK
static int stm32lx_get_flash_status(struct flash_bank *bank, uint32_t *status)
#define OPTION_BYTE_0_PR1
const struct flash_driver stm32lx_flash
static int stm32lx_obl_launch(struct flash_bank *bank)
COMMAND_HANDLER(stm32lx_handle_mass_erase_command)
static int stm32lx_unlock_options_bytes(struct flash_bank *bank)
static int stm32lx_wait_until_bsy_clear_timeout(struct flash_bank *bank, int timeout)
#define FLASH_SECTOR_SIZE
static int stm32lx_enable_write_half_page(struct flash_bank *bank)
static int stm32lx_lock(struct flash_bank *bank)
#define FLASH_PECR__PRGLOCK
static int stm32lx_get_info(struct flash_bank *bank, struct command_invocation *cmd)
static int stm32lx_write(struct flash_bank *bank, const uint8_t *buffer, uint32_t offset, uint32_t count)
enum arm_arch arch
ARM architecture version.
unsigned int common_magic
When run_command is called, a new instance will be created on the stack, filled with the proper value...
Provides details of a flash bank, available either on-chip or through a major interface.
Provides the implementation-independent structure that defines all of the callbacks required by OpenO...
const char * name
Gives a human-readable name of this flash driver, This field is used to select and initialize the dri...
Describes the geometry and status of a single flash sector within a flash bank.
struct stm32lx_part_info part_info
uint16_t first_bank_size_kb
unsigned int pages_per_sector
const struct stm32lx_rev * revs
uint16_t max_flash_size_kb
int target_halt(struct target *target)
int target_write_buffer(struct target *target, target_addr_t address, uint32_t size, const uint8_t *buffer)
int target_alloc_working_area(struct target *target, uint32_t size, struct working_area **area)
int target_write_u32(struct target *target, target_addr_t address, uint32_t value)
int target_poll(struct target *target)
int target_free_working_area(struct target *target, struct working_area *area)
Free a working area.
int target_run_algorithm(struct target *target, int num_mem_params, struct mem_param *mem_params, int num_reg_params, struct reg_param *reg_param, target_addr_t entry_point, target_addr_t exit_point, int timeout_ms, void *arch_info)
Downloads a target-specific native code algorithm to the target, and executes it.
int target_alloc_working_area_try(struct target *target, uint32_t size, struct working_area **area)
int target_read_u16(struct target *target, target_addr_t address, uint16_t *value)
int target_read_u32(struct target *target, target_addr_t address, uint32_t *value)
#define ERROR_TARGET_NOT_HALTED
#define ERROR_TARGET_RESOURCE_NOT_AVAILABLE
#define ARRAY_SIZE(x)
Compute the number of elements of a variable length array.
static struct ublast_lowlevel_priv info