OpenOCD
sh_qspi.c
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1 // SPDX-License-Identifier: GPL-2.0-only
2 
3 /*
4  * SH QSPI (Quad SPI) driver
5  * Copyright (C) 2019 Marek Vasut <marek.vasut@gmail.com>
6  *
7  * Based on U-Boot SH QSPI driver
8  * Copyright (C) 2013 Renesas Electronics Corporation
9  * Copyright (C) 2013 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
10  */
11 
12 #ifdef HAVE_CONFIG_H
13 #include "config.h"
14 #endif
15 
16 #include "imp.h"
17 #include "spi.h"
18 #include <helper/binarybuffer.h>
19 #include <helper/bits.h>
20 #include <helper/time_support.h>
21 #include <helper/types.h>
22 #include <jtag/jtag.h>
23 #include <target/algorithm.h>
24 #include <target/arm.h>
25 #include <target/arm_opcodes.h>
26 #include <target/target.h>
27 
28 /* SH QSPI register bit masks <REG>_<BIT> */
29 #define SPCR_MSTR 0x08
30 #define SPCR_SPE 0x40
31 #define SPSR_SPRFF 0x80
32 #define SPSR_SPTEF 0x20
33 #define SPPCR_IO3FV 0x04
34 #define SPPCR_IO2FV 0x02
35 #define SPPCR_IO1FV 0x01
36 #define SPBDCR_RXBC0 BIT(0)
37 #define SPCMD_SCKDEN BIT(15)
38 #define SPCMD_SLNDEN BIT(14)
39 #define SPCMD_SPNDEN BIT(13)
40 #define SPCMD_SSLKP BIT(7)
41 #define SPCMD_BRDV0 BIT(2)
42 #define SPCMD_INIT1 (SPCMD_SCKDEN | SPCMD_SLNDEN | \
43  SPCMD_SPNDEN | SPCMD_SSLKP | \
44  SPCMD_BRDV0)
45 #define SPCMD_INIT2 (SPCMD_SPNDEN | SPCMD_SSLKP | \
46  SPCMD_BRDV0)
47 #define SPBFCR_TXRST BIT(7)
48 #define SPBFCR_RXRST BIT(6)
49 #define SPBFCR_TXTRG 0x30
50 #define SPBFCR_RXTRG 0x07
51 
52 /* SH QSPI register set */
53 #define SH_QSPI_SPCR 0x00
54 #define SH_QSPI_SSLP 0x01
55 #define SH_QSPI_SPPCR 0x02
56 #define SH_QSPI_SPSR 0x03
57 #define SH_QSPI_SPDR 0x04
58 #define SH_QSPI_SPSCR 0x08
59 #define SH_QSPI_SPSSR 0x09
60 #define SH_QSPI_SPBR 0x0a
61 #define SH_QSPI_SPDCR 0x0b
62 #define SH_QSPI_SPCKD 0x0c
63 #define SH_QSPI_SSLND 0x0d
64 #define SH_QSPI_SPND 0x0e
65 #define SH_QSPI_DUMMY0 0x0f
66 #define SH_QSPI_SPCMD0 0x10
67 #define SH_QSPI_SPCMD1 0x12
68 #define SH_QSPI_SPCMD2 0x14
69 #define SH_QSPI_SPCMD3 0x16
70 #define SH_QSPI_SPBFCR 0x18
71 #define SH_QSPI_DUMMY1 0x19
72 #define SH_QSPI_SPBDCR 0x1a
73 #define SH_QSPI_SPBMUL0 0x1c
74 #define SH_QSPI_SPBMUL1 0x20
75 #define SH_QSPI_SPBMUL2 0x24
76 #define SH_QSPI_SPBMUL3 0x28
77 
79  const struct flash_device *dev;
80  uint32_t io_base;
81  bool probed;
84  unsigned int buffer_size;
85 };
86 
88  char *name;
89  uint32_t tap_idcode;
90  uint32_t io_base;
91 };
92 
93 static const struct sh_qspi_target target_devices[] = {
94  /* name, tap_idcode, io_base */
95  { "SH QSPI", 0x4ba00477, 0xe6b10000 },
96  { NULL, 0, 0 }
97 };
98 
99 static int sh_qspi_init(struct flash_bank *bank)
100 {
101  struct target *target = bank->target;
102  struct sh_qspi_flash_bank *info = bank->driver_priv;
103  uint8_t val;
104  int ret;
105 
106  /* QSPI initialize */
107  /* Set master mode only */
108  ret = target_write_u8(target, info->io_base + SH_QSPI_SPCR, SPCR_MSTR);
109  if (ret != ERROR_OK)
110  return ret;
111 
112  /* Set SSL signal level */
113  ret = target_write_u8(target, info->io_base + SH_QSPI_SSLP, 0x00);
114  if (ret != ERROR_OK)
115  return ret;
116 
117  /* Set MOSI signal value when transfer is in idle state */
118  ret = target_write_u8(target, info->io_base + SH_QSPI_SPPCR,
120  if (ret != ERROR_OK)
121  return ret;
122 
123  /* Set bit rate. See 58.3.8 Quad Serial Peripheral Interface */
124  ret = target_write_u8(target, info->io_base + SH_QSPI_SPBR, 0x01);
125  if (ret != ERROR_OK)
126  return ret;
127 
128  /* Disable Dummy Data Transmission */
129  ret = target_write_u8(target, info->io_base + SH_QSPI_SPDCR, 0x00);
130  if (ret != ERROR_OK)
131  return ret;
132 
133  /* Set clock delay value */
134  ret = target_write_u8(target, info->io_base + SH_QSPI_SPCKD, 0x00);
135  if (ret != ERROR_OK)
136  return ret;
137 
138  /* Set SSL negation delay value */
139  ret = target_write_u8(target, info->io_base + SH_QSPI_SSLND, 0x00);
140  if (ret != ERROR_OK)
141  return ret;
142 
143  /* Set next-access delay value */
144  ret = target_write_u8(target, info->io_base + SH_QSPI_SPND, 0x00);
145  if (ret != ERROR_OK)
146  return ret;
147 
148  /* Set equence command */
149  ret = target_write_u16(target, info->io_base + SH_QSPI_SPCMD0,
150  SPCMD_INIT2);
151  if (ret != ERROR_OK)
152  return ret;
153 
154  /* Reset transfer and receive Buffer */
155  ret = target_read_u8(target, info->io_base + SH_QSPI_SPBFCR, &val);
156  if (ret != ERROR_OK)
157  return ret;
158 
159  val |= SPBFCR_TXRST | SPBFCR_RXRST;
160 
161  ret = target_write_u8(target, info->io_base + SH_QSPI_SPBFCR, val);
162  if (ret != ERROR_OK)
163  return ret;
164 
165  /* Clear transfer and receive Buffer control bit */
166  ret = target_read_u8(target, info->io_base + SH_QSPI_SPBFCR, &val);
167  if (ret != ERROR_OK)
168  return ret;
169 
170  val &= ~(SPBFCR_TXRST | SPBFCR_RXRST);
171 
172  ret = target_write_u8(target, info->io_base + SH_QSPI_SPBFCR, val);
173  if (ret != ERROR_OK)
174  return ret;
175 
176  /* Set equence control method. Use equence0 only */
177  ret = target_write_u8(target, info->io_base + SH_QSPI_SPSCR, 0x00);
178  if (ret != ERROR_OK)
179  return ret;
180 
181  /* Enable SPI function */
182  ret = target_read_u8(target, info->io_base + SH_QSPI_SPCR, &val);
183  if (ret != ERROR_OK)
184  return ret;
185 
186  val |= SPCR_SPE;
187 
188  return target_write_u8(target, info->io_base + SH_QSPI_SPCR, val);
189 }
190 
192 {
193  struct target *target = bank->target;
194  struct sh_qspi_flash_bank *info = bank->driver_priv;
195  uint8_t val;
196  int ret;
197 
198  /* Set master mode only */
199  ret = target_write_u8(target, info->io_base + SH_QSPI_SPCR, SPCR_MSTR);
200  if (ret != ERROR_OK)
201  return ret;
202 
203  /* Set command */
204  ret = target_write_u16(target, info->io_base + SH_QSPI_SPCMD0,
205  SPCMD_INIT1);
206  if (ret != ERROR_OK)
207  return ret;
208 
209  /* Reset transfer and receive Buffer */
210  ret = target_read_u8(target, info->io_base + SH_QSPI_SPBFCR, &val);
211  if (ret != ERROR_OK)
212  return ret;
213 
214  val |= SPBFCR_TXRST | SPBFCR_RXRST;
215 
216  ret = target_write_u8(target, info->io_base + SH_QSPI_SPBFCR, val);
217  if (ret != ERROR_OK)
218  return ret;
219 
220  /* Clear transfer and receive Buffer control bit */
221  ret = target_read_u8(target, info->io_base + SH_QSPI_SPBFCR, &val);
222  if (ret != ERROR_OK)
223  return ret;
224 
225  val &= ~(SPBFCR_TXRST | SPBFCR_RXRST);
226 
227  ret = target_write_u8(target, info->io_base + SH_QSPI_SPBFCR, val);
228  if (ret != ERROR_OK)
229  return ret;
230 
231  /* Set equence control method. Use equence0 only */
232  ret = target_write_u8(target, info->io_base + SH_QSPI_SPSCR, 0x00);
233  if (ret != ERROR_OK)
234  return ret;
235 
236  /* Enable SPI function */
237  ret = target_read_u8(target, info->io_base + SH_QSPI_SPCR, &val);
238  if (ret != ERROR_OK)
239  return ret;
240 
241  val |= SPCR_SPE;
242 
243  return target_write_u8(target, info->io_base + SH_QSPI_SPCR, val);
244 }
245 
247 {
248  struct target *target = bank->target;
249  struct sh_qspi_flash_bank *info = bank->driver_priv;
250  uint8_t val;
251  int ret;
252 
253  /* Disable SPI Function */
254  ret = target_read_u8(target, info->io_base + SH_QSPI_SPCR, &val);
255  if (ret != ERROR_OK)
256  return ret;
257 
258  val &= ~SPCR_SPE;
259 
260  return target_write_u8(target, info->io_base + SH_QSPI_SPCR, val);
261 }
262 
263 static int sh_qspi_wait_for_bit(struct flash_bank *bank, uint8_t reg,
264  uint32_t mask, bool set,
265  unsigned long timeout)
266 {
267  struct target *target = bank->target;
268  struct sh_qspi_flash_bank *info = bank->driver_priv;
269  long long endtime;
270  uint8_t val;
271  int ret;
272 
273  endtime = timeval_ms() + timeout;
274  do {
275  ret = target_read_u8(target, info->io_base + reg, &val);
276  if (ret != ERROR_OK)
277  return ret;
278 
279  if (!set)
280  val = ~val;
281 
282  if ((val & mask) == mask)
283  return ERROR_OK;
284 
285  alive_sleep(1);
286  } while (timeval_ms() < endtime);
287 
288  LOG_ERROR("timeout");
289  return ERROR_TIMEOUT_REACHED;
290 }
291 
293  const uint8_t *dout, unsigned int outlen,
294  uint8_t *din, unsigned int inlen,
295  bool xfer_start, bool xfer_end)
296 {
297  struct target *target = bank->target;
298  struct sh_qspi_flash_bank *info = bank->driver_priv;
299  uint8_t tdata, rdata;
300  uint8_t val;
301  unsigned int nbyte = outlen + inlen;
302  int ret = 0;
303 
304  if (xfer_start) {
305  ret = sh_qspi_cs_activate(bank);
306  if (ret != ERROR_OK)
307  return ret;
308 
309  ret = target_write_u32(target, info->io_base + SH_QSPI_SPBMUL0,
310  nbyte);
311  if (ret != ERROR_OK)
312  return ret;
313 
314  ret = target_read_u8(target, info->io_base + SH_QSPI_SPBFCR,
315  &val);
316  if (ret != ERROR_OK)
317  return ret;
318 
319  val &= ~(SPBFCR_TXTRG | SPBFCR_RXTRG);
320 
321  ret = target_write_u8(target, info->io_base + SH_QSPI_SPBFCR,
322  val);
323  if (ret != ERROR_OK)
324  return ret;
325  }
326 
327  while (nbyte > 0) {
329  true, 1000);
330  if (ret != ERROR_OK)
331  return ret;
332 
333  tdata = outlen ? *dout++ : 0;
334  ret = target_write_u8(target, info->io_base + SH_QSPI_SPDR,
335  tdata);
336  if (ret != ERROR_OK)
337  return ret;
338 
340  true, 1000);
341  if (ret != ERROR_OK)
342  return ret;
343 
344  ret = target_read_u8(target, info->io_base + SH_QSPI_SPDR,
345  &rdata);
346  if (ret != ERROR_OK)
347  return ret;
348  if (!outlen && inlen) {
349  *din++ = rdata;
350  inlen--;
351  }
352 
353  if (outlen)
354  outlen--;
355 
356  nbyte--;
357  }
358 
359  if (xfer_end)
360  return sh_qspi_cs_deactivate(bank);
361  else
362  return ERROR_OK;
363 }
364 
365 /* Send "write enable" command to SPI flash chip. */
367 {
368  uint8_t dout = SPIFLASH_WRITE_ENABLE;
369 
370  return sh_qspi_xfer_common(bank, &dout, 1, NULL, 0, 1, 1);
371 }
372 
373 /* Read the status register of the external SPI flash chip. */
374 static int read_status_reg(struct flash_bank *bank, uint32_t *status)
375 {
376  uint8_t dout = SPIFLASH_READ_STATUS;
377  uint8_t din;
378  int ret;
379 
380  ret = sh_qspi_xfer_common(bank, &dout, 1, &din, 1, 1, 1);
381  if (ret != ERROR_OK)
382  return ret;
383 
384  *status = din & 0xff;
385 
386  return ERROR_OK;
387 }
388 
389 /* check for WIP (write in progress) bit in status register */
390 /* timeout in ms */
391 static int wait_till_ready(struct flash_bank *bank, int timeout)
392 {
393  long long endtime;
394  uint32_t status;
395  int ret;
396 
397  endtime = timeval_ms() + timeout;
398  do {
399  /* read flash status register */
400  ret = read_status_reg(bank, &status);
401  if (ret != ERROR_OK)
402  return ret;
403 
404  if ((status & SPIFLASH_BSY_BIT) == 0)
405  return ERROR_OK;
406  alive_sleep(1);
407  } while (timeval_ms() < endtime);
408 
409  LOG_ERROR("timeout");
410  return ERROR_TIMEOUT_REACHED;
411 }
412 
413 static int sh_qspi_erase_sector(struct flash_bank *bank, int sector)
414 {
415  struct sh_qspi_flash_bank *info = bank->driver_priv;
416  bool addr4b = info->dev->size_in_bytes > (1UL << 24);
417  uint32_t address = (sector * info->dev->sectorsize) <<
418  (addr4b ? 0 : 8);
419  uint8_t dout[5] = {
420  info->dev->erase_cmd,
421  (address >> 24) & 0xff, (address >> 16) & 0xff,
422  (address >> 8) & 0xff, (address >> 0) & 0xff
423  };
424  unsigned int doutlen = addr4b ? 5 : 4;
425  int ret;
426 
427  /* Write Enable */
428  ret = sh_qspi_write_enable(bank);
429  if (ret != ERROR_OK)
430  return ret;
431 
432  /* Erase */
433  ret = sh_qspi_xfer_common(bank, dout, doutlen, NULL, 0, 1, 1);
434  if (ret != ERROR_OK)
435  return ret;
436 
437  /* Poll status register */
438  return wait_till_ready(bank, 3000);
439 }
440 
441 static int sh_qspi_erase(struct flash_bank *bank, unsigned int first,
442  unsigned int last)
443 {
444  struct target *target = bank->target;
445  struct sh_qspi_flash_bank *info = bank->driver_priv;
446  int retval = ERROR_OK;
447 
448  LOG_DEBUG("%s: from sector %u to sector %u", __func__, first, last);
449 
450  if (target->state != TARGET_HALTED) {
451  LOG_ERROR("Target not halted");
453  }
454 
455  if ((last < first) || (last >= bank->num_sectors)) {
456  LOG_ERROR("Flash sector invalid");
458  }
459 
460  if (!info->probed) {
461  LOG_ERROR("Flash bank not probed");
463  }
464 
465  if (info->dev->erase_cmd == 0x00)
467 
468  for (unsigned int sector = first; sector <= last; sector++) {
469  if (bank->sectors[sector].is_protected) {
470  LOG_ERROR("Flash sector %u protected", sector);
471  return ERROR_FAIL;
472  }
473  }
474 
475  for (unsigned int sector = first; sector <= last; sector++) {
476  retval = sh_qspi_erase_sector(bank, sector);
477  if (retval != ERROR_OK)
478  break;
479  keep_alive();
480  }
481 
482  return retval;
483 }
484 
485 static int sh_qspi_write(struct flash_bank *bank, const uint8_t *buffer,
486  uint32_t offset, uint32_t count)
487 {
488  struct target *target = bank->target;
489  struct sh_qspi_flash_bank *info = bank->driver_priv;
490  struct reg_param reg_params[4];
491  struct arm_algorithm arm_algo;
492  uint32_t io_base = (uint32_t)(info->io_base);
493  uint32_t src_base = (uint32_t)(info->source->address);
494  uint32_t chunk;
495  bool addr4b = !!(info->dev->size_in_bytes > (1UL << 24));
496  int ret = ERROR_OK;
497 
498  LOG_DEBUG("%s: offset=0x%08" PRIx32 " count=0x%08" PRIx32,
499  __func__, offset, count);
500 
501  if (target->state != TARGET_HALTED) {
502  LOG_ERROR("Target not halted");
504  }
505 
506  if (offset + count > bank->size) {
507  LOG_WARNING("Write pasts end of flash. Extra data discarded.");
508  count = bank->size - offset;
509  }
510 
511  if (offset & 0xff) {
512  LOG_ERROR("sh_qspi_write_page: unaligned write address: %08" PRIx32,
513  offset);
514  return ERROR_FAIL;
515  }
516 
517  /* Check sector protection */
518  for (unsigned int sector = 0; sector < bank->num_sectors; sector++) {
519  /* Start offset in or before this sector? */
520  /* End offset in or behind this sector? */
521  struct flash_sector *bs = &bank->sectors[sector];
522 
523  if ((offset < (bs->offset + bs->size)) &&
524  ((offset + count - 1) >= bs->offset) &&
525  bs->is_protected) {
526  LOG_ERROR("Flash sector %u protected", sector);
527  return ERROR_FAIL;
528  }
529  }
530 
531  LOG_DEBUG("%s: offset=0x%08" PRIx32 " count=0x%08" PRIx32,
532  __func__, offset, count);
533 
534  if (target->state != TARGET_HALTED) {
535  LOG_ERROR("Target not halted");
537  }
538 
539  if (offset + count > bank->size) {
540  LOG_WARNING("Reads past end of flash. Extra data discarded.");
541  count = bank->size - offset;
542  }
543 
544  arm_algo.common_magic = ARM_COMMON_MAGIC;
545  arm_algo.core_mode = ARM_MODE_SVC;
546  arm_algo.core_state = ARM_STATE_ARM;
547 
548  init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
549  init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
550  init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
551  init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT);
552 
553  while (count > 0) {
554  chunk = (count > info->buffer_size) ?
555  info->buffer_size : count;
556 
557  target_write_buffer(target, info->source->address,
558  chunk, buffer);
559 
560  buf_set_u32(reg_params[0].value, 0, 32, io_base);
561  buf_set_u32(reg_params[1].value, 0, 32, src_base);
562  buf_set_u32(reg_params[2].value, 0, 32,
563  (1 << 31) | (addr4b << 30) |
564  (info->dev->pprog_cmd << 20) | chunk);
565  buf_set_u32(reg_params[3].value, 0, 32, offset);
566 
567  ret = target_run_algorithm(target, 0, NULL, 4, reg_params,
568  info->io_algorithm->address,
569  0, 10000, &arm_algo);
570  if (ret != ERROR_OK) {
571  LOG_ERROR("error executing SH QSPI flash IO algorithm");
573  break;
574  }
575 
576  buffer += chunk;
577  offset += chunk;
578  count -= chunk;
579  }
580 
581  destroy_reg_param(&reg_params[0]);
582  destroy_reg_param(&reg_params[1]);
583  destroy_reg_param(&reg_params[2]);
584  destroy_reg_param(&reg_params[3]);
585 
586  return ret;
587 }
588 
589 static int sh_qspi_read(struct flash_bank *bank, uint8_t *buffer,
590  uint32_t offset, uint32_t count)
591 {
592  struct target *target = bank->target;
593  struct sh_qspi_flash_bank *info = bank->driver_priv;
594  struct reg_param reg_params[4];
595  struct arm_algorithm arm_algo;
596  uint32_t io_base = (uint32_t)(info->io_base);
597  uint32_t src_base = (uint32_t)(info->source->address);
598  uint32_t chunk;
599  bool addr4b = !!(info->dev->size_in_bytes > (1UL << 24));
600  int ret = ERROR_OK;
601 
602  LOG_DEBUG("%s: offset=0x%08" PRIx32 " count=0x%08" PRIx32,
603  __func__, offset, count);
604 
605  if (target->state != TARGET_HALTED) {
606  LOG_ERROR("Target not halted");
608  }
609 
610  if (offset + count > bank->size) {
611  LOG_WARNING("Reads past end of flash. Extra data discarded.");
612  count = bank->size - offset;
613  }
614 
615  arm_algo.common_magic = ARM_COMMON_MAGIC;
616  arm_algo.core_mode = ARM_MODE_SVC;
617  arm_algo.core_state = ARM_STATE_ARM;
618 
619  init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
620  init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
621  init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
622  init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT);
623 
624  while (count > 0) {
625  chunk = (count > info->buffer_size) ?
626  info->buffer_size : count;
627 
628  buf_set_u32(reg_params[0].value, 0, 32, io_base);
629  buf_set_u32(reg_params[1].value, 0, 32, src_base);
630  buf_set_u32(reg_params[2].value, 0, 32,
631  (addr4b << 30) | (info->dev->read_cmd << 20) |
632  chunk);
633  buf_set_u32(reg_params[3].value, 0, 32, offset);
634 
635  ret = target_run_algorithm(target, 0, NULL, 4, reg_params,
636  info->io_algorithm->address,
637  0, 10000, &arm_algo);
638  if (ret != ERROR_OK) {
639  LOG_ERROR("error executing SH QSPI flash IO algorithm");
641  break;
642  }
643 
644  target_read_buffer(target, info->source->address,
645  chunk, buffer);
646 
647  buffer += chunk;
648  offset += chunk;
649  count -= chunk;
650  }
651 
652  destroy_reg_param(&reg_params[0]);
653  destroy_reg_param(&reg_params[1]);
654  destroy_reg_param(&reg_params[2]);
655  destroy_reg_param(&reg_params[3]);
656 
657  return ret;
658 }
659 
660 /* Return ID of flash device */
661 static int read_flash_id(struct flash_bank *bank, uint32_t *id)
662 {
663  struct target *target = bank->target;
664  uint8_t dout = SPIFLASH_READ_ID;
665  uint8_t din[3] = { 0, 0, 0 };
666  int ret;
667 
668  if (target->state != TARGET_HALTED) {
669  LOG_ERROR("Target not halted");
671  }
672 
673  ret = sh_qspi_xfer_common(bank, &dout, 1, din, 3, 1, 1);
674  if (ret != ERROR_OK)
675  return ret;
676 
677  *id = (din[0] << 0) | (din[1] << 8) | (din[2] << 16);
678 
679  if (*id == 0xffffff) {
680  LOG_ERROR("No SPI flash found");
681  return ERROR_FAIL;
682  }
683 
684  return ERROR_OK;
685 }
686 
687 static int sh_qspi_protect(struct flash_bank *bank, int set,
688  unsigned int first, unsigned int last)
689 {
690  for (unsigned int sector = first; sector <= last; sector++)
691  bank->sectors[sector].is_protected = set;
692 
693  return ERROR_OK;
694 }
695 
697 {
698  struct target *target = bank->target;
699  struct sh_qspi_flash_bank *info = bank->driver_priv;
700 
701  /* see contrib/loaders/flash/sh_qspi.s for src */
702  static const uint8_t sh_qspi_io_code[] = {
703 #include "../../../contrib/loaders/flash/sh_qspi/sh_qspi.inc"
704  };
705  int ret;
706 
708  target_free_working_area(target, info->io_algorithm);
709 
710  /* FIXME: Working areas are allocated during flash probe
711  * and eventual target_free_all_working_areas() called in case
712  * of target reset or run is not handled at all.
713  * Not a big problem if area backp is off.
714  */
715  /* flash write code */
716  if (target_alloc_working_area(target, sizeof(sh_qspi_io_code),
717  &info->io_algorithm) != ERROR_OK) {
718  LOG_WARNING("no working area available, can't do block memory writes");
720  }
721 
722  target_write_buffer(target, info->io_algorithm->address,
723  sizeof(sh_qspi_io_code), sh_qspi_io_code);
724 
725  /*
726  * Try to allocate as big work area buffer as possible, start
727  * with 32 kiB and count down. If there is less than 256 Bytes
728  * of work area available, abort.
729  */
730  info->buffer_size = 32768;
731  while (true) {
732  ret = target_alloc_working_area_try(target, info->buffer_size,
733  &info->source);
734  if (ret == ERROR_OK)
735  return ret;
736 
737  info->buffer_size /= 2;
738  if (info->buffer_size <= 256) {
739  target_free_working_area(target, info->io_algorithm);
740 
741  LOG_WARNING("no large enough working area available, can't do block memory writes");
743  }
744  }
745 
746  return ERROR_OK;
747 }
748 
749 static int sh_qspi_probe(struct flash_bank *bank)
750 {
751  struct target *target = bank->target;
752  struct sh_qspi_flash_bank *info = bank->driver_priv;
753  struct flash_sector *sectors;
754  uint32_t id = 0; /* silence uninitialized warning */
755  uint32_t sectorsize;
756  const struct sh_qspi_target *target_device;
757  int ret;
758 
759  if (info->probed)
760  free(bank->sectors);
761 
762  info->probed = false;
763 
764  for (target_device = target_devices; target_device->name;
765  ++target_device)
766  if (target_device->tap_idcode == target->tap->idcode)
767  break;
768  if (!target_device->name) {
769  LOG_ERROR("Device ID 0x%" PRIx32 " is not known",
770  target->tap->idcode);
771  return ERROR_FAIL;
772  }
773 
774  info->io_base = target_device->io_base;
775 
776  LOG_DEBUG("Found device %s at address " TARGET_ADDR_FMT,
777  target_device->name, bank->base);
778 
780  if (ret != ERROR_OK)
781  return ret;
782 
783  ret = sh_qspi_init(bank);
784  if (ret != ERROR_OK)
785  return ret;
786 
787  ret = read_flash_id(bank, &id);
788  if (ret != ERROR_OK)
789  return ret;
790 
791  info->dev = NULL;
792  for (const struct flash_device *p = flash_devices; p->name; p++)
793  if (p->device_id == id) {
794  info->dev = p;
795  break;
796  }
797 
798  if (!info->dev) {
799  LOG_ERROR("Unknown flash device (ID 0x%08" PRIx32 ")", id);
800  return ERROR_FAIL;
801  }
802 
803  LOG_INFO("Found flash device \'%s\' (ID 0x%08" PRIx32 ")",
804  info->dev->name, info->dev->device_id);
805 
806  /* Set correct size value */
807  bank->size = info->dev->size_in_bytes;
808  if (bank->size <= (1UL << 16))
809  LOG_WARNING("device needs 2-byte addresses - not implemented");
810 
811  /* if no sectors, treat whole bank as single sector */
812  sectorsize = info->dev->sectorsize ?
813  info->dev->sectorsize :
814  info->dev->size_in_bytes;
815 
816  /* create and fill sectors array */
817  bank->num_sectors = info->dev->size_in_bytes / sectorsize;
818  sectors = calloc(1, sizeof(*sectors) * bank->num_sectors);
819  if (!sectors) {
820  LOG_ERROR("not enough memory");
821  return ERROR_FAIL;
822  }
823 
824  for (unsigned int sector = 0; sector < bank->num_sectors; sector++) {
825  sectors[sector].offset = sector * sectorsize;
826  sectors[sector].size = sectorsize;
827  sectors[sector].is_erased = 0;
828  sectors[sector].is_protected = 0;
829  }
830 
831  bank->sectors = sectors;
832  info->probed = true;
833  return ERROR_OK;
834 }
835 
836 static int sh_qspi_auto_probe(struct flash_bank *bank)
837 {
838  struct sh_qspi_flash_bank *info = bank->driver_priv;
839 
840  if (info->probed)
841  return ERROR_OK;
842 
843  return sh_qspi_probe(bank);
844 }
845 
847 {
848  /* Not implemented */
849  return ERROR_OK;
850 }
851 
853 {
854  /* Not implemented */
855  return ERROR_OK;
856 }
857 
859 {
860  struct sh_qspi_flash_bank *info = bank->driver_priv;
861 
862  if (!info->probed) {
863  command_print_sameline(cmd, "\nSH QSPI flash bank not probed yet\n");
864  return ERROR_OK;
865  }
866 
867  command_print_sameline(cmd, "\nSH QSPI flash information:\n"
868  " Device \'%s\' (ID 0x%08" PRIx32 ")\n",
869  info->dev->name, info->dev->device_id);
870 
871  return ERROR_OK;
872 }
873 
874 FLASH_BANK_COMMAND_HANDLER(sh_qspi_flash_bank_command)
875 {
876  struct sh_qspi_flash_bank *info;
877 
878  LOG_DEBUG("%s", __func__);
879 
880  if (CMD_ARGC < 6 || CMD_ARGC > 7)
882 
883  if ((CMD_ARGC == 7) && strcmp(CMD_ARGV[6], "cs0")) {
884  LOG_ERROR("Unknown arg: %s", CMD_ARGV[6]);
886  }
887 
888  info = calloc(1, sizeof(struct sh_qspi_flash_bank));
889  if (!info) {
890  LOG_ERROR("not enough memory");
891  return ERROR_FAIL;
892  }
893 
894  bank->driver_priv = info;
895 
896  return ERROR_OK;
897 }
898 
899 const struct flash_driver sh_qspi_flash = {
900  .name = "sh_qspi",
901  .flash_bank_command = sh_qspi_flash_bank_command,
902  .erase = sh_qspi_erase,
903  .protect = sh_qspi_protect,
904  .write = sh_qspi_write,
905  .read = sh_qspi_read,
906  .probe = sh_qspi_probe,
907  .auto_probe = sh_qspi_auto_probe,
908  .erase_check = sh_qspi_flash_blank_check,
909  .protect_check = sh_qspi_protect_check,
910  .info = sh_qspi_get_info,
911  .free_driver_priv = default_flash_free_driver_priv,
912 };
void init_reg_param(struct reg_param *param, char *reg_name, uint32_t size, enum param_direction direction)
Definition: algorithm.c:29
void destroy_reg_param(struct reg_param *param)
Definition: algorithm.c:37
@ PARAM_OUT
Definition: algorithm.h:16
Holds the interface to ARM cores.
#define ARM_COMMON_MAGIC
Definition: arm.h:158
@ ARM_MODE_SVC
Definition: arm.h:78
@ ARM_STATE_ARM
Definition: arm.h:143
Macros used to generate various ARM or Thumb opcodes.
Support functions to access arbitrary bits in a byte array.
static void buf_set_u32(uint8_t *_buffer, unsigned first, unsigned num, uint32_t value)
Sets num bits in _buffer, starting at the first bit, using the bits in value.
Definition: binarybuffer.h:30
void command_print_sameline(struct command_invocation *cmd, const char *format,...)
Definition: command.c:450
#define CMD_ARGV
Use this macro to access the arguments for the command being handled, rather than accessing the varia...
Definition: command.h:155
#define ERROR_COMMAND_SYNTAX_ERROR
Definition: command.h:385
#define CMD_ARGC
Use this macro to access the number of arguments for the command being handled, rather than accessing...
Definition: command.h:150
uint8_t bank
Definition: esirisc.c:135
int mask
Definition: esirisc.c:1698
#define ERROR_FLASH_OPER_UNSUPPORTED
Definition: flash/common.h:36
#define ERROR_FLASH_SECTOR_INVALID
Definition: flash/common.h:29
#define ERROR_FLASH_BANK_NOT_PROBED
Definition: flash/common.h:35
#define ERROR_FLASH_OPERATION_FAILED
Definition: flash/common.h:30
void default_flash_free_driver_priv(struct flash_bank *bank)
Deallocates bank->driver_priv.
The JTAG interface can be implemented with a software or hardware fifo.
void alive_sleep(uint64_t ms)
Definition: log.c:460
void keep_alive(void)
Definition: log.c:419
#define LOG_WARNING(expr ...)
Definition: log.h:120
#define ERROR_FAIL
Definition: log.h:161
#define LOG_ERROR(expr ...)
Definition: log.h:123
#define ERROR_TIMEOUT_REACHED
Definition: log.h:164
#define LOG_INFO(expr ...)
Definition: log.h:117
#define LOG_DEBUG(expr ...)
Definition: log.h:109
#define ERROR_OK
Definition: log.h:155
static int sh_qspi_wait_for_bit(struct flash_bank *bank, uint8_t reg, uint32_t mask, bool set, unsigned long timeout)
Definition: sh_qspi.c:263
static int sh_qspi_write_enable(struct flash_bank *bank)
Definition: sh_qspi.c:366
static int read_flash_id(struct flash_bank *bank, uint32_t *id)
Definition: sh_qspi.c:661
#define SPPCR_IO3FV
Definition: sh_qspi.c:33
#define SPCMD_INIT2
Definition: sh_qspi.c:45
static int sh_qspi_protect_check(struct flash_bank *bank)
Definition: sh_qspi.c:852
#define SPCR_MSTR
Definition: sh_qspi.c:29
static int sh_qspi_get_info(struct flash_bank *bank, struct command_invocation *cmd)
Definition: sh_qspi.c:858
static int sh_qspi_probe(struct flash_bank *bank)
Definition: sh_qspi.c:749
#define SH_QSPI_SPBR
Definition: sh_qspi.c:60
#define SPBFCR_RXTRG
Definition: sh_qspi.c:50
#define SPSR_SPTEF
Definition: sh_qspi.c:32
#define SH_QSPI_SPCR
Definition: sh_qspi.c:53
static int sh_qspi_erase_sector(struct flash_bank *bank, int sector)
Definition: sh_qspi.c:413
static int sh_qspi_protect(struct flash_bank *bank, int set, unsigned int first, unsigned int last)
Definition: sh_qspi.c:687
#define SH_QSPI_SPSCR
Definition: sh_qspi.c:58
static const struct sh_qspi_target target_devices[]
Definition: sh_qspi.c:93
#define SH_QSPI_SPBMUL0
Definition: sh_qspi.c:73
#define SH_QSPI_SPND
Definition: sh_qspi.c:64
static int sh_qspi_upload_helper(struct flash_bank *bank)
Definition: sh_qspi.c:696
static int read_status_reg(struct flash_bank *bank, uint32_t *status)
Definition: sh_qspi.c:374
#define SH_QSPI_SPCKD
Definition: sh_qspi.c:62
static int sh_qspi_init(struct flash_bank *bank)
Definition: sh_qspi.c:99
#define SH_QSPI_SSLP
Definition: sh_qspi.c:54
#define SH_QSPI_SPCMD0
Definition: sh_qspi.c:66
static int sh_qspi_auto_probe(struct flash_bank *bank)
Definition: sh_qspi.c:836
const struct flash_driver sh_qspi_flash
Definition: sh_qspi.c:899
#define SH_QSPI_SPDR
Definition: sh_qspi.c:57
FLASH_BANK_COMMAND_HANDLER(sh_qspi_flash_bank_command)
Definition: sh_qspi.c:874
static int sh_qspi_cs_activate(struct flash_bank *bank)
Definition: sh_qspi.c:191
#define SPCMD_INIT1
Definition: sh_qspi.c:42
static int sh_qspi_write(struct flash_bank *bank, const uint8_t *buffer, uint32_t offset, uint32_t count)
Definition: sh_qspi.c:485
#define SH_QSPI_SPSR
Definition: sh_qspi.c:56
#define SPBFCR_TXTRG
Definition: sh_qspi.c:49
static int wait_till_ready(struct flash_bank *bank, int timeout)
Definition: sh_qspi.c:391
#define SPCR_SPE
Definition: sh_qspi.c:30
static int sh_qspi_xfer_common(struct flash_bank *bank, const uint8_t *dout, unsigned int outlen, uint8_t *din, unsigned int inlen, bool xfer_start, bool xfer_end)
Definition: sh_qspi.c:292
#define SH_QSPI_SPDCR
Definition: sh_qspi.c:61
#define SH_QSPI_SPBFCR
Definition: sh_qspi.c:70
#define SH_QSPI_SPPCR
Definition: sh_qspi.c:55
static int sh_qspi_erase(struct flash_bank *bank, unsigned int first, unsigned int last)
Definition: sh_qspi.c:441
static int sh_qspi_read(struct flash_bank *bank, uint8_t *buffer, uint32_t offset, uint32_t count)
Definition: sh_qspi.c:589
static int sh_qspi_flash_blank_check(struct flash_bank *bank)
Definition: sh_qspi.c:846
static int sh_qspi_cs_deactivate(struct flash_bank *bank)
Definition: sh_qspi.c:246
#define SPBFCR_TXRST
Definition: sh_qspi.c:47
#define SPPCR_IO2FV
Definition: sh_qspi.c:34
#define SPBFCR_RXRST
Definition: sh_qspi.c:48
#define SPSR_SPRFF
Definition: sh_qspi.c:31
#define SH_QSPI_SSLND
Definition: sh_qspi.c:63
const struct flash_device flash_devices[]
Definition: spi.c:24
#define SPIFLASH_READ_STATUS
Definition: spi.h:74
#define SPIFLASH_READ_ID
Definition: spi.h:72
#define SPIFLASH_WRITE_ENABLE
Definition: spi.h:75
#define SPIFLASH_BSY_BIT
Definition: spi.h:67
unsigned int common_magic
Definition: arm.h:256
enum arm_mode core_mode
Definition: arm.h:258
enum arm_state core_state
Definition: arm.h:259
When run_command is called, a new instance will be created on the stack, filled with the proper value...
Definition: command.h:76
Provides details of a flash bank, available either on-chip or through a major interface.
Definition: nor/core.h:75
const char * name
Definition: spi.h:21
Provides the implementation-independent structure that defines all of the callbacks required by OpenO...
Definition: nor/driver.h:39
const char * name
Gives a human-readable name of this flash driver, This field is used to select and initialize the dri...
Definition: nor/driver.h:44
Describes the geometry and status of a single flash sector within a flash bank.
Definition: nor/core.h:28
int is_erased
Indication of erasure status: 0 = not erased, 1 = erased, other = unknown.
Definition: nor/core.h:42
uint32_t offset
Bus offset from start of the flash chip (in bytes).
Definition: nor/core.h:30
int is_protected
Indication of protection status: 0 = unprotected/unlocked, 1 = protected/locked, other = unknown.
Definition: nor/core.h:55
uint32_t size
Number of bytes in this flash sector.
Definition: nor/core.h:32
uint32_t idcode
device identification code
Definition: jtag.h:114
Definition: register.h:111
struct working_area * source
Definition: sh_qspi.c:83
const struct flash_device * dev
Definition: sh_qspi.c:79
struct working_area * io_algorithm
Definition: sh_qspi.c:82
unsigned int buffer_size
Definition: sh_qspi.c:84
uint32_t io_base
Definition: sh_qspi.c:80
uint32_t io_base
Definition: sh_qspi.c:90
char * name
Definition: sh_qspi.c:88
uint32_t tap_idcode
Definition: sh_qspi.c:89
Definition: target.h:120
struct jtag_tap * tap
Definition: target.h:124
enum target_state state
Definition: target.h:162
Definition: psoc6.c:84
int target_write_buffer(struct target *target, target_addr_t address, uint32_t size, const uint8_t *buffer)
Definition: target.c:2408
int target_write_u8(struct target *target, target_addr_t address, uint8_t value)
Definition: target.c:2749
int target_write_u16(struct target *target, target_addr_t address, uint16_t value)
Definition: target.c:2728
int target_read_buffer(struct target *target, target_addr_t address, uint32_t size, uint8_t *buffer)
Definition: target.c:2473
int target_read_u8(struct target *target, target_addr_t address, uint8_t *value)
Definition: target.c:2664
int target_alloc_working_area(struct target *target, uint32_t size, struct working_area **area)
Definition: target.c:2129
int target_write_u32(struct target *target, target_addr_t address, uint32_t value)
Definition: target.c:2707
int target_free_working_area(struct target *target, struct working_area *area)
Free a working area.
Definition: target.c:2187
int target_run_algorithm(struct target *target, int num_mem_params, struct mem_param *mem_params, int num_reg_params, struct reg_param *reg_param, target_addr_t entry_point, target_addr_t exit_point, int timeout_ms, void *arch_info)
Downloads a target-specific native code algorithm to the target, and executes it.
Definition: target.c:846
int target_alloc_working_area_try(struct target *target, uint32_t size, struct working_area **area)
Definition: target.c:2035
#define ERROR_TARGET_NOT_HALTED
Definition: target.h:792
@ TARGET_HALTED
Definition: target.h:55
#define ERROR_TARGET_RESOURCE_NOT_AVAILABLE
Definition: target.h:796
int64_t timeval_ms(void)
#define TARGET_ADDR_FMT
Definition: types.h:342
static struct ublast_lowlevel_priv info
#define NULL
Definition: usb.h:16
uint8_t status[4]
Definition: vdebug.c:17
uint8_t cmd
Definition: vdebug.c:1
uint8_t offset[4]
Definition: vdebug.c:9
uint8_t count[4]
Definition: vdebug.c:22