17 #ifdef HAVE_SYS_IOCTL_H
18 #include <sys/ioctl.h>
24 #define RSH_MMIO_CHANNEL_RSHIM 0x1
27 #define RSH_CS_ROM_BASE 0x80000000
28 #define RSH_CS_TILE_BASE 0x44000000
29 #define RSH_CS_TILE_SIZE 0x04000000
36 #define APB_AP_IDR 0x44770002
39 #define RSH_CORESIGHT_CTL 0x0e00
40 #define RSH_CORESIGHT_CTL_GO_SHIFT 0
41 #define RSH_CORESIGHT_CTL_GO_MASK 0x1ULL
42 #define RSH_CORESIGHT_CTL_ACTION_SHIFT 1
43 #define RSH_CORESIGHT_CTL_ACTION_MASK 0x2ULL
44 #define RSH_CORESIGHT_CTL_ADDR_SHIFT 2
45 #define RSH_CORESIGHT_CTL_ADDR_MASK 0x7ffffffcULL
46 #define RSH_CORESIGHT_CTL_ERR_SHIFT 31
47 #define RSH_CORESIGHT_CTL_ERR_MASK 0x80000000ULL
48 #define RSH_CORESIGHT_CTL_DATA_SHIFT 32
49 #define RSH_CORESIGHT_CTL_DATA_MASK 0xffffffff00000000ULL
52 #define RSH_CS_GET_FIELD(reg, field) \
53 (((uint64_t)(reg) & RSH_CORESIGHT_CTL_##field##_MASK) >> \
54 RSH_CORESIGHT_CTL_##field##_SHIFT)
56 #define RSH_CS_SET_FIELD(reg, field, value) \
57 (reg) = (((reg) & ~RSH_CORESIGHT_CTL_##field##_MASK) | \
58 (((uint64_t)(value) << RSH_CORESIGHT_CTL_##field##_SHIFT) & \
59 RSH_CORESIGHT_CTL_##field##_MASK))
61 #ifdef HAVE_SYS_IOCTL_H
69 RSH_IOC_READ = _IOWR(
'R', 0, rshim_ioctl_msg),
70 RSH_IOC_WRITE = _IOWR(
'R', 1, rshim_ioctl_msg),
95 #define RSHIM_DEV_PATH_DEFAULT "/dev/rshim0/rshim"
105 #ifdef HAVE_SYS_IOCTL_H
106 if (rc < 0 && errno == ENOSYS) {
111 rc = ioctl(
rshim_fd, RSH_IOC_READ, &msg);
127 #ifdef HAVE_SYS_IOCTL_H
128 if (rc < 0 && errno == ENOSYS) {
133 rc = ioctl(
rshim_fd, RSH_IOC_WRITE, &msg);
275 static bool error_flagged;
277 LOG_ERROR(
"ADIv6 dap not supported by rshim dap-direct mode");
278 error_flagged =
true;
339 static bool error_flagged;
341 LOG_ERROR(
"ADIv6 dap not supported by rshim dap-direct mode");
342 error_flagged =
true;
410 rshim_fd = open(path, O_RDWR | O_SYNC);
450 .handler = rshim_dap_device_command,
452 .help =
"set the rshim device",
453 .usage =
"</dev/rshim<N>/rshim>",
462 .help =
"perform rshim management",
This defines formats and data structures used to talk to ADIv5 entities.
#define ADIV5_MEM_AP_REG_DRW
#define ADIV5_MEM_AP_REG_BD3
#define ADIV5_MEM_AP_REG_BD2
#define ADIV5_MEM_AP_REG_CFG
#define ADIV5_MEM_AP_REG_BD1
#define ADIV5_MEM_AP_REG_BASE
#define ADIV5_MEM_AP_REG_CSW
static bool is_adiv6(const struct adiv5_dap *dap)
Check if DAP is ADIv6.
#define ADIV5_MEM_AP_REG_TAR
#define ADIV5_MEM_AP_REG_BD0
void command_print(struct command_invocation *cmd, const char *format,...)
#define CMD
Use this macro to access the command being handled, rather than accessing the variable directly.
#define CMD_ARGV
Use this macro to access the arguments for the command being handled, rather than accessing the varia...
#define ERROR_COMMAND_SYNTAX_ERROR
#define CMD_ARGC
Use this macro to access the number of arguments for the command being handled, rather than accessing...
#define COMMAND_REGISTRATION_DONE
Use this as the last entry in an array of command_registration records.
struct esp_usb_jtag __attribute__
#define LOG_ERROR(expr ...)
#define LOG_INFO(expr ...)
#define RSH_CS_SET_FIELD(reg, field, value)
static int rshim_ap_q_write(struct adiv5_ap *ap, unsigned int reg, uint32_t data)
static int rshim_ap_q_read(struct adiv5_ap *ap, unsigned int reg, uint32_t *data)
static int rshim_dap_retval
static int rshim_dap_reset(int req_trst, int req_srst)
#define RSH_CORESIGHT_CTL
static int rshim_dap_khz(int khz, int *jtag_speed)
static int rshim_connect(struct adiv5_dap *dap)
static int rshim_dev_read(int chan, int addr, uint64_t *value)
static uint32_t dp_id_code
static int rshim_dap_speed(int speed)
static int rshim_dap_speed_div(int speed, int *khz)
static int rshim_dp_q_read(struct adiv5_dap *dap, unsigned int reg, uint32_t *data)
static int(* rshim_write)(int chan, int addr, uint64_t value)
static int rshim_dp_q_write(struct adiv5_dap *dap, unsigned int reg, uint32_t data)
#define RSH_CS_GET_FIELD(reg, field)
static const struct dap_ops rshim_dap_ops
static int coresight_write(uint32_t tile, uint32_t addr, uint32_t wdata)
static int(* rshim_read)(int chan, int addr, uint64_t *value)
COMMAND_HANDLER(rshim_dap_device_command)
static const struct command_registration rshim_dap_subcommand_handlers[]
struct adapter_driver rshim_dap_adapter_driver
static int rshim_ap_q_abort(struct adiv5_dap *dap, uint8_t *ack)
static uint32_t dp_ctrl_stat
static const struct command_registration rshim_dap_command_handlers[]
#define RSH_MMIO_CHANNEL_RSHIM
static int rshim_dp_run(struct adiv5_dap *dap)
static int rshim_dap_init(void)
static int rshim_dap_quit(void)
static void ap_addr_2_tile(int *tile, uint32_t *addr)
static void rshim_disconnect(struct adiv5_dap *dap)
static int rshim_dev_write(int chan, int addr, uint64_t value)
static char * rshim_dev_path
#define RSHIM_DEV_PATH_DEFAULT
static const char *const rshim_dap_transport[]
static uint32_t ap_tar_inc
static int coresight_read(uint32_t tile, uint32_t addr, uint32_t *value)
Represents a driver for a debugging interface.
const char *const name
The name of the interface driver.
This represents an ARM Debug Interface (v5) Access Port (AP).
uint64_t ap_num
ADIv5: Number of this AP (0~255) ADIv6: Base address of this AP (4k aligned) TODO: to be more coheren...
struct adiv5_dap * dap
DAP this AP belongs to.
This represents an ARM Debug Interface (v5) Debug Access Port (DAP).
const char * usage
a string listing the options and arguments, required or optional
Transport-neutral representation of queued DAP transactions, supporting both JTAG and SWD transports.
int(* connect)(struct adiv5_dap *dap)
connect operation for SWD