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etb.c
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1 // SPDX-License-Identifier: GPL-2.0-or-later
2 
3 /***************************************************************************
4  * Copyright (C) 2007 by Dominic Rath *
5  * Dominic.Rath@gmx.de *
6  ***************************************************************************/
7 
8 #ifdef HAVE_CONFIG_H
9 #include "config.h"
10 #endif
11 
12 #include "arm.h"
13 #include "etm.h"
14 #include "etb.h"
15 #include "register.h"
16 
17 static const char * const etb_reg_list[] = {
18  "ETB_identification",
19  "ETB_ram_depth",
20  "ETB_ram_width",
21  "ETB_status",
22  "ETB_ram_data",
23  "ETB_ram_read_pointer",
24  "ETB_ram_write_pointer",
25  "ETB_trigger_counter",
26  "ETB_control",
27 };
28 
29 static int etb_get_reg(struct reg *reg);
30 
31 static int etb_set_instr(struct etb *etb, uint32_t new_instr)
32 {
33  struct jtag_tap *tap;
34 
35  tap = etb->tap;
36  if (!tap)
37  return ERROR_FAIL;
38 
39  if (buf_get_u32(tap->cur_instr, 0, tap->ir_length) != new_instr) {
40  struct scan_field field;
41 
42  field.num_bits = tap->ir_length;
43  void *t = calloc(DIV_ROUND_UP(field.num_bits, 8), 1);
44  field.out_value = t;
45  buf_set_u32(t, 0, field.num_bits, new_instr);
46 
47  field.in_value = NULL;
48 
49  jtag_add_ir_scan(tap, &field, TAP_IDLE);
50 
51  free(t);
52  }
53 
54  return ERROR_OK;
55 }
56 
57 static int etb_scann(struct etb *etb, uint32_t new_scan_chain)
58 {
59  if (etb->cur_scan_chain != new_scan_chain) {
60  struct scan_field field;
61 
62  field.num_bits = 5;
63  void *t = calloc(DIV_ROUND_UP(field.num_bits, 8), 1);
64  field.out_value = t;
65  buf_set_u32(t, 0, field.num_bits, new_scan_chain);
66 
67  field.in_value = NULL;
68 
69  /* select INTEST instruction */
70  etb_set_instr(etb, 0x2);
71  jtag_add_dr_scan(etb->tap, 1, &field, TAP_IDLE);
72 
73  etb->cur_scan_chain = new_scan_chain;
74 
75  free(t);
76  }
77 
78  return ERROR_OK;
79 }
80 
81 static int etb_read_reg_w_check(struct reg *, uint8_t *, uint8_t *);
82 static int etb_set_reg_w_exec(struct reg *, uint8_t *);
83 
84 static int etb_read_reg(struct reg *reg)
85 {
87 }
88 
89 static int etb_get_reg(struct reg *reg)
90 {
91  int retval;
92 
93  retval = etb_read_reg(reg);
94  if (retval != ERROR_OK) {
95  LOG_ERROR("BUG: error scheduling ETB register read");
96  return retval;
97  }
98 
99  retval = jtag_execute_queue();
100  if (retval != ERROR_OK) {
101  LOG_ERROR("ETB register read failed");
102  return retval;
103  }
104 
105  return ERROR_OK;
106 }
107 
108 static const struct reg_arch_type etb_reg_type = {
109  .get = etb_get_reg,
110  .set = etb_set_reg_w_exec,
111 };
112 
114 {
115  struct reg_cache *reg_cache = malloc(sizeof(struct reg_cache));
116  struct reg *reg_list = NULL;
117  struct etb_reg *arch_info = NULL;
118  int num_regs = 9;
119  int i;
120 
121  /* the actual registers are kept in two arrays */
122  reg_list = calloc(num_regs, sizeof(struct reg));
123  arch_info = calloc(num_regs, sizeof(struct etb_reg));
124 
125  /* fill in values for the reg cache */
126  reg_cache->name = "etb registers";
127  reg_cache->next = NULL;
128  reg_cache->reg_list = reg_list;
129  reg_cache->num_regs = num_regs;
130 
131  /* set up registers */
132  for (i = 0; i < num_regs; i++) {
133  reg_list[i].name = etb_reg_list[i];
134  reg_list[i].size = 32;
135  reg_list[i].dirty = false;
136  reg_list[i].valid = false;
137  reg_list[i].value = calloc(1, 4);
138  reg_list[i].arch_info = &arch_info[i];
139  reg_list[i].type = &etb_reg_type;
140  reg_list[i].size = 32;
141  arch_info[i].addr = i;
142  arch_info[i].etb = etb;
143  }
144 
145  return reg_cache;
146 }
147 
149 {
150  uint8_t *in = (uint8_t *)arg;
151 
152  *((uint32_t *)arg) = buf_get_u32(in, 0, 32);
153 }
154 
155 static int etb_read_ram(struct etb *etb, uint32_t *data, int num_frames)
156 {
157  struct scan_field fields[3];
158  int i;
159 
160  etb_scann(etb, 0x0);
161  etb_set_instr(etb, 0xc);
162 
163  fields[0].num_bits = 32;
164  fields[0].out_value = NULL;
165  fields[0].in_value = NULL;
166 
167  fields[1].num_bits = 7;
168  uint8_t temp1 = 0;
169  fields[1].out_value = &temp1;
170  buf_set_u32(&temp1, 0, 7, 4);
171  fields[1].in_value = NULL;
172 
173  fields[2].num_bits = 1;
174  uint8_t temp2 = 0;
175  fields[2].out_value = &temp2;
176  buf_set_u32(&temp2, 0, 1, 0);
177  fields[2].in_value = NULL;
178 
179  jtag_add_dr_scan(etb->tap, 3, fields, TAP_IDLE);
180 
181  for (i = 0; i < num_frames; i++) {
182  /* ensure nR/W remains set to read */
183  buf_set_u32(&temp2, 0, 1, 0);
184 
185  /* address remains set to 0x4 (RAM data) until we read the last frame */
186  if (i < num_frames - 1)
187  buf_set_u32(&temp1, 0, 7, 4);
188  else
189  buf_set_u32(&temp1, 0, 7, 0);
190 
191  fields[0].in_value = (uint8_t *)(data + i);
192  jtag_add_dr_scan(etb->tap, 3, fields, TAP_IDLE);
193 
195  }
196 
198 
199  return ERROR_OK;
200 }
201 
202 static int etb_read_reg_w_check(struct reg *reg,
203  uint8_t *check_value, uint8_t *check_mask)
204 {
205  struct etb_reg *etb_reg = reg->arch_info;
206  uint8_t reg_addr = etb_reg->addr & 0x7f;
207  struct scan_field fields[3];
208 
209  LOG_DEBUG("%i", (int)(etb_reg->addr));
210 
211  etb_scann(etb_reg->etb, 0x0);
212  etb_set_instr(etb_reg->etb, 0xc);
213 
214  fields[0].num_bits = 32;
215  fields[0].out_value = reg->value;
216  fields[0].in_value = NULL;
217  fields[0].check_value = NULL;
218  fields[0].check_mask = NULL;
219 
220  fields[1].num_bits = 7;
221  uint8_t temp1 = 0;
222  fields[1].out_value = &temp1;
223  buf_set_u32(&temp1, 0, 7, reg_addr);
224  fields[1].in_value = NULL;
225  fields[1].check_value = NULL;
226  fields[1].check_mask = NULL;
227 
228  fields[2].num_bits = 1;
229  uint8_t temp2 = 0;
230  fields[2].out_value = &temp2;
231  buf_set_u32(&temp2, 0, 1, 0);
232  fields[2].in_value = NULL;
233  fields[2].check_value = NULL;
234  fields[2].check_mask = NULL;
235 
236  jtag_add_dr_scan(etb_reg->etb->tap, 3, fields, TAP_IDLE);
237 
238  /* read the identification register in the second run, to make sure we
239  * don't read the ETB data register twice, skipping every second entry
240  */
241  buf_set_u32(&temp1, 0, 7, 0x0);
242  fields[0].in_value = reg->value;
243  fields[0].check_value = check_value;
244  fields[0].check_mask = check_mask;
245 
247 
248  return ERROR_OK;
249 }
250 
251 static int etb_write_reg(struct reg *, uint32_t);
252 
253 static int etb_set_reg(struct reg *reg, uint32_t value)
254 {
255  int retval;
256 
257  retval = etb_write_reg(reg, value);
258  if (retval != ERROR_OK) {
259  LOG_ERROR("BUG: error scheduling ETB register write");
260  return retval;
261  }
262 
263  buf_set_u32(reg->value, 0, reg->size, value);
264  reg->valid = true;
265  reg->dirty = false;
266 
267  return ERROR_OK;
268 }
269 
270 static int etb_set_reg_w_exec(struct reg *reg, uint8_t *buf)
271 {
272  int retval;
273 
274  etb_set_reg(reg, buf_get_u32(buf, 0, reg->size));
275 
276  retval = jtag_execute_queue();
277  if (retval != ERROR_OK) {
278  LOG_ERROR("ETB: register write failed");
279  return retval;
280  }
281  return ERROR_OK;
282 }
283 
284 static int etb_write_reg(struct reg *reg, uint32_t value)
285 {
286  struct etb_reg *etb_reg = reg->arch_info;
287  uint8_t reg_addr = etb_reg->addr & 0x7f;
288  struct scan_field fields[3];
289 
290  LOG_DEBUG("%i: 0x%8.8" PRIx32 "", (int)(etb_reg->addr), value);
291 
292  etb_scann(etb_reg->etb, 0x0);
293  etb_set_instr(etb_reg->etb, 0xc);
294 
295  fields[0].num_bits = 32;
296  uint8_t temp0[4];
297  fields[0].out_value = temp0;
298  buf_set_u32(temp0, 0, 32, value);
299  fields[0].in_value = NULL;
300 
301  fields[1].num_bits = 7;
302  uint8_t temp1 = 0;
303  fields[1].out_value = &temp1;
304  buf_set_u32(&temp1, 0, 7, reg_addr);
305  fields[1].in_value = NULL;
306 
307  fields[2].num_bits = 1;
308  uint8_t temp2 = 0;
309  fields[2].out_value = &temp2;
310  buf_set_u32(&temp2, 0, 1, 1);
311  fields[2].in_value = NULL;
312 
313  jtag_add_dr_scan(etb_reg->etb->tap, 3, fields, TAP_IDLE);
314 
315  return ERROR_OK;
316 }
317 
318 COMMAND_HANDLER(handle_etb_config_command)
319 {
320  struct target *target;
321  struct jtag_tap *tap;
322  struct arm *arm;
323 
324  if (CMD_ARGC != 2)
326 
327  target = get_target(CMD_ARGV[0]);
328 
329  if (!target) {
330  LOG_ERROR("ETB: target '%s' not defined", CMD_ARGV[0]);
331  return ERROR_FAIL;
332  }
333 
335  if (!is_arm(arm)) {
336  command_print(CMD, "ETB: '%s' isn't an ARM", CMD_ARGV[0]);
337  return ERROR_FAIL;
338  }
339 
340  tap = jtag_tap_by_string(CMD_ARGV[1]);
341  if (!tap) {
342  command_print(CMD, "ETB: TAP %s does not exist", CMD_ARGV[1]);
343  return ERROR_FAIL;
344  }
345 
346  if (arm->etm) {
347  struct etb *etb = malloc(sizeof(struct etb));
348 
350 
351  etb->tap = tap;
352  etb->cur_scan_chain = 0xffffffff;
353  etb->reg_cache = NULL;
354  etb->ram_width = 0;
355  etb->ram_depth = 0;
356  } else {
357  LOG_ERROR("ETM: target has no ETM defined, ETB left unconfigured");
358  return ERROR_FAIL;
359  }
360 
361  return ERROR_OK;
362 }
363 
364 COMMAND_HANDLER(handle_etb_trigger_percent_command)
365 {
366  struct target *target;
367  struct arm *arm;
368  struct etm_context *etm;
369  struct etb *etb;
370 
373  if (!is_arm(arm)) {
374  command_print(CMD, "ETB: current target isn't an ARM");
375  return ERROR_FAIL;
376  }
377 
378  etm = arm->etm;
379  if (!etm) {
380  command_print(CMD, "ETB: target has no ETM configured");
381  return ERROR_FAIL;
382  }
383  if (etm->capture_driver != &etb_capture_driver) {
384  command_print(CMD, "ETB: target not using ETB");
385  return ERROR_FAIL;
386  }
388 
389  if (CMD_ARGC > 0) {
390  uint32_t new_value;
391 
392  COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], new_value);
393  if ((new_value < 2) || (new_value > 100))
395  "valid percentages are 2%% to 100%%");
396  else
397  etb->trigger_percent = (unsigned) new_value;
398  }
399 
400  command_print(CMD, "%d percent of tracebuffer fills after trigger",
402 
403  return ERROR_OK;
404 }
405 
406 static const struct command_registration etb_config_command_handlers[] = {
407  {
408  /* NOTE: with ADIv5, ETBs are accessed using DAP operations,
409  * possibly over SWD, not through separate TAPs...
410  */
411  .name = "config",
412  .handler = handle_etb_config_command,
413  .mode = COMMAND_CONFIG,
414  .help = "Associate ETB with target and JTAG TAP.",
415  .usage = "target tap",
416  },
417  {
418  .name = "trigger_percent",
419  .handler = handle_etb_trigger_percent_command,
420  .mode = COMMAND_EXEC,
421  .help = "Set percent of trace buffer to be filled "
422  "after the trigger occurs (2..100).",
423  .usage = "[percent]",
424  },
426 };
427 static const struct command_registration etb_command_handlers[] = {
428  {
429  .name = "etb",
430  .mode = COMMAND_ANY,
431  .help = "Embedded Trace Buffer command group",
433  .usage = "",
434  },
436 };
437 
438 static int etb_init(struct etm_context *etm_ctx)
439 {
440  struct etb *etb = etm_ctx->capture_driver_priv;
441 
442  etb->etm_ctx = etm_ctx;
443 
444  /* identify ETB RAM depth and width */
448 
451 
452  etb->trigger_percent = 50;
453 
454  return ERROR_OK;
455 }
456 
458 {
459  struct etb *etb = etm_ctx->capture_driver_priv;
460  struct reg *control = &etb->reg_cache->reg_list[ETB_CTRL];
461  struct reg *status = &etb->reg_cache->reg_list[ETB_STATUS];
462  trace_status_t retval = 0;
463  int etb_timeout = 100;
464 
465  etb->etm_ctx = etm_ctx;
466 
467  /* read control and status registers */
468  etb_read_reg(control);
471 
472  /* See if it's (still) active */
473  retval = buf_get_u32(control->value, 0, 1) ? TRACE_RUNNING : TRACE_IDLE;
474 
475  /* check Full bit to identify wraparound/overflow */
476  if (buf_get_u32(status->value, 0, 1) == 1)
477  retval |= TRACE_OVERFLOWED;
478 
479  /* check Triggered bit to identify trigger condition */
480  if (buf_get_u32(status->value, 1, 1) == 1)
481  retval |= TRACE_TRIGGERED;
482 
483  /* check AcqComp to see if trigger counter dropped to zero */
484  if (buf_get_u32(status->value, 2, 1) == 1) {
485  /* wait for DFEmpty */
486  while (etb_timeout-- && buf_get_u32(status->value, 3, 1) == 0)
488 
489  if (etb_timeout == 0)
490  LOG_ERROR("ETB: DFEmpty won't go high, status 0x%02x",
491  (unsigned) buf_get_u32(status->value, 0, 4));
492 
493  if (!(etm_ctx->capture_status & TRACE_TRIGGERED))
494  LOG_WARNING("ETB: trace complete without triggering?");
495 
496  retval |= TRACE_COMPLETED;
497  }
498 
499  /* NOTE: using a trigger is optional; and at least ETB11 has a mode
500  * where it can ignore the trigger counter.
501  */
502 
503  /* update recorded state */
504  etm_ctx->capture_status = retval;
505 
506  return retval;
507 }
508 
509 static int etb_read_trace(struct etm_context *etm_ctx)
510 {
511  struct etb *etb = etm_ctx->capture_driver_priv;
512  int first_frame = 0;
513  int num_frames = etb->ram_depth;
514  uint32_t *trace_data = NULL;
515  int i, j;
516 
520 
521  /* check if we overflowed, and adjust first frame of the trace accordingly
522  * if we didn't overflow, read only up to the frame that would be written next,
523  * i.e. don't read invalid entries
524  */
527  0,
528  32);
529  else
531  0,
532  32);
533 
535 
536  /* read data into temporary array for unpacking */
537  trace_data = malloc(sizeof(uint32_t) * num_frames);
538  etb_read_ram(etb, trace_data, num_frames);
539 
540  if (etm_ctx->trace_depth > 0)
541  free(etm_ctx->trace_data);
542 
544  etm_ctx->trace_depth = num_frames * 3;
546  etm_ctx->trace_depth = num_frames * 2;
547  else
548  etm_ctx->trace_depth = num_frames;
549 
550  etm_ctx->trace_data = malloc(sizeof(struct etmv1_trace_data) * etm_ctx->trace_depth);
551 
552  for (i = 0, j = 0; i < num_frames; i++) {
554  /* trace word j */
555  etm_ctx->trace_data[j].pipestat = trace_data[i] & 0x7;
556  etm_ctx->trace_data[j].packet = (trace_data[i] & 0x78) >> 3;
557  etm_ctx->trace_data[j].flags = 0;
558  if ((trace_data[i] & 0x80) >> 7)
560  if (etm_ctx->trace_data[j].pipestat == STAT_TR) {
562  0x7;
564  }
565 
566  /* trace word j + 1 */
567  etm_ctx->trace_data[j + 1].pipestat = (trace_data[i] & 0x100) >> 8;
568  etm_ctx->trace_data[j + 1].packet = (trace_data[i] & 0x7800) >> 11;
569  etm_ctx->trace_data[j + 1].flags = 0;
570  if ((trace_data[i] & 0x8000) >> 15)
572  if (etm_ctx->trace_data[j + 1].pipestat == STAT_TR) {
573  etm_ctx->trace_data[j +
574  1].pipestat = etm_ctx->trace_data[j + 1].packet & 0x7;
576  }
577 
578  /* trace word j + 2 */
579  etm_ctx->trace_data[j + 2].pipestat = (trace_data[i] & 0x10000) >> 16;
580  etm_ctx->trace_data[j + 2].packet = (trace_data[i] & 0x780000) >> 19;
581  etm_ctx->trace_data[j + 2].flags = 0;
582  if ((trace_data[i] & 0x800000) >> 23)
584  if (etm_ctx->trace_data[j + 2].pipestat == STAT_TR) {
585  etm_ctx->trace_data[j +
586  2].pipestat = etm_ctx->trace_data[j + 2].packet & 0x7;
588  }
589 
590  j += 3;
591  } else if ((etm_ctx->control & ETM_PORT_WIDTH_MASK) == ETM_PORT_8BIT) {
592  /* trace word j */
593  etm_ctx->trace_data[j].pipestat = trace_data[i] & 0x7;
594  etm_ctx->trace_data[j].packet = (trace_data[i] & 0x7f8) >> 3;
595  etm_ctx->trace_data[j].flags = 0;
596  if ((trace_data[i] & 0x800) >> 11)
598  if (etm_ctx->trace_data[j].pipestat == STAT_TR) {
600  0x7;
602  }
603 
604  /* trace word j + 1 */
605  etm_ctx->trace_data[j + 1].pipestat = (trace_data[i] & 0x7000) >> 12;
606  etm_ctx->trace_data[j + 1].packet = (trace_data[i] & 0x7f8000) >> 15;
607  etm_ctx->trace_data[j + 1].flags = 0;
608  if ((trace_data[i] & 0x800000) >> 23)
610  if (etm_ctx->trace_data[j + 1].pipestat == STAT_TR) {
611  etm_ctx->trace_data[j +
612  1].pipestat = etm_ctx->trace_data[j + 1].packet & 0x7;
614  }
615 
616  j += 2;
617  } else {
618  /* trace word j */
619  etm_ctx->trace_data[j].pipestat = trace_data[i] & 0x7;
620  etm_ctx->trace_data[j].packet = (trace_data[i] & 0x7fff8) >> 3;
621  etm_ctx->trace_data[j].flags = 0;
622  if ((trace_data[i] & 0x80000) >> 19)
624  if (etm_ctx->trace_data[j].pipestat == STAT_TR) {
626  0x7;
628  }
629 
630  j += 1;
631  }
632  }
633 
634  free(trace_data);
635 
636  return ERROR_OK;
637 }
638 
640 {
641  struct etb *etb = etm_ctx->capture_driver_priv;
642  uint32_t etb_ctrl_value = 0x1;
643  uint32_t trigger_count;
644 
647  LOG_ERROR("ETB can't run in demultiplexed mode with a 4 or 16 bit port");
649  }
650  etb_ctrl_value |= 0x2;
651  }
652 
654  LOG_ERROR("ETB: can't run in multiplexed mode");
656  }
657 
658  trigger_count = (etb->ram_depth * etb->trigger_percent) / 100;
659 
662  etb_write_reg(&etb->reg_cache->reg_list[ETB_CTRL], etb_ctrl_value);
664 
665  /* we're starting a new trace, initialize capture status */
667 
668  return ERROR_OK;
669 }
670 
672 {
673  struct etb *etb = etm_ctx->capture_driver_priv;
674  struct reg *etb_ctrl_reg = &etb->reg_cache->reg_list[ETB_CTRL];
675 
676  etb_write_reg(etb_ctrl_reg, 0x0);
678 
679  /* trace stopped, just clear running flag, but preserve others */
680  etm_ctx->capture_status &= ~TRACE_RUNNING;
681 
682  return ERROR_OK;
683 }
684 
686  .name = "etb",
687  .commands = etb_command_handlers,
688  .init = etb_init,
689  .status = etb_status,
690  .start_capture = etb_start_capture,
691  .stop_capture = etb_stop_capture,
692  .read_trace = etb_read_trace,
693 };
Holds the interface to ARM cores.
static bool is_arm(struct arm *arm)
Definition: arm.h:249
static struct arm * target_to_arm(struct target *target)
Convert target handle to generic ARM target state handle.
Definition: arm.h:243
static uint32_t buf_get_u32(const uint8_t *_buffer, unsigned first, unsigned num)
Retrieves num bits from _buffer, starting at the first bit, returning the bits in a 32-bit word.
Definition: binarybuffer.h:98
static void buf_set_u32(uint8_t *_buffer, unsigned first, unsigned num, uint32_t value)
Sets num bits in _buffer, starting at the first bit, using the bits in value.
Definition: binarybuffer.h:30
void command_print(struct command_invocation *cmd, const char *format,...)
Definition: command.c:473
#define CMD
Use this macro to access the command being handled, rather than accessing the variable directly.
Definition: command.h:140
#define CMD_ARGV
Use this macro to access the arguments for the command being handled, rather than accessing the varia...
Definition: command.h:155
#define ERROR_COMMAND_SYNTAX_ERROR
Definition: command.h:385
#define CMD_ARGC
Use this macro to access the number of arguments for the command being handled, rather than accessing...
Definition: command.h:150
#define COMMAND_PARSE_NUMBER(type, in, out)
parses the string in into out as a type, or prints a command error and passes the error code to the c...
Definition: command.h:425
#define CMD_CTX
Use this macro to access the context of the command being handled, rather than accessing the variable...
Definition: command.h:145
#define COMMAND_REGISTRATION_DONE
Use this as the last entry in an array of command_registration records.
Definition: command.h:247
@ COMMAND_CONFIG
Definition: command.h:41
@ COMMAND_ANY
Definition: command.h:42
@ COMMAND_EXEC
Definition: command.h:40
static int etb_set_reg_w_exec(struct reg *, uint8_t *)
Definition: etb.c:270
struct reg_cache * etb_build_reg_cache(struct etb *etb)
Definition: etb.c:113
static int etb_stop_capture(struct etm_context *etm_ctx)
Definition: etb.c:671
static int etb_read_ram(struct etb *etb, uint32_t *data, int num_frames)
Definition: etb.c:155
static int etb_write_reg(struct reg *, uint32_t)
Definition: etb.c:284
static int etb_read_reg(struct reg *reg)
Definition: etb.c:84
static int etb_get_reg(struct reg *reg)
Definition: etb.c:89
static const struct reg_arch_type etb_reg_type
Definition: etb.c:108
static const struct command_registration etb_config_command_handlers[]
Definition: etb.c:406
static int etb_scann(struct etb *etb, uint32_t new_scan_chain)
Definition: etb.c:57
static const struct command_registration etb_command_handlers[]
Definition: etb.c:427
struct etm_capture_driver etb_capture_driver
Definition: etb.c:685
static int etb_read_trace(struct etm_context *etm_ctx)
Definition: etb.c:509
COMMAND_HANDLER(handle_etb_config_command)
Definition: etb.c:318
static int etb_init(struct etm_context *etm_ctx)
Definition: etb.c:438
static int etb_set_instr(struct etb *etb, uint32_t new_instr)
Definition: etb.c:31
static trace_status_t etb_status(struct etm_context *etm_ctx)
Definition: etb.c:457
static void etb_getbuf(jtag_callback_data_t arg)
Definition: etb.c:148
static int etb_start_capture(struct etm_context *etm_ctx)
Definition: etb.c:639
static int etb_read_reg_w_check(struct reg *, uint8_t *, uint8_t *)
Definition: etb.c:202
static const char *const etb_reg_list[]
Definition: etb.c:17
static int etb_set_reg(struct reg *reg, uint32_t value)
Definition: etb.c:253
@ ETB_TRIGGER_COUNTER
Definition: etb.h:20
@ ETB_RAM_READ_POINTER
Definition: etb.h:18
@ ETB_STATUS
Definition: etb.h:16
@ ETB_RAM_WIDTH
Definition: etb.h:15
@ ETB_RAM_WRITE_POINTER
Definition: etb.h:19
@ ETB_CTRL
Definition: etb.h:21
@ ETB_RAM_DEPTH
Definition: etb.h:14
@ ETMV1_TRIGGER_CYCLE
Definition: etm.h:137
@ ETMV1_TRACESYNC_CYCLE
Definition: etm.h:136
#define ERROR_ETM_PORTMODE_NOT_SUPPORTED
Definition: etm.h:209
@ ETM_PORT_4BIT
Definition: etm.h:83
@ ETM_PORT_8BIT
Definition: etm.h:84
@ ETM_PORT_MODE_MASK
Definition: etm.h:117
@ ETM_PORT_WIDTH_MASK
Definition: etm.h:92
@ ETM_PORT_DEMUXED
Definition: etm.h:116
@ ETM_PORT_MUXED
Definition: etm.h:115
@ STAT_TR
Definition: etm.h:185
struct jtag_tap * jtag_tap_by_string(const char *s)
Definition: jtag/core.c:237
int jtag_execute_queue(void)
For software FIFO implementations, the queued commands can be executed during this call or earlier.
Definition: jtag/core.c:1037
void jtag_add_dr_scan_check(struct jtag_tap *active, int in_num_fields, struct scan_field *in_fields, tap_state_t state)
A version of jtag_add_dr_scan() that uses the check_value/mask fields.
Definition: jtag/core.c:439
void jtag_add_ir_scan(struct jtag_tap *active, struct scan_field *in_fields, tap_state_t state)
Generate an IR SCAN with a list of scan fields with one entry for each enabled TAP.
Definition: jtag/core.c:374
void jtag_add_dr_scan(struct jtag_tap *active, int in_num_fields, const struct scan_field *in_fields, tap_state_t state)
Generate a DR SCAN using the fields passed to the function.
Definition: jtag/core.c:451
void jtag_add_callback(jtag_callback1_t f, jtag_callback_data_t data0)
A simpler version of jtag_add_callback4().
@ TAP_IDLE
Definition: jtag.h:52
intptr_t jtag_callback_data_t
Defines the type of data passed to the jtag_callback_t interface.
Definition: jtag.h:333
#define LOG_WARNING(expr ...)
Definition: log.h:120
#define ERROR_FAIL
Definition: log.h:161
#define LOG_ERROR(expr ...)
Definition: log.h:123
#define LOG_DEBUG(expr ...)
Definition: log.h:109
#define ERROR_OK
Definition: log.h:155
struct target * target
Definition: rtt/rtt.c:26
Represents a generic ARM core, with standard application registers.
Definition: arm.h:167
struct etm_context * etm
Handle for the Embedded Trace Module, if one is present.
Definition: arm.h:208
const char * name
Definition: command.h:229
const char * usage
a string listing the options and arguments, required or optional
Definition: command.h:235
Definition: etb.h:38
uint32_t addr
Definition: etb.h:39
struct etb * etb
Definition: etb.h:40
Definition: etb.h:24
struct reg_cache * reg_cache
Definition: etb.h:28
unsigned trigger_percent
how much trace buffer to fill after trigger
Definition: etb.h:35
struct etm_context * etm_ctx
Definition: etb.h:25
struct jtag_tap * tap
Definition: etb.h:26
uint32_t ram_depth
Definition: etb.h:31
uint32_t cur_scan_chain
Definition: etb.h:27
uint32_t ram_width
Definition: etb.h:32
const char * name
Definition: etm.h:126
struct etm_capture_driver * capture_driver
Definition: etm.h:154
struct etmv1_trace_data * trace_data
Definition: etm.h:157
uint32_t trace_depth
Definition: etm.h:158
uint32_t control
Definition: etm.h:159
trace_status_t capture_status
Definition: etm.h:156
void * capture_driver_priv
Definition: etm.h:155
uint8_t pipestat
Definition: etm.h:141
uint16_t packet
Definition: etm.h:142
Definition: jtag.h:100
uint8_t * cur_instr
current instruction
Definition: jtag.h:131
int ir_length
size of instruction register
Definition: jtag.h:109
int(* get)(struct reg *reg)
Definition: register.h:152
const char * name
Definition: register.h:145
unsigned num_regs
Definition: register.h:148
struct reg * reg_list
Definition: register.h:147
struct reg_cache * next
Definition: register.h:146
Definition: register.h:111
bool valid
Definition: register.h:126
uint32_t size
Definition: register.h:132
uint8_t * value
Definition: register.h:122
void * arch_info
Definition: register.h:140
bool dirty
Definition: register.h:124
const struct reg_arch_type * type
Definition: register.h:141
const char * name
Definition: register.h:113
This structure defines a single scan field in the scan.
Definition: jtag.h:86
int num_bits
The number of bits this field specifies.
Definition: jtag.h:88
uint8_t * in_value
A pointer to a 32-bit memory location for data scanned out.
Definition: jtag.h:92
uint8_t * check_value
The value used to check the data scanned out.
Definition: jtag.h:95
const uint8_t * out_value
A pointer to value to be scanned into the device.
Definition: jtag.h:90
uint8_t * check_mask
The mask to go with check_value.
Definition: jtag.h:97
Definition: target.h:120
struct target * get_target(const char *id)
Definition: target.c:492
struct target * get_current_target(struct command_context *cmd_ctx)
Definition: target.c:536
enum trace_status trace_status_t
@ TRACE_OVERFLOWED
Definition: trace.h:41
@ TRACE_RUNNING
Definition: trace.h:38
@ TRACE_COMPLETED
Definition: trace.h:40
@ TRACE_TRIGGERED
Definition: trace.h:39
@ TRACE_IDLE
Definition: trace.h:37
#define DIV_ROUND_UP(m, n)
Rounds m up to the nearest multiple of n using division.
Definition: types.h:79
#define NULL
Definition: usb.h:16
uint8_t status[4]
Definition: vdebug.c:17