Go to the source code of this file.
◆ ESP32_S3_DR_REG_SYSTEM_BASE
#define ESP32_S3_DR_REG_SYSTEM_BASE 0x600c0000 |
◆ ESP32_S3_DRAM_HIGH
#define ESP32_S3_DRAM_HIGH 0x3FD00000 |
◆ ESP32_S3_DRAM_LOW
#define ESP32_S3_DRAM_LOW 0x3FC88000 |
◆ ESP32_S3_EXTRAM_DATA_HIGH
#define ESP32_S3_EXTRAM_DATA_HIGH 0x3E000000 |
◆ ESP32_S3_EXTRAM_DATA_LOW
#define ESP32_S3_EXTRAM_DATA_LOW 0x3D000000 |
◆ ESP32_S3_IRAM_HIGH
#define ESP32_S3_IRAM_HIGH 0x403E0000 |
◆ ESP32_S3_IRAM_LOW
#define ESP32_S3_IRAM_LOW 0x40370000 |
◆ ESP32_S3_IROM_MASK_HIGH
#define ESP32_S3_IROM_MASK_HIGH 0x40060000 |
◆ ESP32_S3_IROM_MASK_LOW
#define ESP32_S3_IROM_MASK_LOW 0x40000000 |
◆ ESP32_S3_RTC_CNTL_SW_CPU_STALL_DEF
#define ESP32_S3_RTC_CNTL_SW_CPU_STALL_DEF 0x0 |
◆ ESP32_S3_RTC_CNTL_SW_CPU_STALL_REG
◆ ESP32_S3_RTC_DATA_HIGH
#define ESP32_S3_RTC_DATA_HIGH 0x50002000 |
◆ ESP32_S3_RTC_DATA_LOW
#define ESP32_S3_RTC_DATA_LOW 0x50000000 |
◆ ESP32_S3_RTC_DRAM_HIGH
#define ESP32_S3_RTC_DRAM_HIGH 0x60100000 |
◆ ESP32_S3_RTC_DRAM_LOW
#define ESP32_S3_RTC_DRAM_LOW 0x600FE000 |
◆ ESP32_S3_RTC_IRAM_HIGH
#define ESP32_S3_RTC_IRAM_HIGH 0x60100000 |
◆ ESP32_S3_RTC_IRAM_LOW
#define ESP32_S3_RTC_IRAM_LOW 0x600FE000 |
◆ ESP32_S3_RTC_SLOW_MEM_BASE
◆ ESP32_S3_RTCCNTL_BASE
#define ESP32_S3_RTCCNTL_BASE 0x60008000 |
◆ ESP32_S3_RTCWDT_CFG
◆ ESP32_S3_RTCWDT_CFG_OFF
#define ESP32_S3_RTCWDT_CFG_OFF 0x98 |
◆ ESP32_S3_RTCWDT_PROTECT
◆ ESP32_S3_RTCWDT_PROTECT_OFF
#define ESP32_S3_RTCWDT_PROTECT_OFF 0xB0 |
◆ ESP32_S3_SWD_AUTO_FEED_EN_M
#define ESP32_S3_SWD_AUTO_FEED_EN_M BIT(31) |
◆ ESP32_S3_SWD_CONF_OFF
#define ESP32_S3_SWD_CONF_OFF 0xB0 |
◆ ESP32_S3_SWD_CONF_REG
◆ ESP32_S3_SWD_WKEY_VALUE
#define ESP32_S3_SWD_WKEY_VALUE 0x8F1D312AU |
◆ ESP32_S3_SWD_WPROTECT_OFF
#define ESP32_S3_SWD_WPROTECT_OFF 0xB4 |
◆ ESP32_S3_SWD_WPROTECT_REG
◆ ESP32_S3_SYS_RAM_HIGH
◆ ESP32_S3_SYS_RAM_LOW
#define ESP32_S3_SYS_RAM_LOW 0x60000000UL |
◆ ESP32_S3_SYSTEM_CONTROL_CORE_1_CLKGATE_EN
#define ESP32_S3_SYSTEM_CONTROL_CORE_1_CLKGATE_EN BIT(1) |
◆ ESP32_S3_SYSTEM_CORE_1_CONTROL_0_REG
◆ ESP32_S3_TIMG0_BASE
#define ESP32_S3_TIMG0_BASE 0x6001F000 |
◆ ESP32_S3_TIMG0WDT_CFG0
◆ ESP32_S3_TIMG0WDT_PROTECT
◆ ESP32_S3_TIMG1_BASE
#define ESP32_S3_TIMG1_BASE 0x60020000 |
◆ ESP32_S3_TIMG1WDT_CFG0
◆ ESP32_S3_TIMG1WDT_PROTECT
◆ ESP32_S3_TIMGWDT_CFG0_OFF
#define ESP32_S3_TIMGWDT_CFG0_OFF 0x48 |
◆ ESP32_S3_TIMGWDT_PROTECT_OFF
#define ESP32_S3_TIMGWDT_PROTECT_OFF 0x64 |
◆ ESP32_S3_TRACEMEM_BLOCK_SZ
#define ESP32_S3_TRACEMEM_BLOCK_SZ 0x4000 |
◆ ESP32_S3_WDT_WKEY_VALUE
#define ESP32_S3_WDT_WKEY_VALUE 0x50D83AA1 |
◆ esp32s3_arch_state()
static int esp32s3_arch_state |
( |
struct target * |
target | ) |
|
|
static |
◆ esp32s3_disable_wdts()
static int esp32s3_disable_wdts |
( |
struct target * |
target | ) |
|
|
static |
Definition at line 228 of file esp32s3.c.
References ERROR_OK, ESP32_S3_RTCWDT_CFG, ESP32_S3_RTCWDT_PROTECT, ESP32_S3_SWD_AUTO_FEED_EN_M, ESP32_S3_SWD_CONF_REG, ESP32_S3_SWD_WKEY_VALUE, ESP32_S3_SWD_WPROTECT_REG, ESP32_S3_TIMG0WDT_CFG0, ESP32_S3_TIMG0WDT_PROTECT, ESP32_S3_TIMG1WDT_CFG0, ESP32_S3_TIMG1WDT_PROTECT, ESP32_S3_WDT_WKEY_VALUE, LOG_ERROR, target_read_u32(), and target_write_u32().
Referenced by esp32s3_on_halt().
◆ esp32s3_on_halt()
static int esp32s3_on_halt |
( |
struct target * |
target | ) |
|
|
static |
◆ esp32s3_soc_reset()
static int esp32s3_soc_reset |
( |
struct target * |
target | ) |
|
|
static |
Definition at line 103 of file esp32s3.c.
References alive_sleep(), xtensa::dbg_mod, ERROR_OK, ERROR_TARGET_TIMEOUT, ESP32_S3_RTC_CNTL_SW_CPU_STALL_DEF, ESP32_S3_RTC_CNTL_SW_CPU_STALL_REG, ESP32_S3_RTC_SLOW_MEM_BASE, esp32s3_reset_stub_code, foreach_smp_target, LOG_DEBUG, LOG_ERROR, LOG_TARGET_DEBUG, LOG_TARGET_ERROR, target::reset_halt, target::smp, target::smp_targets, target::state, xtensa::suppress_dsr_errors, target_list::target, TARGET_HALTED, target_read_buffer(), TARGET_RESET, TARGET_RUNNING, target_to_xtensa(), target_wait_state(), target_write_buffer(), target_write_u32(), timeval_ms(), xtensa_assert_reset(), xtensa_deassert_reset(), xtensa_dm_core_is_stalled(), xtensa_halt(), xtensa_poll(), and xtensa_resume().
◆ esp32s3_target_create()
static int esp32s3_target_create |
( |
struct target * |
target, |
|
|
Jim_Interp * |
interp |
|
) |
| |
|
static |
◆ esp32s3_target_init()
◆ esp32s3_virt2phys()
◆ esp32s3_chip_ops
Initial value:= {
}
static int esp32s3_soc_reset(struct target *target)
static int esp32s3_on_halt(struct target *target)
Definition at line 304 of file esp32s3.c.
◆ esp32s3_command_handlers
Initial value:= {
{
.usage = "",
},
{
.usage = "",
},
{
.help = "ARM Command Group",
.usage = "",
},
}
#define COMMAND_REGISTRATION_DONE
Use this as the last entry in an array of command_registration records.
const struct command_registration esp_xtensa_smp_command_handlers[]
const struct command_registration semihosting_common_handlers[]
const struct command_registration smp_command_handlers[]
Definition at line 329 of file esp32s3.c.
◆ esp32s3_dbg_ops
Initial value:= {
}
int xtensa_dm_queue_reg_read(struct xtensa_debug_module *dm, enum xtensa_dm_reg reg, uint8_t *value)
int xtensa_dm_queue_reg_write(struct xtensa_debug_module *dm, enum xtensa_dm_reg reg, uint32_t value)
int xtensa_dm_queue_enable(struct xtensa_debug_module *dm)
Definition at line 304 of file esp32s3.c.
◆ esp32s3_pwr_ops
Initial value:= {
}
int xtensa_dm_queue_pwr_reg_write(struct xtensa_debug_module *dm, enum xtensa_dm_pwr_reg reg, uint32_t data)
int xtensa_dm_queue_pwr_reg_read(struct xtensa_debug_module *dm, enum xtensa_dm_pwr_reg reg, uint8_t *data, uint32_t clear)
Definition at line 304 of file esp32s3.c.
◆ esp32s3_reset_stub_code
const uint8_t esp32s3_reset_stub_code[] |
|
static |
◆ esp32s3_semihost_ops
Initial value:= {
}
static int esp32s3_disable_wdts(struct target *target)
Definition at line 304 of file esp32s3.c.
◆ esp32s3_target
Holds methods for Xtensa targets.
Definition at line 329 of file esp32s3.c.