Include dependency graph for riscv_reg.h:

This graph shows which files directly or indirectly include this file:

Functions
bool	riscv_reg_cache_any_dirty (const struct target *target, int log_level)
	Check whether there are any dirty registers in the OpenOCD's register cache. More...

void	riscv_reg_cache_invalidate_all (struct target *target)
	Invalidate all registers - forget their cached register values. More...

int	riscv_reg_flush_all (struct target *target)
	Write all dirty registers to the target. More...

void	riscv_reg_free_all (struct target *target)
	Free register cache and associated structures. More...

const char *	riscv_reg_gdb_regno_name (const struct target *target, enum gdb_regno regno)
	This file describes the register cache interface available to the RISC-V target. More...

int	riscv_reg_get (struct target target, riscv_reg_t value, enum gdb_regno r)
	Get register, from the cache if it's in there. More...

int	riscv_reg_set (struct target *target, enum gdb_regno i, riscv_reg_t v)
	Set the register value. More...

int	riscv_reg_write (struct target *target, enum gdb_regno i, riscv_reg_t v)
	Set the register value and immediately write it to the target (write-through mode). More...

Function Documentation

◆ riscv_reg_cache_any_dirty()

bool riscv_reg_cache_any_dirty	(	const struct target *	target,
		int	log_level
	)

Check whether there are any dirty registers in the OpenOCD's register cache.

In addition, all dirty registers will be reported to the log using the supplied "log_level".

Definition at line 880 of file riscv_reg.c.

References reg::dirty, log_printf_lf(), reg::name, reg_cache::num_regs, number, target::reg_cache, riscv_reg_impl_cache_entry(), riscv_reg_impl_is_initialized(), and target_name().

Referenced by handle_became_unavailable(), resume_finish(), riscv_assert_reset(), riscv_halt_go_all_harts(), and riscv_openocd_step_impl().

◆ riscv_reg_cache_invalidate_all()

void riscv_reg_cache_invalidate_all ( struct target * target )

Invalidate all registers - forget their cached register values.

WARNING: If a register was dirty, its walue will be silently lost!

Definition at line 899 of file riscv_reg.c.

References LOG_TARGET_DEBUG, target::reg_cache, and register_cache_invalidate().

Referenced by COMMAND_HANDLER(), execute_resume(), handle_became_unavailable(), resume_finish(), riscv013_step_or_resume_current_hart(), riscv_assert_reset(), riscv_halt_go_all_harts(), and riscv_openocd_step_impl().

◆ riscv_reg_flush_all()

int riscv_reg_flush_all ( struct target * target )

Write all dirty registers to the target.

Definition at line 776 of file riscv_reg.c.

References buf_get_u64(), reg::dirty, ERROR_FAIL, ERROR_OK, LOG_TARGET_DEBUG, reg::name, reg_cache::num_regs, number, target::reg_cache, riscv_reg_impl_cache_entry(), riscv_reg_write(), reg::size, reg::valid, and reg::value.

Referenced by COMMAND_HANDLER(), execute_resume(), riscv013_on_step_or_resume(), riscv013_step_or_resume_current_hart(), riscv_deinit_target(), and riscv_poll_hart().

◆ riscv_reg_free_all()

void riscv_reg_free_all ( struct target * target )

Free register cache and associated structures.

Definition at line 759 of file riscv_reg.c.

References reg::arch_info, free_reg_names(), GDB_REGNO_COUNT, NULL, reg_cache::num_regs, target::reg_cache, reg_cache::reg_list, and reg::value.

Referenced by riscv_deinit_target(), and riscv_reg_impl_init_cache().

◆ riscv_reg_gdb_regno_name()

const char* riscv_reg_gdb_regno_name	(	const struct target *	target,
		enum gdb_regno	regno
	)

This file describes the register cache interface available to the RISC-V target.

Functions declared here should be safe to use once register cache is completely initialized and may be used with caution during register cache initialization. Return the name of the register by it's number in register cache.

Definition at line 171 of file riscv_reg.c.

References default_reg_names, GDB_REGNO_COUNT, GDB_REGNO_CSR0, GDB_REGNO_CSR4095, GDB_REGNO_V0, GDB_REGNO_XPR31, GDB_REGNO_ZERO, info, init_custom_csr_names(), init_reg_name_with_prefix(), NULL, and RISCV_INFO.

Referenced by prep_for_register_access(), read_remote_csr(), register_read(), register_read_direct(), register_read_progbuf(), register_write(), register_write_direct(), register_write_progbuf(), riscv013_access_register_command(), riscv013_get_register(), riscv013_get_register_buf(), riscv013_reg_save(), riscv013_set_register(), riscv_reg_impl_init_cache_entry(), and riscv_run_algorithm().

◆ riscv_reg_get()

int riscv_reg_get	(	struct target *	target,
		riscv_reg_t *	value,
		enum gdb_regno	regid
	)

Get register, from the cache if it's in there.

If possible, the value in cache will be updated. TODO: Currently reg->get/set is implemented in terms of riscv_get/set_register. However, the intention behind riscv_get/set_register is to work with the cache, therefore it accesses and modifyes register cache directly. The idea is to implement riscv_get/set_register in terms of riscv_reg_impl_cache_entry and reg->get/set.

Definition at line 952 of file riscv_reg.c.

References buf_get_u64(), buf_set_u64(), reg::dirty, DTM_DTMCS_VERSION_0_11, ERROR_FAIL, ERROR_OK, reg::exist, GDB_REGNO_DPC, GDB_REGNO_PC, keep_alive(), LOG_TARGET_DEBUG, reg::name, riscv011_get_register(), riscv013_get_register(), RISCV_INFO, riscv_reg_impl_cache_entry(), riscv_reg_impl_gdb_regno_cacheable(), riscv_reg_impl_is_initialized(), reg::size, target::state, TARGET_HALTED, reg::valid, and reg::value.

Referenced by add_trigger(), check_if_trigger_exists(), examine_misa(), examine_mtopi(), examine_vlenb(), get_trigger_types(), maybe_add_trigger_t1(), modify_privilege_for_virt2phys_mode(), prep_for_register_access(), prep_for_vector_access(), remove_trigger(), riscv013_get_register(), riscv013_reg_get(), riscv013_reg_save(), riscv_effective_privilege_mode(), riscv_enumerate_triggers(), riscv_hit_watchpoint(), riscv_interrupts_disable(), riscv_interrupts_restore(), riscv_mmu(), riscv_openocd_poll(), riscv_openocd_step_impl(), riscv_run_algorithm(), riscv_set_or_write_register(), riscv_trigger_detect_hit_bits(), riscv_virt2phys(), riscv_virt2phys_v(), set_dcsr_ebreak(), set_debug_reason(), set_trigger(), and try_set_vsew().

◆ riscv_reg_set()

int riscv_reg_set	(	struct target *	target,
		enum gdb_regno	regid,
		riscv_reg_t	value
	)

Set the register value.

For cacheable registers, only the cache is updated (write-back mode).

Set the register value.

The new value may be cached, and may not be written until the hart is resumed. TODO: Currently reg->get/set is implemented in terms of riscv_get/set_register. However, the intention behind riscv_get/set_register is to work with the cache, therefore it accesses and modifyes register cache directly. The idea is to implement riscv_get/set_register in terms of riscv_reg_impl_cache_entry and reg->get/set.

Definition at line 918 of file riscv_reg.c.

References riscv_set_or_write_register(), and reg::value.

Referenced by add_trigger(), check_if_trigger_exists(), disable_trigger_if_dmode(), modify_privilege_for_virt2phys_mode(), remove_trigger(), restore_privilege_from_virt2phys_mode(), resume_prep(), riscv013_reg_set(), riscv_enumerate_triggers(), riscv_interrupts_disable(), riscv_interrupts_restore(), riscv_openocd_step_impl(), riscv_semihosting_post_result(), riscv_trigger_detect_hit_bits(), set_dcsr_ebreak(), and set_trigger().

◆ riscv_reg_write()

int riscv_reg_write	(	struct target *	target,
		enum gdb_regno	regid,
		riscv_reg_t	value
	)

Set the register value and immediately write it to the target (write-through mode).

The new value may be cached, but it will be written to hart immediately. TODO: Currently reg->get/set is implemented in terms of riscv_get/set_register. However, the intention behind riscv_get/set_register is to work with the cache, therefore it accesses and modifyes register cache directly. The idea is to implement riscv_get/set_register in terms of riscv_reg_impl_cache_entry and reg->get/set.

Definition at line 935 of file riscv_reg.c.

References riscv_set_or_write_register(), and reg::value.

Referenced by cleanup_after_register_access(), cleanup_after_vector_access(), prep_for_register_access(), prep_for_vector_access(), riscv_reg_flush_all(), and try_set_vsew().