OpenOCD
riscv_reg.h
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1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 
3 #ifndef OPENOCD_TARGET_RISCV_RISCV_REG_H
4 #define OPENOCD_TARGET_RISCV_RISCV_REG_H
5 
6 #include "target/target.h"
7 #include "target/register.h"
8 
17 const char *riscv_reg_gdb_regno_name(const struct target *target, enum gdb_regno regno);
18 
20 void riscv_reg_free_all(struct target *target);
21 
23 int riscv_reg_flush_all(struct target *target);
29 bool riscv_reg_cache_any_dirty(const struct target *target, int log_level);
39 int riscv_reg_set(struct target *target, enum gdb_regno i, riscv_reg_t v);
44 int riscv_reg_write(struct target *target, enum gdb_regno i, riscv_reg_t v);
46 int riscv_reg_get(struct target *target, riscv_reg_t *value,
47  enum gdb_regno r);
48 
49 #endif /* OPENOCD_TARGET_RISCV_RISCV_REG_H */
gdb_regno
Definition: gdb_regs.h:10
uint64_t riscv_reg_t
Definition: riscv.h:46
int riscv_reg_set(struct target *target, enum gdb_regno i, riscv_reg_t v)
Set the register value.
Definition: riscv_reg.c:918
void riscv_reg_cache_invalidate_all(struct target *target)
Invalidate all registers - forget their cached register values.
Definition: riscv_reg.c:899
const char * riscv_reg_gdb_regno_name(const struct target *target, enum gdb_regno regno)
This file describes the register cache interface available to the RISC-V target.
Definition: riscv_reg.c:171
int riscv_reg_get(struct target *target, riscv_reg_t *value, enum gdb_regno r)
Get register, from the cache if it's in there.
Definition: riscv_reg.c:952
int riscv_reg_write(struct target *target, enum gdb_regno i, riscv_reg_t v)
Set the register value and immediately write it to the target (write-through mode).
Definition: riscv_reg.c:935
int riscv_reg_flush_all(struct target *target)
Write all dirty registers to the target.
Definition: riscv_reg.c:776
void riscv_reg_free_all(struct target *target)
Free register cache and associated structures.
Definition: riscv_reg.c:759
bool riscv_reg_cache_any_dirty(const struct target *target, int log_level)
Check whether there are any dirty registers in the OpenOCD's register cache.
Definition: riscv_reg.c:880
Definition: target.h:119