riscv.h File Reference

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Data Structures
struct	range_list_t
struct	reg_name_table
struct	riscv_bscan_tunneled_scan_context_t
struct	riscv_info
struct	riscv_mem_access_args
struct	riscv_private_config
struct	riscv_reg_info_t
struct	riscv_sample_buf
struct	riscv_sample_config_t
struct	virt2phys_info_t

Macros
#define	DEFAULT_COMMAND_TIMEOUT_SEC   5
#define	DTM_DTMCS_VERSION_UNKNOWN   ((unsigned int)-1)
#define	PG_MAX_LEVEL   5
#define	RISCV013_DTMCS_ABITS_MAX   32
#define	RISCV013_DTMCS_ABITS_MIN   7
#define	RISCV_BATCH_ALLOC_SIZE   128
#define	RISCV_COMMON_MAGIC   0x52495356U
#define	RISCV_HGATP_MODE(xlen)   ((xlen) == 32 ? HGATP32_MODE : HGATP64_MODE)
#define	RISCV_HGATP_PPN(xlen)   ((xlen) == 32 ? HGATP32_PPN : HGATP64_PPN)
#define	RISCV_INFO(R)   struct riscv_info *R = riscv_info(target);
#define	RISCV_MAX_DMS   100
#define	RISCV_MAX_HARTS   ((int)BIT(20))
#define	RISCV_MAX_HWBPS   16
#define	RISCV_MAX_TRIGGERS   32
#define	RISCV_PGBASE(addr)   ((addr) & ~(RISCV_PGSIZE - 1))
#define	RISCV_PGOFFSET(addr)   ((addr) & (RISCV_PGSIZE - 1))
#define	RISCV_PGSHIFT   12
#define	RISCV_PGSIZE   BIT(RISCV_PGSHIFT)
#define	RISCV_SAMPLE_BUF_TIMESTAMP_AFTER   0x81
#define	RISCV_SAMPLE_BUF_TIMESTAMP_BEFORE   0x80
#define	RISCV_SATP_MODE(xlen)   ((xlen) == 32 ? SATP32_MODE : SATP64_MODE)
#define	RISCV_SATP_PPN(xlen)   ((xlen) == 32 ? SATP32_PPN : SATP64_PPN)
#define	RISCV_TINFO_VERSION_UNKNOWN   (-1)

Typedefs
typedef uint64_t	riscv_addr_t
typedef uint32_t	riscv_insn_t
typedef uint64_t	riscv_reg_t

Enumerations
enum	bscan_tunnel_type_t { BSCAN_TUNNEL_NESTED_TAP , BSCAN_TUNNEL_DATA_REGISTER }
enum	riscv_halt_reason {   RISCV_HALT_INTERRUPT , RISCV_HALT_EBREAK , RISCV_HALT_SINGLESTEP , RISCV_HALT_TRIGGER ,   RISCV_HALT_UNKNOWN , RISCV_HALT_GROUP , RISCV_HALT_ERROR }
enum	riscv_hart_state { RISCV_STATE_NON_EXISTENT , RISCV_STATE_RUNNING , RISCV_STATE_HALTED , RISCV_STATE_UNAVAILABLE }
enum	riscv_isrmasking_mode { RISCV_ISRMASK_OFF , RISCV_ISRMASK_STEPONLY }
enum	riscv_mem_access_method { RISCV_MEM_ACCESS_PROGBUF , RISCV_MEM_ACCESS_SYSBUS , RISCV_MEM_ACCESS_ABSTRACT , RISCV_MEM_ACCESS_MAX_METHODS_NUM }
enum	riscv_priv_mode {   RISCV_MODE_M , RISCV_MODE_S , RISCV_MODE_U , RISCV_MODE_VS ,   RISCV_MODE_VU , N_RISCV_MODE }
enum	riscv_virt2phys_mode { RISCV_VIRT2PHYS_MODE_HW , RISCV_VIRT2PHYS_MODE_SW , RISCV_VIRT2PHYS_MODE_OFF }
enum	yes_no_maybe { YNM_MAYBE , YNM_YES , YNM_NO }

Functions
	COMMAND_HELPER (riscv_print_info_line, const char *section, const char *key, unsigned int value)
int	dtmcs_scan (struct jtag_tap *tap, uint32_t out, uint32_t *in_ptr)
static bool	is_riscv (const struct riscv_info *riscv_info)
void	riscv_add_bscan_tunneled_scan (struct jtag_tap *tap, const struct scan_field *field, riscv_bscan_tunneled_scan_context_t *ctxt)
int	riscv_add_watchpoint (struct target *target, struct watchpoint *watchpoint)
int	riscv_enumerate_triggers (struct target *target)
	Count triggers, and initialize trigger_count for each hart. More...
int	riscv_execute_progbuf (struct target *target, uint32_t *cmderr)
void	riscv_fill_dm_nop (const struct target *target, uint8_t *buf)
void	riscv_fill_dmi_read (const struct target *target, uint8_t *buf, uint32_t a)
void	riscv_fill_dmi_write (const struct target *target, uint8_t *buf, uint32_t a, uint32_t d)
int	riscv_get_command_timeout_sec (void)
uint32_t	riscv_get_dmi_address (const struct target *target, uint32_t dm_address)
unsigned int	riscv_get_dmi_address_bits (const struct target *target)
int	riscv_get_hart_state (struct target *target, enum riscv_hart_state *state)
int	riscv_halt (struct target *target)
static struct riscv_info *	riscv_info (const struct target *target) __attribute__((unused))
static bool	riscv_mem_access_is_read (const struct riscv_mem_access_args args)
static bool	riscv_mem_access_is_valid (const struct riscv_mem_access_args args)
static bool	riscv_mem_access_is_write (const struct riscv_mem_access_args args)
int	riscv_openocd_poll (struct target *target)
int	riscv_openocd_step (struct target *target, bool current, target_addr_t address, bool handle_breakpoints)
static struct riscv_private_config *	riscv_private_config (const struct target *target)
unsigned int	riscv_progbuf_size (struct target *target)
int	riscv_read_by_any_size (struct target *target, target_addr_t address, uint32_t size, uint8_t *buffer)
	Read one memory item using any memory access size that will work. More...
riscv_insn_t	riscv_read_progbuf (struct target *target, int index)
int	riscv_remove_watchpoint (struct target *target, struct watchpoint *watchpoint)
enum semihosting_result	riscv_semihosting (struct target *target, int *retval)
	Check for and process a semihosting request using the ARM protocol). More...
void	riscv_semihosting_init (struct target *target)
	Initialize RISC-V semihosting. More...
bool	riscv_supports_extension (const struct target *target, char letter)
bool	riscv_virt2phys_mode_is_hw (const struct target *target)
bool	riscv_virt2phys_mode_is_sw (const struct target *target)
const char *	riscv_virt2phys_mode_to_str (enum riscv_virt2phys_mode mode)
unsigned int	riscv_vlenb (const struct target *target)
int	riscv_write_by_any_size (struct target *target, target_addr_t address, uint32_t size, uint8_t *buffer)
	Write one memory item using any memory access size that will work. More...
int	riscv_write_progbuf (struct target *target, unsigned int index, riscv_insn_t insn)
unsigned int	riscv_xlen (const struct target *target)
void	select_dmi_via_bscan (struct jtag_tap *tap)

Variables
uint8_t	bscan_tunnel_ir_width
struct scan_field *	bscan_tunneled_select_dmi
uint32_t	bscan_tunneled_select_dmi_num_fields
struct target_type	riscv011_target
struct target_type	riscv013_target
struct scan_field	select_dbus
struct scan_field	select_dtmcontrol
struct scan_field	select_idcode

Macro Definition Documentation

DEFAULT_COMMAND_TIMEOUT_SEC

#define DEFAULT_COMMAND_TIMEOUT_SEC   5

Definition at line 25 of file riscv.h.

DTM_DTMCS_VERSION_UNKNOWN

#define DTM_DTMCS_VERSION_UNKNOWN   ((unsigned int)-1)

Definition at line 125 of file riscv.h.

PG_MAX_LEVEL

#define PG_MAX_LEVEL   5

Definition at line 36 of file riscv.h.

RISCV013_DTMCS_ABITS_MAX

#define RISCV013_DTMCS_ABITS_MAX   32

Definition at line 129 of file riscv.h.

RISCV013_DTMCS_ABITS_MIN

#define RISCV013_DTMCS_ABITS_MIN   7

Definition at line 128 of file riscv.h.

RISCV_BATCH_ALLOC_SIZE

#define RISCV_BATCH_ALLOC_SIZE   128

Definition at line 38 of file riscv.h.

RISCV_COMMON_MAGIC

#define RISCV_COMMON_MAGIC   0x52495356U

Definition at line 18 of file riscv.h.

RISCV_HGATP_MODE

#define RISCV_HGATP_MODE

(

xlen

)

((xlen) == 32 ? HGATP32_MODE : HGATP64_MODE)

Definition at line 29 of file riscv.h.

RISCV_HGATP_PPN

#define RISCV_HGATP_PPN

(

xlen

)

((xlen) == 32 ? HGATP32_PPN : HGATP64_PPN)

Definition at line 30 of file riscv.h.

RISCV_INFO

#define RISCV_INFO

(

R

)

struct riscv_info *R = riscv_info(target);

Definition at line 426 of file riscv.h.

RISCV_MAX_DMS

#define RISCV_MAX_DMS   100

Definition at line 23 of file riscv.h.

RISCV_MAX_HARTS

#define RISCV_MAX_HARTS   ((int)BIT(20))

Definition at line 20 of file riscv.h.

RISCV_MAX_HWBPS

#define RISCV_MAX_HWBPS   16

Definition at line 22 of file riscv.h.

RISCV_MAX_TRIGGERS

#define RISCV_MAX_TRIGGERS   32

Definition at line 21 of file riscv.h.

RISCV_PGBASE

#define RISCV_PGBASE

(

addr

)

((addr) & ~(RISCV_PGSIZE - 1))

Definition at line 33 of file riscv.h.

RISCV_PGOFFSET

#define RISCV_PGOFFSET

(

addr

)

((addr) & (RISCV_PGSIZE - 1))

Definition at line 34 of file riscv.h.

RISCV_PGSHIFT

#define RISCV_PGSHIFT   12

Definition at line 31 of file riscv.h.

RISCV_PGSIZE

#define RISCV_PGSIZE   BIT(RISCV_PGSHIFT)

Definition at line 32 of file riscv.h.

RISCV_SAMPLE_BUF_TIMESTAMP_AFTER

#define RISCV_SAMPLE_BUF_TIMESTAMP_AFTER   0x81

Definition at line 103 of file riscv.h.

RISCV_SAMPLE_BUF_TIMESTAMP_BEFORE

#define RISCV_SAMPLE_BUF_TIMESTAMP_BEFORE   0x80

Definition at line 102 of file riscv.h.

RISCV_SATP_MODE

#define RISCV_SATP_MODE

(

xlen

)

((xlen) == 32 ? SATP32_MODE : SATP64_MODE)

Definition at line 27 of file riscv.h.

RISCV_SATP_PPN

#define RISCV_SATP_PPN

(

xlen

)

((xlen) == 32 ? SATP32_PPN : SATP64_PPN)

Definition at line 28 of file riscv.h.

RISCV_TINFO_VERSION_UNKNOWN

#define RISCV_TINFO_VERSION_UNKNOWN   (-1)

Definition at line 126 of file riscv.h.

Typedef Documentation

riscv_addr_t

typedef uint64_t riscv_addr_t

Definition at line 48 of file riscv.h.

riscv_insn_t

typedef uint32_t riscv_insn_t

Definition at line 47 of file riscv.h.

riscv_reg_t

typedef uint64_t riscv_reg_t

Definition at line 46 of file riscv.h.

Enumeration Type Documentation

bscan_tunnel_type_t

enum bscan_tunnel_type_t

Enumerator
BSCAN_TUNNEL_NESTED_TAP
BSCAN_TUNNEL_DATA_REGISTER

Definition at line 441 of file riscv.h.

riscv_halt_reason

enum riscv_halt_reason

Enumerator
RISCV_HALT_INTERRUPT
RISCV_HALT_EBREAK
RISCV_HALT_SINGLESTEP
RISCV_HALT_TRIGGER
RISCV_HALT_UNKNOWN
RISCV_HALT_GROUP
RISCV_HALT_ERROR

Definition at line 71 of file riscv.h.

riscv_hart_state

enum riscv_hart_state

Enumerator
RISCV_STATE_NON_EXISTENT
RISCV_STATE_RUNNING
RISCV_STATE_HALTED
RISCV_STATE_UNAVAILABLE

Definition at line 88 of file riscv.h.

riscv_isrmasking_mode

enum riscv_isrmasking_mode

Enumerator
RISCV_ISRMASK_OFF
RISCV_ISRMASK_STEPONLY

Definition at line 81 of file riscv.h.

riscv_mem_access_method

enum riscv_mem_access_method

Enumerator
RISCV_MEM_ACCESS_PROGBUF
RISCV_MEM_ACCESS_SYSBUS
RISCV_MEM_ACCESS_ABSTRACT
RISCV_MEM_ACCESS_MAX_METHODS_NUM

Definition at line 56 of file riscv.h.

riscv_priv_mode

enum riscv_priv_mode

Enumerator
RISCV_MODE_M
RISCV_MODE_S
RISCV_MODE_U
RISCV_MODE_VS
RISCV_MODE_VU
N_RISCV_MODE

Definition at line 370 of file riscv.h.

riscv_virt2phys_mode

enum riscv_virt2phys_mode

Enumerator
RISCV_VIRT2PHYS_MODE_HW
RISCV_VIRT2PHYS_MODE_SW
RISCV_VIRT2PHYS_MODE_OFF

Definition at line 63 of file riscv.h.

yes_no_maybe

enum yes_no_maybe

Enumerator
YNM_MAYBE
YNM_YES
YNM_NO

Definition at line 50 of file riscv.h.

Function Documentation

COMMAND_HELPER()

COMMAND_HELPER	(	riscv_print_info_line	,
		const char *	section,
		const char *	key,
		unsigned int	value
	)

Definition at line 5378 of file riscv.c.

References CALL_COMMAND_HANDLER.

dtmcs_scan()

int dtmcs_scan	(	struct jtag_tap *	tap,
		uint32_t	out,
		uint32_t *	in_ptr
	)

Definition at line 416 of file riscv.c.

References bscan_tunnel_ir_width, buf_get_u32(), buf_set_u32(), dtmcs_scan_via_bscan(), ERROR_OK, scan_field::in_value, jtag_add_dr_scan(), jtag_add_ir_scan(), jtag_execute_queue(), jtag_tap_name(), LOG_DEBUG, LOG_ERROR, NULL, scan_field::num_bits, select_dbus, select_dtmcontrol, and TAP_IDLE.

Referenced by examine(), increase_dbus_busy_delay(), increase_dmi_busy_delay(), and riscv_examine().

is_riscv()

static bool is_riscv ( const struct riscv_info *  riscv_info )

inlinestatic

Definition at line 428 of file riscv.h.

References riscv_info::common_magic, and RISCV_COMMON_MAGIC.

Referenced by fespi_write().

riscv_add_bscan_tunneled_scan()

void riscv_add_bscan_tunneled_scan	(	struct jtag_tap *	tap,
		const struct scan_field *	field,
		riscv_bscan_tunneled_scan_context_t *	ctxt
	)

Definition at line 6292 of file riscv.c.

References ARRAY_SIZE, bscan_one, BSCAN_TUNNEL_DATA_REGISTER, bscan_tunnel_type, bscan_zero, scan_field::in_value, jtag_add_dr_scan(), jtag_add_ir_scan(), scan_field::num_bits, scan_field::out_value, select_user4, TAP_IDLE, riscv_bscan_tunneled_scan_context_t::tunneled_dr, and riscv_bscan_tunneled_scan_context_t::tunneled_dr_width.

Referenced by riscv_batch_run_from().

riscv_add_watchpoint()

int riscv_add_watchpoint	(	struct target *	target,
		struct watchpoint *	watchpoint
	)

Definition at line 1735 of file riscv.c.

References add_trigger(), ERROR_OK, ERROR_TARGET_RESOURCE_NOT_AVAILABLE, find_first_trigger_by_id(), LOG_TARGET_ERROR, watchpoint::mask, trigger_from_watchpoint(), watchpoint::unique_id, WATCHPOINT_IGNORE_DATA_VALUE_MASK, and watchpoint_set().

Referenced by enable_watchpoints(), and strict_step().

riscv_enumerate_triggers()

int riscv_enumerate_triggers

(

struct target *

target

)

Count triggers, and initialize trigger_count for each hart.

trigger_count is initialized even if this function fails to discover something. Disable any hardware triggers that have dmode set. We can't have set them ourselves. Maybe they're left over from some killed debug session.

Definition at line 6216 of file riscv.c.

References ARRAY_SIZE, check_if_trigger_exists(), create_wp_trigger_cache(), CSR_TINFO_VERSION, disable_trigger_if_dmode(), ERROR_FAIL, ERROR_OK, ERROR_TARGET_NOT_HALTED, ERROR_TARGET_RESOURCE_NOT_AVAILABLE, GDB_REGNO_TDATA1, GDB_REGNO_TINFO, GDB_REGNO_TSELECT, get_field(), get_trigger_types(), LOG_TARGET_DEBUG, LOG_TARGET_ERROR, LOG_TARGET_INFO, NULL, RISCV_INFO, riscv_reg_get(), riscv_reg_set(), RISCV_TINFO_VERSION_UNKNOWN, target::state, and TARGET_HALTED.

Referenced by add_trigger(), COMMAND_HANDLER(), COMMAND_HELPER(), handle_halt(), remove_trigger(), and riscv_openocd_step_impl().

riscv_execute_progbuf()

int riscv_execute_progbuf	(	struct target *	target,
		uint32_t *	cmderr
	)

Definition at line 6107 of file riscv.c.

References RISCV_INFO.

Referenced by riscv_program_exec().

riscv_fill_dm_nop()

void riscv_fill_dm_nop	(	const struct target *	target,
		uint8_t *	buf
	)

Definition at line 6125 of file riscv.c.

References RISCV_INFO.

Referenced by riscv_batch_add_dmi_read(), riscv_batch_add_dmi_write(), and riscv_batch_add_nop().

riscv_fill_dmi_read()

void riscv_fill_dmi_read	(	const struct target *	target,
		uint8_t *	buf,
		uint32_t	a
	)

Definition at line 6119 of file riscv.c.

References RISCV_INFO.

Referenced by riscv_batch_add_dmi_read().

riscv_fill_dmi_write()

void riscv_fill_dmi_write	(	const struct target *	target,
		uint8_t *	buf,
		uint32_t	a,
		uint32_t	d
	)

Definition at line 6113 of file riscv.c.

References RISCV_INFO.

Referenced by riscv_batch_add_dmi_write().

riscv_get_command_timeout_sec()

int riscv_get_command_timeout_sec

(

void

)

Definition at line 179 of file riscv.c.

References MAX, riscv_command_timeout_sec_value, and riscv_reset_timeout_sec.

Referenced by batch_run_timeout(), deassert_reset(), full_step(), read_sbcs_nonbusy(), reset_dm(), wait_for_authbusy(), wait_for_debugint_clear(), wait_for_idle(), and wait_for_state().

riscv_get_dmi_address()

uint32_t riscv_get_dmi_address	(	const struct target *	target,
		uint32_t	dm_address
	)

Definition at line 4649 of file riscv.c.

References RISCV_INFO.

Referenced by COMMAND_HANDLER(), decode_dmi(), riscv_batch_add_dm_read(), riscv_batch_add_dm_write(), and riscv_dmi_write().

riscv_get_dmi_address_bits()

unsigned int riscv_get_dmi_address_bits

(

const struct target *

target

)

Definition at line 6131 of file riscv.c.

References RISCV_INFO.

Referenced by get_dmi_scan_length(), and log_batch().

riscv_get_hart_state()

int riscv_get_hart_state	(	struct target *	target,
		enum riscv_hart_state *	state
	)

Definition at line 6072 of file riscv.c.

References RISCV_INFO, and state.

Referenced by examine(), riscv_halt_go_all_harts(), and riscv_poll_hart().

riscv_halt()

int riscv_halt

(

struct target *

target

)

Definition at line 2708 of file riscv.c.

References ERROR_FAIL, ERROR_OK, foreach_smp_target, get_target_type(), target_type::halt, halt_finish(), halt_go(), halt_prep(), LOG_TARGET_DEBUG, riscv_info::prepped, riscv_info(), RISCV_INFO, target::smp, target::smp_targets, and target_list::target.

Referenced by riscv013_step_or_resume_current_hart(), riscv_openocd_poll(), and riscv_run_algorithm().

riscv_info()

static struct riscv_info * riscv_info ( const struct target *  target )

inlinestatic

Definition at line 421 of file riscv.h.

References target::arch_info.

Referenced by COMMAND_HANDLER(), examine(), fespi_write(), riscv_halt(), riscv_openocd_poll(), riscv_resume(), and select_prepped_harts().

riscv_mem_access_is_read()

static bool riscv_mem_access_is_read ( const struct riscv_mem_access_args  args )

inlinestatic

Definition at line 154 of file riscv.h.

References riscv_mem_access_args::read_buffer, riscv_mem_access_is_valid(), and riscv_mem_access_args::write_buffer.

Referenced by read_memory(), read_memory_bus_v0(), read_memory_bus_v1(), read_memory_progbuf_inner_ensure_forward_progress(), read_memory_progbuf_inner_extract_batch_data(), read_memory_progbuf_inner_on_ac_busy(), read_memory_progbuf_inner_on_dmi_busy(), read_memory_progbuf_inner_run_and_process_batch(), read_memory_progbuf_inner_try_to_read(), riscv013_access_memory(), and set_buffer_and_log_read().

riscv_mem_access_is_valid()

static bool riscv_mem_access_is_valid ( const struct riscv_mem_access_args  args )

inlinestatic

Definition at line 148 of file riscv.h.

References riscv_mem_access_args::read_buffer, and riscv_mem_access_args::write_buffer.

Referenced by access_memory(), riscv013_access_memory(), riscv_mem_access_is_read(), riscv_mem_access_is_write(), and riscv_rw_memory().

riscv_mem_access_is_write()

static bool riscv_mem_access_is_write ( const struct riscv_mem_access_args  args )

inlinestatic

Definition at line 161 of file riscv.h.

References riscv_mem_access_args::read_buffer, riscv_mem_access_is_valid(), and riscv_mem_access_args::write_buffer.

Referenced by access_memory(), riscv_rw_memory(), write_memory(), write_memory_bus_v0(), and write_memory_bus_v1().

riscv_openocd_poll()

int riscv_openocd_poll

(

struct target *

target

)

Definition at line 4016 of file riscv.c.

References alive_sleep(), CSR_DCSR_CAUSE, CSR_DCSR_CAUSE_GROUP, ERROR_FAIL, ERROR_OK, foreach_smp_target, GDB_REGNO_DCSR, get_field(), riscv_info::halt_group_repoll_count, halted(), info, target_list::lh, list_add(), LOG_TARGET_DEBUG, LOG_TARGET_WARNING, NULL, OOCD_LIST_HEAD, riscv_halt(), RISCV_HALT_GROUP_REPOLL_LIMIT, riscv_info(), riscv_poll_hart(), riscv_reg_get(), riscv_resume(), RPH_NONE, RPH_REMAIN_HALTED, RPH_RESUME, sample_memory(), target::smp, target::smp_targets, target::state, target_list::target, target_call_event_callbacks(), TARGET_DEBUG_RUNNING, TARGET_HALTED, TARGET_RUNNING, and target_was_examined().

Referenced by derive_debug_reason_without_hitbit().

riscv_openocd_step()

int riscv_openocd_step	(	struct target *	target,
		bool	current,
		target_addr_t	address,
		bool	handle_breakpoints
	)

Definition at line 4287 of file riscv.c.

References address, and riscv_openocd_step_impl().

riscv_private_config()

static struct riscv_private_config* riscv_private_config ( const struct target *  target )

inlinestatic

Definition at line 384 of file riscv.h.

References target::private_config.

Referenced by COMMAND_HELPER(), dcsr_ebreak_config_equals_reset_value(), set_dcsr_ebreak(), and set_ebreakx_fields().

riscv_progbuf_size()

unsigned int riscv_progbuf_size

(

struct target *

target

)

Definition at line 6089 of file riscv.c.

References RISCV_INFO.

Referenced by COMMAND_HANDLER(), riscv_program_ebreak(), riscv_program_exec(), and riscv_program_insert().

riscv_read_by_any_size()

int riscv_read_by_any_size	(	struct target *	target,
		target_addr_t	address,
		uint32_t	size,
		uint8_t *	buffer
	)

Read one memory item using any memory access size that will work.

Read larger section of memory and pick out the required portion, if needed.

Definition at line 1579 of file riscv.c.

References address, buffer, ERROR_FAIL, ERROR_OK, read_by_given_size(), and size.

Referenced by riscv_add_breakpoint(), and riscv_semihosting_detect_magic_sequence().

riscv_read_progbuf()

riscv_insn_t riscv_read_progbuf	(	struct target *	target,
		int	index
	)

Definition at line 6101 of file riscv.c.

References RISCV_INFO.

riscv_remove_watchpoint()

int riscv_remove_watchpoint	(	struct target *	target,
		struct watchpoint *	watchpoint
	)

Definition at line 1755 of file riscv.c.

Referenced by disable_watchpoints(), and strict_step().

riscv_semihosting()

enum semihosting_result riscv_semihosting	(	struct target *	target,
		int *	retval
	)

Check for and process a semihosting request using the ARM protocol).

This is meant to be called when the target is stopped due to a debug mode entry.

Parameters

target	Pointer to the target to process.
retval	Pointer to a location where the return code will be stored

Returns

non-zero value if a request was processed or an error encountered

Definition at line 94 of file riscv_semihosting.c.

References riscv_semihosting_post_result(), riscv_semihosting_setup(), and semihosting_common_init().

Referenced by handle_halt(), and riscv_poll_hart().

riscv_semihosting_init()

void riscv_semihosting_init

(

struct target *

target

)

Initialize RISC-V semihosting.

Use common ARM code.

Definition at line 94 of file riscv_semihosting.c.

Referenced by riscv_init_target().

riscv_supports_extension()

bool riscv_supports_extension	(	const struct target *	target,
		char	letter
	)

Definition at line 6047 of file riscv.c.

References BIT, and RISCV_INFO.

Referenced by examine_vlenb(), fpr_read_progbuf(), fpr_write_progbuf(), gdb_regno_reg_data_type(), gdb_regno_size(), riscv013_reg_get(), riscv013_reg_set(), riscv_reg_impl_gdb_regno_exist(), and verify_loadstore().

riscv_virt2phys_mode_is_hw()

bool riscv_virt2phys_mode_is_hw

(

const struct target *

target

)

Definition at line 144 of file riscv.c.

References RISCV_INFO, and RISCV_VIRT2PHYS_MODE_HW.

Referenced by modify_privilege_for_virt2phys_mode(), and restore_privilege_from_virt2phys_mode().

riscv_virt2phys_mode_is_sw()

bool riscv_virt2phys_mode_is_sw

(

const struct target *

target

)

Definition at line 151 of file riscv.c.

References RISCV_INFO, and RISCV_VIRT2PHYS_MODE_SW.

Referenced by riscv_mmu().

riscv_virt2phys_mode_to_str()

const char* riscv_virt2phys_mode_to_str

(

enum riscv_virt2phys_mode

mode

)

Definition at line 158 of file riscv.c.

References mode, RISCV_VIRT2PHYS_MODE_HW, RISCV_VIRT2PHYS_MODE_OFF, and RISCV_VIRT2PHYS_MODE_SW.

Referenced by COMMAND_HANDLER().

riscv_vlenb()

unsigned int riscv_vlenb

(

const struct target *

target

)

Definition at line 6066 of file riscv.c.

References RISCV_INFO.

Referenced by gdb_regno_size(), riscv_reg_impl_init_vector_reg_type(), and vlenb_exists().

riscv_write_by_any_size()

int riscv_write_by_any_size	(	struct target *	target,
		target_addr_t	address,
		uint32_t	size,
		uint8_t *	buffer
	)

Write one memory item using any memory access size that will work.

Utilize read-modify-write, if needed.

Definition at line 1547 of file riscv.c.

References address, buffer, ERROR_FAIL, ERROR_OK, size, and write_by_given_size().

Referenced by riscv_add_breakpoint(), and riscv_remove_breakpoint().

riscv_write_progbuf()

int riscv_write_progbuf	(	struct target *	target,
		unsigned int	index,
		riscv_insn_t	insn
	)

Definition at line 6095 of file riscv.c.

References RISCV_INFO.

Referenced by riscv_program_write().

riscv_xlen()

unsigned int riscv_xlen

(

const struct target *

target

)

Definition at line 6060 of file riscv.c.

References RISCV_INFO.

Referenced by cache_get(), cache_set(), check_if_trigger_exists(), check_misa_mxl(), COMMAND_HANDLER(), disable_trigger_if_dmode(), examine(), execute_resume(), fespi_write(), fill_match_triggers_tdata1_fields_t2(), fpr_read_progbuf(), fpr_write_progbuf(), gdb_regno_size(), get_loadstore_memoffset(), get_trigger_types(), handle_halt_routine(), load(), maybe_add_trigger_t3(), maybe_add_trigger_t4(), maybe_add_trigger_t5(), read_memory_progbuf_inner_extract_batch_data(), read_memory_progbuf_inner_startup(), register_size(), register_write(), riscv011_get_register(), riscv013_data_bits(), riscv_address_translate(), riscv_checksum_memory(), riscv_data_bits(), riscv_get_gdb_arch(), riscv_mmu(), riscv_reg_impl_gdb_regno_exist(), riscv_trigger_detect_hit_bits(), riscv_virt2phys(), riscv_virt2phys_v(), riscv_xlen_nonconst(), scans_add_read(), scans_new(), set_trigger(), slot_offset(), step(), store(), try_set_vsew(), try_setup_single_match_trigger(), verify_loadstore(), and write_memory_progbuf_startup().

select_dmi_via_bscan()

void select_dmi_via_bscan

(

struct jtag_tap *

tap

)

Definition at line 319 of file riscv.c.

References BSCAN_TUNNEL_DATA_REGISTER, bscan_tunnel_data_register_select_dmi, bscan_tunnel_data_register_select_dmi_num_fields, bscan_tunnel_nested_tap_select_dmi, bscan_tunnel_nested_tap_select_dmi_num_fields, bscan_tunnel_type, jtag_add_dr_scan(), jtag_add_ir_scan(), select_user4, and TAP_IDLE.

Referenced by dtmcs_scan_via_bscan(), and select_dmi().

Variable Documentation

bscan_tunnel_ir_width

uint8_t bscan_tunnel_ir_width

extern

Definition at line 60 of file riscv.c.

Referenced by COMMAND_HANDLER(), dtmcs_scan(), dtmcs_scan_via_bscan(), riscv_batch_alloc(), riscv_batch_run_from(), riscv_init_target(), and select_dmi().

bscan_tunneled_select_dmi

struct scan_field* bscan_tunneled_select_dmi

extern

bscan_tunneled_select_dmi_num_fields

uint32_t bscan_tunneled_select_dmi_num_fields

extern

riscv011_target

struct target_type riscv011_target

extern

Definition at line 2436 of file riscv-011.c.

Referenced by get_target_type().

riscv013_target

struct target_type riscv013_target

extern

Definition at line 5087 of file riscv-013.c.

Referenced by get_target_type().

select_dbus

struct scan_field select_dbus

extern

Definition at line 47 of file riscv.c.

Referenced by assert_reset(), deassert_reset(), dtmcs_scan(), halt(), idcode_scan(), poll_target(), read_memory(), riscv011_resume(), riscv_init_target(), select_dmi(), step(), and write_memory().

select_dtmcontrol

struct scan_field select_dtmcontrol

extern

Definition at line 42 of file riscv.c.

Referenced by dtmcs_scan(), and riscv_init_target().

select_idcode

struct scan_field select_idcode

extern

Definition at line 52 of file riscv.c.

Referenced by idcode_scan(), and riscv_init_target().