at91sam9.c

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// SPDX-License-Identifier: GPL-2.0-or-later
 
/*
 * Copyright (C) 2009 by Dean Glazeski
 * dnglaze@gmail.com
 */
 
#ifdef HAVE_CONFIG_H
#include "config.h"
#endif
 
#include <target/arm.h>
#include <helper/log.h>
#include "imp.h"
#include "arm_io.h"
 
#define AT91C_PIOX_SODR (0x30)  
#define AT91C_PIOX_CODR (0x34)  
#define AT91C_PIOX_PDSR (0x3C)  
#define AT91C_ECCX_CR (0x00)    
#define AT91C_ECCX_SR (0x08)    
#define AT91C_ECCX_PR (0x0C)    
#define AT91C_ECCX_NPR (0x10)   
struct at91sam9_pin {
    uint32_t pioc;
 
    uint32_t num;
};
 
struct at91sam9_nand {
    uint32_t ecc;
 
    uint32_t data;
 
    uint32_t cmd;
 
    uint32_t addr;
 
    struct arm_nand_data io;
 
    struct at91sam9_pin busy;
 
    struct at91sam9_pin ce;
};
 
static int at91sam9_halted(struct target *target, const char *label)
{
    if (target->state == TARGET_HALTED)
        return true;
 
    LOG_ERROR("Target must be halted to use NAND controller (%s)", label);
    return false;
}
 
static int at91sam9_init(struct nand_device *nand)
{
    struct target *target = nand->target;
 
    if (!at91sam9_halted(target, "init"))
        return ERROR_NAND_OPERATION_FAILED;
 
    return ERROR_OK;
}
 
static int at91sam9_enable(struct nand_device *nand)
{
    struct at91sam9_nand *info = nand->controller_priv;
    struct target *target = nand->target;
 
    return target_write_u32(target, info->ce.pioc + AT91C_PIOX_CODR, 1 << info->ce.num);
}
 
static int at91sam9_disable(struct nand_device *nand)
{
    struct at91sam9_nand *info = nand->controller_priv;
    struct target *target = nand->target;
 
    return target_write_u32(target, info->ce.pioc + AT91C_PIOX_SODR, 1 << info->ce.num);
}
 
static int at91sam9_command(struct nand_device *nand, uint8_t command)
{
    struct at91sam9_nand *info = nand->controller_priv;
    struct target *target = nand->target;
 
    if (!at91sam9_halted(target, "command"))
        return ERROR_NAND_OPERATION_FAILED;
 
    at91sam9_enable(nand);
 
    return target_write_u8(target, info->cmd, command);
}
 
static int at91sam9_reset(struct nand_device *nand)
{
    if (!at91sam9_halted(nand->target, "reset"))
        return ERROR_NAND_OPERATION_FAILED;
 
    return at91sam9_disable(nand);
}
 
static int at91sam9_address(struct nand_device *nand, uint8_t address)
{
    struct at91sam9_nand *info = nand->controller_priv;
    struct target *target = nand->target;
 
    if (!at91sam9_halted(nand->target, "address"))
        return ERROR_NAND_OPERATION_FAILED;
 
    return target_write_u8(target, info->addr, address);
}
 
static int at91sam9_read_data(struct nand_device *nand, void *data)
{
    struct at91sam9_nand *info = nand->controller_priv;
    struct target *target = nand->target;
 
    if (!at91sam9_halted(nand->target, "read data"))
        return ERROR_NAND_OPERATION_FAILED;
 
    return target_read_u8(target, info->data, data);
}
 
static int at91sam9_write_data(struct nand_device *nand, uint16_t data)
{
    struct at91sam9_nand *info = nand->controller_priv;
    struct target *target = nand->target;
 
    if (!at91sam9_halted(target, "write data"))
        return ERROR_NAND_OPERATION_FAILED;
 
    return target_write_u8(target, info->data, data);
}
 
static int at91sam9_nand_ready(struct nand_device *nand, int timeout)
{
    struct at91sam9_nand *info = nand->controller_priv;
    struct target *target = nand->target;
    uint32_t status;
 
    if (!at91sam9_halted(target, "nand ready"))
        return 0;
 
    do {
        target_read_u32(target, info->busy.pioc + AT91C_PIOX_PDSR, &status);
 
        if (status & (1 << info->busy.num))
            return 1;
 
        alive_sleep(1);
    } while (timeout-- > 0);
 
    return 0;
}
 
static int at91sam9_read_block_data(struct nand_device *nand, uint8_t *data, int size)
{
    struct at91sam9_nand *info = nand->controller_priv;
    struct arm_nand_data *io = &info->io;
 
    if (!at91sam9_halted(nand->target, "read block"))
        return ERROR_NAND_OPERATION_FAILED;
 
    io->chunk_size = nand->page_size;
    return arm_nandread(io, data, size);
}
 
static int at91sam9_write_block_data(struct nand_device *nand, uint8_t *data, int size)
{
    struct at91sam9_nand *info = nand->controller_priv;
    struct arm_nand_data *io = &info->io;
 
    if (!at91sam9_halted(nand->target, "write block"))
        return ERROR_NAND_OPERATION_FAILED;
 
    io->chunk_size = nand->page_size;
    return arm_nandwrite(io, data, size);
}
 
static int at91sam9_ecc_init(struct target *target, struct at91sam9_nand *info)
{
    if (!info->ecc) {
        LOG_ERROR("ECC controller address must be set when not reading raw NAND data");
        return ERROR_NAND_OPERATION_FAILED;
    }
 
    /* reset ECC parity registers */
    return target_write_u32(target, info->ecc + AT91C_ECCX_CR, 1);
}
 
static uint8_t *at91sam9_oob_init(struct nand_device *nand, uint8_t *oob, uint32_t *size)
{
    if (!oob) {
        /* user doesn't want OOB, allocate it */
        if (nand->page_size == 512)
            *size = 16;
        else if (nand->page_size == 2048)
            *size = 64;
 
        oob = malloc(*size);
        if (!oob) {
            LOG_ERROR("Unable to allocate space for OOB");
            return NULL;
        }
 
        memset(oob, 0xFF, *size);
    }
 
    return oob;
}
 
static int at91sam9_read_page(struct nand_device *nand, uint32_t page,
    uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
{
    int retval;
    struct at91sam9_nand *info = nand->controller_priv;
    struct target *target = nand->target;
    uint8_t *oob_data;
    uint32_t status;
 
    retval = at91sam9_ecc_init(target, info);
    if (retval != ERROR_OK)
        return retval;
 
    retval = nand_page_command(nand, page, NAND_CMD_READ0, !data);
    if (retval != ERROR_OK)
        return retval;
 
    if (data) {
        retval = nand_read_data_page(nand, data, data_size);
        if (retval != ERROR_OK)
            return retval;
    }
 
    oob_data = at91sam9_oob_init(nand, oob, &oob_size);
    retval = nand_read_data_page(nand, oob_data, oob_size);
    if (retval == ERROR_OK && data) {
        target_read_u32(target, info->ecc + AT91C_ECCX_SR, &status);
        if (status & 1) {
            LOG_ERROR("Error detected!");
            if (status & 4)
                LOG_ERROR("Multiple errors encountered; unrecoverable!");
            else {
                /* attempt recovery */
                uint32_t parity;
 
                target_read_u32(target,
                    info->ecc + AT91C_ECCX_PR,
                    &parity);
                uint32_t word = (parity & 0x0000FFF0) >> 4;
                uint32_t bit = parity & 0x0F;
 
                data[word] ^= (0x1) << bit;
                LOG_INFO("Data word %" PRIu32 ", bit %" PRIu32 " corrected.",
                    word, bit);
            }
        }
 
        if (status & 2) {
            /* we could write back correct ECC data */
            LOG_ERROR("Error in ECC bytes detected");
        }
    }
 
    if (!oob) {
        /* if it wasn't asked for, free it */
        free(oob_data);
    }
 
    return retval;
}
 
static int at91sam9_write_page(struct nand_device *nand, uint32_t page,
    uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
{
    struct at91sam9_nand *info = nand->controller_priv;
    struct target *target = nand->target;
    int retval;
    uint8_t *oob_data = oob;
    uint32_t parity, nparity;
 
    retval = at91sam9_ecc_init(target, info);
    if (retval != ERROR_OK)
        return retval;
 
    retval = nand_page_command(nand, page, NAND_CMD_SEQIN, !data);
    if (retval != ERROR_OK)
        return retval;
 
    if (data) {
        retval = nand_write_data_page(nand, data, data_size);
        if (retval != ERROR_OK) {
            LOG_ERROR("Unable to write data to NAND device");
            return retval;
        }
    }
 
    oob_data = at91sam9_oob_init(nand, oob, &oob_size);
 
    if (!oob) {
        /* no OOB given, so read in the ECC parity from the ECC controller */
        target_read_u32(target, info->ecc + AT91C_ECCX_PR, &parity);
        target_read_u32(target, info->ecc + AT91C_ECCX_NPR, &nparity);
 
        oob_data[0] = (uint8_t) parity;
        oob_data[1] = (uint8_t) (parity >> 8);
        oob_data[2] = (uint8_t) nparity;
        oob_data[3] = (uint8_t) (nparity >> 8);
    }
 
    retval = nand_write_data_page(nand, oob_data, oob_size);
 
    if (!oob)
        free(oob_data);
 
    if (retval != ERROR_OK) {
        LOG_ERROR("Unable to write OOB data to NAND");
        return retval;
    }
 
    return nand_write_finish(nand);
}
 
NAND_DEVICE_COMMAND_HANDLER(at91sam9_nand_device_command)
{
    unsigned long chip = 0, ecc = 0;
    struct at91sam9_nand *info = NULL;
 
    LOG_DEBUG("AT91SAM9 NAND Device Command");
 
    if (CMD_ARGC < 3 || CMD_ARGC > 4) {
        LOG_ERROR("parameters: %s target chip_addr", CMD_ARGV[0]);
        return ERROR_NAND_OPERATION_FAILED;
    }
 
    COMMAND_PARSE_NUMBER(ulong, CMD_ARGV[2], chip);
    if (chip == 0) {
        LOG_ERROR("invalid NAND chip address: %s", CMD_ARGV[2]);
        return ERROR_NAND_OPERATION_FAILED;
    }
 
    if (CMD_ARGC == 4) {
        COMMAND_PARSE_NUMBER(ulong, CMD_ARGV[3], ecc);
        if (ecc == 0) {
            LOG_ERROR("invalid ECC controller address: %s", CMD_ARGV[3]);
            return ERROR_NAND_OPERATION_FAILED;
        }
    }
 
    info = calloc(1, sizeof(*info));
    if (!info) {
        LOG_ERROR("unable to allocate space for controller private data");
        return ERROR_NAND_OPERATION_FAILED;
    }
 
    info->data = chip;
    info->cmd = chip | (1 << 22);
    info->addr = chip | (1 << 21);
    info->ecc = ecc;
 
    nand->controller_priv = info;
    info->io.target = nand->target;
    info->io.data = info->data;
    info->io.op = ARM_NAND_NONE;
 
    return ERROR_OK;
}
 
COMMAND_HANDLER(handle_at91sam9_cle_command)
{
    struct nand_device *nand = NULL;
    struct at91sam9_nand *info = NULL;
    unsigned int num, address_line;
 
    if (CMD_ARGC != 2) {
        command_print(CMD, "incorrect number of arguments for 'at91sam9 cle' command");
        return ERROR_OK;
    }
 
    COMMAND_PARSE_NUMBER(uint, CMD_ARGV[0], num);
    nand = get_nand_device_by_num(num);
    if (!nand) {
        command_print(CMD, "invalid nand device number: %s", CMD_ARGV[0]);
        return ERROR_OK;
    }
 
    info = nand->controller_priv;
 
    COMMAND_PARSE_NUMBER(uint, CMD_ARGV[1], address_line);
    info->cmd = info->data | (1 << address_line);
 
    return ERROR_OK;
}
 
COMMAND_HANDLER(handle_at91sam9_ale_command)
{
    struct nand_device *nand = NULL;
    struct at91sam9_nand *info = NULL;
    unsigned int num, address_line;
 
    if (CMD_ARGC != 2)
        return ERROR_COMMAND_SYNTAX_ERROR;
 
    COMMAND_PARSE_NUMBER(uint, CMD_ARGV[0], num);
    nand = get_nand_device_by_num(num);
    if (!nand) {
        command_print(CMD, "invalid nand device number: %s", CMD_ARGV[0]);
        return ERROR_COMMAND_ARGUMENT_INVALID;
    }
 
    info = nand->controller_priv;
 
    COMMAND_PARSE_NUMBER(uint, CMD_ARGV[1], address_line);
    info->addr = info->data | (1 << address_line);
 
    return ERROR_OK;
}
 
COMMAND_HANDLER(handle_at91sam9_rdy_busy_command)
{
    struct nand_device *nand = NULL;
    struct at91sam9_nand *info = NULL;
    unsigned int num, base_pioc, pin_num;
 
    if (CMD_ARGC != 3)
        return ERROR_COMMAND_SYNTAX_ERROR;
 
    COMMAND_PARSE_NUMBER(uint, CMD_ARGV[0], num);
    nand = get_nand_device_by_num(num);
    if (!nand) {
        command_print(CMD, "invalid nand device number: %s", CMD_ARGV[0]);
        return ERROR_COMMAND_ARGUMENT_INVALID;
    }
 
    info = nand->controller_priv;
 
    COMMAND_PARSE_NUMBER(uint, CMD_ARGV[1], base_pioc);
    info->busy.pioc = base_pioc;
 
    COMMAND_PARSE_NUMBER(uint, CMD_ARGV[2], pin_num);
    info->busy.num = pin_num;
 
    return ERROR_OK;
}
 
COMMAND_HANDLER(handle_at91sam9_ce_command)
{
    struct nand_device *nand = NULL;
    struct at91sam9_nand *info = NULL;
    unsigned int num, base_pioc, pin_num;
 
    if (CMD_ARGC != 3)
        return ERROR_COMMAND_SYNTAX_ERROR;
 
    COMMAND_PARSE_NUMBER(uint, CMD_ARGV[0], num);
    nand = get_nand_device_by_num(num);
    if (!nand) {
        command_print(CMD, "invalid nand device number: %s", CMD_ARGV[0]);
        return ERROR_COMMAND_ARGUMENT_INVALID;
    }
 
    info = nand->controller_priv;
 
    COMMAND_PARSE_NUMBER(uint, CMD_ARGV[1], base_pioc);
    info->ce.pioc = base_pioc;
 
    COMMAND_PARSE_NUMBER(uint, CMD_ARGV[2], pin_num);
    info->ce.num = pin_num;
 
    return ERROR_OK;
}
 
static const struct command_registration at91sam9_sub_command_handlers[] = {
    {
        .name = "cle",
        .handler = handle_at91sam9_cle_command,
        .mode = COMMAND_CONFIG,
        .help = "set command latch enable address line (default is 22)",
        .usage = "bank_id address_line",
    },
    {
        .name = "ale",
        .handler = handle_at91sam9_ale_command,
        .mode = COMMAND_CONFIG,
        .help = "set address latch enable address line (default is 21)",
        .usage = "bank_id address_line",
    },
    {
        .name = "rdy_busy",
        .handler = handle_at91sam9_rdy_busy_command,
        .mode = COMMAND_CONFIG,
        .help = "set the GPIO input pin connected to "
            "the RDY/~BUSY signal (no default)",
        .usage = "bank_id pio_base_addr pin_num",
    },
    {
        .name = "ce",
        .handler = handle_at91sam9_ce_command,
        .mode = COMMAND_CONFIG,
        .help = "set the GPIO output pin connected to "
            "the chip enable signal (no default)",
        .usage = "bank_id pio_base_addr pin_num",
    },
    COMMAND_REGISTRATION_DONE
};
 
static const struct command_registration at91sam9_command_handler[] = {
    {
        .name = "at91sam9",
        .mode = COMMAND_ANY,
        .help = "AT91SAM9 NAND flash controller commands",
        .usage = "",
        .chain = at91sam9_sub_command_handlers,
    },
    COMMAND_REGISTRATION_DONE
};
 
struct nand_flash_controller at91sam9_nand_controller = {
    .name = "at91sam9",
    .nand_device_command = at91sam9_nand_device_command,
    .commands = at91sam9_command_handler,
    .init = at91sam9_init,
    .command = at91sam9_command,
    .reset = at91sam9_reset,
    .address = at91sam9_address,
    .read_data = at91sam9_read_data,
    .write_data = at91sam9_write_data,
    .nand_ready = at91sam9_nand_ready,
    .read_block_data = at91sam9_read_block_data,
    .write_block_data = at91sam9_write_block_data,
    .read_page = at91sam9_read_page,
    .write_page = at91sam9_write_page,
};