OpenOCD
armv7a.h
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1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 
3 /***************************************************************************
4  * Copyright (C) 2009 by David Brownell *
5  ***************************************************************************/
6 
7 #ifndef OPENOCD_TARGET_ARMV7A_H
8 #define OPENOCD_TARGET_ARMV7A_H
9 
10 #include "arm_adi_v5.h"
11 #include "armv7a_cache.h"
12 #include "arm.h"
13 #include "armv4_5_mmu.h"
14 #include "armv4_5_cache.h"
15 #include "arm_dpm.h"
16 
17 enum {
18  ARM_PC = 15,
19  ARM_CPSR = 16
20 };
21 
22 #define ARMV7_COMMON_MAGIC 0x0A450999U
23 
24 /* VA to PA translation operations opc2 values*/
25 #define V2PCWPR 0
26 #define V2PCWPW 1
27 #define V2PCWUR 2
28 #define V2PCWUW 3
29 #define V2POWPR 4
30 #define V2POWPW 5
31 #define V2POWUR 6
32 #define V2POWUW 7
33 /* L210/L220 cache controller support */
35  uint32_t base;
36  uint32_t way;
37 };
38 
40  /* cache dimensioning */
41  uint32_t linelen;
42  uint32_t associativity;
43  uint32_t nsets;
44  uint32_t cachesize;
45  /* info for set way operation on cache */
46  uint32_t index;
47  uint32_t index_shift;
48  uint32_t way;
49  uint32_t way_shift;
50 };
51 
52 /* information about one architecture cache at any level */
54  int ctype; /* cache type, CLIDR encoding */
55  struct armv7a_cachesize d_u_size; /* data cache */
56  struct armv7a_cachesize i_size; /* instruction cache */
57 };
58 
59 /* common cache information */
61  int info; /* -1 invalid, else valid */
62  int loc; /* level of coherency */
63  uint32_t dminline; /* minimum d-cache linelen */
64  uint32_t iminline; /* minimum i-cache linelen */
65  struct armv7a_arch_cache arch[6]; /* cache info, L1 - L7 */
68  int auto_cache_enabled; /* openocd automatic
69  * cache handling */
70  /* outer unified cache if some */
71  void *outer_cache;
73 };
74 
76  /* following field mmu working way */
77  int32_t cached; /* 0: not initialized, 1: initialized */
78  uint32_t ttbcr; /* cache for ttbcr register */
79  uint32_t ttbr[2];
80  uint32_t ttbr_mask[2];
81  uint32_t ttbr_range[2];
82 
83  int (*read_physical_memory)(struct target *target, target_addr_t address, uint32_t size,
84  uint32_t count, uint8_t *buffer);
86  uint32_t mmu_enabled;
87 };
88 
89 struct armv7a_common {
90  unsigned int common_magic;
91 
92  struct arm arm;
94 
95  /* Core Debug Unit */
96  struct arm_dpm dpm;
98  struct adiv5_ap *debug_ap;
99  /* mdir */
102  uint8_t level2_id;
103  uint8_t cluster_id;
104  uint8_t cpu_id;
105  bool is_armv7r;
106  uint32_t rev;
107  uint32_t partnum;
108  uint32_t arch;
109  uint32_t variant;
110  uint32_t implementor;
111 
112  /* cache specific to V7 Memory Management Unit compatible with v4_5*/
114 
116  int (*post_debug_entry)(struct target *target);
117 
119 };
120 
121 static inline struct armv7a_common *
123 {
124  return container_of(target->arch_info, struct armv7a_common, arm);
125 }
126 
127 static inline bool is_armv7a(struct armv7a_common *armv7a)
128 {
129  return armv7a->common_magic == ARMV7_COMMON_MAGIC;
130 }
131 
132 
133 /* register offsets from armv7a.debug_base */
134 
135 /* See ARMv7a arch spec section C10.2 */
136 #define CPUDBG_DIDR 0x000
137 
138 /* See ARMv7a arch spec section C10.3 */
139 #define CPUDBG_WFAR 0x018
140 /* PCSR at 0x084 -or- 0x0a0 -or- both ... based on flags in DIDR */
141 #define CPUDBG_DSCR 0x088
142 #define CPUDBG_DRCR 0x090
143 #define CPUDBG_PRCR 0x310
144 #define CPUDBG_PRSR 0x314
145 
146 /* See ARMv7a arch spec section C10.4 */
147 #define CPUDBG_DTRRX 0x080
148 #define CPUDBG_ITR 0x084
149 #define CPUDBG_DTRTX 0x08c
150 
151 /* See ARMv7a arch spec section C10.5 */
152 #define CPUDBG_BVR_BASE 0x100
153 #define CPUDBG_BCR_BASE 0x140
154 #define CPUDBG_WVR_BASE 0x180
155 #define CPUDBG_WCR_BASE 0x1C0
156 #define CPUDBG_VCR 0x01C
157 
158 /* See ARMv7a arch spec section C10.6 */
159 #define CPUDBG_OSLAR 0x300
160 #define CPUDBG_OSLSR 0x304
161 #define CPUDBG_OSSRR 0x308
162 #define CPUDBG_ECR 0x024
163 
164 /* See ARMv7a arch spec section C10.7 */
165 #define CPUDBG_DSCCR 0x028
166 #define CPUDBG_DSMCR 0x02C
167 
168 /* See ARMv7a arch spec section C10.8 */
169 #define CPUDBG_AUTHSTATUS 0xFB8
170 
171 /* See ARMv7a arch spec DDI 0406C C11.10 */
172 #define CPUDBG_ID_PFR1 0xD24
173 
174 /* Masks for Vector Catch register */
175 #define DBG_VCR_FIQ_MASK ((1 << 31) | (1 << 7))
176 #define DBG_VCR_IRQ_MASK ((1 << 30) | (1 << 6))
177 #define DBG_VCR_DATA_ABORT_MASK ((1 << 28) | (1 << 4))
178 #define DBG_VCR_PREF_ABORT_MASK ((1 << 27) | (1 << 3))
179 #define DBG_VCR_SVC_MASK ((1 << 26) | (1 << 2))
180 
181 /* Masks for Multiprocessor Affinity Register */
182 #define MPIDR_MP_EXT (1UL << 31)
183 
184 int armv7a_arch_state(struct target *target);
185 int armv7a_identify_cache(struct target *target);
186 int armv7a_init_arch_info(struct target *target, struct armv7a_common *armv7a);
187 
189  struct armv7a_cache_common *armv7a_cache);
190 int armv7a_read_ttbcr(struct target *target);
191 
192 extern const struct command_registration armv7a_command_handlers[];
193 
194 #endif /* OPENOCD_TARGET_ARMV7A_H */
Holds the interface to ARM cores.
This defines formats and data structures used to talk to ADIv5 entities.
This is the interface to the Debug Programmers Model for ARMv6 and ARMv7 processors.
int armv7a_handle_cache_info_command(struct command_invocation *cmd, struct armv7a_cache_common *armv7a_cache)
Definition: armv7a.c:230
int armv7a_read_ttbcr(struct target *target)
Definition: armv7a.c:118
int armv7a_arch_state(struct target *target)
Definition: armv7a.c:532
#define ARMV7_COMMON_MAGIC
Definition: armv7a.h:22
const struct command_registration armv7a_command_handlers[]
Definition: armv7a.c:588
@ ARM_PC
Definition: armv7a.h:18
@ ARM_CPSR
Definition: armv7a.h:19
static struct armv7a_common * target_to_armv7a(struct target *target)
Definition: armv7a.h:122
int armv7a_init_arch_info(struct target *target, struct armv7a_common *armv7a)
Definition: armv7a.c:515
static bool is_armv7a(struct armv7a_common *armv7a)
Definition: armv7a.h:127
int armv7a_identify_cache(struct target *target)
Definition: armv7a.c:364
struct target * target
Definition: rtt/rtt.c:26
size_t size
Size of the control block search area.
Definition: rtt/rtt.c:30
This represents an ARM Debug Interface (v5) Access Port (AP).
Definition: arm_adi_v5.h:243
This wraps an implementation of DPM primitives.
Definition: arm_dpm.h:47
Represents a generic ARM core, with standard application registers.
Definition: arm.h:167
struct armv7a_cachesize i_size
Definition: armv7a.h:56
struct armv7a_cachesize d_u_size
Definition: armv7a.h:55
int(* flush_all_data_cache)(struct target *target)
Definition: armv7a.h:72
uint32_t dminline
Definition: armv7a.h:63
struct armv7a_arch_cache arch[6]
Definition: armv7a.h:65
uint32_t iminline
Definition: armv7a.h:64
void * outer_cache
Definition: armv7a.h:71
int auto_cache_enabled
Definition: armv7a.h:68
int d_u_cache_enabled
Definition: armv7a.h:67
uint32_t linelen
Definition: armv7a.h:41
uint32_t way
Definition: armv7a.h:48
uint32_t index
Definition: armv7a.h:46
uint32_t index_shift
Definition: armv7a.h:47
uint32_t way_shift
Definition: armv7a.h:49
uint32_t nsets
Definition: armv7a.h:43
uint32_t associativity
Definition: armv7a.h:42
uint32_t cachesize
Definition: armv7a.h:44
bool is_armv7r
Definition: armv7a.h:105
int(* post_debug_entry)(struct target *target)
Definition: armv7a.h:116
uint32_t arch
Definition: armv7a.h:108
uint8_t cpu_id
Definition: armv7a.h:104
uint8_t multi_threading_processor
Definition: armv7a.h:101
int(* examine_debug_reason)(struct target *target)
Definition: armv7a.h:115
uint8_t multi_processor_system
Definition: armv7a.h:100
uint8_t level2_id
Definition: armv7a.h:102
target_addr_t debug_base
Definition: armv7a.h:97
uint32_t rev
Definition: armv7a.h:106
uint32_t variant
Definition: armv7a.h:109
struct armv7a_mmu_common armv7a_mmu
Definition: armv7a.h:113
struct arm_dpm dpm
Definition: armv7a.h:96
struct adiv5_ap * debug_ap
Definition: armv7a.h:98
uint8_t cluster_id
Definition: armv7a.h:103
void(* pre_restore_context)(struct target *target)
Definition: armv7a.h:118
uint32_t partnum
Definition: armv7a.h:107
uint32_t implementor
Definition: armv7a.h:110
struct reg_cache * core_cache
Definition: armv7a.h:93
unsigned int common_magic
Definition: armv7a.h:90
uint32_t base
Definition: armv7a.h:35
uint32_t way
Definition: armv7a.h:36
uint32_t ttbr_range[2]
Definition: armv7a.h:81
struct armv7a_cache_common armv7a_cache
Definition: armv7a.h:85
int32_t cached
Definition: armv7a.h:77
int(* read_physical_memory)(struct target *target, target_addr_t address, uint32_t size, uint32_t count, uint8_t *buffer)
Definition: armv7a.h:83
uint32_t ttbr[2]
Definition: armv7a.h:79
uint32_t ttbr_mask[2]
Definition: armv7a.h:80
uint32_t ttbcr
Definition: armv7a.h:78
uint32_t mmu_enabled
Definition: armv7a.h:86
When run_command is called, a new instance will be created on the stack, filled with the proper value...
Definition: command.h:76
Definition: target.h:120
void * arch_info
Definition: target.h:169
uint64_t target_addr_t
Definition: types.h:335
#define container_of(ptr, type, member)
Cast a member of a structure out to the containing structure.
Definition: types.h:68
uint8_t cmd
Definition: vdebug.c:1
uint8_t count[4]
Definition: vdebug.c:22