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lpc3180.c
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1 // SPDX-License-Identifier: GPL-2.0-or-later
2 
3 /***************************************************************************
4  * Copyright (C) 2007 by Dominic Rath *
5  * Dominic.Rath@gmx.de *
6  *
7  * Copyright (C) 2010 richard vegh <vegh.ricsi@gmail.com> *
8  * Copyright (C) 2010 Oyvind Harboe <oyvind.harboe@zylin.com> *
9  ***************************************************************************/
10 
11 #ifdef HAVE_CONFIG_H
12 #include "config.h"
13 #endif
14 
15 #include "imp.h"
16 #include "lpc3180.h"
17 #include <target/target.h>
18 
19 static int lpc3180_reset(struct nand_device *nand);
20 static int lpc3180_controller_ready(struct nand_device *nand, int timeout);
21 static int lpc3180_tc_ready(struct nand_device *nand, int timeout);
22 
23 #define ECC_OFFS 0x120
24 #define SPARE_OFFS 0x140
25 #define DATA_OFFS 0x200
26 
27 /* nand device lpc3180 <target#> <oscillator_frequency>
28  */
29 NAND_DEVICE_COMMAND_HANDLER(lpc3180_nand_device_command)
30 {
31  if (CMD_ARGC < 3)
33 
34  uint32_t osc_freq;
35  COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], osc_freq);
36 
37  struct lpc3180_nand_controller *lpc3180_info;
38  lpc3180_info = malloc(sizeof(struct lpc3180_nand_controller));
39  nand->controller_priv = lpc3180_info;
40 
41  lpc3180_info->osc_freq = osc_freq;
42 
43  if ((lpc3180_info->osc_freq < 1000) || (lpc3180_info->osc_freq > 20000))
45  "LPC3180 oscillator frequency should be between 1000 and 20000 kHz, was %i",
46  lpc3180_info->osc_freq);
48  lpc3180_info->sw_write_protection = 0;
49  lpc3180_info->sw_wp_lower_bound = 0x0;
50  lpc3180_info->sw_wp_upper_bound = 0x0;
51 
52  return ERROR_OK;
53 }
54 
55 static int lpc3180_pll(int fclkin, uint32_t pll_ctrl)
56 {
57  int bypass = (pll_ctrl & 0x8000) >> 15;
58  int direct = (pll_ctrl & 0x4000) >> 14;
59  int feedback = (pll_ctrl & 0x2000) >> 13;
60  int p = (1 << ((pll_ctrl & 0x1800) >> 11) * 2);
61  int n = ((pll_ctrl & 0x0600) >> 9) + 1;
62  int m = ((pll_ctrl & 0x01fe) >> 1) + 1;
63  int lock = (pll_ctrl & 0x1);
64 
65  if (!lock)
66  LOG_WARNING("PLL is not locked");
67 
68  if (!bypass && direct) /* direct mode */
69  return (m * fclkin) / n;
70 
71  if (bypass && !direct) /* bypass mode */
72  return fclkin / (2 * p);
73 
74  if (bypass & direct) /* direct bypass mode */
75  return fclkin;
76 
77  if (feedback) /* integer mode */
78  return m * (fclkin / n);
79  else /* non-integer mode */
80  return (m / (2 * p)) * (fclkin / n);
81 }
82 
83 static float lpc3180_cycle_time(struct nand_device *nand)
84 {
85  struct lpc3180_nand_controller *lpc3180_info = nand->controller_priv;
86  struct target *target = nand->target;
87  uint32_t sysclk_ctrl, pwr_ctrl, hclkdiv_ctrl, hclkpll_ctrl;
88  int sysclk;
89  int hclk;
90  int hclk_pll;
91  float cycle;
92 
93  /* calculate timings */
94 
95  /* determine current SYSCLK (13'MHz or main oscillator) */
96  target_read_u32(target, 0x40004050, &sysclk_ctrl);
97 
98  if ((sysclk_ctrl & 1) == 0)
99  sysclk = lpc3180_info->osc_freq;
100  else
101  sysclk = 13000;
102 
103  /* determine selected HCLK source */
104  target_read_u32(target, 0x40004044, &pwr_ctrl);
105 
106  if ((pwr_ctrl & (1 << 2)) == 0) /* DIRECT RUN mode */
107  hclk = sysclk;
108  else {
109  target_read_u32(target, 0x40004058, &hclkpll_ctrl);
110  hclk_pll = lpc3180_pll(sysclk, hclkpll_ctrl);
111 
112  target_read_u32(target, 0x40004040, &hclkdiv_ctrl);
113 
114  if (pwr_ctrl & (1 << 10)) /* ARM_CLK and HCLK use PERIPH_CLK */
115  hclk = hclk_pll / (((hclkdiv_ctrl & 0x7c) >> 2) + 1);
116  else /* HCLK uses HCLK_PLL */
117  hclk = hclk_pll / (1 << (hclkdiv_ctrl & 0x3));
118  }
119 
120  LOG_DEBUG("LPC3180 HCLK currently clocked at %i kHz", hclk);
121 
122  cycle = (1.0 / hclk) * 1000000.0;
123 
124  return cycle;
125 }
126 
127 static int lpc3180_init(struct nand_device *nand)
128 {
129  struct lpc3180_nand_controller *lpc3180_info = nand->controller_priv;
130  struct target *target = nand->target;
131  int bus_width = nand->bus_width ? nand->bus_width : 8;
132  int address_cycles = nand->address_cycles ? nand->address_cycles : 3;
133  int page_size = nand->page_size ? nand->page_size : 512;
134 
135  if (target->state != TARGET_HALTED) {
136  LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
138  }
139 
140  /* sanitize arguments */
141  if ((bus_width != 8) && (bus_width != 16)) {
142  LOG_ERROR("LPC3180 only supports 8 or 16 bit bus width, not %i", bus_width);
144  }
145 
146  /* The LPC3180 only brings out 8 bit NAND data bus, but the controller
147  * would support 16 bit, too, so we just warn about this for now
148  */
149  if (bus_width == 16)
150  LOG_WARNING("LPC3180 only supports 8 bit bus width");
151 
152  /* inform calling code about selected bus width */
153  nand->bus_width = bus_width;
154 
155  if ((address_cycles != 3) && (address_cycles != 4)) {
156  LOG_ERROR("LPC3180 only supports 3 or 4 address cycles, not %i", address_cycles);
158  }
159 
160  if ((page_size != 512) && (page_size != 2048)) {
161  LOG_ERROR("LPC3180 only supports 512 or 2048 byte pages, not %i", page_size);
163  }
164 
165  /* select MLC controller if none is currently selected */
166  if (lpc3180_info->selected_controller == LPC3180_NO_CONTROLLER) {
167  LOG_DEBUG("no LPC3180 NAND flash controller selected, using default 'mlc'");
169  }
170 
171  if (lpc3180_info->selected_controller == LPC3180_MLC_CONTROLLER) {
172  uint32_t mlc_icr_value = 0x0;
173  float cycle;
174  int twp, twh, trp, treh, trhz, trbwb, tcea;
175 
176  /* FLASHCLK_CTRL = 0x22 (enable clock for MLC flash controller) */
177  target_write_u32(target, 0x400040c8, 0x22);
178 
179  /* MLC_CEH = 0x0 (Force nCE assert) */
180  target_write_u32(target, 0x200b804c, 0x0);
181 
182  /* MLC_LOCK = 0xa25e (unlock protected registers) */
183  target_write_u32(target, 0x200b8044, 0xa25e);
184 
185  /* MLC_ICR = configuration */
186  if (lpc3180_info->sw_write_protection)
187  mlc_icr_value |= 0x8;
188  if (page_size == 2048)
189  mlc_icr_value |= 0x4;
190  if (address_cycles == 4)
191  mlc_icr_value |= 0x2;
192  if (bus_width == 16)
193  mlc_icr_value |= 0x1;
194  target_write_u32(target, 0x200b8030, mlc_icr_value);
195 
196  /* calculate NAND controller timings */
197  cycle = lpc3180_cycle_time(nand);
198 
199  twp = ((40 / cycle) + 1);
200  twh = ((20 / cycle) + 1);
201  trp = ((30 / cycle) + 1);
202  treh = ((15 / cycle) + 1);
203  trhz = ((30 / cycle) + 1);
204  trbwb = ((100 / cycle) + 1);
205  tcea = ((45 / cycle) + 1);
206 
207  /* MLC_LOCK = 0xa25e (unlock protected registers) */
208  target_write_u32(target, 0x200b8044, 0xa25e);
209 
210  /* MLC_TIME_REG */
211  target_write_u32(target, 0x200b8034, (twp & 0xf) | ((twh & 0xf) << 4) |
212  ((trp & 0xf) << 8) | ((treh & 0xf) << 12) | ((trhz & 0x7) << 16) |
213  ((trbwb & 0x1f) << 19) | ((tcea & 0x3) << 24));
214 
215  lpc3180_reset(nand);
216  } else if (lpc3180_info->selected_controller == LPC3180_SLC_CONTROLLER) {
217  float cycle;
218  int r_setup, r_hold, r_width, r_rdy;
219  int w_setup, w_hold, w_width, w_rdy;
220 
221  /* FLASHCLK_CTRL = 0x05 (enable clock for SLC flash controller) */
222  target_write_u32(target, 0x400040c8, 0x05);
223 
224  /* after reset set other registers of SLC so reset calling is here at the beginning */
225  lpc3180_reset(nand);
226 
227  /* SLC_CFG = 0x (Force nCE assert, DMA ECC enabled, ECC enabled, DMA burst enabled,
228  *DMA read from SLC, WIDTH = bus_width) */
229  target_write_u32(target, 0x20020014, 0x3e | ((bus_width == 16) ? 1 : 0));
230 
231  /* SLC_IEN = 3 (INT_RDY_EN = 1) ,(INT_TC_STAT = 1) */
232  target_write_u32(target, 0x20020020, 0x03);
233 
234  /* DMA configuration
235  * DMACLK_CTRL = 0x01 (enable clock for DMA controller) */
236  target_write_u32(target, 0x400040e8, 0x01);
237  /* DMACConfig = DMA enabled*/
238  target_write_u32(target, 0x31000030, 0x01);
239 
240 
241  /* calculate NAND controller timings */
242  cycle = lpc3180_cycle_time(nand);
243 
244  r_setup = w_setup = 0;
245  r_hold = w_hold = 10 / cycle;
246  r_width = 30 / cycle;
247  w_width = 40 / cycle;
248  r_rdy = w_rdy = 100 / cycle;
249 
250  /* SLC_TAC: SLC timing arcs register */
251  target_write_u32(target, 0x2002002c, (r_setup & 0xf) | ((r_hold & 0xf) << 4) |
252  ((r_width & 0xf) << 8) | ((r_rdy & 0xf) << 12) | ((w_setup & 0xf) << 16) |
253  ((w_hold & 0xf) << 20) | ((w_width & 0xf) << 24) | ((w_rdy & 0xf) << 28));
254 
255  }
256 
257  return ERROR_OK;
258 }
259 
260 static int lpc3180_reset(struct nand_device *nand)
261 {
262  struct lpc3180_nand_controller *lpc3180_info = nand->controller_priv;
263  struct target *target = nand->target;
264 
265  if (target->state != TARGET_HALTED) {
266  LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
268  }
269 
270  if (lpc3180_info->selected_controller == LPC3180_NO_CONTROLLER) {
271  LOG_ERROR("BUG: no LPC3180 NAND flash controller selected");
273  } else if (lpc3180_info->selected_controller == LPC3180_MLC_CONTROLLER) {
274  /* MLC_CMD = 0xff (reset controller and NAND device) */
275  target_write_u32(target, 0x200b8000, 0xff);
276 
277  if (!lpc3180_controller_ready(nand, 100)) {
278  LOG_ERROR("LPC3180 NAND controller timed out after reset");
280  }
281  } else if (lpc3180_info->selected_controller == LPC3180_SLC_CONTROLLER) {
282  /* SLC_CTRL = 0x6 (ECC_CLEAR, SW_RESET) */
283  target_write_u32(target, 0x20020010, 0x6);
284 
285  if (!lpc3180_controller_ready(nand, 100)) {
286  LOG_ERROR("LPC3180 NAND controller timed out after reset");
288  }
289  }
290 
291  return ERROR_OK;
292 }
293 
294 static int lpc3180_command(struct nand_device *nand, uint8_t command)
295 {
296  struct lpc3180_nand_controller *lpc3180_info = nand->controller_priv;
297  struct target *target = nand->target;
298 
299  if (target->state != TARGET_HALTED) {
300  LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
302  }
303 
304  if (lpc3180_info->selected_controller == LPC3180_NO_CONTROLLER) {
305  LOG_ERROR("BUG: no LPC3180 NAND flash controller selected");
307  } else if (lpc3180_info->selected_controller == LPC3180_MLC_CONTROLLER) {
308  /* MLC_CMD = command */
309  target_write_u32(target, 0x200b8000, command);
310  } else if (lpc3180_info->selected_controller == LPC3180_SLC_CONTROLLER) {
311  /* SLC_CMD = command */
312  target_write_u32(target, 0x20020008, command);
313  }
314 
315  return ERROR_OK;
316 }
317 
318 static int lpc3180_address(struct nand_device *nand, uint8_t address)
319 {
320  struct lpc3180_nand_controller *lpc3180_info = nand->controller_priv;
321  struct target *target = nand->target;
322 
323  if (target->state != TARGET_HALTED) {
324  LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
326  }
327 
328  if (lpc3180_info->selected_controller == LPC3180_NO_CONTROLLER) {
329  LOG_ERROR("BUG: no LPC3180 NAND flash controller selected");
331  } else if (lpc3180_info->selected_controller == LPC3180_MLC_CONTROLLER) {
332  /* MLC_ADDR = address */
333  target_write_u32(target, 0x200b8004, address);
334  } else if (lpc3180_info->selected_controller == LPC3180_SLC_CONTROLLER) {
335  /* SLC_ADDR = address */
336  target_write_u32(target, 0x20020004, address);
337  }
338 
339  return ERROR_OK;
340 }
341 
342 static int lpc3180_write_data(struct nand_device *nand, uint16_t data)
343 {
344  struct lpc3180_nand_controller *lpc3180_info = nand->controller_priv;
345  struct target *target = nand->target;
346 
347  if (target->state != TARGET_HALTED) {
348  LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
350  }
351 
352  if (lpc3180_info->selected_controller == LPC3180_NO_CONTROLLER) {
353  LOG_ERROR("BUG: no LPC3180 NAND flash controller selected");
355  } else if (lpc3180_info->selected_controller == LPC3180_MLC_CONTROLLER) {
356  /* MLC_DATA = data */
357  target_write_u32(target, 0x200b0000, data);
358  } else if (lpc3180_info->selected_controller == LPC3180_SLC_CONTROLLER) {
359  /* SLC_DATA = data */
360  target_write_u32(target, 0x20020000, data);
361  }
362 
363  return ERROR_OK;
364 }
365 
366 static int lpc3180_read_data(struct nand_device *nand, void *data)
367 {
368  struct lpc3180_nand_controller *lpc3180_info = nand->controller_priv;
369  struct target *target = nand->target;
370 
371  if (target->state != TARGET_HALTED) {
372  LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
374  }
375 
376  if (lpc3180_info->selected_controller == LPC3180_NO_CONTROLLER) {
377  LOG_ERROR("BUG: no LPC3180 NAND flash controller selected");
379  } else if (lpc3180_info->selected_controller == LPC3180_MLC_CONTROLLER) {
380  /* data = MLC_DATA, use sized access */
381  if (nand->bus_width == 8) {
382  uint8_t *data8 = data;
383  target_read_u8(target, 0x200b0000, data8);
384  } else if (nand->bus_width == 16) {
385  uint16_t *data16 = data;
386  target_read_u16(target, 0x200b0000, data16);
387  } else {
388  LOG_ERROR("BUG: bus_width neither 8 nor 16 bit");
390  }
391  } else if (lpc3180_info->selected_controller == LPC3180_SLC_CONTROLLER) {
392  uint32_t data32;
393 
394  /* data = SLC_DATA, must use 32-bit access */
395  target_read_u32(target, 0x20020000, &data32);
396 
397  if (nand->bus_width == 8) {
398  uint8_t *data8 = data;
399  *data8 = data32 & 0xff;
400  } else if (nand->bus_width == 16) {
401  uint16_t *data16 = data;
402  *data16 = data32 & 0xffff;
403  } else {
404  LOG_ERROR("BUG: bus_width neither 8 nor 16 bit");
406  }
407  }
408 
409  return ERROR_OK;
410 }
411 
412 static int lpc3180_write_page(struct nand_device *nand,
413  uint32_t page,
414  uint8_t *data,
415  uint32_t data_size,
416  uint8_t *oob,
417  uint32_t oob_size)
418 {
419  struct lpc3180_nand_controller *lpc3180_info = nand->controller_priv;
420  struct target *target = nand->target;
421  int retval;
422  uint8_t status;
423  uint8_t *page_buffer;
424 
425  if (target->state != TARGET_HALTED) {
426  LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
428  }
429 
430  if (lpc3180_info->selected_controller == LPC3180_NO_CONTROLLER) {
431  LOG_ERROR("BUG: no LPC3180 NAND flash controller selected");
433  } else if (lpc3180_info->selected_controller == LPC3180_MLC_CONTROLLER) {
434  uint8_t *oob_buffer;
435  int quarter, num_quarters;
436 
437  if (!data && oob) {
438  LOG_ERROR("LPC3180 MLC controller can't write OOB data only");
440  }
441 
442  if (oob && (oob_size > 24)) {
443  LOG_ERROR("LPC3180 MLC controller can't write more "
444  "than 6 bytes for each quarter's OOB data");
446  }
447 
448  if (data_size > (uint32_t)nand->page_size) {
449  LOG_ERROR("data size exceeds page size");
451  }
452 
453  /* MLC_CMD = sequential input */
454  target_write_u32(target, 0x200b8000, NAND_CMD_SEQIN);
455 
456  page_buffer = malloc(512);
457  oob_buffer = malloc(6);
458 
459  if (nand->page_size == 512) {
460  /* MLC_ADDR = 0x0 (one column cycle) */
461  target_write_u32(target, 0x200b8004, 0x0);
462 
463  /* MLC_ADDR = row */
464  target_write_u32(target, 0x200b8004, page & 0xff);
465  target_write_u32(target, 0x200b8004, (page >> 8) & 0xff);
466 
467  if (nand->address_cycles == 4)
468  target_write_u32(target, 0x200b8004, (page >> 16) & 0xff);
469  } else {
470  /* MLC_ADDR = 0x0 (two column cycles) */
471  target_write_u32(target, 0x200b8004, 0x0);
472  target_write_u32(target, 0x200b8004, 0x0);
473 
474  /* MLC_ADDR = row */
475  target_write_u32(target, 0x200b8004, page & 0xff);
476  target_write_u32(target, 0x200b8004, (page >> 8) & 0xff);
477  }
478 
479  /* when using the MLC controller, we have to treat a large page device
480  * as being made out of four quarters, each the size of a small page device
481  */
482  num_quarters = (nand->page_size == 2048) ? 4 : 1;
483 
484  for (quarter = 0; quarter < num_quarters; quarter++) {
485  int thisrun_data_size = (data_size > 512) ? 512 : data_size;
486  int thisrun_oob_size = (oob_size > 6) ? 6 : oob_size;
487 
488  memset(page_buffer, 0xff, 512);
489  if (data) {
490  memcpy(page_buffer, data, thisrun_data_size);
491  data_size -= thisrun_data_size;
492  data += thisrun_data_size;
493  }
494 
495  memset(oob_buffer, 0xff, 6);
496  if (oob) {
497  memcpy(oob_buffer, oob, thisrun_oob_size);
498  oob_size -= thisrun_oob_size;
499  oob += thisrun_oob_size;
500  }
501 
502  /* write MLC_ECC_ENC_REG to start encode cycle */
503  target_write_u32(target, 0x200b8008, 0x0);
504 
505  target_write_memory(target, 0x200a8000,
506  4, 128, page_buffer);
507  target_write_memory(target, 0x200a8000,
508  1, 6, oob_buffer);
509 
510  /* write MLC_ECC_AUTO_ENC_REG to start auto encode */
511  target_write_u32(target, 0x200b8010, 0x0);
512 
513  if (!lpc3180_controller_ready(nand, 1000)) {
514  LOG_ERROR("timeout while waiting for completion of auto encode cycle");
515  free(page_buffer);
516  free(oob_buffer);
518  }
519  }
520 
521  /* MLC_CMD = auto program command */
523 
524  retval = nand_read_status(nand, &status);
525  if (retval != ERROR_OK) {
526  LOG_ERROR("couldn't read status");
527  free(page_buffer);
528  free(oob_buffer);
530  }
531 
532  if (status & NAND_STATUS_FAIL) {
533  LOG_ERROR("write operation didn't pass, status: 0x%2.2x", status);
534  free(page_buffer);
535  free(oob_buffer);
537  }
538 
539  free(page_buffer);
540  free(oob_buffer);
541  } else if (lpc3180_info->selected_controller == LPC3180_SLC_CONTROLLER) {
542 
543  /**********************************************************************
544  * Write both SLC NAND flash page main area and spare area.
545  * Small page -
546  * ------------------------------------------
547  * | 512 bytes main | 16 bytes spare |
548  * ------------------------------------------
549  * Large page -
550  * ------------------------------------------
551  * | 2048 bytes main | 64 bytes spare |
552  * ------------------------------------------
553  * If DMA & ECC enabled, then the ECC generated for the 1st 256-byte
554  * data is written to the 3rd word of the spare area. The ECC
555  * generated for the 2nd 256-byte data is written to the 4th word
556  * of the spare area. The ECC generated for the 3rd 256-byte data is
557  * written to the 7th word of the spare area. The ECC generated
558  * for the 4th 256-byte data is written to the 8th word of the
559  * spare area and so on.
560  *
561  **********************************************************************/
562 
563  int i = 0, target_mem_base;
564  uint8_t *ecc_flash_buffer;
565  struct working_area *pworking_area;
566 
567  if (lpc3180_info->is_bulk) {
568 
569  if (!data && oob) {
570  /*if oob only mode is active original method is used as SLC
571  *controller hangs during DMA interworking. Anyway the code supports
572  *the oob only mode below. */
573  return nand_write_page_raw(nand,
574  page,
575  data,
576  data_size,
577  oob,
578  oob_size);
579  }
580  retval = nand_page_command(nand, page, NAND_CMD_SEQIN, !data);
581  if (retval != ERROR_OK)
582  return retval;
583 
584  /* allocate a working area */
585  if (target->working_area_size < (uint32_t) nand->page_size + 0x200) {
586  LOG_ERROR("Reserve at least 0x%x physical target working area",
587  nand->page_size + 0x200);
589  }
590  if (target->working_area_phys%4) {
591  LOG_ERROR(
592  "Reserve the physical target working area at word boundary");
594  }
596  &pworking_area) != ERROR_OK) {
597  LOG_ERROR("no working area specified, can't read LPC internal flash");
599  }
600  target_mem_base = target->working_area_phys;
601 
602  if (nand->page_size == 2048)
603  page_buffer = malloc(2048);
604  else
605  page_buffer = malloc(512);
606 
607  ecc_flash_buffer = malloc(64);
608 
609  /* SLC_CFG = 0x (Force nCE assert, DMA ECC enabled, ECC enabled, DMA burst
610  *enabled, DMA write to SLC, WIDTH = bus_width) */
611  target_write_u32(target, 0x20020014, 0x3c);
612 
613  if (data && !oob) {
614  /* set DMA LLI-s in target memory and in DMA*/
615  for (i = 0; i < nand->page_size/0x100; i++) {
616 
617  int tmp;
618  /* -------LLI for 256 byte block---------
619  * DMACC0SrcAddr = SRAM */
621  target_mem_base+0+i*32,
622  target_mem_base+DATA_OFFS+i*256);
623  if (i == 0)
625  0x31000100,
626  target_mem_base+DATA_OFFS);
627  /* DMACCxDestAddr = SLC_DMA_DATA */
628  target_write_u32(target, target_mem_base+4+i*32, 0x20020038);
629  if (i == 0)
630  target_write_u32(target, 0x31000104, 0x20020038);
631  /* DMACCxLLI = next element */
632  tmp = (target_mem_base+(1+i*2)*16)&0xfffffffc;
633  target_write_u32(target, target_mem_base+8+i*32, tmp);
634  if (i == 0)
635  target_write_u32(target, 0x31000108, tmp);
636  /* DMACCxControl = TransferSize =64, Source burst size =16,
637  * Destination burst size = 16, Source transfer width = 32 bit,
638  * Destination transfer width = 32 bit, Source AHB master select = M0,
639  * Destination AHB master select = M0, Source increment = 1,
640  * Destination increment = 0, Terminal count interrupt enable bit = 0*/
642  target_mem_base+12+i*32,
643  0x40 | 3<<12 | 3<<15 | 2<<18 | 2<<21 | 0<<24 | 0<<25 | 1<<26 |
644  0<<27 | 0<<31);
645  if (i == 0)
647  0x3100010c,
648  0x40 | 3<<12 | 3<<15 | 2<<18 | 2<<21 | 0<<24 | 0<<25 | 1<<26 |
649  0<<27 | 0<<31);
650 
651  /* -------LLI for 3 byte ECC---------
652  * DMACC0SrcAddr = SLC_ECC*/
653  target_write_u32(target, target_mem_base+16+i*32, 0x20020034);
654  /* DMACCxDestAddr = SRAM */
656  target_mem_base+20+i*32,
657  target_mem_base+SPARE_OFFS+8+16*(i>>1)+(i%2)*4);
658  /* DMACCxLLI = next element */
659  tmp = (target_mem_base+(2+i*2)*16)&0xfffffffc;
660  target_write_u32(target, target_mem_base+24+i*32, tmp);
661  /* DMACCxControl = TransferSize =1, Source burst size =4,
662  * Destination burst size = 4, Source transfer width = 32 bit,
663  * Destination transfer width = 32 bit, Source AHB master select = M0,
664  * Destination AHB master select = M0, Source increment = 0,
665  * Destination increment = 1, Terminal count interrupt enable bit = 0*/
667  target_mem_base+28+i*32,
668  0x01 | 1<<12 | 1<<15 | 2<<18 | 2<<21 | 0<<24 | 0<<25 | 0<<26 | 1<<27 | 0<<
669  31);
670  }
671  } else if (data && oob) {
672  /* -------LLI for 512 or 2048 bytes page---------
673  * DMACC0SrcAddr = SRAM */
674  target_write_u32(target, target_mem_base, target_mem_base+DATA_OFFS);
675  target_write_u32(target, 0x31000100, target_mem_base+DATA_OFFS);
676  /* DMACCxDestAddr = SLC_DMA_DATA */
677  target_write_u32(target, target_mem_base+4, 0x20020038);
678  target_write_u32(target, 0x31000104, 0x20020038);
679  /* DMACCxLLI = next element */
681  target_mem_base+8,
682  (target_mem_base+32)&0xfffffffc);
683  target_write_u32(target, 0x31000108,
684  (target_mem_base+32)&0xfffffffc);
685  /* DMACCxControl = TransferSize =512 or 128, Source burst size =16,
686  * Destination burst size = 16, Source transfer width = 32 bit,
687  * Destination transfer width = 32 bit, Source AHB master select = M0,
688  * Destination AHB master select = M0, Source increment = 1,
689  * Destination increment = 0, Terminal count interrupt enable bit = 0*/
691  target_mem_base+12,
692  (nand->page_size ==
693  2048 ? 512 : 128) | 3<<12 | 3<<15 | 2<<18 | 2<<21 | 0<<24 | 0<<25 |
694  1<<26 | 0<<27 | 0<<31);
696  0x3100010c,
697  (nand->page_size ==
698  2048 ? 512 : 128) | 3<<12 | 3<<15 | 2<<18 | 2<<21 | 0<<24 | 0<<25 |
699  1<<26 | 0<<27 | 0<<31);
700  i = 1;
701  } else if (!data && oob)
702  i = 0;
703 
704  /* -------LLI for spare area---------
705  * DMACC0SrcAddr = SRAM*/
706  target_write_u32(target, target_mem_base+0+i*32, target_mem_base+SPARE_OFFS);
707  if (i == 0)
708  target_write_u32(target, 0x31000100, target_mem_base+SPARE_OFFS);
709  /* DMACCxDestAddr = SLC_DMA_DATA */
710  target_write_u32(target, target_mem_base+4+i*32, 0x20020038);
711  if (i == 0)
712  target_write_u32(target, 0x31000104, 0x20020038);
713  /* DMACCxLLI = next element = NULL */
714  target_write_u32(target, target_mem_base+8+i*32, 0);
715  if (i == 0)
716  target_write_u32(target, 0x31000108, 0);
717  /* DMACCxControl = TransferSize =16 for large page or 4 for small page,
718  * Source burst size =16, Destination burst size = 16, Source transfer width = 32 bit,
719  * Destination transfer width = 32 bit, Source AHB master select = M0,
720  * Destination AHB master select = M0, Source increment = 1,
721  * Destination increment = 0, Terminal count interrupt enable bit = 0*/
723  target_mem_base+12+i*32,
724  (nand->page_size ==
725  2048 ? 0x10 : 0x04) | 3<<12 | 3<<15 | 2<<18 | 2<<21 | 0<<24 | 0<<25 | 1<<26 |
726  0<<27 | 0<<31);
727  if (i == 0)
728  target_write_u32(target, 0x3100010c,
729  (nand->page_size == 2048 ?
730  0x10 : 0x04) | 3<<12 | 3<<15 | 2<<18 | 2<<21 | 0<<24 |
731  0<<25 | 1<<26 | 0<<27 | 0<<31);
732 
733  memset(ecc_flash_buffer, 0xff, 64);
734  if (oob)
735  memcpy(ecc_flash_buffer, oob, oob_size);
737  target_mem_base+SPARE_OFFS,
738  4,
739  16,
740  ecc_flash_buffer);
741 
742  if (data) {
743  memset(page_buffer, 0xff, nand->page_size == 2048 ? 2048 : 512);
744  memcpy(page_buffer, data, data_size);
746  target_mem_base+DATA_OFFS,
747  4,
748  nand->page_size == 2048 ? 512 : 128,
749  page_buffer);
750  }
751 
752  free(page_buffer);
753  free(ecc_flash_buffer);
754 
755  /* Enable DMA after channel set up !
756  LLI only works when DMA is the flow controller!
757  */
758  /* DMACCxConfig= E=1, SrcPeripheral = 1 (SLC), DestPeripheral = 1 (SLC),
759  *FlowCntrl = 2 (Pher -> Mem, DMA), IE = 0, ITC = 0, L= 0, H=0*/
761  0x31000110,
762  1 | 1<<1 | 1<<6 | 2<<11 | 0<<14 | 0<<15 | 0<<16 | 0<<18);
763 
764  /* SLC_CTRL = 3 (START DMA), ECC_CLEAR */
765  target_write_u32(target, 0x20020010, 0x3);
766 
767  /* SLC_ICR = 2, INT_TC_CLR, clear pending TC*/
768  target_write_u32(target, 0x20020028, 2);
769 
770  /* SLC_TC */
771  if (!data && oob)
772  target_write_u32(target, 0x20020030,
773  (nand->page_size == 2048 ? 0x10 : 0x04));
774  else
775  target_write_u32(target, 0x20020030,
776  (nand->page_size == 2048 ? 0x840 : 0x210));
777 
778  nand_write_finish(nand);
779 
780  if (!lpc3180_tc_ready(nand, 1000)) {
781  LOG_ERROR("timeout while waiting for completion of DMA");
783  }
784 
785  target_free_working_area(target, pworking_area);
786 
787  LOG_INFO("Page = 0x%" PRIx32 " was written.", page);
788 
789  } else
790  return nand_write_page_raw(nand, page, data, data_size, oob, oob_size);
791  }
792 
793  return ERROR_OK;
794 }
795 
796 static int lpc3180_read_page(struct nand_device *nand,
797  uint32_t page,
798  uint8_t *data,
799  uint32_t data_size,
800  uint8_t *oob,
801  uint32_t oob_size)
802 {
803  struct lpc3180_nand_controller *lpc3180_info = nand->controller_priv;
804  struct target *target = nand->target;
805  uint8_t *page_buffer;
806 
807  if (target->state != TARGET_HALTED) {
808  LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
810  }
811 
812  if (lpc3180_info->selected_controller == LPC3180_NO_CONTROLLER) {
813  LOG_ERROR("BUG: no LPC3180 NAND flash controller selected");
815  } else if (lpc3180_info->selected_controller == LPC3180_MLC_CONTROLLER) {
816  uint8_t *oob_buffer;
817  uint32_t page_bytes_done = 0;
818  uint32_t oob_bytes_done = 0;
819  uint32_t mlc_isr;
820 
821 #if 0
822  if (oob && (oob_size > 6)) {
823  LOG_ERROR("LPC3180 MLC controller can't read more than 6 bytes of OOB data");
825  }
826 #endif
827 
828  if (data_size > (uint32_t)nand->page_size) {
829  LOG_ERROR("data size exceeds page size");
831  }
832 
833  if (nand->page_size == 2048) {
834  page_buffer = malloc(2048);
835  oob_buffer = malloc(64);
836  } else {
837  page_buffer = malloc(512);
838  oob_buffer = malloc(16);
839  }
840 
841  if (!data && oob) {
842  /* MLC_CMD = Read OOB
843  * we can use the READOOB command on both small and large page devices,
844  * as the controller translates the 0x50 command to a 0x0 with appropriate
845  * positioning of the serial buffer read pointer
846  */
848  } else {
849  /* MLC_CMD = Read0 */
850  target_write_u32(target, 0x200b8000, NAND_CMD_READ0);
851  }
852 
853  if (nand->page_size == 512) {
854  /* small page device
855  * MLC_ADDR = 0x0 (one column cycle) */
856  target_write_u32(target, 0x200b8004, 0x0);
857 
858  /* MLC_ADDR = row */
859  target_write_u32(target, 0x200b8004, page & 0xff);
860  target_write_u32(target, 0x200b8004, (page >> 8) & 0xff);
861 
862  if (nand->address_cycles == 4)
863  target_write_u32(target, 0x200b8004, (page >> 16) & 0xff);
864  } else {
865  /* large page device
866  * MLC_ADDR = 0x0 (two column cycles) */
867  target_write_u32(target, 0x200b8004, 0x0);
868  target_write_u32(target, 0x200b8004, 0x0);
869 
870  /* MLC_ADDR = row */
871  target_write_u32(target, 0x200b8004, page & 0xff);
872  target_write_u32(target, 0x200b8004, (page >> 8) & 0xff);
873 
874  /* MLC_CMD = Read Start */
876  }
877 
878  while (page_bytes_done < (uint32_t)nand->page_size) {
879  /* MLC_ECC_AUTO_DEC_REG = dummy */
880  target_write_u32(target, 0x200b8014, 0xaa55aa55);
881 
882  if (!lpc3180_controller_ready(nand, 1000)) {
883  LOG_ERROR("timeout while waiting for completion of auto decode cycle");
884  free(page_buffer);
885  free(oob_buffer);
887  }
888 
889  target_read_u32(target, 0x200b8048, &mlc_isr);
890 
891  if (mlc_isr & 0x8) {
892  if (mlc_isr & 0x40) {
893  LOG_ERROR("uncorrectable error detected: 0x%2.2" PRIx32, mlc_isr);
894  free(page_buffer);
895  free(oob_buffer);
897  }
898 
899  LOG_WARNING("%i symbol error detected and corrected",
900  ((int)(((mlc_isr & 0x30) >> 4) + 1)));
901  }
902 
903  if (data)
905  0x200a8000,
906  4,
907  128,
908  page_buffer + page_bytes_done);
909 
910  if (oob)
912  0x200a8000,
913  4,
914  4,
915  oob_buffer + oob_bytes_done);
916 
917  page_bytes_done += 512;
918  oob_bytes_done += 16;
919  }
920 
921  if (data)
922  memcpy(data, page_buffer, data_size);
923 
924  if (oob)
925  memcpy(oob, oob_buffer, oob_size);
926 
927  free(page_buffer);
928  free(oob_buffer);
929  } else if (lpc3180_info->selected_controller == LPC3180_SLC_CONTROLLER) {
930 
931  /**********************************************************************
932  * Read both SLC NAND flash page main area and spare area.
933  * Small page -
934  * ------------------------------------------
935  * | 512 bytes main | 16 bytes spare |
936  * ------------------------------------------
937  * Large page -
938  * ------------------------------------------
939  * | 2048 bytes main | 64 bytes spare |
940  * ------------------------------------------
941  * If DMA & ECC enabled, then the ECC generated for the 1st 256-byte
942  * data is compared with the 3rd word of the spare area. The ECC
943  * generated for the 2nd 256-byte data is compared with the 4th word
944  * of the spare area. The ECC generated for the 3rd 256-byte data is
945  * compared with the 7th word of the spare area. The ECC generated
946  * for the 4th 256-byte data is compared with the 8th word of the
947  * spare area and so on.
948  *
949  **********************************************************************/
950 
951  int retval, i, target_mem_base;
952  uint8_t *ecc_hw_buffer;
953  uint8_t *ecc_flash_buffer;
954  struct working_area *pworking_area;
955 
956  if (lpc3180_info->is_bulk) {
957 
958  /* read always the data and also oob areas*/
959 
960  retval = nand_page_command(nand, page, NAND_CMD_READ0, 0);
961  if (retval != ERROR_OK)
962  return retval;
963 
964  /* allocate a working area */
965  if (target->working_area_size < (uint32_t) nand->page_size + 0x200) {
966  LOG_ERROR("Reserve at least 0x%x physical target working area",
967  nand->page_size + 0x200);
969  }
970  if (target->working_area_phys%4) {
971  LOG_ERROR(
972  "Reserve the physical target working area at word boundary");
974  }
976  &pworking_area) != ERROR_OK) {
977  LOG_ERROR("no working area specified, can't read LPC internal flash");
979  }
980  target_mem_base = target->working_area_phys;
981 
982  if (nand->page_size == 2048)
983  page_buffer = malloc(2048);
984  else
985  page_buffer = malloc(512);
986 
987  ecc_hw_buffer = malloc(32);
988  ecc_flash_buffer = malloc(64);
989 
990  /* SLC_CFG = 0x (Force nCE assert, DMA ECC enabled, ECC enabled, DMA burst
991  *enabled, DMA read from SLC, WIDTH = bus_width) */
992  target_write_u32(target, 0x20020014, 0x3e);
993 
994  /* set DMA LLI-s in target memory and in DMA*/
995  for (i = 0; i < nand->page_size/0x100; i++) {
996  int tmp;
997  /* -------LLI for 256 byte block---------
998  * DMACC0SrcAddr = SLC_DMA_DATA*/
999  target_write_u32(target, target_mem_base+0+i*32, 0x20020038);
1000  if (i == 0)
1001  target_write_u32(target, 0x31000100, 0x20020038);
1002  /* DMACCxDestAddr = SRAM */
1004  target_mem_base+4+i*32,
1005  target_mem_base+DATA_OFFS+i*256);
1006  if (i == 0)
1008  0x31000104,
1009  target_mem_base+DATA_OFFS);
1010  /* DMACCxLLI = next element */
1011  tmp = (target_mem_base+(1+i*2)*16)&0xfffffffc;
1012  target_write_u32(target, target_mem_base+8+i*32, tmp);
1013  if (i == 0)
1014  target_write_u32(target, 0x31000108, tmp);
1015  /* DMACCxControl = TransferSize =64, Source burst size =16,
1016  * Destination burst size = 16, Source transfer width = 32 bit,
1017  * Destination transfer width = 32 bit, Source AHB master select = M0,
1018  * Destination AHB master select = M0, Source increment = 0,
1019  * Destination increment = 1, Terminal count interrupt enable bit = 0*/
1021  target_mem_base+12+i*32,
1022  0x40 | 3<<12 | 3<<15 | 2<<18 | 2<<21 | 0<<24 | 0<<25 | 0<<26 | 1<<27 | 0<<
1023  31);
1024  if (i == 0)
1026  0x3100010c,
1027  0x40 | 3<<12 | 3<<15 | 2<<18 | 2<<21 | 0<<24 | 0<<25 | 0<<26 | 1<<27 | 0<<
1028  31);
1029 
1030  /* -------LLI for 3 byte ECC---------
1031  * DMACC0SrcAddr = SLC_ECC*/
1032  target_write_u32(target, target_mem_base+16+i*32, 0x20020034);
1033  /* DMACCxDestAddr = SRAM */
1035  target_mem_base+20+i*32,
1036  target_mem_base+ECC_OFFS+i*4);
1037  /* DMACCxLLI = next element */
1038  tmp = (target_mem_base+(2+i*2)*16)&0xfffffffc;
1039  target_write_u32(target, target_mem_base+24+i*32, tmp);
1040  /* DMACCxControl = TransferSize =1, Source burst size =4,
1041  * Destination burst size = 4, Source transfer width = 32 bit,
1042  * Destination transfer width = 32 bit, Source AHB master select = M0,
1043  * Destination AHB master select = M0, Source increment = 0,
1044  * Destination increment = 1, Terminal count interrupt enable bit = 0*/
1046  target_mem_base+28+i*32,
1047  0x01 | 1<<12 | 1<<15 | 2<<18 | 2<<21 | 0<<24 | 0<<25 | 0<<26 | 1<<27 | 0<<
1048  31);
1049  }
1050 
1051  /* -------LLI for spare area---------
1052  * DMACC0SrcAddr = SLC_DMA_DATA*/
1053  target_write_u32(target, target_mem_base+0+i*32, 0x20020038);
1054  /* DMACCxDestAddr = SRAM */
1055  target_write_u32(target, target_mem_base+4+i*32, target_mem_base+SPARE_OFFS);
1056  /* DMACCxLLI = next element = NULL */
1057  target_write_u32(target, target_mem_base+8+i*32, 0);
1058  /* DMACCxControl = TransferSize =16 for large page or 4 for small page,
1059  * Source burst size =16, Destination burst size = 16, Source transfer width = 32 bit,
1060  * Destination transfer width = 32 bit, Source AHB master select = M0,
1061  * Destination AHB master select = M0, Source increment = 0,
1062  * Destination increment = 1, Terminal count interrupt enable bit = 0*/
1064  target_mem_base + 12 + i * 32,
1065  (nand->page_size == 2048 ? 0x10 : 0x04) | 3<<12 | 3<<15 | 2<<18 | 2<<21 |
1066  0<<24 | 0<<25 | 0<<26 | 1<<27 | 0<<31);
1067 
1068  /* Enable DMA after channel set up !
1069  LLI only works when DMA is the flow controller!
1070  */
1071  /* DMACCxConfig= E=1, SrcPeripheral = 1 (SLC), DestPeripheral = 1 (SLC),
1072  *FlowCntrl = 2 (Pher-> Mem, DMA), IE = 0, ITC = 0, L= 0, H=0*/
1074  0x31000110,
1075  1 | 1<<1 | 1<<6 | 2<<11 | 0<<14 | 0<<15 | 0<<16 | 0<<18);
1076 
1077  /* SLC_CTRL = 3 (START DMA), ECC_CLEAR */
1078  target_write_u32(target, 0x20020010, 0x3);
1079 
1080  /* SLC_ICR = 2, INT_TC_CLR, clear pending TC*/
1081  target_write_u32(target, 0x20020028, 2);
1082 
1083  /* SLC_TC */
1084  target_write_u32(target, 0x20020030,
1085  (nand->page_size == 2048 ? 0x840 : 0x210));
1086 
1087  if (!lpc3180_tc_ready(nand, 1000)) {
1088  LOG_ERROR("timeout while waiting for completion of DMA");
1089  free(page_buffer);
1090  free(ecc_hw_buffer);
1091  free(ecc_flash_buffer);
1092  target_free_working_area(target, pworking_area);
1094  }
1095 
1096  if (data) {
1098  target_mem_base+DATA_OFFS,
1099  4,
1100  nand->page_size == 2048 ? 512 : 128,
1101  page_buffer);
1102  memcpy(data, page_buffer, data_size);
1103 
1104  LOG_INFO("Page = 0x%" PRIx32 " was read.", page);
1105 
1106  /* check hw generated ECC for each 256 bytes block with the saved
1107  *ECC in flash spare area*/
1108  int idx = nand->page_size/0x200;
1110  target_mem_base+SPARE_OFFS,
1111  4,
1112  16,
1113  ecc_flash_buffer);
1115  target_mem_base+ECC_OFFS,
1116  4,
1117  8,
1118  ecc_hw_buffer);
1119  for (i = 0; i < idx; i++) {
1120  if ((0x00ffffff & *(uint32_t *)(void *)(ecc_hw_buffer+i*8)) !=
1121  (0x00ffffff & *(uint32_t *)(void *)(ecc_flash_buffer+8+i*16)))
1122  LOG_WARNING(
1123  "ECC mismatch at 256 bytes size block= %d at page= 0x%" PRIx32,
1124  i * 2 + 1, page);
1125  if ((0x00ffffff & *(uint32_t *)(void *)(ecc_hw_buffer+4+i*8)) !=
1126  (0x00ffffff & *(uint32_t *)(void *)(ecc_flash_buffer+12+i*16)))
1127  LOG_WARNING(
1128  "ECC mismatch at 256 bytes size block= %d at page= 0x%" PRIx32,
1129  i * 2 + 2, page);
1130  }
1131  }
1132 
1133  if (oob)
1134  memcpy(oob, ecc_flash_buffer, oob_size);
1135 
1136  free(page_buffer);
1137  free(ecc_hw_buffer);
1138  free(ecc_flash_buffer);
1139 
1140  target_free_working_area(target, pworking_area);
1141 
1142  } else
1143  return nand_read_page_raw(nand, page, data, data_size, oob, oob_size);
1144  }
1145 
1146  return ERROR_OK;
1147 }
1148 
1149 static int lpc3180_controller_ready(struct nand_device *nand, int timeout)
1150 {
1151  struct lpc3180_nand_controller *lpc3180_info = nand->controller_priv;
1152  struct target *target = nand->target;
1153 
1154  if (target->state != TARGET_HALTED) {
1155  LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
1157  }
1158 
1159  LOG_DEBUG("lpc3180_controller_ready count start=%d", timeout);
1160 
1161  do {
1162  if (lpc3180_info->selected_controller == LPC3180_MLC_CONTROLLER) {
1163  uint8_t status;
1164 
1165  /* Read MLC_ISR, wait for controller to become ready */
1166  target_read_u8(target, 0x200b8048, &status);
1167 
1168  if (status & 2) {
1169  LOG_DEBUG("lpc3180_controller_ready count=%d",
1170  timeout);
1171  return 1;
1172  }
1173  } else if (lpc3180_info->selected_controller == LPC3180_SLC_CONTROLLER) {
1174  uint32_t status;
1175 
1176  /* Read SLC_STAT and check READY bit */
1177  target_read_u32(target, 0x20020018, &status);
1178 
1179  if (status & 1) {
1180  LOG_DEBUG("lpc3180_controller_ready count=%d",
1181  timeout);
1182  return 1;
1183  }
1184  }
1185 
1186  alive_sleep(1);
1187  } while (timeout-- > 0);
1188 
1189  return 0;
1190 }
1191 
1192 static int lpc3180_nand_ready(struct nand_device *nand, int timeout)
1193 {
1194  struct lpc3180_nand_controller *lpc3180_info = nand->controller_priv;
1195  struct target *target = nand->target;
1196 
1197  if (target->state != TARGET_HALTED) {
1198  LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
1200  }
1201 
1202  LOG_DEBUG("lpc3180_nand_ready count start=%d", timeout);
1203 
1204  do {
1205  if (lpc3180_info->selected_controller == LPC3180_MLC_CONTROLLER) {
1206  uint8_t status = 0x0;
1207 
1208  /* Read MLC_ISR, wait for NAND flash device to become ready */
1209  target_read_u8(target, 0x200b8048, &status);
1210 
1211  if (status & 1) {
1212  LOG_DEBUG("lpc3180_nand_ready count end=%d",
1213  timeout);
1214  return 1;
1215  }
1216  } else if (lpc3180_info->selected_controller == LPC3180_SLC_CONTROLLER) {
1217  uint32_t status = 0x0;
1218 
1219  /* Read SLC_STAT and check READY bit */
1220  target_read_u32(target, 0x20020018, &status);
1221 
1222  if (status & 1) {
1223  LOG_DEBUG("lpc3180_nand_ready count end=%d",
1224  timeout);
1225  return 1;
1226  }
1227  }
1228 
1229  alive_sleep(1);
1230  } while (timeout-- > 0);
1231 
1232  return 0;
1233 }
1234 
1235 static int lpc3180_tc_ready(struct nand_device *nand, int timeout)
1236 {
1237  struct lpc3180_nand_controller *lpc3180_info = nand->controller_priv;
1238  struct target *target = nand->target;
1239 
1240  if (target->state != TARGET_HALTED) {
1241  LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
1243  }
1244 
1245  LOG_DEBUG("lpc3180_tc_ready count start=%d",
1246  timeout);
1247 
1248  do {
1249  if (lpc3180_info->selected_controller == LPC3180_SLC_CONTROLLER) {
1250  uint32_t status = 0x0;
1251  /* Read SLC_INT_STAT and check INT_TC_STAT bit */
1252  target_read_u32(target, 0x2002001c, &status);
1253 
1254  if (status & 2) {
1255  LOG_DEBUG("lpc3180_tc_ready count=%d",
1256  timeout);
1257  return 1;
1258  }
1259  }
1260 
1261  alive_sleep(1);
1262  } while (timeout-- > 0);
1263 
1264  return 0;
1265 }
1266 
1267 COMMAND_HANDLER(handle_lpc3180_select_command)
1268 {
1269  struct lpc3180_nand_controller *lpc3180_info = NULL;
1270  char *selected[] = {
1271  "no", "mlc", "slc"
1272  };
1273 
1274  if ((CMD_ARGC < 1) || (CMD_ARGC > 3))
1276 
1277  unsigned int num;
1278  COMMAND_PARSE_NUMBER(uint, CMD_ARGV[0], num);
1279  struct nand_device *nand = get_nand_device_by_num(num);
1280  if (!nand) {
1281  command_print(CMD, "nand device '#%s' is out of bounds", CMD_ARGV[0]);
1282  return ERROR_OK;
1283  }
1284 
1285  lpc3180_info = nand->controller_priv;
1286 
1287  if (CMD_ARGC >= 2) {
1288  if (strcmp(CMD_ARGV[1], "mlc") == 0)
1290  else if (strcmp(CMD_ARGV[1], "slc") == 0) {
1292  if (CMD_ARGC == 3 && strcmp(CMD_ARGV[2], "bulk") == 0)
1293  lpc3180_info->is_bulk = 1;
1294  else
1295  lpc3180_info->is_bulk = 0;
1296  } else
1298  }
1299 
1300  if (lpc3180_info->selected_controller == LPC3180_MLC_CONTROLLER)
1301  command_print(CMD, "%s controller selected",
1302  selected[lpc3180_info->selected_controller]);
1303  else
1305  lpc3180_info->is_bulk ? "%s controller selected bulk mode is available" :
1306  "%s controller selected bulk mode is not available",
1307  selected[lpc3180_info->selected_controller]);
1308 
1309  return ERROR_OK;
1310 }
1311 
1312 static const struct command_registration lpc3180_exec_command_handlers[] = {
1313  {
1314  .name = "select",
1315  .handler = handle_lpc3180_select_command,
1316  .mode = COMMAND_EXEC,
1317  .help =
1318  "select MLC or SLC controller (default is MLC), SLC can be set to bulk mode",
1319  .usage = "bank_id ['mlc'|'slc' ['bulk'] ]",
1320  },
1322 };
1323 static const struct command_registration lpc3180_command_handler[] = {
1324  {
1325  .name = "lpc3180",
1326  .mode = COMMAND_ANY,
1327  .help = "LPC3180 NAND flash controller commands",
1328  .usage = "",
1330  },
1332 };
1333 
1335  .name = "lpc3180",
1336  .commands = lpc3180_command_handler,
1337  .nand_device_command = lpc3180_nand_device_command,
1338  .init = lpc3180_init,
1339  .reset = lpc3180_reset,
1340  .command = lpc3180_command,
1341  .address = lpc3180_address,
1342  .write_data = lpc3180_write_data,
1343  .read_data = lpc3180_read_data,
1344  .write_page = lpc3180_write_page,
1345  .read_page = lpc3180_read_page,
1346  .nand_ready = lpc3180_nand_ready,
1347 };
void command_print(struct command_invocation *cmd, const char *format,...)
Definition: command.c:443
#define CMD
Use this macro to access the command being handled, rather than accessing the variable directly.
Definition: command.h:141
#define CMD_ARGV
Use this macro to access the arguments for the command being handled, rather than accessing the varia...
Definition: command.h:156
#define ERROR_COMMAND_SYNTAX_ERROR
Definition: command.h:402
#define CMD_ARGC
Use this macro to access the number of arguments for the command being handled, rather than accessing...
Definition: command.h:151
#define COMMAND_PARSE_NUMBER(type, in, out)
parses the string in into out as a type, or prints a command error and passes the error code to the c...
Definition: command.h:442
#define COMMAND_REGISTRATION_DONE
Use this as the last entry in an array of command_registration records.
Definition: command.h:253
@ COMMAND_ANY
Definition: command.h:42
@ COMMAND_EXEC
Definition: command.h:40
#define ERROR_FLASH_OPERATION_FAILED
Definition: flash/common.h:30
int nand_read_page_raw(struct nand_device *nand, uint32_t page, uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
int nand_read_status(struct nand_device *nand, uint8_t *status)
int nand_write_finish(struct nand_device *nand)
int nand_write_page_raw(struct nand_device *nand, uint32_t page, uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
struct nand_device * get_nand_device_by_num(int num)
int nand_page_command(struct nand_device *nand, uint32_t page, uint8_t cmd, bool oob_only)
void alive_sleep(uint64_t ms)
Definition: log.c:456
#define LOG_WARNING(expr ...)
Definition: log.h:129
#define LOG_ERROR(expr ...)
Definition: log.h:132
#define LOG_INFO(expr ...)
Definition: log.h:126
#define LOG_DEBUG(expr ...)
Definition: log.h:109
#define ERROR_OK
Definition: log.h:164
#define DATA_OFFS
Definition: lpc3180.c:25
static int lpc3180_init(struct nand_device *nand)
Definition: lpc3180.c:127
static int lpc3180_controller_ready(struct nand_device *nand, int timeout)
Definition: lpc3180.c:1149
static int lpc3180_pll(int fclkin, uint32_t pll_ctrl)
Definition: lpc3180.c:55
#define ECC_OFFS
Definition: lpc3180.c:23
static int lpc3180_read_page(struct nand_device *nand, uint32_t page, uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
Definition: lpc3180.c:796
COMMAND_HANDLER(handle_lpc3180_select_command)
Definition: lpc3180.c:1267
static const struct command_registration lpc3180_exec_command_handlers[]
Definition: lpc3180.c:1312
static int lpc3180_read_data(struct nand_device *nand, void *data)
Definition: lpc3180.c:366
static int lpc3180_command(struct nand_device *nand, uint8_t command)
Definition: lpc3180.c:294
static float lpc3180_cycle_time(struct nand_device *nand)
Definition: lpc3180.c:83
static int lpc3180_write_page(struct nand_device *nand, uint32_t page, uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
Definition: lpc3180.c:412
static int lpc3180_write_data(struct nand_device *nand, uint16_t data)
Definition: lpc3180.c:342
static int lpc3180_tc_ready(struct nand_device *nand, int timeout)
Definition: lpc3180.c:1235
static int lpc3180_address(struct nand_device *nand, uint8_t address)
Definition: lpc3180.c:318
static int lpc3180_reset(struct nand_device *nand)
Definition: lpc3180.c:260
static int lpc3180_nand_ready(struct nand_device *nand, int timeout)
Definition: lpc3180.c:1192
#define SPARE_OFFS
Definition: lpc3180.c:24
NAND_DEVICE_COMMAND_HANDLER(lpc3180_nand_device_command)
Definition: lpc3180.c:29
static const struct command_registration lpc3180_command_handler[]
Definition: lpc3180.c:1323
@ LPC3180_MLC_CONTROLLER
Definition: lpc3180.h:13
@ LPC3180_SLC_CONTROLLER
Definition: lpc3180.h:14
@ LPC3180_NO_CONTROLLER
Definition: lpc3180.h:12
#define ERROR_NAND_OPERATION_TIMEOUT
Definition: nand/core.h:218
#define ERROR_NAND_OPERATION_FAILED
Definition: nand/core.h:217
@ NAND_CMD_SEQIN
Definition: nand/core.h:148
@ NAND_CMD_READSTART
Definition: nand/core.h:155
@ NAND_CMD_READOOB
Definition: nand/core.h:144
@ NAND_CMD_READ0
Definition: nand/core.h:140
@ NAND_CMD_PAGEPROG
Definition: nand/core.h:143
@ NAND_STATUS_FAIL
Definition: nand/core.h:162
#define ERROR_NAND_OPERATION_NOT_SUPPORTED
Definition: nand/core.h:219
const char * name
Definition: command.h:235
uint32_t sw_wp_upper_bound
Definition: lpc3180.h:23
enum lpc3180_selected_controller selected_controller
Definition: lpc3180.h:19
uint32_t sw_wp_lower_bound
Definition: lpc3180.h:22
void * controller_priv
Definition: nand/core.h:51
int page_size
Definition: nand/core.h:56
int address_cycles
Definition: nand/core.h:55
int bus_width
Definition: nand/core.h:54
struct target * target
Definition: nand/core.h:49
Interface for NAND flash controllers.
Definition: nand/driver.h:23
Definition: target.h:116
uint32_t working_area_size
Definition: target.h:151
enum target_state state
Definition: target.h:157
target_addr_t working_area_phys
Definition: target.h:150
Definition: psoc6.c:83
bool free
Definition: target.h:88
int target_read_u8(struct target *target, target_addr_t address, uint8_t *value)
Definition: target.c:2598
int target_write_memory(struct target *target, target_addr_t address, uint32_t size, uint32_t count, const uint8_t *buffer)
Write count items of size bytes to the memory of target at the address given.
Definition: target.c:1265
int target_alloc_working_area(struct target *target, uint32_t size, struct working_area **area)
Definition: target.c:2060
int target_write_u32(struct target *target, target_addr_t address, uint32_t value)
Definition: target.c:2641
int target_free_working_area(struct target *target, struct working_area *area)
Free a working area.
Definition: target.c:2118
int target_read_u16(struct target *target, target_addr_t address, uint16_t *value)
Definition: target.c:2574
int target_read_u32(struct target *target, target_addr_t address, uint32_t *value)
Definition: target.c:2550
int target_read_memory(struct target *target, target_addr_t address, uint32_t size, uint32_t count, uint8_t *buffer)
Read count items of size bytes from the memory of target at the address given.
Definition: target.c:1237
@ TARGET_HALTED
Definition: target.h:56
#define NULL
Definition: usb.h:16
uint8_t status[4]
Definition: vdebug.c:17