OpenOCD
at91sam4.c
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1 // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-Source-Code)
2 
3 /*
4  * Copyright (C) 2009 by Duane Ellis <openocd@duaneellis.com>
5  *
6  * at91sam3s* support
7  * Copyright (C) 2010 by Olaf Lüke <olaf@uni-paderborn.de>
8  *
9  * at91sam3x* & at91sam4 support
10  * Copyright (C) 2011 by Olivier Schonken, Jim Norris
11  *
12  * Some of the lower level code was based on code supplied by
13  * ATMEL under BSD-Source-Code License and this copyright.
14  * ATMEL Microcontroller Software Support
15  * Copyright (c) 2009, Atmel Corporation. All rights reserved.
16  */
17 
18 #ifdef HAVE_CONFIG_H
19 #include "config.h"
20 #endif
21 
22 #include "imp.h"
23 #include <helper/time_support.h>
24 
25 #define REG_NAME_WIDTH (12)
26 
27 /* at91sam4s/at91sam4e/at91sam4c series (has always one flash bank)*/
28 #define FLASH_BANK_BASE_S 0x00400000
29 #define FLASH_BANK_BASE_C 0x01000000
30 
31 /* at91sam4sd series (two one flash banks), first bank address */
32 #define FLASH_BANK0_BASE_SD FLASH_BANK_BASE_S
33 /* at91sam4sd16x, second bank address */
34 #define FLASH_BANK1_BASE_1024K_SD (FLASH_BANK0_BASE_SD+(1024*1024/2))
35 /* at91sam4sd32x, second bank address */
36 #define FLASH_BANK1_BASE_2048K_SD (FLASH_BANK0_BASE_SD+(2048*1024/2))
37 
38 /* at91sam4c32x, first and second bank address */
39 #define FLASH_BANK0_BASE_C32 FLASH_BANK_BASE_C
40 #define FLASH_BANK1_BASE_C32 (FLASH_BANK_BASE_C+(2048*1024/2))
41 
42 #define AT91C_EFC_FCMD_GETD (0x0) /* (EFC) Get Flash Descriptor */
43 #define AT91C_EFC_FCMD_WP (0x1) /* (EFC) Write Page */
44 #define AT91C_EFC_FCMD_WPL (0x2) /* (EFC) Write Page and Lock */
45 #define AT91C_EFC_FCMD_EWP (0x3) /* (EFC) Erase Page and Write Page */
46 #define AT91C_EFC_FCMD_EWPL (0x4) /* (EFC) Erase Page and Write Page then Lock */
47 #define AT91C_EFC_FCMD_EA (0x5) /* (EFC) Erase All */
48 /* cmd6 is not present in the at91sam4u4/2/1 data sheet table 19-2 */
49 /* #define AT91C_EFC_FCMD_EPL (0x6) // (EFC) Erase plane? */
50 #define AT91C_EFC_FCMD_EPA (0x7) /* (EFC) Erase pages */
51 #define AT91C_EFC_FCMD_SLB (0x8) /* (EFC) Set Lock Bit */
52 #define AT91C_EFC_FCMD_CLB (0x9) /* (EFC) Clear Lock Bit */
53 #define AT91C_EFC_FCMD_GLB (0xA) /* (EFC) Get Lock Bit */
54 #define AT91C_EFC_FCMD_SFB (0xB) /* (EFC) Set Fuse Bit */
55 #define AT91C_EFC_FCMD_CFB (0xC) /* (EFC) Clear Fuse Bit */
56 #define AT91C_EFC_FCMD_GFB (0xD) /* (EFC) Get Fuse Bit */
57 #define AT91C_EFC_FCMD_STUI (0xE) /* (EFC) Start Read Unique ID */
58 #define AT91C_EFC_FCMD_SPUI (0xF) /* (EFC) Stop Read Unique ID */
59 
60 #define OFFSET_EFC_FMR 0
61 #define OFFSET_EFC_FCR 4
62 #define OFFSET_EFC_FSR 8
63 #define OFFSET_EFC_FRR 12
64 
65 static float _tomhz(uint32_t freq_hz)
66 {
67  return ((float)freq_hz) / 1000000.0;
68 }
69 
70 /* How the chip is configured. */
71 struct sam4_cfg {
72  uint32_t unique_id[4];
73 
74  uint32_t slow_freq;
75  uint32_t rc_freq;
76  uint32_t mainosc_freq;
77  uint32_t plla_freq;
78  uint32_t mclk_freq;
79  uint32_t cpu_freq;
80  uint32_t fclk_freq;
81  uint32_t pclk0_freq;
82  uint32_t pclk1_freq;
83  uint32_t pclk2_freq;
84 
85 
86 #define SAM4_CHIPID_CIDR (0x400E0740)
87  uint32_t CHIPID_CIDR;
88 #define SAM4_CHIPID_EXID (0x400E0744)
89  uint32_t CHIPID_EXID;
90 
91 #define SAM4_PMC_BASE (0x400E0400)
92 #define SAM4_PMC_SCSR (SAM4_PMC_BASE + 0x0008)
93  uint32_t PMC_SCSR;
94 #define SAM4_PMC_PCSR (SAM4_PMC_BASE + 0x0018)
95  uint32_t PMC_PCSR;
96 #define SAM4_CKGR_UCKR (SAM4_PMC_BASE + 0x001c)
97  uint32_t CKGR_UCKR;
98 #define SAM4_CKGR_MOR (SAM4_PMC_BASE + 0x0020)
99  uint32_t CKGR_MOR;
100 #define SAM4_CKGR_MCFR (SAM4_PMC_BASE + 0x0024)
101  uint32_t CKGR_MCFR;
102 #define SAM4_CKGR_PLLAR (SAM4_PMC_BASE + 0x0028)
103  uint32_t CKGR_PLLAR;
104 #define SAM4_PMC_MCKR (SAM4_PMC_BASE + 0x0030)
105  uint32_t PMC_MCKR;
106 #define SAM4_PMC_PCK0 (SAM4_PMC_BASE + 0x0040)
107  uint32_t PMC_PCK0;
108 #define SAM4_PMC_PCK1 (SAM4_PMC_BASE + 0x0044)
109  uint32_t PMC_PCK1;
110 #define SAM4_PMC_PCK2 (SAM4_PMC_BASE + 0x0048)
111  uint32_t PMC_PCK2;
112 #define SAM4_PMC_SR (SAM4_PMC_BASE + 0x0068)
113  uint32_t PMC_SR;
114 #define SAM4_PMC_IMR (SAM4_PMC_BASE + 0x006c)
115  uint32_t PMC_IMR;
116 #define SAM4_PMC_FSMR (SAM4_PMC_BASE + 0x0070)
117  uint32_t PMC_FSMR;
118 #define SAM4_PMC_FSPR (SAM4_PMC_BASE + 0x0074)
119  uint32_t PMC_FSPR;
120 };
121 
122 struct sam4_bank_private {
123  bool probed;
124  /* DANGER: THERE ARE DRAGONS HERE.. */
125  /* NOTE: If you add more 'ghost' pointers */
126  /* be aware that you must *manually* update */
127  /* these pointers in the function sam4_get_details() */
128  /* See the comment "Here there be dragons" */
129 
130  /* so we can find the chip we belong to */
131  struct sam4_chip *chip;
132  /* so we can find the original bank pointer */
133  struct flash_bank *bank;
134  unsigned int bank_number;
135  uint32_t controller_address;
136  uint32_t base_address;
137  uint32_t flash_wait_states;
138  bool present;
139  unsigned int size_bytes;
140  unsigned int nsectors;
141  unsigned int sector_size;
142  unsigned int page_size;
143 };
144 
145 struct sam4_chip_details {
146  /* THERE ARE DRAGONS HERE.. */
147  /* note: If you add pointers here */
148  /* be careful about them as they */
149  /* may need to be updated inside */
150  /* the function: "sam4_get_details() */
151  /* which copy/overwrites the */
152  /* 'runtime' copy of this structure */
153  uint32_t chipid_cidr;
154  const char *name;
155 
156  unsigned int n_gpnvms;
157 #define SAM4_N_NVM_BITS 3
158  unsigned int gpnvm[SAM4_N_NVM_BITS];
159  unsigned int total_flash_size;
160  unsigned int total_sram_size;
161  unsigned int n_banks;
162 #define SAM4_MAX_FLASH_BANKS 2
163  /* these are "initialized" from the global const data */
164  struct sam4_bank_private bank[SAM4_MAX_FLASH_BANKS];
165 };
166 
167 struct sam4_chip {
168  struct sam4_chip *next;
169  bool probed;
170 
171  /* this is "initialized" from the global const structure */
172  struct sam4_chip_details details;
173  struct target *target;
174  struct sam4_cfg cfg;
175 };
176 
177 
178 struct sam4_reg_list {
179  uint32_t address; size_t struct_offset; const char *name;
180  void (*explain_func)(struct sam4_chip *chip);
181 };
182 
183 static struct sam4_chip *all_sam4_chips;
184 
185 static struct sam4_chip *get_current_sam4(struct command_invocation *cmd)
186 {
187  struct target *t;
188  static struct sam4_chip *p;
189 
190  t = get_current_target(cmd->ctx);
191  if (!t) {
192  command_print_sameline(cmd, "No current target?\n");
193  return NULL;
194  }
195 
196  p = all_sam4_chips;
197  if (!p) {
198  /* this should not happen */
199  /* the command is not registered until the chip is created? */
200  command_print_sameline(cmd, "No SAM4 chips exist?\n");
201  return NULL;
202  }
203 
204  while (p) {
205  if (p->target == t)
206  return p;
207  p = p->next;
208  }
209  command_print_sameline(cmd, "Cannot find SAM4 chip?\n");
210  return NULL;
211 }
212 
213 /*The actual sector size of the SAM4S flash memory is 65536 bytes. 16 sectors for a 1024KB device*/
214 /*The lockregions are 8KB per lock region, with a 1024KB device having 128 lock regions. */
215 /*For the best results, nsectors are thus set to the amount of lock regions, and the sector_size*/
216 /*set to the lock region size. Page erases are used to erase 8KB sections when programming*/
217 
218 /* these are used to *initialize* the "chip->details" structure. */
219 static const struct sam4_chip_details all_sam4_details[] = {
220  /* Start at91sam4c* series */
221  /* at91sam4c32e - LQFP144 */
222  {
223  .chipid_cidr = 0xA66D0EE0,
224  .name = "at91sam4c32e",
225  .total_flash_size = 2024 * 1024,
226  .total_sram_size = 256 * 1024,
227  .n_gpnvms = 3,
228  .n_banks = 2,
229 /* .bank[0] = { */
230  {
231  {
232  .probed = false,
233  .chip = NULL,
234  .bank = NULL,
235  .bank_number = 0,
236  .base_address = FLASH_BANK0_BASE_C32,
237  .controller_address = 0x400e0a00,
238  .flash_wait_states = 5,
239  .present = true,
240  .size_bytes = 1024 * 1024,
241  .nsectors = 128,
242  .sector_size = 8192,
243  .page_size = 512,
244  },
245 /* .bank[1] = { */
246  {
247  .probed = false,
248  .chip = NULL,
249  .bank = NULL,
250  .bank_number = 1,
251  .base_address = FLASH_BANK1_BASE_C32,
252  .controller_address = 0x400e0c00,
253  .flash_wait_states = 5,
254  .present = true,
255  .size_bytes = 1024 * 1024,
256  .nsectors = 128,
257  .sector_size = 8192,
258  .page_size = 512,
259  },
260  },
261  },
262  /* at91sam4c32c - LQFP100 */
263  {
264  .chipid_cidr = 0xA64D0EE0,
265  .name = "at91sam4c32c",
266  .total_flash_size = 2024 * 1024,
267  .total_sram_size = 256 * 1024,
268  .n_gpnvms = 3,
269  .n_banks = 2,
270 /* .bank[0] = { */
271  {
272  {
273  .probed = false,
274  .chip = NULL,
275  .bank = NULL,
276  .bank_number = 0,
277  .base_address = FLASH_BANK0_BASE_C32,
278  .controller_address = 0x400e0a00,
279  .flash_wait_states = 5,
280  .present = true,
281  .size_bytes = 1024 * 1024,
282  .nsectors = 128,
283  .sector_size = 8192,
284  .page_size = 512,
285  },
286 /* .bank[1] = { */
287  {
288  .probed = false,
289  .chip = NULL,
290  .bank = NULL,
291  .bank_number = 1,
292  .base_address = FLASH_BANK1_BASE_C32,
293  .controller_address = 0x400e0c00,
294  .flash_wait_states = 5,
295  .present = true,
296  .size_bytes = 1024 * 1024,
297  .nsectors = 128,
298  .sector_size = 8192,
299  .page_size = 512,
300  },
301  },
302  },
303  /* at91sam4c16c - LQFP100 */
304  {
305  .chipid_cidr = 0xA64C0CE0,
306  .name = "at91sam4c16c",
307  .total_flash_size = 1024 * 1024,
308  .total_sram_size = 128 * 1024,
309  .n_gpnvms = 2,
310  .n_banks = 1,
311  {
312 /* .bank[0] = {*/
313  {
314  .probed = false,
315  .chip = NULL,
316  .bank = NULL,
317  .bank_number = 0,
318  .base_address = FLASH_BANK_BASE_C,
319  .controller_address = 0x400e0a00,
320  .flash_wait_states = 5,
321  .present = true,
322  .size_bytes = 1024 * 1024,
323  .nsectors = 128,
324  .sector_size = 8192,
325  .page_size = 512,
326  },
327 /* .bank[1] = {*/
328  {
329  .present = false,
330  .probed = false,
331  .bank_number = 1,
332 
333  },
334  },
335  },
336  /* at91sam4c8c - LQFP100 */
337  {
338  .chipid_cidr = 0xA64C0AE0,
339  .name = "at91sam4c8c",
340  .total_flash_size = 512 * 1024,
341  .total_sram_size = 128 * 1024,
342  .n_gpnvms = 2,
343  .n_banks = 1,
344  {
345 /* .bank[0] = {*/
346  {
347  .probed = false,
348  .chip = NULL,
349  .bank = NULL,
350  .bank_number = 0,
351  .base_address = FLASH_BANK_BASE_C,
352  .controller_address = 0x400e0a00,
353  .flash_wait_states = 5,
354  .present = true,
355  .size_bytes = 512 * 1024,
356  .nsectors = 64,
357  .sector_size = 8192,
358  .page_size = 512,
359  },
360 /* .bank[1] = {*/
361  {
362  .present = false,
363  .probed = false,
364  .bank_number = 1,
365 
366  },
367  },
368  },
369  /* at91sam4c4c (rev B) - LQFP100 */
370  {
371  .chipid_cidr = 0xA64C0CE5,
372  .name = "at91sam4c4c",
373  .total_flash_size = 256 * 1024,
374  .total_sram_size = 128 * 1024,
375  .n_gpnvms = 2,
376  .n_banks = 1,
377  {
378 /* .bank[0] = {*/
379  {
380  .probed = false,
381  .chip = NULL,
382  .bank = NULL,
383  .bank_number = 0,
384  .base_address = FLASH_BANK_BASE_C,
385  .controller_address = 0x400e0a00,
386  .flash_wait_states = 5,
387  .present = true,
388  .size_bytes = 256 * 1024,
389  .nsectors = 32,
390  .sector_size = 8192,
391  .page_size = 512,
392  },
393 /* .bank[1] = {*/
394  {
395  .present = false,
396  .probed = false,
397  .bank_number = 1,
398 
399  },
400  },
401  },
402 
403  /* Start at91sam4e* series */
404  /*atsam4e16e - LQFP144/LFBGA144*/
405  {
406  .chipid_cidr = 0xA3CC0CE0,
407  .name = "at91sam4e16e",
408  .total_flash_size = 1024 * 1024,
409  .total_sram_size = 128 * 1024,
410  .n_gpnvms = 2,
411  .n_banks = 1,
412  {
413 /* .bank[0] = {*/
414  {
415  .probed = false,
416  .chip = NULL,
417  .bank = NULL,
418  .bank_number = 0,
419  .base_address = FLASH_BANK_BASE_S,
420  .controller_address = 0x400e0a00,
421  .flash_wait_states = 5,
422  .present = true,
423  .size_bytes = 1024 * 1024,
424  .nsectors = 128,
425  .sector_size = 8192,
426  .page_size = 512,
427  },
428 /* .bank[1] = {*/
429  {
430  .present = false,
431  .probed = false,
432  .bank_number = 1,
433 
434  },
435  },
436  },
437 
438  /* Start at91sam4n* series */
439  /*atsam4n8a - LQFP48/QFN48*/
440  {
441  .chipid_cidr = 0x293B0AE0,
442  .name = "at91sam4n8a",
443  .total_flash_size = 512 * 1024,
444  .total_sram_size = 64 * 1024,
445  .n_gpnvms = 2,
446  .n_banks = 1,
447  {
448 /* .bank[0] = {*/
449  {
450  .probed = false,
451  .chip = NULL,
452  .bank = NULL,
453  .bank_number = 0,
454  .base_address = FLASH_BANK_BASE_S,
455  .controller_address = 0x400e0a00,
456  .flash_wait_states = 5,
457  .present = true,
458  .size_bytes = 512 * 1024,
459  .nsectors = 64,
460  .sector_size = 8192,
461  .page_size = 512,
462  },
463 /* .bank[1] = {*/
464  {
465  .present = false,
466  .probed = false,
467  .bank_number = 1,
468 
469  },
470  },
471  },
472  /*atsam4n8b - LQFP64/QFN64*/
473  {
474  .chipid_cidr = 0x294B0AE0,
475  .name = "at91sam4n8b",
476  .total_flash_size = 512 * 1024,
477  .total_sram_size = 64 * 1024,
478  .n_gpnvms = 2,
479  .n_banks = 1,
480  {
481 /* .bank[0] = {*/
482  {
483  .probed = false,
484  .chip = NULL,
485  .bank = NULL,
486  .bank_number = 0,
487  .base_address = FLASH_BANK_BASE_S,
488  .controller_address = 0x400e0a00,
489  .flash_wait_states = 5,
490  .present = true,
491  .size_bytes = 512 * 1024,
492  .nsectors = 64,
493  .sector_size = 8192,
494  .page_size = 512,
495  },
496 /* .bank[1] = {*/
497  {
498  .present = false,
499  .probed = false,
500  .bank_number = 1,
501 
502  },
503  },
504  },
505  /*atsam4n8c - LQFP100/TFBGA100/VFBGA100*/
506  {
507  .chipid_cidr = 0x295B0AE0,
508  .name = "at91sam4n8c",
509  .total_flash_size = 512 * 1024,
510  .total_sram_size = 64 * 1024,
511  .n_gpnvms = 2,
512  .n_banks = 1,
513  {
514 /* .bank[0] = {*/
515  {
516  .probed = false,
517  .chip = NULL,
518  .bank = NULL,
519  .bank_number = 0,
520  .base_address = FLASH_BANK_BASE_S,
521  .controller_address = 0x400e0a00,
522  .flash_wait_states = 5,
523  .present = true,
524  .size_bytes = 512 * 1024,
525  .nsectors = 64,
526  .sector_size = 8192,
527  .page_size = 512,
528  },
529 /* .bank[1] = {*/
530  {
531  .present = false,
532  .probed = false,
533  .bank_number = 1,
534 
535  },
536  },
537  },
538  /*atsam4n16b - LQFP64/QFN64*/
539  {
540  .chipid_cidr = 0x29460CE0,
541  .name = "at91sam4n16b",
542  .total_flash_size = 1024 * 1024,
543  .total_sram_size = 80 * 1024,
544  .n_gpnvms = 2,
545  .n_banks = 1,
546  {
547 /* .bank[0] = {*/
548  {
549  .probed = false,
550  .chip = NULL,
551  .bank = NULL,
552  .bank_number = 0,
553  .base_address = FLASH_BANK_BASE_S,
554  .controller_address = 0x400e0a00,
555  .flash_wait_states = 5,
556  .present = true,
557  .size_bytes = 1024 * 1024,
558  .nsectors = 128,
559  .sector_size = 8192,
560  .page_size = 512,
561  },
562 /* .bank[1] = {*/
563  {
564  .present = false,
565  .probed = false,
566  .bank_number = 1,
567 
568  },
569  },
570  },
571  /*atsam4n16c - LQFP100/TFBGA100/VFBGA100*/
572  {
573  .chipid_cidr = 0x29560CE0,
574  .name = "at91sam4n16c",
575  .total_flash_size = 1024 * 1024,
576  .total_sram_size = 80 * 1024,
577  .n_gpnvms = 2,
578  .n_banks = 1,
579  {
580 /* .bank[0] = {*/
581  {
582  .probed = false,
583  .chip = NULL,
584  .bank = NULL,
585  .bank_number = 0,
586  .base_address = FLASH_BANK_BASE_S,
587  .controller_address = 0x400e0a00,
588  .flash_wait_states = 5,
589  .present = true,
590  .size_bytes = 1024 * 1024,
591  .nsectors = 128,
592  .sector_size = 8192,
593  .page_size = 512,
594  },
595 /* .bank[1] = {*/
596  {
597  .present = false,
598  .probed = false,
599  .bank_number = 1,
600 
601  },
602  },
603  },
604 
605  /* Start at91sam4s* series */
606  /*atsam4s16c - LQFP100/BGA100*/
607  {
608  .chipid_cidr = 0x28AC0CE0,
609  .name = "at91sam4s16c",
610  .total_flash_size = 1024 * 1024,
611  .total_sram_size = 128 * 1024,
612  .n_gpnvms = 2,
613  .n_banks = 1,
614  {
615 /* .bank[0] = {*/
616  {
617  .probed = false,
618  .chip = NULL,
619  .bank = NULL,
620  .bank_number = 0,
621  .base_address = FLASH_BANK_BASE_S,
622  .controller_address = 0x400e0a00,
623  .flash_wait_states = 5,
624  .present = true,
625  .size_bytes = 1024 * 1024,
626  .nsectors = 128,
627  .sector_size = 8192,
628  .page_size = 512,
629  },
630 /* .bank[1] = {*/
631  {
632  .present = false,
633  .probed = false,
634  .bank_number = 1,
635 
636  },
637  },
638  },
639  /*at91sam4sa16c - TFBGA100/VFBGA100/LQFP100*/
640  {
641  .chipid_cidr = 0x28a70ce0,
642  .name = "at91sam4sa16c",
643  .total_flash_size = 1024 * 1024,
644  .total_sram_size = 160 * 1024,
645  .n_gpnvms = 2,
646  .n_banks = 1,
647 
648 /* .bank[0] = { */
649  {
650  {
651  .probed = false,
652  .chip = NULL,
653  .bank = NULL,
654  .bank_number = 0,
655  .base_address = FLASH_BANK_BASE_S,
656  .controller_address = 0x400e0a00,
657  .flash_wait_states = 5,
658  .present = true,
659  .size_bytes = 1024 * 1024,
660  .nsectors = 128,
661  .sector_size = 8192,
662  .page_size = 512,
663  },
664 /* .bank[1] = {*/
665  {
666  .present = false,
667  .probed = false,
668  .bank_number = 1,
669 
670  },
671  },
672  },
673  /*atsam4s16b - LQFP64/QFN64/WLCSP64*/
674  {
675  .chipid_cidr = 0x289C0CE0,
676  .name = "at91sam4s16b",
677  .total_flash_size = 1024 * 1024,
678  .total_sram_size = 128 * 1024,
679  .n_gpnvms = 2,
680  .n_banks = 1,
681  {
682 /* .bank[0] = {*/
683  {
684  .probed = false,
685  .chip = NULL,
686  .bank = NULL,
687  .bank_number = 0,
688  .base_address = FLASH_BANK_BASE_S,
689  .controller_address = 0x400e0a00,
690  .flash_wait_states = 5,
691  .present = true,
692  .size_bytes = 1024 * 1024,
693  .nsectors = 128,
694  .sector_size = 8192,
695  .page_size = 512,
696  },
697 /* .bank[1] = {*/
698  {
699  .present = false,
700  .probed = false,
701  .bank_number = 1,
702 
703  },
704  },
705  },
706  /*atsam4sa16b - LQFP64/QFN64*/
707  {
708  .chipid_cidr = 0x28970CE0,
709  .name = "at91sam4sa16b",
710  .total_flash_size = 1024 * 1024,
711  .total_sram_size = 160 * 1024,
712  .n_gpnvms = 2,
713  .n_banks = 1,
714  {
715 /* .bank[0] = {*/
716  {
717  .probed = false,
718  .chip = NULL,
719  .bank = NULL,
720  .bank_number = 0,
721  .base_address = FLASH_BANK_BASE_S,
722  .controller_address = 0x400e0a00,
723  .flash_wait_states = 5,
724  .present = true,
725  .size_bytes = 1024 * 1024,
726  .nsectors = 128,
727  .sector_size = 8192,
728  .page_size = 512,
729  },
730 /* .bank[1] = {*/
731  {
732  .present = false,
733  .probed = false,
734  .bank_number = 1,
735 
736  },
737  },
738  },
739  /*atsam4s16a - LQFP48/QFN48*/
740  {
741  .chipid_cidr = 0x288C0CE0,
742  .name = "at91sam4s16a",
743  .total_flash_size = 1024 * 1024,
744  .total_sram_size = 128 * 1024,
745  .n_gpnvms = 2,
746  .n_banks = 1,
747  {
748 /* .bank[0] = {*/
749  {
750  .probed = false,
751  .chip = NULL,
752  .bank = NULL,
753  .bank_number = 0,
754  .base_address = FLASH_BANK_BASE_S,
755  .controller_address = 0x400e0a00,
756  .flash_wait_states = 5,
757  .present = true,
758  .size_bytes = 1024 * 1024,
759  .nsectors = 128,
760  .sector_size = 8192,
761  .page_size = 512,
762  },
763 /* .bank[1] = {*/
764  {
765  .present = false,
766  .probed = false,
767  .bank_number = 1,
768 
769  },
770  },
771  },
772  /*atsam4s8c - LQFP100/BGA100*/
773  {
774  .chipid_cidr = 0x28AC0AE0,
775  .name = "at91sam4s8c",
776  .total_flash_size = 512 * 1024,
777  .total_sram_size = 128 * 1024,
778  .n_gpnvms = 2,
779  .n_banks = 1,
780  {
781 /* .bank[0] = {*/
782  {
783  .probed = false,
784  .chip = NULL,
785  .bank = NULL,
786  .bank_number = 0,
787  .base_address = FLASH_BANK_BASE_S,
788  .controller_address = 0x400e0a00,
789  .flash_wait_states = 5,
790  .present = true,
791  .size_bytes = 512 * 1024,
792  .nsectors = 64,
793  .sector_size = 8192,
794  .page_size = 512,
795  },
796 /* .bank[1] = {*/
797  {
798  .present = false,
799  .probed = false,
800  .bank_number = 1,
801 
802  },
803  },
804  },
805  /*atsam4s8b - LQFP64/QFN64/WLCSP64*/
806  {
807  .chipid_cidr = 0x289C0AE0,
808  .name = "at91sam4s8b",
809  .total_flash_size = 512 * 1024,
810  .total_sram_size = 128 * 1024,
811  .n_gpnvms = 2,
812  .n_banks = 1,
813  {
814 /* .bank[0] = {*/
815  {
816  .probed = false,
817  .chip = NULL,
818  .bank = NULL,
819  .bank_number = 0,
820  .base_address = FLASH_BANK_BASE_S,
821  .controller_address = 0x400e0a00,
822  .flash_wait_states = 5,
823  .present = true,
824  .size_bytes = 512 * 1024,
825  .nsectors = 64,
826  .sector_size = 8192,
827  .page_size = 512,
828  },
829 /* .bank[1] = {*/
830  {
831  .present = false,
832  .probed = false,
833  .bank_number = 1,
834 
835  },
836  },
837  },
838  /*atsam4s8a - LQFP48/BGA48*/
839  {
840  .chipid_cidr = 0x288C0AE0,
841  .name = "at91sam4s8a",
842  .total_flash_size = 512 * 1024,
843  .total_sram_size = 128 * 1024,
844  .n_gpnvms = 2,
845  .n_banks = 1,
846  {
847 /* .bank[0] = {*/
848  {
849  .probed = false,
850  .chip = NULL,
851  .bank = NULL,
852  .bank_number = 0,
853  .base_address = FLASH_BANK_BASE_S,
854  .controller_address = 0x400e0a00,
855  .flash_wait_states = 5,
856  .present = true,
857  .size_bytes = 512 * 1024,
858  .nsectors = 64,
859  .sector_size = 8192,
860  .page_size = 512,
861  },
862 /* .bank[1] = {*/
863  {
864  .present = false,
865  .probed = false,
866  .bank_number = 1,
867 
868  },
869  },
870  },
871 
872  /*atsam4s4c - LQFP100/BGA100*/
873  {
874  .chipid_cidr = 0x28ab09e0,
875  .name = "at91sam4s4c",
876  .total_flash_size = 256 * 1024,
877  .total_sram_size = 64 * 1024,
878  .n_gpnvms = 2,
879  .n_banks = 1,
880  {
881 /* .bank[0] = {*/
882  {
883  .probed = false,
884  .chip = NULL,
885  .bank = NULL,
886  .bank_number = 0,
887  .base_address = FLASH_BANK_BASE_S,
888  .controller_address = 0x400e0a00,
889  .flash_wait_states = 5,
890  .present = true,
891  .size_bytes = 256 * 1024,
892  .nsectors = 32,
893  .sector_size = 8192,
894  .page_size = 512,
895  },
896 /* .bank[1] = {*/
897  {
898  .present = false,
899  .probed = false,
900  .bank_number = 1,
901 
902  },
903  },
904  },
905 
906  /*atsam4s4b - LQFP64/QFN64/WLCSP64*/
907  {
908  .chipid_cidr = 0x289b09e0,
909  .name = "at91sam4s4b",
910  .total_flash_size = 256 * 1024,
911  .total_sram_size = 64 * 1024,
912  .n_gpnvms = 2,
913  .n_banks = 1,
914  {
915 /* .bank[0] = {*/
916  {
917  .probed = false,
918  .chip = NULL,
919  .bank = NULL,
920  .bank_number = 0,
921  .base_address = FLASH_BANK_BASE_S,
922  .controller_address = 0x400e0a00,
923  .flash_wait_states = 5,
924  .present = true,
925  .size_bytes = 256 * 1024,
926  .nsectors = 32,
927  .sector_size = 8192,
928  .page_size = 512,
929  },
930 /* .bank[1] = {*/
931  {
932  .present = false,
933  .probed = false,
934  .bank_number = 1,
935 
936  },
937  },
938  },
939 
940  /*atsam4s4a - LQFP48/QFN48*/
941  {
942  .chipid_cidr = 0x288b09e0,
943  .name = "at91sam4s4a",
944  .total_flash_size = 256 * 1024,
945  .total_sram_size = 64 * 1024,
946  .n_gpnvms = 2,
947  .n_banks = 1,
948  {
949 /* .bank[0] = {*/
950  {
951  .probed = false,
952  .chip = NULL,
953  .bank = NULL,
954  .bank_number = 0,
955  .base_address = FLASH_BANK_BASE_S,
956  .controller_address = 0x400e0a00,
957  .flash_wait_states = 5,
958  .present = true,
959  .size_bytes = 256 * 1024,
960  .nsectors = 32,
961  .sector_size = 8192,
962  .page_size = 512,
963  },
964 /* .bank[1] = {*/
965  {
966  .present = false,
967  .probed = false,
968  .bank_number = 1,
969 
970  },
971  },
972  },
973 
974  /*atsam4s2c - LQFP100/BGA100*/
975  {
976  .chipid_cidr = 0x28ab07e0,
977  .name = "at91sam4s2c",
978  .total_flash_size = 128 * 1024,
979  .total_sram_size = 64 * 1024,
980  .n_gpnvms = 2,
981  .n_banks = 1,
982  {
983 /* .bank[0] = {*/
984  {
985  .probed = false,
986  .chip = NULL,
987  .bank = NULL,
988  .bank_number = 0,
989  .base_address = FLASH_BANK_BASE_S,
990  .controller_address = 0x400e0a00,
991  .flash_wait_states = 5,
992  .present = true,
993  .size_bytes = 128 * 1024,
994  .nsectors = 16,
995  .sector_size = 8192,
996  .page_size = 512,
997  },
998 /* .bank[1] = {*/
999  {
1000  .present = false,
1001  .probed = false,
1002  .bank_number = 1,
1003 
1004  },
1005  },
1006  },
1007 
1008  /*atsam4s2b - LQPF64/QFN64/WLCSP64*/
1009  {
1010  .chipid_cidr = 0x289b07e0,
1011  .name = "at91sam4s2b",
1012  .total_flash_size = 128 * 1024,
1013  .total_sram_size = 64 * 1024,
1014  .n_gpnvms = 2,
1015  .n_banks = 1,
1016  {
1017 /* .bank[0] = {*/
1018  {
1019  .probed = false,
1020  .chip = NULL,
1021  .bank = NULL,
1022  .bank_number = 0,
1023  .base_address = FLASH_BANK_BASE_S,
1024  .controller_address = 0x400e0a00,
1025  .flash_wait_states = 5,
1026  .present = true,
1027  .size_bytes = 128 * 1024,
1028  .nsectors = 16,
1029  .sector_size = 8192,
1030  .page_size = 512,
1031  },
1032 /* .bank[1] = {*/
1033  {
1034  .present = false,
1035  .probed = false,
1036  .bank_number = 1,
1037 
1038  },
1039  },
1040  },
1041 
1042  /*atsam4s2a - LQFP48/QFN48*/
1043  {
1044  .chipid_cidr = 0x288b07e0,
1045  .name = "at91sam4s2a",
1046  .total_flash_size = 128 * 1024,
1047  .total_sram_size = 64 * 1024,
1048  .n_gpnvms = 2,
1049  .n_banks = 1,
1050  {
1051 /* .bank[0] = {*/
1052  {
1053  .probed = false,
1054  .chip = NULL,
1055  .bank = NULL,
1056  .bank_number = 0,
1057  .base_address = FLASH_BANK_BASE_S,
1058  .controller_address = 0x400e0a00,
1059  .flash_wait_states = 5,
1060  .present = true,
1061  .size_bytes = 128 * 1024,
1062  .nsectors = 16,
1063  .sector_size = 8192,
1064  .page_size = 512,
1065  },
1066 /* .bank[1] = {*/
1067  {
1068  .present = false,
1069  .probed = false,
1070  .bank_number = 1,
1071 
1072  },
1073  },
1074  },
1075 
1076  /*at91sam4sd32c - LQFP100/BGA100*/
1077  {
1078  .chipid_cidr = 0x29a70ee0,
1079  .name = "at91sam4sd32c",
1080  .total_flash_size = 2048 * 1024,
1081  .total_sram_size = 160 * 1024,
1082  .n_gpnvms = 3,
1083  .n_banks = 2,
1084 
1085 /* .bank[0] = { */
1086  {
1087  {
1088  .probed = false,
1089  .chip = NULL,
1090  .bank = NULL,
1091  .bank_number = 0,
1092  .base_address = FLASH_BANK0_BASE_SD,
1093  .controller_address = 0x400e0a00,
1094  .flash_wait_states = 5,
1095  .present = true,
1096  .size_bytes = 1024 * 1024,
1097  .nsectors = 128,
1098  .sector_size = 8192,
1099  .page_size = 512,
1100  },
1101 
1102 /* .bank[1] = { */
1103  {
1104  .probed = false,
1105  .chip = NULL,
1106  .bank = NULL,
1107  .bank_number = 1,
1108  .base_address = FLASH_BANK1_BASE_2048K_SD,
1109  .controller_address = 0x400e0c00,
1110  .flash_wait_states = 5,
1111  .present = true,
1112  .size_bytes = 1024 * 1024,
1113  .nsectors = 128,
1114  .sector_size = 8192,
1115  .page_size = 512,
1116  },
1117  },
1118  },
1119 
1120  /*at91sam4sd32b - LQFP64/BGA64*/
1121  {
1122  .chipid_cidr = 0x29970ee0,
1123  .name = "at91sam4sd32b",
1124  .total_flash_size = 2048 * 1024,
1125  .total_sram_size = 160 * 1024,
1126  .n_gpnvms = 3,
1127  .n_banks = 2,
1128 
1129 /* .bank[0] = { */
1130  {
1131  {
1132  .probed = false,
1133  .chip = NULL,
1134  .bank = NULL,
1135  .bank_number = 0,
1136  .base_address = FLASH_BANK0_BASE_SD,
1137  .controller_address = 0x400e0a00,
1138  .flash_wait_states = 5,
1139  .present = true,
1140  .size_bytes = 1024 * 1024,
1141  .nsectors = 128,
1142  .sector_size = 8192,
1143  .page_size = 512,
1144  },
1145 
1146 /* .bank[1] = { */
1147  {
1148  .probed = false,
1149  .chip = NULL,
1150  .bank = NULL,
1151  .bank_number = 1,
1152  .base_address = FLASH_BANK1_BASE_2048K_SD,
1153  .controller_address = 0x400e0c00,
1154  .flash_wait_states = 5,
1155  .present = true,
1156  .size_bytes = 1024 * 1024,
1157  .nsectors = 128,
1158  .sector_size = 8192,
1159  .page_size = 512,
1160  },
1161  },
1162  },
1163 
1164  /*at91sam4sd16c - LQFP100/BGA100*/
1165  {
1166  .chipid_cidr = 0x29a70ce0,
1167  .name = "at91sam4sd16c",
1168  .total_flash_size = 1024 * 1024,
1169  .total_sram_size = 160 * 1024,
1170  .n_gpnvms = 3,
1171  .n_banks = 2,
1172 
1173 /* .bank[0] = { */
1174  {
1175  {
1176  .probed = false,
1177  .chip = NULL,
1178  .bank = NULL,
1179  .bank_number = 0,
1180  .base_address = FLASH_BANK0_BASE_SD,
1181  .controller_address = 0x400e0a00,
1182  .flash_wait_states = 5,
1183  .present = true,
1184  .size_bytes = 512 * 1024,
1185  .nsectors = 64,
1186  .sector_size = 8192,
1187  .page_size = 512,
1188  },
1189 
1190 /* .bank[1] = { */
1191  {
1192  .probed = false,
1193  .chip = NULL,
1194  .bank = NULL,
1195  .bank_number = 1,
1196  .base_address = FLASH_BANK1_BASE_1024K_SD,
1197  .controller_address = 0x400e0c00,
1198  .flash_wait_states = 5,
1199  .present = true,
1200  .size_bytes = 512 * 1024,
1201  .nsectors = 64,
1202  .sector_size = 8192,
1203  .page_size = 512,
1204  },
1205  },
1206  },
1207 
1208  /*at91sam4sd16b - LQFP64/BGA64*/
1209  {
1210  .chipid_cidr = 0x29970ce0,
1211  .name = "at91sam4sd16b",
1212  .total_flash_size = 1024 * 1024,
1213  .total_sram_size = 160 * 1024,
1214  .n_gpnvms = 3,
1215  .n_banks = 2,
1216 
1217 /* .bank[0] = { */
1218  {
1219  {
1220  .probed = false,
1221  .chip = NULL,
1222  .bank = NULL,
1223  .bank_number = 0,
1224  .base_address = FLASH_BANK0_BASE_SD,
1225  .controller_address = 0x400e0a00,
1226  .flash_wait_states = 5,
1227  .present = true,
1228  .size_bytes = 512 * 1024,
1229  .nsectors = 64,
1230  .sector_size = 8192,
1231  .page_size = 512,
1232  },
1233 
1234 /* .bank[1] = { */
1235  {
1236  .probed = false,
1237  .chip = NULL,
1238  .bank = NULL,
1239  .bank_number = 1,
1240  .base_address = FLASH_BANK1_BASE_1024K_SD,
1241  .controller_address = 0x400e0c00,
1242  .flash_wait_states = 5,
1243  .present = true,
1244  .size_bytes = 512 * 1024,
1245  .nsectors = 64,
1246  .sector_size = 8192,
1247  .page_size = 512,
1248  },
1249  },
1250  },
1251 
1252  /* atsamg53n19 */
1253  {
1254  .chipid_cidr = 0x247e0ae0,
1255  .name = "atsamg53n19",
1256  .total_flash_size = 512 * 1024,
1257  .total_sram_size = 96 * 1024,
1258  .n_gpnvms = 2,
1259  .n_banks = 1,
1260 
1261 /* .bank[0] = {*/
1262  {
1263  {
1264  .probed = false,
1265  .chip = NULL,
1266  .bank = NULL,
1267  .bank_number = 0,
1268  .base_address = FLASH_BANK_BASE_S,
1269  .controller_address = 0x400e0a00,
1270  .flash_wait_states = 5,
1271  .present = true,
1272  .size_bytes = 512 * 1024,
1273  .nsectors = 64,
1274  .sector_size = 8192,
1275  .page_size = 512,
1276  },
1277 /* .bank[1] = {*/
1278  {
1279  .present = false,
1280  .probed = false,
1281  .bank_number = 1,
1282 
1283  },
1284  }
1285  },
1286 
1287  /* atsamg55g19 Rev.A */
1288  {
1289  .chipid_cidr = 0x24470ae0,
1290  .name = "atsamg55g19",
1291  .total_flash_size = 512 * 1024,
1292  .total_sram_size = 160 * 1024,
1293  .n_gpnvms = 2,
1294  .n_banks = 1,
1295 
1296  {
1297 /* .bank[0] = */
1298  {
1299  .probed = false,
1300  .chip = NULL,
1301  .bank = NULL,
1302  .bank_number = 0,
1303  .base_address = FLASH_BANK_BASE_S,
1304  .controller_address = 0x400e0a00,
1305  .flash_wait_states = 5,
1306  .present = true,
1307  .size_bytes = 512 * 1024,
1308  .nsectors = 64,
1309  .sector_size = 8192,
1310  .page_size = 512,
1311  },
1312 /* .bank[1] = */
1313  {
1314  .present = false,
1315  .probed = false,
1316  .bank_number = 1,
1317  },
1318  }
1319  },
1320 
1321  /* atsamg55g19 Rev.B */
1322  {
1323  .chipid_cidr = 0x24470ae1,
1324  .name = "atsamg55g19b",
1325  .total_flash_size = 512 * 1024,
1326  .total_sram_size = 160 * 1024,
1327  .n_gpnvms = 2,
1328  .n_banks = 1,
1329 
1330  {
1331 /* .bank[0] = */
1332  {
1333  .probed = false,
1334  .chip = NULL,
1335  .bank = NULL,
1336  .bank_number = 0,
1337  .base_address = FLASH_BANK_BASE_S,
1338  .controller_address = 0x400e0a00,
1339  .flash_wait_states = 5,
1340  .present = true,
1341  .size_bytes = 512 * 1024,
1342  .nsectors = 64,
1343  .sector_size = 8192,
1344  .page_size = 512,
1345  },
1346 /* .bank[1] = */
1347  {
1348  .present = false,
1349  .probed = false,
1350  .bank_number = 1,
1351  },
1352  }
1353  },
1354 
1355  /* atsamg55j19 Rev.A */
1356  {
1357  .chipid_cidr = 0x24570ae0,
1358  .name = "atsamg55j19",
1359  .total_flash_size = 512 * 1024,
1360  .total_sram_size = 160 * 1024,
1361  .n_gpnvms = 2,
1362  .n_banks = 1,
1363 
1364  {
1365 /* .bank[0] = */
1366  {
1367  .probed = false,
1368  .chip = NULL,
1369  .bank = NULL,
1370  .bank_number = 0,
1371  .base_address = FLASH_BANK_BASE_S,
1372  .controller_address = 0x400e0a00,
1373  .flash_wait_states = 5,
1374  .present = true,
1375  .size_bytes = 512 * 1024,
1376  .nsectors = 64,
1377  .sector_size = 8192,
1378  .page_size = 512,
1379  },
1380 /* .bank[1] = */
1381  {
1382  .present = false,
1383  .probed = false,
1384  .bank_number = 1,
1385  },
1386  }
1387  },
1388 
1389  /* atsamg55j19 Rev.B */
1390  {
1391  .chipid_cidr = 0x24570ae1,
1392  .name = "atsamg55j19b",
1393  .total_flash_size = 512 * 1024,
1394  .total_sram_size = 160 * 1024,
1395  .n_gpnvms = 2,
1396  .n_banks = 1,
1397 
1398  {
1399 /* .bank[0] = */
1400  {
1401  .probed = false,
1402  .chip = NULL,
1403  .bank = NULL,
1404  .bank_number = 0,
1405  .base_address = FLASH_BANK_BASE_S,
1406  .controller_address = 0x400e0a00,
1407  .flash_wait_states = 5,
1408  .present = true,
1409  .size_bytes = 512 * 1024,
1410  .nsectors = 64,
1411  .sector_size = 8192,
1412  .page_size = 512,
1413  },
1414 /* .bank[1] = */
1415  {
1416  .present = false,
1417  .probed = false,
1418  .bank_number = 1,
1419  },
1420  }
1421  },
1422 
1423  /* terminate */
1424  {
1425  .chipid_cidr = 0,
1426  .name = NULL,
1427  }
1428 };
1429 
1430 /* Globals above */
1431 /***********************************************************************
1432  **********************************************************************
1433  **********************************************************************
1434  **********************************************************************
1435  **********************************************************************
1436  **********************************************************************/
1437 /* *ATMEL* style code - from the SAM4 driver code */
1438 
1445 static int efc_get_status(struct sam4_bank_private *private, uint32_t *v)
1446 {
1447  int r;
1448  r = target_read_u32(private->chip->target,
1449  private->controller_address + OFFSET_EFC_FSR,
1450  v);
1451  LOG_DEBUG("Status: 0x%08x (lockerror: %d, cmderror: %d, ready: %d)",
1452  (unsigned int)(*v),
1453  ((unsigned int)((*v >> 2) & 1)),
1454  ((unsigned int)((*v >> 1) & 1)),
1455  ((unsigned int)((*v >> 0) & 1)));
1456 
1457  return r;
1458 }
1459 
1465 static int efc_get_result(struct sam4_bank_private *private, uint32_t *v)
1466 {
1467  int r;
1468  uint32_t rv;
1469  r = target_read_u32(private->chip->target,
1470  private->controller_address + OFFSET_EFC_FRR,
1471  &rv);
1472  if (v)
1473  *v = rv;
1474  LOG_DEBUG("Result: 0x%08x", ((unsigned int)(rv)));
1475  return r;
1476 }
1477 
1478 static int efc_start_command(struct sam4_bank_private *private,
1479  unsigned int command, unsigned int argument)
1480 {
1481  uint32_t n, v;
1482  int r;
1483  int retry;
1484 
1485  retry = 0;
1486 do_retry:
1487 
1488  /* Check command & argument */
1489  switch (command) {
1490  case AT91C_EFC_FCMD_WP:
1491  case AT91C_EFC_FCMD_WPL:
1492  case AT91C_EFC_FCMD_EWP:
1493  case AT91C_EFC_FCMD_EWPL:
1494  /* case AT91C_EFC_FCMD_EPL: */
1495  case AT91C_EFC_FCMD_EPA:
1496  case AT91C_EFC_FCMD_SLB:
1497  case AT91C_EFC_FCMD_CLB:
1498  n = (private->size_bytes / private->page_size);
1499  if (argument >= n)
1500  LOG_ERROR("*BUG*: Embedded flash has only %" PRIu32 " pages", n);
1501  break;
1502 
1503  case AT91C_EFC_FCMD_SFB:
1504  case AT91C_EFC_FCMD_CFB:
1505  if (argument >= private->chip->details.n_gpnvms) {
1506  LOG_ERROR("*BUG*: Embedded flash has only %d GPNVMs",
1507  private->chip->details.n_gpnvms);
1508  }
1509  break;
1510 
1511  case AT91C_EFC_FCMD_GETD:
1512  case AT91C_EFC_FCMD_EA:
1513  case AT91C_EFC_FCMD_GLB:
1514  case AT91C_EFC_FCMD_GFB:
1515  case AT91C_EFC_FCMD_STUI:
1516  case AT91C_EFC_FCMD_SPUI:
1517  if (argument != 0)
1518  LOG_ERROR("Argument is meaningless for cmd: %d", command);
1519  break;
1520  default:
1521  LOG_ERROR("Unknown command %d", command);
1522  break;
1523  }
1524 
1525  if (command == AT91C_EFC_FCMD_SPUI) {
1526  /* this is a very special situation. */
1527  /* Situation (1) - error/retry - see below */
1528  /* And we are being called recursively */
1529  /* Situation (2) - normal, finished reading unique id */
1530  } else {
1531  /* it should be "ready" */
1532  efc_get_status(private, &v);
1533  if (v & 1) {
1534  /* then it is ready */
1535  /* we go on */
1536  } else {
1537  if (retry) {
1538  /* we have done this before */
1539  /* the controller is not responding. */
1540  LOG_ERROR("flash controller(%d) is not ready! Error",
1541  private->bank_number);
1542  return ERROR_FAIL;
1543  } else {
1544  retry++;
1545  LOG_ERROR("Flash controller(%d) is not ready, attempting reset",
1546  private->bank_number);
1547  /* we do that by issuing the *STOP* command */
1548  efc_start_command(private, AT91C_EFC_FCMD_SPUI, 0);
1549  /* above is recursive, and further recursion is blocked by */
1550  /* if (command == AT91C_EFC_FCMD_SPUI) above */
1551  goto do_retry;
1552  }
1553  }
1554  }
1555 
1556  v = (0x5A << 24) | (argument << 8) | command;
1557  LOG_DEBUG("Command: 0x%08x", ((unsigned int)(v)));
1558  r = target_write_u32(private->bank->target,
1559  private->controller_address + OFFSET_EFC_FCR, v);
1560  if (r != ERROR_OK)
1561  LOG_DEBUG("Error Write failed");
1562  return r;
1563 }
1564 
1572 static int efc_perform_command(struct sam4_bank_private *private,
1573  unsigned int command,
1574  unsigned int argument,
1575  uint32_t *status)
1576 {
1577 
1578  int r;
1579  uint32_t v;
1580  int64_t ms_now, ms_end;
1581 
1582  /* default */
1583  if (status)
1584  *status = 0;
1585 
1586  r = efc_start_command(private, command, argument);
1587  if (r != ERROR_OK)
1588  return r;
1589 
1590  ms_end = 10000 + timeval_ms();
1591 
1592  do {
1593  r = efc_get_status(private, &v);
1594  if (r != ERROR_OK)
1595  return r;
1596  ms_now = timeval_ms();
1597  if (ms_now > ms_end) {
1598  /* error */
1599  LOG_ERROR("Command timeout");
1600  return ERROR_FAIL;
1601  }
1602  } while ((v & 1) == 0);
1603 
1604  /* error bits.. */
1605  if (status)
1606  *status = (v & 0x6);
1607  return ERROR_OK;
1608 
1609 }
1610 
1616 static int flashd_read_uid(struct sam4_bank_private *private)
1617 {
1618  int r;
1619  uint32_t v;
1620  int x;
1621  /* assume 0 */
1622  private->chip->cfg.unique_id[0] = 0;
1623  private->chip->cfg.unique_id[1] = 0;
1624  private->chip->cfg.unique_id[2] = 0;
1625  private->chip->cfg.unique_id[3] = 0;
1626 
1627  LOG_DEBUG("Begin");
1628  r = efc_start_command(private, AT91C_EFC_FCMD_STUI, 0);
1629  if (r < 0)
1630  return r;
1631 
1632  for (x = 0; x < 4; x++) {
1633  r = target_read_u32(private->chip->target,
1634  private->bank->base + (x * 4),
1635  &v);
1636  if (r < 0)
1637  return r;
1638  private->chip->cfg.unique_id[x] = v;
1639  }
1640 
1641  r = efc_perform_command(private, AT91C_EFC_FCMD_SPUI, 0, NULL);
1642  LOG_DEBUG("End: R=%d, id = 0x%08x, 0x%08x, 0x%08x, 0x%08x",
1643  r,
1644  (unsigned int)(private->chip->cfg.unique_id[0]),
1645  (unsigned int)(private->chip->cfg.unique_id[1]),
1646  (unsigned int)(private->chip->cfg.unique_id[2]),
1647  (unsigned int)(private->chip->cfg.unique_id[3]));
1648  return r;
1649 
1650 }
1651 
1656 static int flashd_erase_entire_bank(struct sam4_bank_private *private)
1657 {
1658  LOG_DEBUG("Here");
1659  return efc_perform_command(private, AT91C_EFC_FCMD_EA, 0, NULL);
1660 }
1661 
1669 static int flashd_erase_pages(struct sam4_bank_private *private,
1670  int first_page,
1671  int num_pages,
1672  uint32_t *status)
1673 {
1674  LOG_DEBUG("Here");
1675  uint8_t erase_pages;
1676  switch (num_pages) {
1677  case 4:
1678  erase_pages = 0x00;
1679  break;
1680  case 8:
1681  erase_pages = 0x01;
1682  break;
1683  case 16:
1684  erase_pages = 0x02;
1685  break;
1686  case 32:
1687  erase_pages = 0x03;
1688  break;
1689  default:
1690  erase_pages = 0x00;
1691  break;
1692  }
1693 
1694  /* AT91C_EFC_FCMD_EPA
1695  * According to the datasheet FARG[15:2] defines the page from which
1696  * the erase will start.This page must be modulo 4, 8, 16 or 32
1697  * according to the number of pages to erase. FARG[1:0] defines the
1698  * number of pages to be erased. Previously (firstpage << 2) was used
1699  * to conform to this, seems it should not be shifted...
1700  */
1701  return efc_perform_command(private,
1702  /* send Erase Page */
1703  AT91C_EFC_FCMD_EPA,
1704  (first_page) | erase_pages,
1705  status);
1706 }
1707 
1714 /* ------------------------------------------------------------------------------ */
1715 static int flashd_get_gpnvm(struct sam4_bank_private *private, unsigned int gpnvm, unsigned int *puthere)
1716 {
1717  uint32_t v;
1718  int r;
1719 
1720  LOG_DEBUG("Here");
1721  if (private->bank_number != 0) {
1722  LOG_ERROR("GPNVM only works with Bank0");
1723  return ERROR_FAIL;
1724  }
1725 
1726  if (gpnvm >= private->chip->details.n_gpnvms) {
1727  LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
1728  gpnvm, private->chip->details.n_gpnvms);
1729  return ERROR_FAIL;
1730  }
1731 
1732  /* Get GPNVMs status */
1733  r = efc_perform_command(private, AT91C_EFC_FCMD_GFB, 0, NULL);
1734  if (r != ERROR_OK) {
1735  LOG_ERROR("Failed");
1736  return r;
1737  }
1738 
1739  r = efc_get_result(private, &v);
1740 
1741  if (puthere) {
1742  /* Check if GPNVM is set */
1743  /* get the bit and make it a 0/1 */
1744  *puthere = (v >> gpnvm) & 1;
1745  }
1746 
1747  return r;
1748 }
1749 
1756 static int flashd_clr_gpnvm(struct sam4_bank_private *private, unsigned int gpnvm)
1757 {
1758  int r;
1759  unsigned int v;
1760 
1761  LOG_DEBUG("Here");
1762  if (private->bank_number != 0) {
1763  LOG_ERROR("GPNVM only works with Bank0");
1764  return ERROR_FAIL;
1765  }
1766 
1767  if (gpnvm >= private->chip->details.n_gpnvms) {
1768  LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
1769  gpnvm, private->chip->details.n_gpnvms);
1770  return ERROR_FAIL;
1771  }
1772 
1773  r = flashd_get_gpnvm(private, gpnvm, &v);
1774  if (r != ERROR_OK) {
1775  LOG_DEBUG("Failed: %d", r);
1776  return r;
1777  }
1778  r = efc_perform_command(private, AT91C_EFC_FCMD_CFB, gpnvm, NULL);
1779  LOG_DEBUG("End: %d", r);
1780  return r;
1781 }
1782 
1788 static int flashd_set_gpnvm(struct sam4_bank_private *private, unsigned int gpnvm)
1789 {
1790  int r;
1791  unsigned int v;
1792 
1793  if (private->bank_number != 0) {
1794  LOG_ERROR("GPNVM only works with Bank0");
1795  return ERROR_FAIL;
1796  }
1797 
1798  if (gpnvm >= private->chip->details.n_gpnvms) {
1799  LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
1800  gpnvm, private->chip->details.n_gpnvms);
1801  return ERROR_FAIL;
1802  }
1803 
1804  r = flashd_get_gpnvm(private, gpnvm, &v);
1805  if (r != ERROR_OK)
1806  return r;
1807  if (v) {
1808  /* already set */
1809  r = ERROR_OK;
1810  } else {
1811  /* set it */
1812  r = efc_perform_command(private, AT91C_EFC_FCMD_SFB, gpnvm, NULL);
1813  }
1814  return r;
1815 }
1816 
1822 static int flashd_get_lock_bits(struct sam4_bank_private *private, uint32_t *v)
1823 {
1824  int r;
1825  LOG_DEBUG("Here");
1826  r = efc_perform_command(private, AT91C_EFC_FCMD_GLB, 0, NULL);
1827  if (r == ERROR_OK) {
1828  efc_get_result(private, v);
1829  efc_get_result(private, v);
1830  efc_get_result(private, v);
1831  r = efc_get_result(private, v);
1832  }
1833  LOG_DEBUG("End: %d", r);
1834  return r;
1835 }
1836 
1844 static int flashd_unlock(struct sam4_bank_private *private,
1845  unsigned int start_sector,
1846  unsigned int end_sector)
1847 {
1848  int r;
1849  uint32_t status;
1850  uint32_t pg;
1851  uint32_t pages_per_sector;
1852 
1853  pages_per_sector = private->sector_size / private->page_size;
1854 
1855  /* Unlock all pages */
1856  while (start_sector <= end_sector) {
1857  pg = start_sector * pages_per_sector;
1858 
1859  r = efc_perform_command(private, AT91C_EFC_FCMD_CLB, pg, &status);
1860  if (r != ERROR_OK)
1861  return r;
1862  start_sector++;
1863  }
1864 
1865  return ERROR_OK;
1866 }
1867 
1874 static int flashd_lock(struct sam4_bank_private *private,
1875  unsigned int start_sector,
1876  unsigned int end_sector)
1877 {
1878  uint32_t status;
1879  uint32_t pg;
1880  uint32_t pages_per_sector;
1881  int r;
1882 
1883  pages_per_sector = private->sector_size / private->page_size;
1884 
1885  /* Lock all pages */
1886  while (start_sector <= end_sector) {
1887  pg = start_sector * pages_per_sector;
1888 
1889  r = efc_perform_command(private, AT91C_EFC_FCMD_SLB, pg, &status);
1890  if (r != ERROR_OK)
1891  return r;
1892  start_sector++;
1893  }
1894  return ERROR_OK;
1895 }
1896 
1897 /****** END SAM4 CODE ********/
1898 
1899 /* begin helpful debug code */
1900 /* print the fieldname, the field value, in dec & hex, and return field value */
1901 static uint32_t sam4_reg_fieldname(struct sam4_chip *chip,
1902  const char *regname,
1903  uint32_t value,
1904  unsigned int shift,
1905  unsigned int width)
1906 {
1907  uint32_t v;
1908  int hwidth, dwidth;
1909 
1910 
1911  /* extract the field */
1912  v = value >> shift;
1913  v = v & ((1 << width)-1);
1914  if (width <= 16) {
1915  hwidth = 4;
1916  dwidth = 5;
1917  } else {
1918  hwidth = 8;
1919  dwidth = 12;
1920  }
1921 
1922  /* show the basics */
1923  LOG_USER_N("\t%*s: %*" PRIu32 " [0x%0*" PRIx32 "] ",
1924  REG_NAME_WIDTH, regname,
1925  dwidth, v,
1926  hwidth, v);
1927  return v;
1928 }
1929 
1930 static const char _unknown[] = "unknown";
1931 static const char *const eproc_names[] = {
1932  "Cortex-M7", /* 0 */
1933  "arm946es", /* 1 */
1934  "arm7tdmi", /* 2 */
1935  "Cortex-M3", /* 3 */
1936  "arm920t", /* 4 */
1937  "arm926ejs", /* 5 */
1938  "Cortex-A5", /* 6 */
1939  "Cortex-M4", /* 7 */
1940  _unknown, /* 8 */
1941  _unknown, /* 9 */
1942  _unknown, /* 10 */
1943  _unknown, /* 11 */
1944  _unknown, /* 12 */
1945  _unknown, /* 13 */
1946  _unknown, /* 14 */
1947  _unknown, /* 15 */
1948 };
1949 
1950 #define nvpsize2 nvpsize /* these two tables are identical */
1951 static const char *const nvpsize[] = {
1952  "none", /* 0 */
1953  "8K bytes", /* 1 */
1954  "16K bytes", /* 2 */
1955  "32K bytes", /* 3 */
1956  _unknown, /* 4 */
1957  "64K bytes", /* 5 */
1958  _unknown, /* 6 */
1959  "128K bytes", /* 7 */
1960  "160K bytes", /* 8 */
1961  "256K bytes", /* 9 */
1962  "512K bytes", /* 10 */
1963  _unknown, /* 11 */
1964  "1024K bytes", /* 12 */
1965  _unknown, /* 13 */
1966  "2048K bytes", /* 14 */
1967  _unknown, /* 15 */
1968 };
1969 
1970 static const char *const sramsize[] = {
1971  "48K Bytes", /* 0 */
1972  "1K Bytes", /* 1 */
1973  "2K Bytes", /* 2 */
1974  "6K Bytes", /* 3 */
1975  "112K Bytes", /* 4 */
1976  "4K Bytes", /* 5 */
1977  "80K Bytes", /* 6 */
1978  "160K Bytes", /* 7 */
1979  "8K Bytes", /* 8 */
1980  "16K Bytes", /* 9 */
1981  "32K Bytes", /* 10 */
1982  "64K Bytes", /* 11 */
1983  "128K Bytes", /* 12 */
1984  "256K Bytes", /* 13 */
1985  "96K Bytes", /* 14 */
1986  "512K Bytes", /* 15 */
1987 
1988 };
1989 
1990 static const struct archnames { unsigned int value; const char *name; } archnames[] = {
1991  { 0x19, "AT91SAM9xx Series" },
1992  { 0x29, "AT91SAM9XExx Series" },
1993  { 0x34, "AT91x34 Series" },
1994  { 0x37, "CAP7 Series" },
1995  { 0x39, "CAP9 Series" },
1996  { 0x3B, "CAP11 Series" },
1997  { 0x3C, "ATSAM4E" },
1998  { 0x40, "AT91x40 Series" },
1999  { 0x42, "AT91x42 Series" },
2000  { 0x43, "SAMG51 Series"
2001  },
2002  { 0x44, "SAMG55 Series (49-pin WLCSP)" },
2003  { 0x45, "SAMG55 Series (64-pin)" },
2004  { 0x47, "SAMG53 Series"
2005  },
2006  { 0x55, "AT91x55 Series" },
2007  { 0x60, "AT91SAM7Axx Series" },
2008  { 0x61, "AT91SAM7AQxx Series" },
2009  { 0x63, "AT91x63 Series" },
2010  { 0x64, "SAM4CxxC (100-pin version)" },
2011  { 0x66, "SAM4CxxE (144-pin version)" },
2012  { 0x70, "AT91SAM7Sxx Series" },
2013  { 0x71, "AT91SAM7XCxx Series" },
2014  { 0x72, "AT91SAM7SExx Series" },
2015  { 0x73, "AT91SAM7Lxx Series" },
2016  { 0x75, "AT91SAM7Xxx Series" },
2017  { 0x76, "AT91SAM7SLxx Series" },
2018  { 0x80, "ATSAM3UxC Series (100-pin version)" },
2019  { 0x81, "ATSAM3UxE Series (144-pin version)" },
2020  { 0x83, "ATSAM3A/SAM4A xC Series (100-pin version)"},
2021  { 0x84, "ATSAM3X/SAM4X xC Series (100-pin version)"},
2022  { 0x85, "ATSAM3X/SAM4X xE Series (144-pin version)"},
2023  { 0x86, "ATSAM3X/SAM4X xG Series (208/217-pin version)" },
2024  { 0x88, "ATSAM3S/SAM4S xA Series (48-pin version)" },
2025  { 0x89, "ATSAM3S/SAM4S xB Series (64-pin version)" },
2026  { 0x8A, "ATSAM3S/SAM4S xC Series (100-pin version)"},
2027  { 0x92, "AT91x92 Series" },
2028  { 0x93, "ATSAM3NxA Series (48-pin version)" },
2029  { 0x94, "ATSAM3NxB Series (64-pin version)" },
2030  { 0x95, "ATSAM3NxC Series (100-pin version)" },
2031  { 0x98, "ATSAM3SDxA Series (48-pin version)" },
2032  { 0x99, "ATSAM3SDxB Series (64-pin version)" },
2033  { 0x9A, "ATSAM3SDxC Series (100-pin version)" },
2034  { 0xA5, "ATSAM5A" },
2035  { 0xF0, "AT75Cxx Series" },
2036  { -1, NULL },
2037 };
2038 
2039 static const char *const nvptype[] = {
2040  "rom", /* 0 */
2041  "romless or onchip flash", /* 1 */
2042  "embedded flash memory",/* 2 */
2043  "rom(nvpsiz) + embedded flash (nvpsiz2)", /* 3 */
2044  "sram emulating flash", /* 4 */
2045  _unknown, /* 5 */
2046  _unknown, /* 6 */
2047  _unknown, /* 7 */
2048 };
2049 
2050 static const char *_yes_or_no(uint32_t v)
2051 {
2052  if (v)
2053  return "YES";
2054  else
2055  return "NO";
2056 }
2057 
2058 static const char *const _rc_freq[] = {
2059  "4 MHz", "8 MHz", "12 MHz", "reserved"
2060 };
2061 
2062 static void sam4_explain_ckgr_mor(struct sam4_chip *chip)
2063 {
2064  uint32_t v;
2065  uint32_t rcen;
2066 
2067  v = sam4_reg_fieldname(chip, "MOSCXTEN", chip->cfg.CKGR_MOR, 0, 1);
2068  LOG_USER("(main xtal enabled: %s)", _yes_or_no(v));
2069  v = sam4_reg_fieldname(chip, "MOSCXTBY", chip->cfg.CKGR_MOR, 1, 1);
2070  LOG_USER("(main osc bypass: %s)", _yes_or_no(v));
2071  rcen = sam4_reg_fieldname(chip, "MOSCRCEN", chip->cfg.CKGR_MOR, 3, 1);
2072  LOG_USER("(onchip RC-OSC enabled: %s)", _yes_or_no(rcen));
2073  v = sam4_reg_fieldname(chip, "MOSCRCF", chip->cfg.CKGR_MOR, 4, 3);
2074  LOG_USER("(onchip RC-OSC freq: %s)", _rc_freq[v]);
2075 
2076  chip->cfg.rc_freq = 0;
2077  if (rcen) {
2078  switch (v) {
2079  case 0:
2080  chip->cfg.rc_freq = 4 * 1000 * 1000;
2081  break;
2082  case 1:
2083  chip->cfg.rc_freq = 8 * 1000 * 1000;
2084  break;
2085  case 2:
2086  chip->cfg.rc_freq = 12 * 1000 * 1000;
2087  break;
2088  default:
2089  chip->cfg.rc_freq = 0;
2090  break;
2091  }
2092  }
2093 
2094  v = sam4_reg_fieldname(chip, "MOSCXTST", chip->cfg.CKGR_MOR, 8, 8);
2095  LOG_USER("(startup clks, time= %f uSecs)",
2096  ((float)(v * 1000000)) / ((float)(chip->cfg.slow_freq)));
2097  v = sam4_reg_fieldname(chip, "MOSCSEL", chip->cfg.CKGR_MOR, 24, 1);
2098  LOG_USER("(mainosc source: %s)",
2099  v ? "external xtal" : "internal RC");
2100 
2101  v = sam4_reg_fieldname(chip, "CFDEN", chip->cfg.CKGR_MOR, 25, 1);
2102  LOG_USER("(clock failure enabled: %s)",
2103  _yes_or_no(v));
2104 }
2105 
2106 static void sam4_explain_chipid_cidr(struct sam4_chip *chip)
2107 {
2108  int x;
2109  uint32_t v;
2110  const char *cp;
2111 
2112  sam4_reg_fieldname(chip, "Version", chip->cfg.CHIPID_CIDR, 0, 5);
2113  LOG_USER_N("\n");
2114 
2115  v = sam4_reg_fieldname(chip, "EPROC", chip->cfg.CHIPID_CIDR, 5, 3);
2116  LOG_USER("%s", eproc_names[v]);
2117 
2118  v = sam4_reg_fieldname(chip, "NVPSIZE", chip->cfg.CHIPID_CIDR, 8, 4);
2119  LOG_USER("%s", nvpsize[v]);
2120 
2121  v = sam4_reg_fieldname(chip, "NVPSIZE2", chip->cfg.CHIPID_CIDR, 12, 4);
2122  LOG_USER("%s", nvpsize2[v]);
2123 
2124  v = sam4_reg_fieldname(chip, "SRAMSIZE", chip->cfg.CHIPID_CIDR, 16, 4);
2125  LOG_USER("%s", sramsize[v]);
2126 
2127  v = sam4_reg_fieldname(chip, "ARCH", chip->cfg.CHIPID_CIDR, 20, 8);
2128  cp = _unknown;
2129  for (x = 0; archnames[x].name; x++) {
2130  if (v == archnames[x].value) {
2131  cp = archnames[x].name;
2132  break;
2133  }
2134  }
2135 
2136  LOG_USER("%s", cp);
2137 
2138  v = sam4_reg_fieldname(chip, "NVPTYP", chip->cfg.CHIPID_CIDR, 28, 3);
2139  LOG_USER("%s", nvptype[v]);
2140 
2141  v = sam4_reg_fieldname(chip, "EXTID", chip->cfg.CHIPID_CIDR, 31, 1);
2142  LOG_USER("(exists: %s)", _yes_or_no(v));
2143 }
2144 
2145 static void sam4_explain_ckgr_mcfr(struct sam4_chip *chip)
2146 {
2147  uint32_t v;
2148 
2149  v = sam4_reg_fieldname(chip, "MAINFRDY", chip->cfg.CKGR_MCFR, 16, 1);
2150  LOG_USER("(main ready: %s)", _yes_or_no(v));
2151 
2152  v = sam4_reg_fieldname(chip, "MAINF", chip->cfg.CKGR_MCFR, 0, 16);
2153 
2154  v = (v * chip->cfg.slow_freq) / 16;
2155  chip->cfg.mainosc_freq = v;
2156 
2157  LOG_USER("(%3.03f Mhz (%" PRIu32 ".%03" PRIu32 "khz slowclk)",
2158  _tomhz(v),
2159  (uint32_t)(chip->cfg.slow_freq / 1000),
2160  (uint32_t)(chip->cfg.slow_freq % 1000));
2161 }
2162 
2163 static void sam4_explain_ckgr_plla(struct sam4_chip *chip)
2164 {
2165  uint32_t mula, diva;
2166 
2167  diva = sam4_reg_fieldname(chip, "DIVA", chip->cfg.CKGR_PLLAR, 0, 8);
2168  LOG_USER_N("\n");
2169  mula = sam4_reg_fieldname(chip, "MULA", chip->cfg.CKGR_PLLAR, 16, 11);
2170  LOG_USER_N("\n");
2171  chip->cfg.plla_freq = 0;
2172  if (mula == 0)
2173  LOG_USER("\tPLLA Freq: (Disabled,mula = 0)");
2174  else if (diva == 0)
2175  LOG_USER("\tPLLA Freq: (Disabled,diva = 0)");
2176  else if (diva >= 1) {
2177  chip->cfg.plla_freq = (chip->cfg.mainosc_freq * (mula + 1) / diva);
2178  LOG_USER("\tPLLA Freq: %3.03f MHz",
2179  _tomhz(chip->cfg.plla_freq));
2180  }
2181 }
2182 
2183 static void sam4_explain_mckr(struct sam4_chip *chip)
2184 {
2185  uint32_t css, pres, fin = 0;
2186  int pdiv = 0;
2187  const char *cp = NULL;
2188 
2189  css = sam4_reg_fieldname(chip, "CSS", chip->cfg.PMC_MCKR, 0, 2);
2190  switch (css & 3) {
2191  case 0:
2192  fin = chip->cfg.slow_freq;
2193  cp = "slowclk";
2194  break;
2195  case 1:
2196  fin = chip->cfg.mainosc_freq;
2197  cp = "mainosc";
2198  break;
2199  case 2:
2200  fin = chip->cfg.plla_freq;
2201  cp = "plla";
2202  break;
2203  case 3:
2204  if (chip->cfg.CKGR_UCKR & (1 << 16)) {
2205  fin = 480 * 1000 * 1000;
2206  cp = "upll";
2207  } else {
2208  fin = 0;
2209  cp = "upll (*ERROR* UPLL is disabled)";
2210  }
2211  break;
2212  default:
2213  assert(0);
2214  break;
2215  }
2216 
2217  LOG_USER("%s (%3.03f Mhz)",
2218  cp,
2219  _tomhz(fin));
2220  pres = sam4_reg_fieldname(chip, "PRES", chip->cfg.PMC_MCKR, 4, 3);
2221  switch (pres & 0x07) {
2222  case 0:
2223  pdiv = 1;
2224  cp = "selected clock";
2225  break;
2226  case 1:
2227  pdiv = 2;
2228  cp = "clock/2";
2229  break;
2230  case 2:
2231  pdiv = 4;
2232  cp = "clock/4";
2233  break;
2234  case 3:
2235  pdiv = 8;
2236  cp = "clock/8";
2237  break;
2238  case 4:
2239  pdiv = 16;
2240  cp = "clock/16";
2241  break;
2242  case 5:
2243  pdiv = 32;
2244  cp = "clock/32";
2245  break;
2246  case 6:
2247  pdiv = 64;
2248  cp = "clock/64";
2249  break;
2250  case 7:
2251  pdiv = 6;
2252  cp = "clock/6";
2253  break;
2254  default:
2255  assert(0);
2256  break;
2257  }
2258  LOG_USER("(%s)", cp);
2259  fin = fin / pdiv;
2260  /* sam4 has a *SINGLE* clock - */
2261  /* other at91 series parts have divisors for these. */
2262  chip->cfg.cpu_freq = fin;
2263  chip->cfg.mclk_freq = fin;
2264  chip->cfg.fclk_freq = fin;
2265  LOG_USER("\t\tResult CPU Freq: %3.03f",
2266  _tomhz(fin));
2267 }
2268 
2269 #if 0
2270 static struct sam4_chip *target2sam4(struct target *target)
2271 {
2272  struct sam4_chip *chip;
2273 
2274  if (!target)
2275  return NULL;
2276 
2277  chip = all_sam4_chips;
2278  while (chip) {
2279  if (chip->target == target)
2280  break; /* return below */
2281  else
2282  chip = chip->next;
2283  }
2284  return chip;
2285 }
2286 #endif
2287 
2288 static uint32_t *sam4_get_reg_ptr(struct sam4_cfg *cfg, const struct sam4_reg_list *list)
2289 {
2290  /* this function exists to help */
2291  /* keep funky offsetof() errors */
2292  /* and casting from causing bugs */
2293 
2294  /* By using prototypes - we can detect what would */
2295  /* be casting errors. */
2296 
2297  return (uint32_t *)(void *)(((char *)(cfg)) + list->struct_offset);
2298 }
2299 
2300 
2301 #define SAM4_ENTRY(NAME, FUNC) { .address = SAM4_ ## NAME, .struct_offset = offsetof( \
2302  struct sam4_cfg, \
2303  NAME), # NAME, FUNC }
2304 static const struct sam4_reg_list sam4_all_regs[] = {
2305  SAM4_ENTRY(CKGR_MOR, sam4_explain_ckgr_mor),
2306  SAM4_ENTRY(CKGR_MCFR, sam4_explain_ckgr_mcfr),
2307  SAM4_ENTRY(CKGR_PLLAR, sam4_explain_ckgr_plla),
2308  SAM4_ENTRY(CKGR_UCKR, NULL),
2309  SAM4_ENTRY(PMC_FSMR, NULL),
2310  SAM4_ENTRY(PMC_FSPR, NULL),
2311  SAM4_ENTRY(PMC_IMR, NULL),
2312  SAM4_ENTRY(PMC_MCKR, sam4_explain_mckr),
2313  SAM4_ENTRY(PMC_PCK0, NULL),
2314  SAM4_ENTRY(PMC_PCK1, NULL),
2315  SAM4_ENTRY(PMC_PCK2, NULL),
2316  SAM4_ENTRY(PMC_PCSR, NULL),
2317  SAM4_ENTRY(PMC_SCSR, NULL),
2318  SAM4_ENTRY(PMC_SR, NULL),
2319  SAM4_ENTRY(CHIPID_CIDR, sam4_explain_chipid_cidr),
2320  SAM4_ENTRY(CHIPID_EXID, NULL),
2321  /* TERMINATE THE LIST */
2322  { .name = NULL }
2323 };
2324 #undef SAM4_ENTRY
2325 
2326 static struct sam4_bank_private *get_sam4_bank_private(struct flash_bank *bank)
2327 {
2328  return bank->driver_priv;
2329 }
2330 
2335 static const struct sam4_reg_list *sam4_get_reg(struct sam4_chip *chip, uint32_t *goes_here)
2336 {
2337  const struct sam4_reg_list *reg;
2338 
2339  reg = &(sam4_all_regs[0]);
2340  while (reg->name) {
2341  uint32_t *possible;
2342 
2343  /* calculate where this one go.. */
2344  /* it is "possibly" this register. */
2345 
2346  possible = ((uint32_t *)(void *)(((char *)(&(chip->cfg))) + reg->struct_offset));
2347 
2348  /* well? Is it this register */
2349  if (possible == goes_here) {
2350  /* Jump for joy! */
2351  return reg;
2352  }
2353 
2354  /* next... */
2355  reg++;
2356  }
2357  /* This is *TOTAL*PANIC* - we are totally screwed. */
2358  LOG_ERROR("INVALID SAM4 REGISTER");
2359  return NULL;
2360 }
2361 
2362 static int sam4_read_this_reg(struct sam4_chip *chip, uint32_t *goes_here)
2363 {
2364  const struct sam4_reg_list *reg;
2365  int r;
2366 
2367  reg = sam4_get_reg(chip, goes_here);
2368  if (!reg)
2369  return ERROR_FAIL;
2370 
2371  r = target_read_u32(chip->target, reg->address, goes_here);
2372  if (r != ERROR_OK) {
2373  LOG_ERROR("Cannot read SAM4 register: %s @ 0x%08" PRIx32 ", Err: %d",
2374  reg->name, reg->address, r);
2375  }
2376  return r;
2377 }
2378 
2379 static int sam4_read_all_regs(struct sam4_chip *chip)
2380 {
2381  int r;
2382  const struct sam4_reg_list *reg;
2383 
2384  reg = &(sam4_all_regs[0]);
2385  while (reg->name) {
2386  r = sam4_read_this_reg(chip,
2387  sam4_get_reg_ptr(&(chip->cfg), reg));
2388  if (r != ERROR_OK) {
2389  LOG_ERROR("Cannot read SAM4 register: %s @ 0x%08" PRIx32 ", Error: %d",
2390  reg->name, reg->address, r);
2391  return r;
2392  }
2393  reg++;
2394  }
2395 
2396  return ERROR_OK;
2397 }
2398 
2399 static int sam4_get_info(struct sam4_chip *chip)
2400 {
2401  const struct sam4_reg_list *reg;
2402  uint32_t regval;
2403  int r;
2404 
2405  r = sam4_read_all_regs(chip);
2406  if (r != ERROR_OK)
2407  return r;
2408 
2409  reg = &(sam4_all_regs[0]);
2410  while (reg->name) {
2411  /* display all regs */
2412  LOG_DEBUG("Start: %s", reg->name);
2413  regval = *sam4_get_reg_ptr(&(chip->cfg), reg);
2414  LOG_USER("%*s: [0x%08" PRIx32 "] -> 0x%08" PRIx32,
2415  REG_NAME_WIDTH,
2416  reg->name,
2417  reg->address,
2418  regval);
2419  if (reg->explain_func)
2420  (*(reg->explain_func))(chip);
2421  LOG_DEBUG("End: %s", reg->name);
2422  reg++;
2423  }
2424  LOG_USER(" rc-osc: %3.03f MHz", _tomhz(chip->cfg.rc_freq));
2425  LOG_USER(" mainosc: %3.03f MHz", _tomhz(chip->cfg.mainosc_freq));
2426  LOG_USER(" plla: %3.03f MHz", _tomhz(chip->cfg.plla_freq));
2427  LOG_USER(" cpu-freq: %3.03f MHz", _tomhz(chip->cfg.cpu_freq));
2428  LOG_USER("mclk-freq: %3.03f MHz", _tomhz(chip->cfg.mclk_freq));
2429 
2430  LOG_USER(" UniqueId: 0x%08" PRIx32 " 0x%08" PRIx32 " 0x%08" PRIx32 " 0x%08"PRIx32,
2431  chip->cfg.unique_id[0],
2432  chip->cfg.unique_id[1],
2433  chip->cfg.unique_id[2],
2434  chip->cfg.unique_id[3]);
2435 
2436  return ERROR_OK;
2437 }
2438 
2439 static int sam4_protect_check(struct flash_bank *bank)
2440 {
2441  int r;
2442  uint32_t v[4] = {0};
2443  unsigned int x;
2444  struct sam4_bank_private *private;
2445 
2446  LOG_DEBUG("Begin");
2447  if (bank->target->state != TARGET_HALTED) {
2448  LOG_ERROR("Target not halted");
2449  return ERROR_TARGET_NOT_HALTED;
2450  }
2451 
2452  private = get_sam4_bank_private(bank);
2453  if (!private) {
2454  LOG_ERROR("no private for this bank?");
2455  return ERROR_FAIL;
2456  }
2457  if (!(private->probed))
2458  return ERROR_FLASH_BANK_NOT_PROBED;
2459 
2460  r = flashd_get_lock_bits(private, v);
2461  if (r != ERROR_OK) {
2462  LOG_DEBUG("Failed: %d", r);
2463  return r;
2464  }
2465 
2466  for (x = 0; x < private->nsectors; x++)
2467  bank->sectors[x].is_protected = (!!(v[x >> 5] & (1 << (x % 32))));
2468  LOG_DEBUG("Done");
2469  return ERROR_OK;
2470 }
2471 
2472 FLASH_BANK_COMMAND_HANDLER(sam4_flash_bank_command)
2473 {
2474  struct sam4_chip *chip;
2475 
2476  chip = all_sam4_chips;
2477 
2478  /* is this an existing chip? */
2479  while (chip) {
2480  if (chip->target == bank->target)
2481  break;
2482  chip = chip->next;
2483  }
2484 
2485  if (!chip) {
2486  /* this is a *NEW* chip */
2487  chip = calloc(1, sizeof(struct sam4_chip));
2488  if (!chip) {
2489  LOG_ERROR("NO RAM!");
2490  return ERROR_FAIL;
2491  }
2492  chip->target = bank->target;
2493  /* insert at head */
2494  chip->next = all_sam4_chips;
2495  all_sam4_chips = chip;
2496  chip->target = bank->target;
2497  /* assumption is this runs at 32khz */
2498  chip->cfg.slow_freq = 32768;
2499  chip->probed = false;
2500  }
2501 
2502  switch (bank->base) {
2503  /* at91sam4s series only has bank 0*/
2504  /* at91sam4sd series has the same address for bank 0 (FLASH_BANK0_BASE_SD)*/
2505  case FLASH_BANK_BASE_S:
2506  case FLASH_BANK_BASE_C:
2507  bank->driver_priv = &chip->details.bank[0];
2508  bank->bank_number = 0;
2509  chip->details.bank[0].chip = chip;
2510  chip->details.bank[0].bank = bank;
2511  break;
2512 
2513  /* Bank 1 of at91sam4sd/at91sam4c32 series */
2514  case FLASH_BANK1_BASE_1024K_SD:
2515  case FLASH_BANK1_BASE_2048K_SD:
2516  case FLASH_BANK1_BASE_C32:
2517  bank->driver_priv = &chip->details.bank[1];
2518  bank->bank_number = 1;
2519  chip->details.bank[1].chip = chip;
2520  chip->details.bank[1].bank = bank;
2521  break;
2522 
2523  default:
2524  LOG_ERROR("Address " TARGET_ADDR_FMT " invalid bank address (try 0x%08x"
2525  "[at91sam4s series] )",
2526  bank->base,
2527  FLASH_BANK_BASE_S);
2528  return ERROR_FAIL;
2529  }
2530 
2531  /* we initialize after probing. */
2532  return ERROR_OK;
2533 }
2534 
2540 static void sam4_free_driver_priv(struct flash_bank *bank)
2541 {
2542  struct sam4_chip *chip = all_sam4_chips;
2543  while (chip) {
2544  struct sam4_chip *next = chip->next;
2545  free(chip);
2546  chip = next;
2547  }
2548  all_sam4_chips = NULL;
2549 }
2550 
2551 static int sam4_get_details(struct sam4_bank_private *private)
2552 {
2553  const struct sam4_chip_details *details;
2554  struct sam4_chip *chip;
2555  struct flash_bank *saved_banks[SAM4_MAX_FLASH_BANKS];
2556  unsigned int x;
2557 
2558  LOG_DEBUG("Begin");
2559  details = all_sam4_details;
2560  while (details->name) {
2561  /* Compare cidr without version bits */
2562  if (details->chipid_cidr == (private->chip->cfg.CHIPID_CIDR & 0xFFFFFFE0))
2563  break;
2564  else
2565  details++;
2566  }
2567  if (!details->name) {
2568  LOG_ERROR("SAM4 ChipID 0x%08x not found in table (perhaps you can ID this chip?)",
2569  (unsigned int)(private->chip->cfg.CHIPID_CIDR));
2570  /* Help the victim, print details about the chip */
2571  LOG_INFO("SAM4 CHIPID_CIDR: 0x%08" PRIx32 " decodes as follows",
2572  private->chip->cfg.CHIPID_CIDR);
2573  sam4_explain_chipid_cidr(private->chip);
2574  return ERROR_FAIL;
2575  } else {
2576  LOG_DEBUG("SAM4 Found chip %s, CIDR 0x%08" PRIx32, details->name, details->chipid_cidr);
2577  }
2578 
2579  /* DANGER: THERE ARE DRAGONS HERE */
2580 
2581  /* get our chip - it is going */
2582  /* to be over-written shortly */
2583  chip = private->chip;
2584 
2585  /* Note that, in reality: */
2586  /* */
2587  /* private = &(chip->details.bank[0]) */
2588  /* or private = &(chip->details.bank[1]) */
2589  /* */
2590 
2591  /* save the "bank" pointers */
2592  for (x = 0; x < SAM4_MAX_FLASH_BANKS; x++)
2593  saved_banks[x] = chip->details.bank[x].bank;
2594 
2595  /* Overwrite the "details" structure. */
2596  memcpy(&(private->chip->details),
2597  details,
2598  sizeof(private->chip->details));
2599 
2600  /* now fix the ghosted pointers */
2601  for (x = 0; x < SAM4_MAX_FLASH_BANKS; x++) {
2602  chip->details.bank[x].chip = chip;
2603  chip->details.bank[x].bank = saved_banks[x];
2604  }
2605 
2606  /* update the *BANK*SIZE* */
2607 
2608  LOG_DEBUG("End");
2609  return ERROR_OK;
2610 }
2611 
2612 static int sam4_info(struct flash_bank *bank, struct command_invocation *cmd)
2613 {
2614  struct sam4_bank_private *private;
2615  int k = bank->size / 1024;
2616 
2617  private = get_sam4_bank_private(bank);
2618  if (!private)
2619  return ERROR_FAIL;
2620 
2621  command_print_sameline(cmd, "%s bank %d: %d kB at " TARGET_ADDR_FMT,
2622  private->chip->details.name,
2623  private->bank_number,
2624  k,
2625  bank->base);
2626 
2627  return ERROR_OK;
2628 }
2629 
2630 static int sam4_probe(struct flash_bank *bank)
2631 {
2632  int r;
2633  struct sam4_bank_private *private;
2634 
2635 
2636  LOG_DEBUG("Begin: Bank: %u", bank->bank_number);
2637  if (bank->target->state != TARGET_HALTED) {
2638  LOG_ERROR("Target not halted");
2639  return ERROR_TARGET_NOT_HALTED;
2640  }
2641 
2642  private = get_sam4_bank_private(bank);
2643  if (!private) {
2644  LOG_ERROR("Invalid/unknown bank number");
2645  return ERROR_FAIL;
2646  }
2647 
2648  r = sam4_read_all_regs(private->chip);
2649  if (r != ERROR_OK)
2650  return r;
2651 
2652  LOG_DEBUG("Here");
2653  if (private->chip->probed)
2654  r = sam4_get_info(private->chip);
2655  else
2656  r = sam4_get_details(private);
2657  if (r != ERROR_OK)
2658  return r;
2659 
2660  /* update the flash bank size */
2661  for (unsigned int x = 0; x < SAM4_MAX_FLASH_BANKS; x++) {
2662  if (bank->base == private->chip->details.bank[x].base_address) {
2663  bank->size = private->chip->details.bank[x].size_bytes;
2664  LOG_DEBUG("SAM4 Set flash bank to " TARGET_ADDR_FMT " - "
2665  TARGET_ADDR_FMT ", idx %d", bank->base,
2666  bank->base + bank->size, x);
2667  break;
2668  }
2669  }
2670 
2671  if (!bank->sectors) {
2672  bank->sectors = calloc(private->nsectors, (sizeof((bank->sectors)[0])));
2673  if (!bank->sectors) {
2674  LOG_ERROR("No memory!");
2675  return ERROR_FAIL;
2676  }
2677  bank->num_sectors = private->nsectors;
2678 
2679  for (unsigned int x = 0; x < bank->num_sectors; x++) {
2680  bank->sectors[x].size = private->sector_size;
2681  bank->sectors[x].offset = x * (private->sector_size);
2682  /* mark as unknown */
2683  bank->sectors[x].is_erased = -1;
2684  bank->sectors[x].is_protected = -1;
2685  }
2686  }
2687 
2688  private->probed = true;
2689 
2690  r = sam4_protect_check(bank);
2691  if (r != ERROR_OK)
2692  return r;
2693 
2694  LOG_DEBUG("Bank = %d, nbanks = %d",
2695  private->bank_number, private->chip->details.n_banks);
2696  if ((private->bank_number + 1) == private->chip->details.n_banks) {
2697  /* read unique id, */
2698  /* it appears to be associated with the *last* flash bank. */
2699  flashd_read_uid(private);
2700  }
2701 
2702  return r;
2703 }
2704 
2705 static int sam4_auto_probe(struct flash_bank *bank)
2706 {
2707  struct sam4_bank_private *private;
2708 
2709  private = get_sam4_bank_private(bank);
2710  if (private && private->probed)
2711  return ERROR_OK;
2712 
2713  return sam4_probe(bank);
2714 }
2715 
2716 static int sam4_erase(struct flash_bank *bank, unsigned int first,
2717  unsigned int last)
2718 {
2719  struct sam4_bank_private *private;
2720  int r;
2721  int page_count;
2722  /*16 pages equals 8KB - Same size as a lock region*/
2723  page_count = 16;
2724  uint32_t status;
2725 
2726  LOG_DEBUG("Here");
2727  if (bank->target->state != TARGET_HALTED) {
2728  LOG_ERROR("Target not halted");
2729  return ERROR_TARGET_NOT_HALTED;
2730  }
2731 
2732  r = sam4_auto_probe(bank);
2733  if (r != ERROR_OK) {
2734  LOG_DEBUG("Here,r=%d", r);
2735  return r;
2736  }
2737 
2738  private = get_sam4_bank_private(bank);
2739  if (!(private->probed))
2740  return ERROR_FLASH_BANK_NOT_PROBED;
2741 
2742  if ((first == 0) && ((last + 1) == private->nsectors)) {
2743  /* whole chip */
2744  LOG_DEBUG("Here");
2745  return flashd_erase_entire_bank(private);
2746  }
2747  LOG_INFO("sam4 does not auto-erase while programming (Erasing relevant sectors)");
2748  LOG_INFO("sam4 First: 0x%08x Last: 0x%08x", first, last);
2749  for (unsigned int i = first; i <= last; i++) {
2750  /*16 pages equals 8KB - Same size as a lock region*/
2751  r = flashd_erase_pages(private, (i * page_count), page_count, &status);
2752  LOG_INFO("Erasing sector: 0x%08x", i);
2753  if (r != ERROR_OK)
2754  LOG_ERROR("SAM4: Error performing Erase page @ lock region number %u",
2755  i);
2756  if (status & (1 << 2)) {
2757  LOG_ERROR("SAM4: Lock Region %u is locked", i);
2758  return ERROR_FAIL;
2759  }
2760  if (status & (1 << 1)) {
2761  LOG_ERROR("SAM4: Flash Command error @lock region %u", i);
2762  return ERROR_FAIL;
2763  }
2764  }
2765 
2766  return ERROR_OK;
2767 }
2768 
2769 static int sam4_protect(struct flash_bank *bank, int set, unsigned int first,
2770  unsigned int last)
2771 {
2772  struct sam4_bank_private *private;
2773  int r;
2774 
2775  LOG_DEBUG("Here");
2776  if (bank->target->state != TARGET_HALTED) {
2777  LOG_ERROR("Target not halted");
2778  return ERROR_TARGET_NOT_HALTED;
2779  }
2780 
2781  private = get_sam4_bank_private(bank);
2782  if (!(private->probed))
2783  return ERROR_FLASH_BANK_NOT_PROBED;
2784 
2785  if (set)
2786  r = flashd_lock(private, first, last);
2787  else
2788  r = flashd_unlock(private, first, last);
2789  LOG_DEBUG("End: r=%d", r);
2790 
2791  return r;
2792 
2793 }
2794 
2795 static int sam4_page_read(struct sam4_bank_private *private, unsigned int pagenum, uint8_t *buf)
2796 {
2797  uint32_t adr;
2798  int r;
2799 
2800  adr = pagenum * private->page_size;
2801  adr = adr + private->base_address;
2802 
2803  r = target_read_memory(private->chip->target,
2804  adr,
2805  4, /* THIS*MUST*BE* in 32bit values */
2806  private->page_size / 4,
2807  buf);
2808  if (r != ERROR_OK)
2809  LOG_ERROR("SAM4: Flash program failed to read page phys address: 0x%08x",
2810  (unsigned int)(adr));
2811  return r;
2812 }
2813 
2814 static int sam4_set_wait(struct sam4_bank_private *private)
2815 {
2816  uint32_t fmr; /* EEFC Flash Mode Register */
2817  int r;
2818 
2819  /* Get flash mode register value */
2820  r = target_read_u32(private->chip->target, private->controller_address, &fmr);
2821  if (r != ERROR_OK) {
2822  LOG_ERROR("Error Read failed: read flash mode register");
2823  return r;
2824  }
2825 
2826  /* Clear flash wait state field */
2827  fmr &= 0xfffff0ff;
2828 
2829  /* set FWS (flash wait states) field in the FMR (flash mode register) */
2830  fmr |= (private->flash_wait_states << 8);
2831 
2832  LOG_DEBUG("Flash Mode: 0x%08x", ((unsigned int)(fmr)));
2833  r = target_write_u32(private->bank->target, private->controller_address, fmr);
2834  if (r != ERROR_OK)
2835  LOG_ERROR("Error Write failed: set flash mode register");
2836 
2837  return r;
2838 }
2839 
2840 static int sam4_page_write(struct sam4_bank_private *private, unsigned int pagenum, const uint8_t *buf)
2841 {
2842  uint32_t adr;
2843  uint32_t status;
2844  int r;
2845 
2846  adr = pagenum * private->page_size;
2847  adr = (adr + private->base_address);
2848 
2849  /* 1st sector 8kBytes - page 0 - 15*/
2850  /* 2nd sector 8kBytes - page 16 - 30*/
2851  /* 3rd sector 48kBytes - page 31 - 127*/
2852  LOG_DEBUG("Wr Page %u @ phys address: 0x%08x", pagenum, (unsigned int)(adr));
2853  r = target_write_memory(private->chip->target,
2854  adr,
2855  4, /* THIS*MUST*BE* in 32bit values */
2856  private->page_size / 4,
2857  buf);
2858  if (r != ERROR_OK) {
2859  LOG_ERROR("SAM4: Failed to write (buffer) page at phys address 0x%08x",
2860  (unsigned int)(adr));
2861  return r;
2862  }
2863 
2864  r = efc_perform_command(private,
2865  /* send Erase & Write Page */
2866  AT91C_EFC_FCMD_WP, /*AT91C_EFC_FCMD_EWP only works on first two 8kb sectors*/
2867  pagenum,
2868  &status);
2869 
2870  if (r != ERROR_OK)
2871  LOG_ERROR("SAM4: Error performing Write page @ phys address 0x%08x",
2872  (unsigned int)(adr));
2873  if (status & (1 << 2)) {
2874  LOG_ERROR("SAM4: Page @ Phys address 0x%08x is locked", (unsigned int)(adr));
2875  return ERROR_FAIL;
2876  }
2877  if (status & (1 << 1)) {
2878  LOG_ERROR("SAM4: Flash Command error @phys address 0x%08x", (unsigned int)(adr));
2879  return ERROR_FAIL;
2880  }
2881  return ERROR_OK;
2882 }
2883 
2884 static int sam4_write(struct flash_bank *bank,
2885  const uint8_t *buffer,
2886  uint32_t offset,
2887  uint32_t count)
2888 {
2889  int n;
2890  unsigned int page_cur;
2891  unsigned int page_end;
2892  int r;
2893  unsigned int page_offset;
2894  struct sam4_bank_private *private;
2895  uint8_t *pagebuffer;
2896 
2897  /* in case we bail further below, set this to null */
2898  pagebuffer = NULL;
2899 
2900  /* ignore dumb requests */
2901  if (count == 0) {
2902  r = ERROR_OK;
2903  goto done;
2904  }
2905 
2906  if (bank->target->state != TARGET_HALTED) {
2907  LOG_ERROR("Target not halted");
2908  r = ERROR_TARGET_NOT_HALTED;
2909  goto done;
2910  }
2911 
2912  private = get_sam4_bank_private(bank);
2913  if (!(private->probed)) {
2914  r = ERROR_FLASH_BANK_NOT_PROBED;
2915  goto done;
2916  }
2917 
2918  if ((offset + count) > private->size_bytes) {
2919  LOG_ERROR("Flash write error - past end of bank");
2920  LOG_ERROR(" offset: 0x%08x, count 0x%08x, BankEnd: 0x%08x",
2921  (unsigned int)(offset),
2922  (unsigned int)(count),
2923  (unsigned int)(private->size_bytes));
2924  r = ERROR_FAIL;
2925  goto done;
2926  }
2927 
2928  pagebuffer = malloc(private->page_size);
2929  if (!pagebuffer) {
2930  LOG_ERROR("No memory for %d Byte page buffer", (int)(private->page_size));
2931  r = ERROR_FAIL;
2932  goto done;
2933  }
2934 
2935  r = sam4_set_wait(private);
2936  if (r != ERROR_OK)
2937  goto done;
2938 
2939  /* what page do we start & end in? */
2940  page_cur = offset / private->page_size;
2941  page_end = (offset + count - 1) / private->page_size;
2942 
2943  LOG_DEBUG("Offset: 0x%08x, Count: 0x%08x", (unsigned int)(offset), (unsigned int)(count));
2944  LOG_DEBUG("Page start: %d, Page End: %d", (int)(page_cur), (int)(page_end));
2945 
2946  /* Special case: all one page */
2947  /* */
2948  /* Otherwise: */
2949  /* (1) non-aligned start */
2950  /* (2) body pages */
2951  /* (3) non-aligned end. */
2952 
2953  /* Handle special case - all one page. */
2954  if (page_cur == page_end) {
2955  LOG_DEBUG("Special case, all in one page");
2956  r = sam4_page_read(private, page_cur, pagebuffer);
2957  if (r != ERROR_OK)
2958  goto done;
2959 
2960  page_offset = (offset & (private->page_size-1));
2961  memcpy(pagebuffer + page_offset,
2962  buffer,
2963  count);
2964 
2965  r = sam4_page_write(private, page_cur, pagebuffer);
2966  if (r != ERROR_OK)
2967  goto done;
2968  r = ERROR_OK;
2969  goto done;
2970  }
2971 
2972  /* non-aligned start */
2973  page_offset = offset & (private->page_size - 1);
2974  if (page_offset) {
2975  LOG_DEBUG("Not-Aligned start");
2976  /* read the partial */
2977  r = sam4_page_read(private, page_cur, pagebuffer);
2978  if (r != ERROR_OK)
2979  goto done;
2980 
2981  /* over-write with new data */
2982  n = (private->page_size - page_offset);
2983  memcpy(pagebuffer + page_offset,
2984  buffer,
2985  n);
2986 
2987  r = sam4_page_write(private, page_cur, pagebuffer);
2988  if (r != ERROR_OK)
2989  goto done;
2990 
2991  count -= n;
2992  offset += n;
2993  buffer += n;
2994  page_cur++;
2995  }
2996 
2997  /* By checking that offset is correct here, we also
2998  fix a clang warning */
2999  assert(offset % private->page_size == 0);
3000 
3001  /* intermediate large pages */
3002  /* also - the final *terminal* */
3003  /* if that terminal page is a full page */
3004  LOG_DEBUG("Full Page Loop: cur=%d, end=%d, count = 0x%08x",
3005  (int)page_cur, (int)page_end, (unsigned int)(count));
3006 
3007  while ((page_cur < page_end) &&
3008  (count >= private->page_size)) {
3009  r = sam4_page_write(private, page_cur, buffer);
3010  if (r != ERROR_OK)
3011  goto done;
3012  count -= private->page_size;
3013  buffer += private->page_size;
3014  page_cur += 1;
3015  }
3016 
3017  /* terminal partial page? */
3018  if (count) {
3019  LOG_DEBUG("Terminal partial page, count = 0x%08x", (unsigned int)(count));
3020  /* we have a partial page */
3021  r = sam4_page_read(private, page_cur, pagebuffer);
3022  if (r != ERROR_OK)
3023  goto done;
3024  /* data goes at start */
3025  memcpy(pagebuffer, buffer, count);
3026  r = sam4_page_write(private, page_cur, pagebuffer);
3027  if (r != ERROR_OK)
3028  goto done;
3029  }
3030  LOG_DEBUG("Done!");
3031  r = ERROR_OK;
3032 done:
3033  free(pagebuffer);
3034  return r;
3035 }
3036 
3037 COMMAND_HANDLER(sam4_handle_info_command)
3038 {
3039  struct sam4_chip *chip;
3040  chip = get_current_sam4(CMD);
3041  if (!chip)
3042  return ERROR_OK;
3043 
3044  unsigned int x;
3045  int r;
3046 
3047  /* bank0 must exist before we can do anything */
3048  if (!chip->details.bank[0].bank) {
3049  x = 0;
3050 need_define:
3051  command_print(CMD,
3052  "Please define bank %d via command: flash bank %s ... ",
3053  x,
3054  at91sam4_flash.name);
3055  return ERROR_FAIL;
3056  }
3057 
3058  /* if bank 0 is not probed, then probe it */
3059  if (!(chip->details.bank[0].probed)) {
3060  r = sam4_auto_probe(chip->details.bank[0].bank);
3061  if (r != ERROR_OK)
3062  return ERROR_FAIL;
3063  }
3064  /* above guarantees the "chip details" structure is valid */
3065  /* and thus, bank private areas are valid */
3066  /* and we have a SAM4 chip, what a concept! */
3067 
3068  /* auto-probe other banks, 0 done above */
3069  for (x = 1; x < SAM4_MAX_FLASH_BANKS; x++) {
3070  /* skip banks not present */
3071  if (!(chip->details.bank[x].present))
3072  continue;
3073 
3074  if (!chip->details.bank[x].bank)
3075  goto need_define;
3076 
3077  if (chip->details.bank[x].probed)
3078  continue;
3079 
3080  r = sam4_auto_probe(chip->details.bank[x].bank);
3081  if (r != ERROR_OK)
3082  return r;
3083  }
3084 
3085  r = sam4_get_info(chip);
3086  if (r != ERROR_OK) {
3087  LOG_DEBUG("Sam4Info, Failed %d", r);
3088  return r;
3089  }
3090 
3091  return ERROR_OK;
3092 }
3093 
3094 COMMAND_HANDLER(sam4_handle_gpnvm_command)
3095 {
3096  unsigned int x, v;
3097  int r, who;
3098  struct sam4_chip *chip;
3099 
3100  chip = get_current_sam4(CMD);
3101  if (!chip)
3102  return ERROR_OK;
3103 
3104  if (chip->target->state != TARGET_HALTED) {
3105  LOG_ERROR("sam4 - target not halted");
3106  return ERROR_TARGET_NOT_HALTED;
3107  }
3108 
3109  if (!chip->details.bank[0].bank) {
3110  command_print(CMD, "Bank0 must be defined first via: flash bank %s ...",
3111  at91sam4_flash.name);
3112  return ERROR_FAIL;
3113  }
3114  if (!chip->details.bank[0].probed) {
3115  r = sam4_auto_probe(chip->details.bank[0].bank);
3116  if (r != ERROR_OK)
3117  return r;
3118  }
3119 
3120  switch (CMD_ARGC) {
3121  case 0:
3122  goto showall;
3123  case 1:
3124  who = -1;
3125  break;
3126  case 2:
3127  if ((strcmp(CMD_ARGV[0], "show") == 0) && (strcmp(CMD_ARGV[1], "all") == 0)) {
3128  who = -1;
3129  } else {
3130  uint32_t v32;
3131  COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], v32);
3132  who = v32;
3133  }
3134  break;
3135  default:
3136  return ERROR_COMMAND_SYNTAX_ERROR;
3137  }
3138 
3139  if (strcmp("show", CMD_ARGV[0]) == 0) {
3140  if (who == -1) {
3141 showall:
3142  r = ERROR_OK;
3143  for (x = 0; x < chip->details.n_gpnvms; x++) {
3144  r = flashd_get_gpnvm(&(chip->details.bank[0]), x, &v);
3145  if (r != ERROR_OK)
3146  break;
3147  command_print(CMD, "sam4-gpnvm%u: %u", x, v);
3148  }
3149  return r;
3150  }
3151  if ((who >= 0) && (((unsigned)(who)) < chip->details.n_gpnvms)) {
3152  r = flashd_get_gpnvm(&(chip->details.bank[0]), who, &v);
3153  if (r == ERROR_OK)
3154  command_print(CMD, "sam4-gpnvm%u: %u", who, v);
3155  return r;
3156  } else {
3157  command_print(CMD, "sam4-gpnvm invalid GPNVM: %u", who);
3158  return ERROR_COMMAND_SYNTAX_ERROR;
3159  }
3160  }
3161 
3162  if (who == -1) {
3163  command_print(CMD, "Missing GPNVM number");
3164  return ERROR_COMMAND_SYNTAX_ERROR;
3165  }
3166 
3167  if (strcmp("set", CMD_ARGV[0]) == 0)
3168  r = flashd_set_gpnvm(&(chip->details.bank[0]), who);
3169  else if ((strcmp("clr", CMD_ARGV[0]) == 0) ||
3170  (strcmp("clear", CMD_ARGV[0]) == 0)) /* quietly accept both */
3171  r = flashd_clr_gpnvm(&(chip->details.bank[0]), who);
3172  else {
3173  command_print(CMD, "Unknown command: %s", CMD_ARGV[0]);
3174  r = ERROR_COMMAND_SYNTAX_ERROR;
3175  }
3176  return r;
3177 }
3178 
3179 COMMAND_HANDLER(sam4_handle_slowclk_command)
3180 {
3181  struct sam4_chip *chip;
3182 
3183  chip = get_current_sam4(CMD);
3184  if (!chip)
3185  return ERROR_OK;
3186 
3187  switch (CMD_ARGC) {
3188  case 0:
3189  /* show */
3190  break;
3191  case 1:
3192  {
3193  /* set */
3194  uint32_t v;
3195  COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], v);
3196  if (v > 200000) {
3197  /* absurd slow clock of 200Khz? */
3198  command_print(CMD, "Absurd/illegal slow clock freq: %d\n", (int)(v));
3199  return ERROR_COMMAND_SYNTAX_ERROR;
3200  }
3201  chip->cfg.slow_freq = v;
3202  break;
3203  }
3204  default:
3205  /* error */
3206  command_print(CMD, "Too many parameters");
3207  return ERROR_COMMAND_SYNTAX_ERROR;
3208  }
3209  command_print(CMD, "Slowclk freq: %d.%03dkhz",
3210  (int)(chip->cfg.slow_freq / 1000),
3211  (int)(chip->cfg.slow_freq % 1000));
3212  return ERROR_OK;
3213 }
3214 
3215 static const struct command_registration at91sam4_exec_command_handlers[] = {
3216  {
3217  .name = "gpnvm",
3218  .handler = sam4_handle_gpnvm_command,
3219  .mode = COMMAND_EXEC,
3220  .usage = "[('clr'|'set'|'show') bitnum]",
3221  .help = "Without arguments, shows all bits in the gpnvm "
3222  "register. Otherwise, clears, sets, or shows one "
3223  "General Purpose Non-Volatile Memory (gpnvm) bit.",
3224  },
3225  {
3226  .name = "info",
3227  .handler = sam4_handle_info_command,
3228  .mode = COMMAND_EXEC,
3229  .help = "Print information about the current at91sam4 chip "
3230  "and its flash configuration.",
3231  .usage = "",
3232  },
3233  {
3234  .name = "slowclk",
3235  .handler = sam4_handle_slowclk_command,
3236  .mode = COMMAND_EXEC,
3237  .usage = "[clock_hz]",
3238  .help = "Display or set the slowclock frequency "
3239  "(default 32768 Hz).",
3240  },
3241  COMMAND_REGISTRATION_DONE
3242 };
3243 static const struct command_registration at91sam4_command_handlers[] = {
3244  {
3245  .name = "at91sam4",
3246  .mode = COMMAND_ANY,
3247  .help = "at91sam4 flash command group",
3248  .usage = "",
3249  .chain = at91sam4_exec_command_handlers,
3250  },
3251  COMMAND_REGISTRATION_DONE
3252 };
3253 
3254 const struct flash_driver at91sam4_flash = {
3255  .name = "at91sam4",
3256  .commands = at91sam4_command_handlers,
3257  .flash_bank_command = sam4_flash_bank_command,
3258  .erase = sam4_erase,
3259  .protect = sam4_protect,
3260  .write = sam4_write,
3261  .read = default_flash_read,
3262  .probe = sam4_probe,
3263  .auto_probe = sam4_auto_probe,
3264  .erase_check = default_flash_blank_check,
3265  .protect_check = sam4_protect_check,
3266  .info = sam4_info,
3267  .free_driver_priv = sam4_free_driver_priv,
3268 };
FLASH_BANK0_BASE_C32
#define FLASH_BANK0_BASE_C32
Definition: at91sam4.c:39
FLASH_BANK1_BASE_2048K_SD
#define FLASH_BANK1_BASE_2048K_SD
Definition: at91sam4.c:36
AT91C_EFC_FCMD_WPL
#define AT91C_EFC_FCMD_WPL
Definition: at91sam4.c:44
sam4_page_write
static int sam4_page_write(struct sam4_bank_private *private, unsigned int pagenum, const uint8_t *buf)
Definition: at91sam4.c:2840
AT91C_EFC_FCMD_GLB
#define AT91C_EFC_FCMD_GLB
Definition: at91sam4.c:53
FLASH_BANK_BASE_S
#define FLASH_BANK_BASE_S
Definition: at91sam4.c:28
sam4_get_reg
static const struct sam4_reg_list * sam4_get_reg(struct sam4_chip *chip, uint32_t *goes_here)
Given a pointer to where it goes in the structure, determine the register name, address from the all ...
Definition: at91sam4.c:2335
eproc_names
static const char *const eproc_names[]
Definition: at91sam4.c:1931
AT91C_EFC_FCMD_EWPL
#define AT91C_EFC_FCMD_EWPL
Definition: at91sam4.c:46
all_sam4_details
static const struct sam4_chip_details all_sam4_details[]
Definition: at91sam4.c:219
REG_NAME_WIDTH
#define REG_NAME_WIDTH
Definition: at91sam4.c:25
sam4_write
static int sam4_write(struct flash_bank *bank, const uint8_t *buffer, uint32_t offset, uint32_t count)
Definition: at91sam4.c:2884
COMMAND_HANDLER
COMMAND_HANDLER(sam4_handle_info_command)
Definition: at91sam4.c:3037
sam4_info
static int sam4_info(struct flash_bank *bank, struct command_invocation *cmd)
Definition: at91sam4.c:2612
sam4_explain_chipid_cidr
static void sam4_explain_chipid_cidr(struct sam4_chip *chip)
Definition: at91sam4.c:2106
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static const char _unknown[]
Definition: at91sam4.c:1930
flashd_get_gpnvm
static int flashd_get_gpnvm(struct sam4_bank_private *private, unsigned int gpnvm, unsigned int *puthere)
Gets current GPNVM state.
Definition: at91sam4.c:1715
OFFSET_EFC_FRR
#define OFFSET_EFC_FRR
Definition: at91sam4.c:63
sam4_auto_probe
static int sam4_auto_probe(struct flash_bank *bank)
Definition: at91sam4.c:2705
_yes_or_no
static const char * _yes_or_no(uint32_t v)
Definition: at91sam4.c:2050
get_sam4_bank_private
static struct sam4_bank_private * get_sam4_bank_private(struct flash_bank *bank)
Definition: at91sam4.c:2326
sam4_explain_ckgr_plla
static void sam4_explain_ckgr_plla(struct sam4_chip *chip)
Definition: at91sam4.c:2163
AT91C_EFC_FCMD_SFB
#define AT91C_EFC_FCMD_SFB
Definition: at91sam4.c:54
AT91C_EFC_FCMD_EA
#define AT91C_EFC_FCMD_EA
Definition: at91sam4.c:47
sam4_get_details
static int sam4_get_details(struct sam4_bank_private *private)
Definition: at91sam4.c:2551
FLASH_BANK1_BASE_1024K_SD
#define FLASH_BANK1_BASE_1024K_SD
Definition: at91sam4.c:34
AT91C_EFC_FCMD_EPA
#define AT91C_EFC_FCMD_EPA
Definition: at91sam4.c:50
all_sam4_chips
static struct sam4_chip * all_sam4_chips
Definition: at91sam4.c:183
sam4_read_this_reg
static int sam4_read_this_reg(struct sam4_chip *chip, uint32_t *goes_here)
Definition: at91sam4.c:2362
AT91C_EFC_FCMD_GFB
#define AT91C_EFC_FCMD_GFB
Definition: at91sam4.c:56
sam4_explain_ckgr_mor
static void sam4_explain_ckgr_mor(struct sam4_chip *chip)
Definition: at91sam4.c:2062
SAM4_ENTRY
#define SAM4_ENTRY(NAME, FUNC)
Definition: at91sam4.c:2301
sam4_get_reg_ptr
static uint32_t * sam4_get_reg_ptr(struct sam4_cfg *cfg, const struct sam4_reg_list *list)
Definition: at91sam4.c:2288
FLASH_BANK_BASE_C
#define FLASH_BANK_BASE_C
Definition: at91sam4.c:29
sam4_all_regs
static const struct sam4_reg_list sam4_all_regs[]
Definition: at91sam4.c:2304
sam4_protect_check
static int sam4_protect_check(struct flash_bank *bank)
Definition: at91sam4.c:2439
get_current_sam4
static struct sam4_chip * get_current_sam4(struct command_invocation *cmd)
Definition: at91sam4.c:185
efc_get_status
static int efc_get_status(struct sam4_bank_private *private, uint32_t *v)
Get the current status of the EEFC and the value of some status bits (LOCKE, PROGE).
Definition: at91sam4.c:1445
nvpsize
static const char *const nvpsize[]
Definition: at91sam4.c:1951
sam4_explain_mckr
static void sam4_explain_mckr(struct sam4_chip *chip)
Definition: at91sam4.c:2183
AT91C_EFC_FCMD_EWP
#define AT91C_EFC_FCMD_EWP
Definition: at91sam4.c:45
_tomhz
static float _tomhz(uint32_t freq_hz)
Definition: at91sam4.c:65
at91sam4_exec_command_handlers
static const struct command_registration at91sam4_exec_command_handlers[]
Definition: at91sam4.c:3215
AT91C_EFC_FCMD_WP
#define AT91C_EFC_FCMD_WP
Definition: at91sam4.c:43
flashd_get_lock_bits
static int flashd_get_lock_bits(struct sam4_bank_private *private, uint32_t *v)
Returns a bit field (at most 64) of locked regions within a page.
Definition: at91sam4.c:1822
flashd_read_uid
static int flashd_read_uid(struct sam4_bank_private *private)
Read the unique ID.
Definition: at91sam4.c:1616
SAM4_MAX_FLASH_BANKS
#define SAM4_MAX_FLASH_BANKS
Definition: at91sam4.c:162
at91sam4_command_handlers
static const struct command_registration at91sam4_command_handlers[]
Definition: at91sam4.c:3243
flashd_set_gpnvm
static int flashd_set_gpnvm(struct sam4_bank_private *private, unsigned int gpnvm)
Sets the selected GPNVM bit.
Definition: at91sam4.c:1788
nvptype
static const char *const nvptype[]
Definition: at91sam4.c:2039
sam4_reg_fieldname
static uint32_t sam4_reg_fieldname(struct sam4_chip *chip, const char *regname, uint32_t value, unsigned int shift, unsigned int width)
Definition: at91sam4.c:1901
FLASH_BANK1_BASE_C32
#define FLASH_BANK1_BASE_C32
Definition: at91sam4.c:40
sam4_explain_ckgr_mcfr
static void sam4_explain_ckgr_mcfr(struct sam4_chip *chip)
Definition: at91sam4.c:2145
OFFSET_EFC_FCR
#define OFFSET_EFC_FCR
Definition: at91sam4.c:61
FLASH_BANK0_BASE_SD
#define FLASH_BANK0_BASE_SD
Definition: at91sam4.c:32
SAM4_N_NVM_BITS
#define SAM4_N_NVM_BITS
Definition: at91sam4.c:157
efc_start_command
static int efc_start_command(struct sam4_bank_private *private, unsigned int command, unsigned int argument)
Definition: at91sam4.c:1478
nvpsize2
#define nvpsize2
Definition: at91sam4.c:1950
OFFSET_EFC_FSR
#define OFFSET_EFC_FSR
Definition: at91sam4.c:62
flashd_lock
static int flashd_lock(struct sam4_bank_private *private, unsigned int start_sector, unsigned int end_sector)
Locks regions.
Definition: at91sam4.c:1874
sam4_set_wait
static int sam4_set_wait(struct sam4_bank_private *private)
Definition: at91sam4.c:2814
AT91C_EFC_FCMD_STUI
#define AT91C_EFC_FCMD_STUI
Definition: at91sam4.c:57
sam4_free_driver_priv
static void sam4_free_driver_priv(struct flash_bank *bank)
Remove all chips from the internal list without distinguishing which one is owned by this bank.
Definition: at91sam4.c:2540
flashd_unlock
static int flashd_unlock(struct sam4_bank_private *private, unsigned int start_sector, unsigned int end_sector)
Unlocks all the regions in the given address range.
Definition: at91sam4.c:1844
AT91C_EFC_FCMD_GETD
#define AT91C_EFC_FCMD_GETD
Definition: at91sam4.c:42
flashd_erase_pages
static int flashd_erase_pages(struct sam4_bank_private *private, int first_page, int num_pages, uint32_t *status)
Erases the entire flash.
Definition: at91sam4.c:1669
sam4_protect
static int sam4_protect(struct flash_bank *bank, int set, unsigned int first, unsigned int last)
Definition: at91sam4.c:2769
FLASH_BANK_COMMAND_HANDLER
FLASH_BANK_COMMAND_HANDLER(sam4_flash_bank_command)
Definition: at91sam4.c:2472
efc_get_result
static int efc_get_result(struct sam4_bank_private *private, uint32_t *v)
Get the result of the last executed command.
Definition: at91sam4.c:1465
sam4_read_all_regs
static int sam4_read_all_regs(struct sam4_chip *chip)
Definition: at91sam4.c:2379
sramsize
static const char *const sramsize[]
Definition: at91sam4.c:1970
at91sam4_flash
const struct flash_driver at91sam4_flash
Definition: at91sam4.c:3254
sam4_probe
static int sam4_probe(struct flash_bank *bank)
Definition: at91sam4.c:2630
flashd_clr_gpnvm
static int flashd_clr_gpnvm(struct sam4_bank_private *private, unsigned int gpnvm)
Clears the selected GPNVM bit.
Definition: at91sam4.c:1756
AT91C_EFC_FCMD_SPUI
#define AT91C_EFC_FCMD_SPUI
Definition: at91sam4.c:58
sam4_page_read
static int sam4_page_read(struct sam4_bank_private *private, unsigned int pagenum, uint8_t *buf)
Definition: at91sam4.c:2795
AT91C_EFC_FCMD_CLB
#define AT91C_EFC_FCMD_CLB
Definition: at91sam4.c:52
flashd_erase_entire_bank
static int flashd_erase_entire_bank(struct sam4_bank_private *private)
Erases the entire flash.
Definition: at91sam4.c:1656
sam4_get_info
static int sam4_get_info(struct sam4_chip *chip)
Definition: at91sam4.c:2399
AT91C_EFC_FCMD_SLB
#define AT91C_EFC_FCMD_SLB
Definition: at91sam4.c:51
sam4_erase
static int sam4_erase(struct flash_bank *bank, unsigned int first, unsigned int last)
Definition: at91sam4.c:2716
_rc_freq
static const char *const _rc_freq[]
Definition: at91sam4.c:2058
AT91C_EFC_FCMD_CFB
#define AT91C_EFC_FCMD_CFB
Definition: at91sam4.c:55
efc_perform_command
static int efc_perform_command(struct sam4_bank_private *private, unsigned int command, unsigned int argument, uint32_t *status)
Performs the given command and wait until its completion (or an error).
Definition: at91sam4.c:1572
CKGR_MOR
#define CKGR_MOR
Definition: at91sam7.c:45
PMC_MCKR
#define PMC_MCKR
Definition: at91sam7.c:50
CKGR_MCFR
#define CKGR_MCFR
Definition: at91sam7.c:44
command_print_sameline
void command_print_sameline(struct command_invocation *cmd, const char *format,...)
Definition: command.c:378
command_print
void command_print(struct command_invocation *cmd, const char *format,...)
Definition: command.c:389
CMD
#define CMD
Use this macro to access the command being handled, rather than accessing the variable directly.
Definition: command.h:146
CMD_ARGV
#define CMD_ARGV
Use this macro to access the arguments for the command being handled, rather than accessing the varia...
Definition: command.h:161
ERROR_COMMAND_SYNTAX_ERROR
#define ERROR_COMMAND_SYNTAX_ERROR
Definition: command.h:405
CMD_ARGC
#define CMD_ARGC
Use this macro to access the number of arguments for the command being handled, rather than accessing...
Definition: command.h:156
COMMAND_PARSE_NUMBER
#define COMMAND_PARSE_NUMBER(type, in, out)
parses the string in into out as a type, or prints a command error and passes the error code to the c...
Definition: command.h:445
COMMAND_REGISTRATION_DONE
#define COMMAND_REGISTRATION_DONE
Use this as the last entry in an array of command_registration records.
Definition: command.h:256
COMMAND_ANY
@ COMMAND_ANY
Definition: command.h:42
COMMAND_EXEC
@ COMMAND_EXEC
Definition: command.h:40
buffer
uint64_t buffer
Pointer to data buffer to send over SPI.
Definition: dw-spi-helper.h:0
width
unsigned short width
Definition: embeddedice.c:47
bank
uint8_t bank
Definition: esirisc.c:135
ERROR_FLASH_BANK_NOT_PROBED
#define ERROR_FLASH_BANK_NOT_PROBED
Definition: flash/common.h:35
default_flash_blank_check
int default_flash_blank_check(struct flash_bank *bank)
Provides default erased-bank check handling.
Definition: flash/nor/core.c:377
default_flash_read
int default_flash_read(struct flash_bank *bank, uint8_t *buffer, uint32_t offset, uint32_t count)
Provides default read implementation for flash memory.
Definition: flash/nor/core.c:121
LOG_USER
#define LOG_USER(expr ...)
Definition: log.h:150
ERROR_FAIL
#define ERROR_FAIL
Definition: log.h:188
LOG_USER_N
#define LOG_USER_N(expr ...)
Definition: log.h:153
LOG_ERROR
#define LOG_ERROR(expr ...)
Definition: log.h:147
LOG_INFO
#define LOG_INFO(expr ...)
Definition: log.h:141
LOG_DEBUG
#define LOG_DEBUG(expr ...)
Definition: log.h:124
ERROR_OK
#define ERROR_OK
Definition: log.h:182
archnames::name
const char * name
Definition: at91sam3.c:2490
archnames::value
unsigned int value
Definition: at91sam3.c:2490
command_invocation
When run_command is called, a new instance will be created on the stack, filled with the proper value...
Definition: command.h:76
command_registration
Definition: command.h:238
command_registration::name
const char * name
Definition: command.h:239
flash_bank
Provides details of a flash bank, available either on-chip or through a major interface.
Definition: nor/core.h:75
flash_driver
Provides the implementation-independent structure that defines all of the callbacks required by OpenO...
Definition: nor/driver.h:39
flash_driver::name
const char * name
Gives a human-readable name of this flash driver, This field is used to select and initialize the dri...
Definition: nor/driver.h:44
reg
Definition: register.h:111
reg::name
const char * name
Definition: register.h:113
sam4_bank_private
Definition: at91sam4.c:122
sam4_bank_private::controller_address
uint32_t controller_address
Definition: at91sam4.c:135
sam4_bank_private::size_bytes
unsigned int size_bytes
Definition: at91sam4.c:139
sam4_bank_private::chip
struct sam4_chip * chip
Definition: at91sam4.c:131
sam4_bank_private::probed
bool probed
Definition: at91sam4.c:123
sam4_bank_private::bank_number
unsigned int bank_number
Definition: at91sam4.c:134
sam4_bank_private::base_address
uint32_t base_address
Definition: at91sam4.c:136
sam4_bank_private::flash_wait_states
uint32_t flash_wait_states
Definition: at91sam4.c:137
sam4_bank_private::present
bool present
Definition: at91sam4.c:138
sam4_bank_private::bank
struct flash_bank * bank
Definition: at91sam4.c:133
sam4_bank_private::page_size
unsigned int page_size
Definition: at91sam4.c:142
sam4_bank_private::nsectors
unsigned int nsectors
Definition: at91sam4.c:140
sam4_bank_private::sector_size
unsigned int sector_size
Definition: at91sam4.c:141
sam4_cfg
Definition: at91sam4.c:71
sam4_cfg::rc_freq
uint32_t rc_freq
Definition: at91sam4.c:75
sam4_cfg::unique_id
uint32_t unique_id[4]
Definition: at91sam4.c:72
sam4_cfg::fclk_freq
uint32_t fclk_freq
Definition: at91sam4.c:80
sam4_cfg::PMC_IMR
uint32_t PMC_IMR
Definition: at91sam4.c:115
sam4_cfg::CHIPID_CIDR
uint32_t CHIPID_CIDR
Definition: at91sam4.c:87
sam4_cfg::CKGR_UCKR
uint32_t CKGR_UCKR
Definition: at91sam4.c:97
sam4_cfg::PMC_MCKR
uint32_t PMC_MCKR
Definition: at91sam4.c:105
sam4_cfg::PMC_FSPR
uint32_t PMC_FSPR
Definition: at91sam4.c:119
sam4_cfg::PMC_PCK2
uint32_t PMC_PCK2
Definition: at91sam4.c:111
sam4_cfg::mainosc_freq
uint32_t mainosc_freq
Definition: at91sam4.c:76
sam4_cfg::pclk2_freq
uint32_t pclk2_freq
Definition: at91sam4.c:83
sam4_cfg::pclk0_freq
uint32_t pclk0_freq
Definition: at91sam4.c:81
sam4_cfg::mclk_freq
uint32_t mclk_freq
Definition: at91sam4.c:78
sam4_cfg::pclk1_freq
uint32_t pclk1_freq
Definition: at91sam4.c:82
sam4_cfg::slow_freq
uint32_t slow_freq
Definition: at91sam4.c:74
sam4_cfg::PMC_PCK0
uint32_t PMC_PCK0
Definition: at91sam4.c:107
sam4_cfg::CHIPID_EXID
uint32_t CHIPID_EXID
Definition: at91sam4.c:89
sam4_cfg::cpu_freq
uint32_t cpu_freq
Definition: at91sam4.c:79
sam4_cfg::PMC_FSMR
uint32_t PMC_FSMR
Definition: at91sam4.c:117
sam4_cfg::plla_freq
uint32_t plla_freq
Definition: at91sam4.c:77
sam4_cfg::PMC_SCSR
uint32_t PMC_SCSR
Definition: at91sam4.c:93
sam4_cfg::CKGR_MCFR
uint32_t CKGR_MCFR
Definition: at91sam4.c:101
sam4_cfg::CKGR_PLLAR
uint32_t CKGR_PLLAR
Definition: at91sam4.c:103
sam4_cfg::CKGR_MOR
uint32_t CKGR_MOR
Definition: at91sam4.c:99
sam4_cfg::PMC_PCK1
uint32_t PMC_PCK1
Definition: at91sam4.c:109
sam4_cfg::PMC_PCSR
uint32_t PMC_PCSR
Definition: at91sam4.c:95
sam4_cfg::PMC_SR
uint32_t PMC_SR
Definition: at91sam4.c:113
sam4_chip_details
Definition: at91sam4.c:145
sam4_chip_details::chipid_cidr
uint32_t chipid_cidr
Definition: at91sam4.c:153
sam4_chip_details::n_banks
unsigned int n_banks
Definition: at91sam4.c:161
sam4_chip_details::name
const char * name
Definition: at91sam4.c:154
sam4_chip_details::total_flash_size
unsigned int total_flash_size
Definition: at91sam4.c:159
sam4_chip_details::bank
struct sam4_bank_private bank[SAM4_MAX_FLASH_BANKS]
Definition: at91sam4.c:164
sam4_chip_details::n_gpnvms
unsigned int n_gpnvms
Definition: at91sam4.c:156
sam4_chip_details::total_sram_size
unsigned int total_sram_size
Definition: at91sam4.c:160
sam4_chip_details::gpnvm
unsigned int gpnvm[SAM4_N_NVM_BITS]
Definition: at91sam4.c:158
sam4_chip
Definition: at91sam4.c:167
sam4_chip::probed
bool probed
Definition: at91sam4.c:169
sam4_chip::cfg
struct sam4_cfg cfg
Definition: at91sam4.c:174
sam4_chip::details
struct sam4_chip_details details
Definition: at91sam4.c:172
sam4_chip::next
struct sam4_chip * next
Definition: at91sam4.c:168
sam4_chip::target
struct target * target
Definition: at91sam4.c:173
sam4_reg_list
Definition: at91sam4.c:178
sam4_reg_list::name
const char * name
Definition: at91sam4.c:179
sam4_reg_list::struct_offset
size_t struct_offset
Definition: at91sam4.c:179
sam4_reg_list::address
uint32_t address
Definition: at91sam4.c:179
sam4_reg_list::explain_func
void(* explain_func)(struct sam4_chip *chip)
Definition: at91sam4.c:180
target
Definition: target.h:119
target::state
enum target_state state
Definition: target.h:167
target_write_memory
int target_write_memory(struct target *target, target_addr_t address, uint32_t size, uint32_t count, const uint8_t *buffer)
Write count items of size bytes to the memory of target at the address given.
Definition: target.c:1288
target_write_u32
int target_write_u32(struct target *target, target_addr_t address, uint32_t value)
Definition: target.c:2635
target_read_u32
int target_read_u32(struct target *target, target_addr_t address, uint32_t *value)
Definition: target.c:2561
target_read_memory
int target_read_memory(struct target *target, target_addr_t address, uint32_t size, uint32_t count, uint8_t *buffer)
Read count items of size bytes from the memory of target at the address given.
Definition: target.c:1260
get_current_target
struct target * get_current_target(struct command_context *cmd_ctx)
Definition: target.c:468
ERROR_TARGET_NOT_HALTED
#define ERROR_TARGET_NOT_HALTED
Definition: target.h:817
TARGET_HALTED
@ TARGET_HALTED
Definition: target.h:58
time_support.h
timeval_ms
int64_t timeval_ms(void)
Definition: time_support_common.c:23
TARGET_ADDR_FMT
#define TARGET_ADDR_FMT
Definition: types.h:286
NULL
#define NULL
Definition: usb.h:16
status
uint8_t status[4]
Definition: vdebug.c:17
cmd
uint8_t cmd
Definition: vdebug.c:1
offset
uint8_t offset[4]
Definition: vdebug.c:9
count
uint8_t count[4]
Definition: vdebug.c:22