OpenOCD
at91sam3.c
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1 // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-Source-Code)
2 
3 /*
4  * Copyright (C) 2009 by Duane Ellis <openocd@duaneellis.com>
5  *
6  * at91sam3s* support
7  * Copyright (C) 2010 by Olaf Lüke <olaf@uni-paderborn.de>
8  * Copyright (C) 2011 by Olivier Schonken and Jim Norris
9  *
10  * Some of the lower level code was based on code supplied by
11  * ATMEL under BSD-Source-Code License and this copyright.
12  * ATMEL Microcontroller Software Support
13  * Copyright (c) 2009, Atmel Corporation. All rights reserved.
14  */
15 
16 #ifdef HAVE_CONFIG_H
17 #include "config.h"
18 #endif
19 
20 #include "imp.h"
21 #include <helper/time_support.h>
22 
23 #define REG_NAME_WIDTH (12)
24 
25 /* at91sam3u series (has one or two flash banks) */
26 #define FLASH_BANK0_BASE_U 0x00080000
27 #define FLASH_BANK1_BASE_U 0x00100000
28 
29 /* at91sam3s series (has always one flash bank) */
30 #define FLASH_BANK_BASE_S 0x00400000
31 
32 /* at91sam3sd series (has always two flash banks) */
33 #define FLASH_BANK0_BASE_SD FLASH_BANK_BASE_S
34 #define FLASH_BANK1_BASE_512K_SD (FLASH_BANK0_BASE_SD+(512*1024/2))
35 
36 
37 /* at91sam3n series (has always one flash bank) */
38 #define FLASH_BANK_BASE_N 0x00400000
39 
40 /* at91sam3a/x series has two flash banks*/
41 #define FLASH_BANK0_BASE_AX 0x00080000
42 /*Bank 1 of the at91sam3a/x series starts at 0x00080000 + half flash size*/
43 #define FLASH_BANK1_BASE_256K_AX 0x000A0000
44 #define FLASH_BANK1_BASE_512K_AX 0x000C0000
45 
46 #define AT91C_EFC_FCMD_GETD (0x0) /* (EFC) Get Flash Descriptor */
47 #define AT91C_EFC_FCMD_WP (0x1) /* (EFC) Write Page */
48 #define AT91C_EFC_FCMD_WPL (0x2) /* (EFC) Write Page and Lock */
49 #define AT91C_EFC_FCMD_EWP (0x3) /* (EFC) Erase Page and Write Page */
50 #define AT91C_EFC_FCMD_EWPL (0x4) /* (EFC) Erase Page and Write Page then Lock */
51 #define AT91C_EFC_FCMD_EA (0x5) /* (EFC) Erase All */
52 /* cmd6 is not present in the at91sam3u4/2/1 data sheet table 17-2 */
53 /* #define AT91C_EFC_FCMD_EPL (0x6) // (EFC) Erase plane? */
54 /* cmd7 is not present in the at91sam3u4/2/1 data sheet table 17-2 */
55 /* #define AT91C_EFC_FCMD_EPA (0x7) // (EFC) Erase pages? */
56 #define AT91C_EFC_FCMD_SLB (0x8) /* (EFC) Set Lock Bit */
57 #define AT91C_EFC_FCMD_CLB (0x9) /* (EFC) Clear Lock Bit */
58 #define AT91C_EFC_FCMD_GLB (0xA) /* (EFC) Get Lock Bit */
59 #define AT91C_EFC_FCMD_SFB (0xB) /* (EFC) Set Fuse Bit */
60 #define AT91C_EFC_FCMD_CFB (0xC) /* (EFC) Clear Fuse Bit */
61 #define AT91C_EFC_FCMD_GFB (0xD) /* (EFC) Get Fuse Bit */
62 #define AT91C_EFC_FCMD_STUI (0xE) /* (EFC) Start Read Unique ID */
63 #define AT91C_EFC_FCMD_SPUI (0xF) /* (EFC) Stop Read Unique ID */
64 
65 #define OFFSET_EFC_FMR 0
66 #define OFFSET_EFC_FCR 4
67 #define OFFSET_EFC_FSR 8
68 #define OFFSET_EFC_FRR 12
69 
70 static float _tomhz(uint32_t freq_hz)
71 {
72  return ((float)freq_hz) / 1000000.0;
73 }
74 
75 /* How the chip is configured. */
76 struct sam3_cfg {
77  uint32_t unique_id[4];
78 
79  uint32_t slow_freq;
80  uint32_t rc_freq;
81  uint32_t mainosc_freq;
82  uint32_t plla_freq;
83  uint32_t mclk_freq;
84  uint32_t cpu_freq;
85  uint32_t fclk_freq;
86  uint32_t pclk0_freq;
87  uint32_t pclk1_freq;
88  uint32_t pclk2_freq;
89 
90 
91 #define SAM3_CHIPID_CIDR (0x400E0740)
92  uint32_t CHIPID_CIDR;
93 #define SAM3_CHIPID_CIDR2 (0x400E0940) /*SAM3X and SAM3A cidr at this address*/
94  uint32_t CHIPID_CIDR2;
95 #define SAM3_CHIPID_EXID (0x400E0744)
96  uint32_t CHIPID_EXID;
97 #define SAM3_CHIPID_EXID2 (0x400E0944) /*SAM3X and SAM3A cidr at this address*/
98  uint32_t CHIPID_EXID2;
99 
100 
101 #define SAM3_PMC_BASE (0x400E0400)
102 #define SAM3_PMC_SCSR (SAM3_PMC_BASE + 0x0008)
103  uint32_t PMC_SCSR;
104 #define SAM3_PMC_PCSR (SAM3_PMC_BASE + 0x0018)
105  uint32_t PMC_PCSR;
106 #define SAM3_CKGR_UCKR (SAM3_PMC_BASE + 0x001c)
107  uint32_t CKGR_UCKR;
108 #define SAM3_CKGR_MOR (SAM3_PMC_BASE + 0x0020)
109  uint32_t CKGR_MOR;
110 #define SAM3_CKGR_MCFR (SAM3_PMC_BASE + 0x0024)
111  uint32_t CKGR_MCFR;
112 #define SAM3_CKGR_PLLAR (SAM3_PMC_BASE + 0x0028)
113  uint32_t CKGR_PLLAR;
114 #define SAM3_PMC_MCKR (SAM3_PMC_BASE + 0x0030)
115  uint32_t PMC_MCKR;
116 #define SAM3_PMC_PCK0 (SAM3_PMC_BASE + 0x0040)
117  uint32_t PMC_PCK0;
118 #define SAM3_PMC_PCK1 (SAM3_PMC_BASE + 0x0044)
119  uint32_t PMC_PCK1;
120 #define SAM3_PMC_PCK2 (SAM3_PMC_BASE + 0x0048)
121  uint32_t PMC_PCK2;
122 #define SAM3_PMC_SR (SAM3_PMC_BASE + 0x0068)
123  uint32_t PMC_SR;
124 #define SAM3_PMC_IMR (SAM3_PMC_BASE + 0x006c)
125  uint32_t PMC_IMR;
126 #define SAM3_PMC_FSMR (SAM3_PMC_BASE + 0x0070)
127  uint32_t PMC_FSMR;
128 #define SAM3_PMC_FSPR (SAM3_PMC_BASE + 0x0074)
129  uint32_t PMC_FSPR;
130 };
131 
132 /*
133  * The AT91SAM3N data sheet 04-Oct-2010, AT91SAM3U data sheet 22-Aug-2011
134  * and AT91SAM3S data sheet 09-Feb-2011 state that for flash writes
135  * the flash wait state (FWS) should be set to 6. It seems like that the
136  * cause of the problem is not the flash itself, but the flash write
137  * buffer. Ie the wait states have to be set before writing into the
138  * buffer.
139  * Tested and confirmed with SAM3N and SAM3U
140  */
141 
142 struct sam3_bank_private {
143  bool probed;
144  /* DANGER: THERE ARE DRAGONS HERE.. */
145  /* NOTE: If you add more 'ghost' pointers */
146  /* be aware that you must *manually* update */
147  /* these pointers in the function sam3_get_details() */
148  /* See the comment "Here there be dragons" */
149 
150  /* so we can find the chip we belong to */
151  struct sam3_chip *chip;
152  /* so we can find the original bank pointer */
153  struct flash_bank *bank;
154  unsigned int bank_number;
155  uint32_t controller_address;
156  uint32_t base_address;
157  uint32_t flash_wait_states;
158  bool present;
159  unsigned int size_bytes;
160  unsigned int nsectors;
161  unsigned int sector_size;
162  unsigned int page_size;
163 };
164 
165 struct sam3_chip_details {
166  /* THERE ARE DRAGONS HERE.. */
167  /* note: If you add pointers here */
168  /* be careful about them as they */
169  /* may need to be updated inside */
170  /* the function: "sam3_get_details() */
171  /* which copy/overwrites the */
172  /* 'runtime' copy of this structure */
173  uint32_t chipid_cidr;
174  const char *name;
175 
176  unsigned int n_gpnvms;
177 #define SAM3_N_NVM_BITS 3
178  unsigned int gpnvm[SAM3_N_NVM_BITS];
179  unsigned int total_flash_size;
180  unsigned int total_sram_size;
181  unsigned int n_banks;
182 #define SAM3_MAX_FLASH_BANKS 2
183  /* these are "initialized" from the global const data */
184  struct sam3_bank_private bank[SAM3_MAX_FLASH_BANKS];
185 };
186 
187 struct sam3_chip {
188  struct sam3_chip *next;
189  bool probed;
190 
191  /* this is "initialized" from the global const structure */
192  struct sam3_chip_details details;
193  struct target *target;
194  struct sam3_cfg cfg;
195 };
196 
197 
198 struct sam3_reg_list {
199  uint32_t address; size_t struct_offset; const char *name;
200  void (*explain_func)(struct sam3_chip *chip);
201 };
202 
203 static struct sam3_chip *all_sam3_chips;
204 
205 static struct sam3_chip *get_current_sam3(struct command_invocation *cmd)
206 {
207  struct target *t;
208  static struct sam3_chip *p;
209 
210  t = get_current_target(cmd->ctx);
211  if (!t) {
212  command_print_sameline(cmd, "No current target?\n");
213  return NULL;
214  }
215 
216  p = all_sam3_chips;
217  if (!p) {
218  /* this should not happen */
219  /* the command is not registered until the chip is created? */
220  command_print_sameline(cmd, "No SAM3 chips exist?\n");
221  return NULL;
222  }
223 
224  while (p) {
225  if (p->target == t)
226  return p;
227  p = p->next;
228  }
229  command_print_sameline(cmd, "Cannot find SAM3 chip?\n");
230  return NULL;
231 }
232 
233 /* these are used to *initialize* the "chip->details" structure. */
234 static const struct sam3_chip_details all_sam3_details[] = {
235  /* Start at91sam3u* series */
236  {
237  .chipid_cidr = 0x28100960,
238  .name = "at91sam3u4e",
239  .total_flash_size = 256 * 1024,
240  .total_sram_size = 52 * 1024,
241  .n_gpnvms = 3,
242  .n_banks = 2,
243 
244  /* System boots at address 0x0 */
245  /* gpnvm[1] = selects boot code */
246  /* if gpnvm[1] == 0 */
247  /* boot is via "SAMBA" (rom) */
248  /* else */
249  /* boot is via FLASH */
250  /* Selection is via gpnvm[2] */
251  /* endif */
252  /* */
253  /* NOTE: banks 0 & 1 switch places */
254  /* if gpnvm[2] == 0 */
255  /* Bank0 is the boot rom */
256  /* else */
257  /* Bank1 is the boot rom */
258  /* endif */
259 /* .bank[0] = { */
260  {
261  {
262  .probed = false,
263  .chip = NULL,
264  .bank = NULL,
265  .bank_number = 0,
266  .base_address = FLASH_BANK0_BASE_U,
267  .controller_address = 0x400e0800,
268  .flash_wait_states = 6, /* workaround silicon bug */
269  .present = 1,
270  .size_bytes = 128 * 1024,
271  .nsectors = 16,
272  .sector_size = 8192,
273  .page_size = 256,
274  },
275 
276 /* .bank[1] = { */
277  {
278  .probed = false,
279  .chip = NULL,
280  .bank = NULL,
281  .bank_number = 1,
282  .base_address = FLASH_BANK1_BASE_U,
283  .controller_address = 0x400e0a00,
284  .flash_wait_states = 6, /* workaround silicon bug */
285  .present = 1,
286  .size_bytes = 128 * 1024,
287  .nsectors = 16,
288  .sector_size = 8192,
289  .page_size = 256,
290  },
291  },
292  },
293 
294  {
295  .chipid_cidr = 0x281a0760,
296  .name = "at91sam3u2e",
297  .total_flash_size = 128 * 1024,
298  .total_sram_size = 36 * 1024,
299  .n_gpnvms = 2,
300  .n_banks = 1,
301 
302  /* System boots at address 0x0 */
303  /* gpnvm[1] = selects boot code */
304  /* if gpnvm[1] == 0 */
305  /* boot is via "SAMBA" (rom) */
306  /* else */
307  /* boot is via FLASH */
308  /* Selection is via gpnvm[2] */
309  /* endif */
310 /* .bank[0] = { */
311  {
312  {
313  .probed = false,
314  .chip = NULL,
315  .bank = NULL,
316  .bank_number = 0,
317  .base_address = FLASH_BANK0_BASE_U,
318  .controller_address = 0x400e0800,
319  .flash_wait_states = 6, /* workaround silicon bug */
320  .present = 1,
321  .size_bytes = 128 * 1024,
322  .nsectors = 16,
323  .sector_size = 8192,
324  .page_size = 256,
325  },
326 /* .bank[1] = { */
327  {
328  .present = 0,
329  .probed = false,
330  .bank_number = 1,
331  },
332  },
333  },
334  {
335  .chipid_cidr = 0x28190560,
336  .name = "at91sam3u1e",
337  .total_flash_size = 64 * 1024,
338  .total_sram_size = 20 * 1024,
339  .n_gpnvms = 2,
340  .n_banks = 1,
341 
342  /* System boots at address 0x0 */
343  /* gpnvm[1] = selects boot code */
344  /* if gpnvm[1] == 0 */
345  /* boot is via "SAMBA" (rom) */
346  /* else */
347  /* boot is via FLASH */
348  /* Selection is via gpnvm[2] */
349  /* endif */
350  /* */
351 
352 /* .bank[0] = { */
353  {
354  {
355  .probed = false,
356  .chip = NULL,
357  .bank = NULL,
358  .bank_number = 0,
359  .base_address = FLASH_BANK0_BASE_U,
360  .controller_address = 0x400e0800,
361  .flash_wait_states = 6, /* workaround silicon bug */
362  .present = 1,
363  .size_bytes = 64 * 1024,
364  .nsectors = 8,
365  .sector_size = 8192,
366  .page_size = 256,
367  },
368 
369 /* .bank[1] = { */
370  {
371  .present = 0,
372  .probed = false,
373  .bank_number = 1,
374  },
375  },
376  },
377 
378  {
379  .chipid_cidr = 0x28000960,
380  .name = "at91sam3u4c",
381  .total_flash_size = 256 * 1024,
382  .total_sram_size = 52 * 1024,
383  .n_gpnvms = 3,
384  .n_banks = 2,
385 
386  /* System boots at address 0x0 */
387  /* gpnvm[1] = selects boot code */
388  /* if gpnvm[1] == 0 */
389  /* boot is via "SAMBA" (rom) */
390  /* else */
391  /* boot is via FLASH */
392  /* Selection is via gpnvm[2] */
393  /* endif */
394  /* */
395  /* NOTE: banks 0 & 1 switch places */
396  /* if gpnvm[2] == 0 */
397  /* Bank0 is the boot rom */
398  /* else */
399  /* Bank1 is the boot rom */
400  /* endif */
401  {
402  {
403 /* .bank[0] = { */
404  .probed = false,
405  .chip = NULL,
406  .bank = NULL,
407  .bank_number = 0,
408  .base_address = FLASH_BANK0_BASE_U,
409  .controller_address = 0x400e0800,
410  .flash_wait_states = 6, /* workaround silicon bug */
411  .present = 1,
412  .size_bytes = 128 * 1024,
413  .nsectors = 16,
414  .sector_size = 8192,
415  .page_size = 256,
416  },
417 /* .bank[1] = { */
418  {
419  .probed = false,
420  .chip = NULL,
421  .bank = NULL,
422  .bank_number = 1,
423  .base_address = FLASH_BANK1_BASE_U,
424  .controller_address = 0x400e0a00,
425  .flash_wait_states = 6, /* workaround silicon bug */
426  .present = 1,
427  .size_bytes = 128 * 1024,
428  .nsectors = 16,
429  .sector_size = 8192,
430  .page_size = 256,
431  },
432  },
433  },
434 
435  {
436  .chipid_cidr = 0x280a0760,
437  .name = "at91sam3u2c",
438  .total_flash_size = 128 * 1024,
439  .total_sram_size = 36 * 1024,
440  .n_gpnvms = 2,
441  .n_banks = 1,
442 
443  /* System boots at address 0x0 */
444  /* gpnvm[1] = selects boot code */
445  /* if gpnvm[1] == 0 */
446  /* boot is via "SAMBA" (rom) */
447  /* else */
448  /* boot is via FLASH */
449  /* Selection is via gpnvm[2] */
450  /* endif */
451  {
452 /* .bank[0] = { */
453  {
454  .probed = false,
455  .chip = NULL,
456  .bank = NULL,
457  .bank_number = 0,
458  .base_address = FLASH_BANK0_BASE_U,
459  .controller_address = 0x400e0800,
460  .flash_wait_states = 6, /* workaround silicon bug */
461  .present = 1,
462  .size_bytes = 128 * 1024,
463  .nsectors = 16,
464  .sector_size = 8192,
465  .page_size = 256,
466  },
467 /* .bank[1] = { */
468  {
469  .present = 0,
470  .probed = false,
471  .bank_number = 1,
472  },
473  },
474  },
475  {
476  .chipid_cidr = 0x28090560,
477  .name = "at91sam3u1c",
478  .total_flash_size = 64 * 1024,
479  .total_sram_size = 20 * 1024,
480  .n_gpnvms = 2,
481  .n_banks = 1,
482 
483  /* System boots at address 0x0 */
484  /* gpnvm[1] = selects boot code */
485  /* if gpnvm[1] == 0 */
486  /* boot is via "SAMBA" (rom) */
487  /* else */
488  /* boot is via FLASH */
489  /* Selection is via gpnvm[2] */
490  /* endif */
491  /* */
492 
493  {
494 /* .bank[0] = { */
495  {
496  .probed = false,
497  .chip = NULL,
498  .bank = NULL,
499  .bank_number = 0,
500  .base_address = FLASH_BANK0_BASE_U,
501  .controller_address = 0x400e0800,
502  .flash_wait_states = 6, /* workaround silicon bug */
503  .present = 1,
504  .size_bytes = 64 * 1024,
505  .nsectors = 8,
506  .sector_size = 8192,
507  .page_size = 256,
508  },
509 /* .bank[1] = { */
510  {
511  .present = 0,
512  .probed = false,
513  .bank_number = 1,
514 
515  },
516  },
517  },
518 
519  /* Start at91sam3s* series */
520 
521  /* Note: The preliminary at91sam3s datasheet says on page 302 */
522  /* that the flash controller is at address 0x400E0800. */
523  /* This is _not_ the case, the controller resides at address 0x400e0a00. */
524  {
525  .chipid_cidr = 0x28A00960,
526  .name = "at91sam3s4c",
527  .total_flash_size = 256 * 1024,
528  .total_sram_size = 48 * 1024,
529  .n_gpnvms = 2,
530  .n_banks = 1,
531  {
532 /* .bank[0] = { */
533  {
534  .probed = false,
535  .chip = NULL,
536  .bank = NULL,
537  .bank_number = 0,
538  .base_address = FLASH_BANK_BASE_S,
539  .controller_address = 0x400e0a00,
540  .flash_wait_states = 6, /* workaround silicon bug */
541  .present = 1,
542  .size_bytes = 256 * 1024,
543  .nsectors = 16,
544  .sector_size = 16384,
545  .page_size = 256,
546  },
547 /* .bank[1] = { */
548  {
549  .present = 0,
550  .probed = false,
551  .bank_number = 1,
552 
553  },
554  },
555  },
556 
557  {
558  .chipid_cidr = 0x28900960,
559  .name = "at91sam3s4b",
560  .total_flash_size = 256 * 1024,
561  .total_sram_size = 48 * 1024,
562  .n_gpnvms = 2,
563  .n_banks = 1,
564  {
565 /* .bank[0] = { */
566  {
567  .probed = false,
568  .chip = NULL,
569  .bank = NULL,
570  .bank_number = 0,
571  .base_address = FLASH_BANK_BASE_S,
572  .controller_address = 0x400e0a00,
573  .flash_wait_states = 6, /* workaround silicon bug */
574  .present = 1,
575  .size_bytes = 256 * 1024,
576  .nsectors = 16,
577  .sector_size = 16384,
578  .page_size = 256,
579  },
580 /* .bank[1] = { */
581  {
582  .present = 0,
583  .probed = false,
584  .bank_number = 1,
585 
586  },
587  },
588  },
589  {
590  .chipid_cidr = 0x28800960,
591  .name = "at91sam3s4a",
592  .total_flash_size = 256 * 1024,
593  .total_sram_size = 48 * 1024,
594  .n_gpnvms = 2,
595  .n_banks = 1,
596  {
597 /* .bank[0] = { */
598  {
599  .probed = false,
600  .chip = NULL,
601  .bank = NULL,
602  .bank_number = 0,
603  .base_address = FLASH_BANK_BASE_S,
604  .controller_address = 0x400e0a00,
605  .flash_wait_states = 6, /* workaround silicon bug */
606  .present = 1,
607  .size_bytes = 256 * 1024,
608  .nsectors = 16,
609  .sector_size = 16384,
610  .page_size = 256,
611  },
612 /* .bank[1] = { */
613  {
614  .present = 0,
615  .probed = false,
616  .bank_number = 1,
617 
618  },
619  },
620  },
621  {
622  .chipid_cidr = 0x28AA0760,
623  .name = "at91sam3s2c",
624  .total_flash_size = 128 * 1024,
625  .total_sram_size = 32 * 1024,
626  .n_gpnvms = 2,
627  .n_banks = 1,
628  {
629 /* .bank[0] = { */
630  {
631  .probed = false,
632  .chip = NULL,
633  .bank = NULL,
634  .bank_number = 0,
635  .base_address = FLASH_BANK_BASE_S,
636  .controller_address = 0x400e0a00,
637  .flash_wait_states = 6, /* workaround silicon bug */
638  .present = 1,
639  .size_bytes = 128 * 1024,
640  .nsectors = 8,
641  .sector_size = 16384,
642  .page_size = 256,
643  },
644 /* .bank[1] = { */
645  {
646  .present = 0,
647  .probed = false,
648  .bank_number = 1,
649 
650  },
651  },
652  },
653  {
654  .chipid_cidr = 0x289A0760,
655  .name = "at91sam3s2b",
656  .total_flash_size = 128 * 1024,
657  .total_sram_size = 32 * 1024,
658  .n_gpnvms = 2,
659  .n_banks = 1,
660  {
661 /* .bank[0] = { */
662  {
663  .probed = false,
664  .chip = NULL,
665  .bank = NULL,
666  .bank_number = 0,
667  .base_address = FLASH_BANK_BASE_S,
668  .controller_address = 0x400e0a00,
669  .flash_wait_states = 6, /* workaround silicon bug */
670  .present = 1,
671  .size_bytes = 128 * 1024,
672  .nsectors = 8,
673  .sector_size = 16384,
674  .page_size = 256,
675  },
676 /* .bank[1] = { */
677  {
678  .present = 0,
679  .probed = false,
680  .bank_number = 1,
681 
682  },
683  },
684  },
685  {
686  .chipid_cidr = 0x298B0A60,
687  .name = "at91sam3sd8a",
688  .total_flash_size = 512 * 1024,
689  .total_sram_size = 64 * 1024,
690  .n_gpnvms = 3,
691  .n_banks = 2,
692  {
693 /* .bank[0] = { */
694  {
695  .probed = false,
696  .chip = NULL,
697  .bank = NULL,
698  .bank_number = 0,
699  .base_address = FLASH_BANK0_BASE_SD,
700  .controller_address = 0x400e0a00,
701  .flash_wait_states = 6, /* workaround silicon bug */
702  .present = 1,
703  .size_bytes = 256 * 1024,
704  .nsectors = 16,
705  .sector_size = 32768,
706  .page_size = 256,
707  },
708 /* .bank[1] = { */
709  {
710  .probed = false,
711  .chip = NULL,
712  .bank = NULL,
713  .bank_number = 1,
714  .base_address = FLASH_BANK1_BASE_512K_SD,
715  .controller_address = 0x400e0a00,
716  .flash_wait_states = 6, /* workaround silicon bug */
717  .present = 1,
718  .size_bytes = 256 * 1024,
719  .nsectors = 16,
720  .sector_size = 32768,
721  .page_size = 256,
722  },
723  },
724  },
725  {
726  .chipid_cidr = 0x299B0A60,
727  .name = "at91sam3sd8b",
728  .total_flash_size = 512 * 1024,
729  .total_sram_size = 64 * 1024,
730  .n_gpnvms = 3,
731  .n_banks = 2,
732  {
733 /* .bank[0] = { */
734  {
735  .probed = false,
736  .chip = NULL,
737  .bank = NULL,
738  .bank_number = 0,
739  .base_address = FLASH_BANK0_BASE_SD,
740  .controller_address = 0x400e0a00,
741  .flash_wait_states = 6, /* workaround silicon bug */
742  .present = 1,
743  .size_bytes = 256 * 1024,
744  .nsectors = 16,
745  .sector_size = 32768,
746  .page_size = 256,
747  },
748 /* .bank[1] = { */
749  {
750  .probed = false,
751  .chip = NULL,
752  .bank = NULL,
753  .bank_number = 1,
754  .base_address = FLASH_BANK1_BASE_512K_SD,
755  .controller_address = 0x400e0a00,
756  .flash_wait_states = 6, /* workaround silicon bug */
757  .present = 1,
758  .size_bytes = 256 * 1024,
759  .nsectors = 16,
760  .sector_size = 32768,
761  .page_size = 256,
762  },
763  },
764  },
765  {
766  .chipid_cidr = 0x29ab0a60,
767  .name = "at91sam3sd8c",
768  .total_flash_size = 512 * 1024,
769  .total_sram_size = 64 * 1024,
770  .n_gpnvms = 3,
771  .n_banks = 2,
772  {
773 /* .bank[0] = { */
774  {
775  .probed = false,
776  .chip = NULL,
777  .bank = NULL,
778  .bank_number = 0,
779  .base_address = FLASH_BANK0_BASE_SD,
780  .controller_address = 0x400e0a00,
781  .flash_wait_states = 6, /* workaround silicon bug */
782  .present = 1,
783  .size_bytes = 256 * 1024,
784  .nsectors = 16,
785  .sector_size = 32768,
786  .page_size = 256,
787  },
788 /* .bank[1] = { */
789  {
790  .probed = false,
791  .chip = NULL,
792  .bank = NULL,
793  .bank_number = 1,
794  .base_address = FLASH_BANK1_BASE_512K_SD,
795  .controller_address = 0x400e0a00,
796  .flash_wait_states = 6, /* workaround silicon bug */
797  .present = 1,
798  .size_bytes = 256 * 1024,
799  .nsectors = 16,
800  .sector_size = 32768,
801  .page_size = 256,
802  },
803  },
804  },
805  {
806  .chipid_cidr = 0x288A0760,
807  .name = "at91sam3s2a",
808  .total_flash_size = 128 * 1024,
809  .total_sram_size = 32 * 1024,
810  .n_gpnvms = 2,
811  .n_banks = 1,
812  {
813 /* .bank[0] = { */
814  {
815  .probed = false,
816  .chip = NULL,
817  .bank = NULL,
818  .bank_number = 0,
819  .base_address = FLASH_BANK_BASE_S,
820  .controller_address = 0x400e0a00,
821  .flash_wait_states = 6, /* workaround silicon bug */
822  .present = 1,
823  .size_bytes = 128 * 1024,
824  .nsectors = 8,
825  .sector_size = 16384,
826  .page_size = 256,
827  },
828 /* .bank[1] = { */
829  {
830  .present = 0,
831  .probed = false,
832  .bank_number = 1,
833 
834  },
835  },
836  },
837  {
838  .chipid_cidr = 0x28A90560,
839  .name = "at91sam3s1c",
840  .total_flash_size = 64 * 1024,
841  .total_sram_size = 16 * 1024,
842  .n_gpnvms = 2,
843  .n_banks = 1,
844  {
845 /* .bank[0] = { */
846  {
847  .probed = false,
848  .chip = NULL,
849  .bank = NULL,
850  .bank_number = 0,
851  .base_address = FLASH_BANK_BASE_S,
852  .controller_address = 0x400e0a00,
853  .flash_wait_states = 6, /* workaround silicon bug */
854  .present = 1,
855  .size_bytes = 64 * 1024,
856  .nsectors = 4,
857  .sector_size = 16384,
858  .page_size = 256,
859  },
860 /* .bank[1] = { */
861  {
862  .present = 0,
863  .probed = false,
864  .bank_number = 1,
865 
866  },
867  },
868  },
869  {
870  .chipid_cidr = 0x28990560,
871  .name = "at91sam3s1b",
872  .total_flash_size = 64 * 1024,
873  .total_sram_size = 16 * 1024,
874  .n_gpnvms = 2,
875  .n_banks = 1,
876  {
877 /* .bank[0] = { */
878  {
879  .probed = false,
880  .chip = NULL,
881  .bank = NULL,
882  .bank_number = 0,
883  .base_address = FLASH_BANK_BASE_S,
884  .controller_address = 0x400e0a00,
885  .flash_wait_states = 6, /* workaround silicon bug */
886  .present = 1,
887  .size_bytes = 64 * 1024,
888  .nsectors = 4,
889  .sector_size = 16384,
890  .page_size = 256,
891  },
892 /* .bank[1] = { */
893  {
894  .present = 0,
895  .probed = false,
896  .bank_number = 1,
897 
898  },
899  },
900  },
901  {
902  .chipid_cidr = 0x28890560,
903  .name = "at91sam3s1a",
904  .total_flash_size = 64 * 1024,
905  .total_sram_size = 16 * 1024,
906  .n_gpnvms = 2,
907  .n_banks = 1,
908  {
909 /* .bank[0] = { */
910  {
911  .probed = false,
912  .chip = NULL,
913  .bank = NULL,
914  .bank_number = 0,
915  .base_address = FLASH_BANK_BASE_S,
916  .controller_address = 0x400e0a00,
917  .flash_wait_states = 6, /* workaround silicon bug */
918  .present = 1,
919  .size_bytes = 64 * 1024,
920  .nsectors = 4,
921  .sector_size = 16384,
922  .page_size = 256,
923  },
924 /* .bank[1] = { */
925  {
926  .present = 0,
927  .probed = false,
928  .bank_number = 1,
929 
930  },
931  },
932  },
933  {
934  .chipid_cidr = 0x288B0A60,
935  .name = "at91sam3s8a",
936  .total_flash_size = 256 * 2048,
937  .total_sram_size = 64 * 1024,
938  .n_gpnvms = 2,
939  .n_banks = 1,
940  {
941 /* .bank[0] = { */
942  {
943  .probed = false,
944  .chip = NULL,
945  .bank = NULL,
946  .bank_number = 0,
947  .base_address = FLASH_BANK_BASE_S,
948  .controller_address = 0x400e0a00,
949  .flash_wait_states = 6, /* workaround silicon bug */
950  .present = 1,
951  .size_bytes = 256 * 2048,
952  .nsectors = 16,
953  .sector_size = 32768,
954  .page_size = 256,
955  },
956 /* .bank[1] = { */
957  {
958  .present = 0,
959  .probed = false,
960  .bank_number = 1,
961 
962  },
963  },
964  },
965  {
966  .chipid_cidr = 0x289B0A60,
967  .name = "at91sam3s8b",
968  .total_flash_size = 256 * 2048,
969  .total_sram_size = 64 * 1024,
970  .n_gpnvms = 2,
971  .n_banks = 1,
972  {
973 /* .bank[0] = { */
974  {
975  .probed = false,
976  .chip = NULL,
977  .bank = NULL,
978  .bank_number = 0,
979  .base_address = FLASH_BANK_BASE_S,
980  .controller_address = 0x400e0a00,
981  .flash_wait_states = 6, /* workaround silicon bug */
982  .present = 1,
983  .size_bytes = 256 * 2048,
984  .nsectors = 16,
985  .sector_size = 32768,
986  .page_size = 256,
987  },
988 /* .bank[1] = { */
989  {
990  .present = 0,
991  .probed = false,
992  .bank_number = 1,
993 
994  },
995  },
996  },
997  {
998  .chipid_cidr = 0x28AB0A60,
999  .name = "at91sam3s8c",
1000  .total_flash_size = 256 * 2048,
1001  .total_sram_size = 64 * 1024,
1002  .n_gpnvms = 2,
1003  .n_banks = 1,
1004  {
1005 /* .bank[0] = { */
1006  {
1007  .probed = false,
1008  .chip = NULL,
1009  .bank = NULL,
1010  .bank_number = 0,
1011  .base_address = FLASH_BANK_BASE_S,
1012  .controller_address = 0x400e0a00,
1013  .flash_wait_states = 6, /* workaround silicon bug */
1014  .present = 1,
1015  .size_bytes = 256 * 2048,
1016  .nsectors = 16,
1017  .sector_size = 32768,
1018  .page_size = 256,
1019  },
1020 /* .bank[1] = { */
1021  {
1022  .present = 0,
1023  .probed = false,
1024  .bank_number = 1,
1025 
1026  },
1027  },
1028  },
1029 
1030  /* Start at91sam3n* series */
1031  {
1032  .chipid_cidr = 0x29540960,
1033  .name = "at91sam3n4c",
1034  .total_flash_size = 256 * 1024,
1035  .total_sram_size = 24 * 1024,
1036  .n_gpnvms = 3,
1037  .n_banks = 1,
1038 
1039  /* System boots at address 0x0 */
1040  /* gpnvm[1] = selects boot code */
1041  /* if gpnvm[1] == 0 */
1042  /* boot is via "SAMBA" (rom) */
1043  /* else */
1044  /* boot is via FLASH */
1045  /* Selection is via gpnvm[2] */
1046  /* endif */
1047  /* */
1048  /* NOTE: banks 0 & 1 switch places */
1049  /* if gpnvm[2] == 0 */
1050  /* Bank0 is the boot rom */
1051  /* else */
1052  /* Bank1 is the boot rom */
1053  /* endif */
1054 /* .bank[0] = { */
1055  {
1056  {
1057  .probed = false,
1058  .chip = NULL,
1059  .bank = NULL,
1060  .bank_number = 0,
1061  .base_address = FLASH_BANK_BASE_N,
1062  .controller_address = 0x400e0A00,
1063  .flash_wait_states = 6, /* workaround silicon bug */
1064  .present = 1,
1065  .size_bytes = 256 * 1024,
1066  .nsectors = 16,
1067  .sector_size = 16384,
1068  .page_size = 256,
1069  },
1070 
1071 /* .bank[1] = { */
1072  {
1073  .present = 0,
1074  .probed = false,
1075  .bank_number = 1,
1076  },
1077  },
1078  },
1079 
1080  {
1081  .chipid_cidr = 0x29440960,
1082  .name = "at91sam3n4b",
1083  .total_flash_size = 256 * 1024,
1084  .total_sram_size = 24 * 1024,
1085  .n_gpnvms = 3,
1086  .n_banks = 1,
1087 
1088  /* System boots at address 0x0 */
1089  /* gpnvm[1] = selects boot code */
1090  /* if gpnvm[1] == 0 */
1091  /* boot is via "SAMBA" (rom) */
1092  /* else */
1093  /* boot is via FLASH */
1094  /* Selection is via gpnvm[2] */
1095  /* endif */
1096  /* */
1097  /* NOTE: banks 0 & 1 switch places */
1098  /* if gpnvm[2] == 0 */
1099  /* Bank0 is the boot rom */
1100  /* else */
1101  /* Bank1 is the boot rom */
1102  /* endif */
1103 /* .bank[0] = { */
1104  {
1105  {
1106  .probed = false,
1107  .chip = NULL,
1108  .bank = NULL,
1109  .bank_number = 0,
1110  .base_address = FLASH_BANK_BASE_N,
1111  .controller_address = 0x400e0A00,
1112  .flash_wait_states = 6, /* workaround silicon bug */
1113  .present = 1,
1114  .size_bytes = 256 * 1024,
1115  .nsectors = 16,
1116  .sector_size = 16384,
1117  .page_size = 256,
1118  },
1119 
1120 /* .bank[1] = { */
1121  {
1122  .present = 0,
1123  .probed = false,
1124  .bank_number = 1,
1125  },
1126  },
1127  },
1128 
1129  {
1130  .chipid_cidr = 0x29340960,
1131  .name = "at91sam3n4a",
1132  .total_flash_size = 256 * 1024,
1133  .total_sram_size = 24 * 1024,
1134  .n_gpnvms = 3,
1135  .n_banks = 1,
1136 
1137  /* System boots at address 0x0 */
1138  /* gpnvm[1] = selects boot code */
1139  /* if gpnvm[1] == 0 */
1140  /* boot is via "SAMBA" (rom) */
1141  /* else */
1142  /* boot is via FLASH */
1143  /* Selection is via gpnvm[2] */
1144  /* endif */
1145  /* */
1146  /* NOTE: banks 0 & 1 switch places */
1147  /* if gpnvm[2] == 0 */
1148  /* Bank0 is the boot rom */
1149  /* else */
1150  /* Bank1 is the boot rom */
1151  /* endif */
1152 /* .bank[0] = { */
1153  {
1154  {
1155  .probed = false,
1156  .chip = NULL,
1157  .bank = NULL,
1158  .bank_number = 0,
1159  .base_address = FLASH_BANK_BASE_N,
1160  .controller_address = 0x400e0A00,
1161  .flash_wait_states = 6, /* workaround silicon bug */
1162  .present = 1,
1163  .size_bytes = 256 * 1024,
1164  .nsectors = 16,
1165  .sector_size = 16384,
1166  .page_size = 256,
1167  },
1168 
1169 /* .bank[1] = { */
1170  {
1171  .present = 0,
1172  .probed = false,
1173  .bank_number = 1,
1174  },
1175  },
1176  },
1177 
1178  {
1179  .chipid_cidr = 0x29590760,
1180  .name = "at91sam3n2c",
1181  .total_flash_size = 128 * 1024,
1182  .total_sram_size = 16 * 1024,
1183  .n_gpnvms = 3,
1184  .n_banks = 1,
1185 
1186  /* System boots at address 0x0 */
1187  /* gpnvm[1] = selects boot code */
1188  /* if gpnvm[1] == 0 */
1189  /* boot is via "SAMBA" (rom) */
1190  /* else */
1191  /* boot is via FLASH */
1192  /* Selection is via gpnvm[2] */
1193  /* endif */
1194  /* */
1195  /* NOTE: banks 0 & 1 switch places */
1196  /* if gpnvm[2] == 0 */
1197  /* Bank0 is the boot rom */
1198  /* else */
1199  /* Bank1 is the boot rom */
1200  /* endif */
1201 /* .bank[0] = { */
1202  {
1203  {
1204  .probed = false,
1205  .chip = NULL,
1206  .bank = NULL,
1207  .bank_number = 0,
1208  .base_address = FLASH_BANK_BASE_N,
1209  .controller_address = 0x400e0A00,
1210  .flash_wait_states = 6, /* workaround silicon bug */
1211  .present = 1,
1212  .size_bytes = 128 * 1024,
1213  .nsectors = 8,
1214  .sector_size = 16384,
1215  .page_size = 256,
1216  },
1217 
1218 /* .bank[1] = { */
1219  {
1220  .present = 0,
1221  .probed = false,
1222  .bank_number = 1,
1223  },
1224  },
1225  },
1226 
1227  {
1228  .chipid_cidr = 0x29490760,
1229  .name = "at91sam3n2b",
1230  .total_flash_size = 128 * 1024,
1231  .total_sram_size = 16 * 1024,
1232  .n_gpnvms = 3,
1233  .n_banks = 1,
1234 
1235  /* System boots at address 0x0 */
1236  /* gpnvm[1] = selects boot code */
1237  /* if gpnvm[1] == 0 */
1238  /* boot is via "SAMBA" (rom) */
1239  /* else */
1240  /* boot is via FLASH */
1241  /* Selection is via gpnvm[2] */
1242  /* endif */
1243  /* */
1244  /* NOTE: banks 0 & 1 switch places */
1245  /* if gpnvm[2] == 0 */
1246  /* Bank0 is the boot rom */
1247  /* else */
1248  /* Bank1 is the boot rom */
1249  /* endif */
1250 /* .bank[0] = { */
1251  {
1252  {
1253  .probed = false,
1254  .chip = NULL,
1255  .bank = NULL,
1256  .bank_number = 0,
1257  .base_address = FLASH_BANK_BASE_N,
1258  .controller_address = 0x400e0A00,
1259  .flash_wait_states = 6, /* workaround silicon bug */
1260  .present = 1,
1261  .size_bytes = 128 * 1024,
1262  .nsectors = 8,
1263  .sector_size = 16384,
1264  .page_size = 256,
1265  },
1266 
1267 /* .bank[1] = { */
1268  {
1269  .present = 0,
1270  .probed = false,
1271  .bank_number = 1,
1272  },
1273  },
1274  },
1275 
1276  {
1277  .chipid_cidr = 0x29390760,
1278  .name = "at91sam3n2a",
1279  .total_flash_size = 128 * 1024,
1280  .total_sram_size = 16 * 1024,
1281  .n_gpnvms = 3,
1282  .n_banks = 1,
1283 
1284  /* System boots at address 0x0 */
1285  /* gpnvm[1] = selects boot code */
1286  /* if gpnvm[1] == 0 */
1287  /* boot is via "SAMBA" (rom) */
1288  /* else */
1289  /* boot is via FLASH */
1290  /* Selection is via gpnvm[2] */
1291  /* endif */
1292  /* */
1293  /* NOTE: banks 0 & 1 switch places */
1294  /* if gpnvm[2] == 0 */
1295  /* Bank0 is the boot rom */
1296  /* else */
1297  /* Bank1 is the boot rom */
1298  /* endif */
1299 /* .bank[0] = { */
1300  {
1301  {
1302  .probed = false,
1303  .chip = NULL,
1304  .bank = NULL,
1305  .bank_number = 0,
1306  .base_address = FLASH_BANK_BASE_N,
1307  .controller_address = 0x400e0A00,
1308  .flash_wait_states = 6, /* workaround silicon bug */
1309  .present = 1,
1310  .size_bytes = 128 * 1024,
1311  .nsectors = 8,
1312  .sector_size = 16384,
1313  .page_size = 256,
1314  },
1315 
1316 /* .bank[1] = { */
1317  {
1318  .present = 0,
1319  .probed = false,
1320  .bank_number = 1,
1321  },
1322  },
1323  },
1324 
1325  {
1326  .chipid_cidr = 0x29580560,
1327  .name = "at91sam3n1c",
1328  .total_flash_size = 64 * 1024,
1329  .total_sram_size = 8 * 1024,
1330  .n_gpnvms = 3,
1331  .n_banks = 1,
1332 
1333  /* System boots at address 0x0 */
1334  /* gpnvm[1] = selects boot code */
1335  /* if gpnvm[1] == 0 */
1336  /* boot is via "SAMBA" (rom) */
1337  /* else */
1338  /* boot is via FLASH */
1339  /* Selection is via gpnvm[2] */
1340  /* endif */
1341  /* */
1342  /* NOTE: banks 0 & 1 switch places */
1343  /* if gpnvm[2] == 0 */
1344  /* Bank0 is the boot rom */
1345  /* else */
1346  /* Bank1 is the boot rom */
1347  /* endif */
1348 /* .bank[0] = { */
1349  {
1350  {
1351  .probed = false,
1352  .chip = NULL,
1353  .bank = NULL,
1354  .bank_number = 0,
1355  .base_address = FLASH_BANK_BASE_N,
1356  .controller_address = 0x400e0A00,
1357  .flash_wait_states = 6, /* workaround silicon bug */
1358  .present = 1,
1359  .size_bytes = 64 * 1024,
1360  .nsectors = 4,
1361  .sector_size = 16384,
1362  .page_size = 256,
1363  },
1364 
1365 /* .bank[1] = { */
1366  {
1367  .present = 0,
1368  .probed = false,
1369  .bank_number = 1,
1370  },
1371  },
1372  },
1373 
1374  {
1375  .chipid_cidr = 0x29480560,
1376  .name = "at91sam3n1b",
1377  .total_flash_size = 64 * 1024,
1378  .total_sram_size = 8 * 1024,
1379  .n_gpnvms = 3,
1380  .n_banks = 1,
1381 
1382  /* System boots at address 0x0 */
1383  /* gpnvm[1] = selects boot code */
1384  /* if gpnvm[1] == 0 */
1385  /* boot is via "SAMBA" (rom) */
1386  /* else */
1387  /* boot is via FLASH */
1388  /* Selection is via gpnvm[2] */
1389  /* endif */
1390  /* */
1391  /* NOTE: banks 0 & 1 switch places */
1392  /* if gpnvm[2] == 0 */
1393  /* Bank0 is the boot rom */
1394  /* else */
1395  /* Bank1 is the boot rom */
1396  /* endif */
1397 /* .bank[0] = { */
1398  {
1399  {
1400  .probed = false,
1401  .chip = NULL,
1402  .bank = NULL,
1403  .bank_number = 0,
1404  .base_address = FLASH_BANK_BASE_N,
1405  .controller_address = 0x400e0A00,
1406  .flash_wait_states = 6, /* workaround silicon bug */
1407  .present = 1,
1408  .size_bytes = 64 * 1024,
1409  .nsectors = 4,
1410  .sector_size = 16384,
1411  .page_size = 256,
1412  },
1413 
1414 /* .bank[1] = { */
1415  {
1416  .present = 0,
1417  .probed = false,
1418  .bank_number = 1,
1419  },
1420  },
1421  },
1422 
1423  {
1424  .chipid_cidr = 0x29380560,
1425  .name = "at91sam3n1a",
1426  .total_flash_size = 64 * 1024,
1427  .total_sram_size = 8 * 1024,
1428  .n_gpnvms = 3,
1429  .n_banks = 1,
1430 
1431  /* System boots at address 0x0 */
1432  /* gpnvm[1] = selects boot code */
1433  /* if gpnvm[1] == 0 */
1434  /* boot is via "SAMBA" (rom) */
1435  /* else */
1436  /* boot is via FLASH */
1437  /* Selection is via gpnvm[2] */
1438  /* endif */
1439  /* */
1440  /* NOTE: banks 0 & 1 switch places */
1441  /* if gpnvm[2] == 0 */
1442  /* Bank0 is the boot rom */
1443  /* else */
1444  /* Bank1 is the boot rom */
1445  /* endif */
1446 /* .bank[0] = { */
1447  {
1448  {
1449  .probed = false,
1450  .chip = NULL,
1451  .bank = NULL,
1452  .bank_number = 0,
1453  .base_address = FLASH_BANK_BASE_N,
1454  .controller_address = 0x400e0A00,
1455  .flash_wait_states = 6, /* workaround silicon bug */
1456  .present = 1,
1457  .size_bytes = 64 * 1024,
1458  .nsectors = 4,
1459  .sector_size = 16384,
1460  .page_size = 256,
1461  },
1462 
1463 /* .bank[1] = { */
1464  {
1465  .present = 0,
1466  .probed = false,
1467  .bank_number = 1,
1468  },
1469  },
1470  },
1471 
1472  {
1473  .chipid_cidr = 0x29480360,
1474  .name = "at91sam3n0b",
1475  .total_flash_size = 32 * 1024,
1476  .total_sram_size = 8 * 1024,
1477  .n_gpnvms = 3,
1478  .n_banks = 1,
1479 
1480 /* .bank[0] = { */
1481  {
1482  {
1483  .probed = false,
1484  .chip = NULL,
1485  .bank = NULL,
1486  .bank_number = 0,
1487  .base_address = FLASH_BANK_BASE_N,
1488  .controller_address = 0x400e0A00,
1489  .flash_wait_states = 6, /* workaround silicon bug */
1490  .present = 1,
1491  .size_bytes = 32 * 1024,
1492  .nsectors = 2,
1493  .sector_size = 16384,
1494  .page_size = 256,
1495  },
1496 
1497 /* .bank[1] = { */
1498  {
1499  .present = 0,
1500  .probed = false,
1501  .bank_number = 1,
1502  },
1503  },
1504  },
1505 
1506  {
1507  .chipid_cidr = 0x29380360,
1508  .name = "at91sam3n0a",
1509  .total_flash_size = 32 * 1024,
1510  .total_sram_size = 8 * 1024,
1511  .n_gpnvms = 3,
1512  .n_banks = 1,
1513 
1514 /* .bank[0] = { */
1515  {
1516  {
1517  .probed = false,
1518  .chip = NULL,
1519  .bank = NULL,
1520  .bank_number = 0,
1521  .base_address = FLASH_BANK_BASE_N,
1522  .controller_address = 0x400e0A00,
1523  .flash_wait_states = 6, /* workaround silicon bug */
1524  .present = 1,
1525  .size_bytes = 32 * 1024,
1526  .nsectors = 2,
1527  .sector_size = 16384,
1528  .page_size = 256,
1529  },
1530 
1531 /* .bank[1] = { */
1532  {
1533  .present = 0,
1534  .probed = false,
1535  .bank_number = 1,
1536  },
1537  },
1538  },
1539 
1540  {
1541  .chipid_cidr = 0x29450260,
1542  .name = "at91sam3n00b",
1543  .total_flash_size = 16 * 1024,
1544  .total_sram_size = 4 * 1024,
1545  .n_gpnvms = 3,
1546  .n_banks = 1,
1547 
1548 /* .bank[0] = { */
1549  {
1550  {
1551  .probed = false,
1552  .chip = NULL,
1553  .bank = NULL,
1554  .bank_number = 0,
1555  .base_address = FLASH_BANK_BASE_N,
1556  .controller_address = 0x400e0A00,
1557  .flash_wait_states = 6, /* workaround silicon bug */
1558  .present = 1,
1559  .size_bytes = 16 * 1024,
1560  .nsectors = 1,
1561  .sector_size = 16384,
1562  .page_size = 256,
1563  },
1564 
1565 /* .bank[1] = { */
1566  {
1567  .present = 0,
1568  .probed = false,
1569  .bank_number = 1,
1570  },
1571  },
1572  },
1573 
1574  {
1575  .chipid_cidr = 0x29350260,
1576  .name = "at91sam3n00a",
1577  .total_flash_size = 16 * 1024,
1578  .total_sram_size = 4 * 1024,
1579  .n_gpnvms = 3,
1580  .n_banks = 1,
1581 
1582 /* .bank[0] = { */
1583  {
1584  {
1585  .probed = false,
1586  .chip = NULL,
1587  .bank = NULL,
1588  .bank_number = 0,
1589  .base_address = FLASH_BANK_BASE_N,
1590  .controller_address = 0x400e0A00,
1591  .flash_wait_states = 6, /* workaround silicon bug */
1592  .present = 1,
1593  .size_bytes = 16 * 1024,
1594  .nsectors = 1,
1595  .sector_size = 16384,
1596  .page_size = 256,
1597  },
1598 
1599 /* .bank[1] = { */
1600  {
1601  .present = 0,
1602  .probed = false,
1603  .bank_number = 1,
1604  },
1605  },
1606  },
1607 
1608 
1609  /* Start at91sam3a series*/
1610  /* System boots at address 0x0 */
1611  /* gpnvm[1] = selects boot code */
1612  /* if gpnvm[1] == 0 */
1613  /* boot is via "SAMBA" (rom) */
1614  /* else */
1615  /* boot is via FLASH */
1616  /* Selection is via gpnvm[2] */
1617  /* endif */
1618  /* */
1619  /* NOTE: banks 0 & 1 switch places */
1620  /* if gpnvm[2] == 0 */
1621  /* Bank0 is the boot rom */
1622  /* else */
1623  /* Bank1 is the boot rom */
1624  /* endif */
1625 
1626  {
1627  .chipid_cidr = 0x283E0A60,
1628  .name = "at91sam3a8c",
1629  .total_flash_size = 512 * 1024,
1630  .total_sram_size = 96 * 1024,
1631  .n_gpnvms = 3,
1632  .n_banks = 2,
1633  {
1634 /* .bank[0] = { */
1635  {
1636  .probed = false,
1637  .chip = NULL,
1638  .bank = NULL,
1639  .bank_number = 0,
1640  .base_address = FLASH_BANK0_BASE_AX,
1641  .controller_address = 0x400e0a00,
1642  .flash_wait_states = 6, /* workaround silicon bug */
1643  .present = 1,
1644  .size_bytes = 256 * 1024,
1645  .nsectors = 16,
1646  .sector_size = 16384,
1647  .page_size = 256,
1648  },
1649 /* .bank[1] = { */
1650  {
1651  .probed = false,
1652  .chip = NULL,
1653  .bank = NULL,
1654  .bank_number = 1,
1655  .base_address = FLASH_BANK1_BASE_512K_AX,
1656  .controller_address = 0x400e0c00,
1657  .flash_wait_states = 6, /* workaround silicon bug */
1658  .present = 1,
1659  .size_bytes = 256 * 1024,
1660  .nsectors = 16,
1661  .sector_size = 16384,
1662  .page_size = 256,
1663 
1664  },
1665  },
1666  },
1667  {
1668  .chipid_cidr = 0x283B0960,
1669  .name = "at91sam3a4c",
1670  .total_flash_size = 256 * 1024,
1671  .total_sram_size = 64 * 1024,
1672  .n_gpnvms = 3,
1673  .n_banks = 2,
1674  {
1675 /* .bank[0] = { */
1676  {
1677  .probed = false,
1678  .chip = NULL,
1679  .bank = NULL,
1680  .bank_number = 0,
1681  .base_address = FLASH_BANK0_BASE_AX,
1682  .controller_address = 0x400e0a00,
1683  .flash_wait_states = 6, /* workaround silicon bug */
1684  .present = 1,
1685  .size_bytes = 128 * 1024,
1686  .nsectors = 8,
1687  .sector_size = 16384,
1688  .page_size = 256,
1689  },
1690 /* .bank[1] = { */
1691  {
1692  .probed = false,
1693  .chip = NULL,
1694  .bank = NULL,
1695  .bank_number = 1,
1696  .base_address = FLASH_BANK1_BASE_256K_AX,
1697  .controller_address = 0x400e0c00,
1698  .flash_wait_states = 6, /* workaround silicon bug */
1699  .present = 1,
1700  .size_bytes = 128 * 1024,
1701  .nsectors = 8,
1702  .sector_size = 16384,
1703  .page_size = 256,
1704 
1705  },
1706  },
1707  },
1708 
1709  /* Start at91sam3x* series */
1710  /* System boots at address 0x0 */
1711  /* gpnvm[1] = selects boot code */
1712  /* if gpnvm[1] == 0 */
1713  /* boot is via "SAMBA" (rom) */
1714  /* else */
1715  /* boot is via FLASH */
1716  /* Selection is via gpnvm[2] */
1717  /* endif */
1718  /* */
1719  /* NOTE: banks 0 & 1 switch places */
1720  /* if gpnvm[2] == 0 */
1721  /* Bank0 is the boot rom */
1722  /* else */
1723  /* Bank1 is the boot rom */
1724  /* endif */
1725  /*at91sam3x8h - ES has an incorrect CIDR of 0x286E0A20*/
1726  {
1727  .chipid_cidr = 0x286E0A20,
1728  .name = "at91sam3x8h - ES",
1729  .total_flash_size = 512 * 1024,
1730  .total_sram_size = 96 * 1024,
1731  .n_gpnvms = 3,
1732  .n_banks = 2,
1733  {
1734 /* .bank[0] = { */
1735  {
1736  .probed = false,
1737  .chip = NULL,
1738  .bank = NULL,
1739  .bank_number = 0,
1740  .base_address = FLASH_BANK0_BASE_AX,
1741  .controller_address = 0x400e0a00,
1742  .flash_wait_states = 6, /* workaround silicon bug */
1743  .present = 1,
1744  .size_bytes = 256 * 1024,
1745  .nsectors = 16,
1746  .sector_size = 16384,
1747  .page_size = 256,
1748  },
1749 /* .bank[1] = { */
1750  {
1751  .probed = false,
1752  .chip = NULL,
1753  .bank = NULL,
1754  .bank_number = 1,
1755  .base_address = FLASH_BANK1_BASE_512K_AX,
1756  .controller_address = 0x400e0c00,
1757  .flash_wait_states = 6, /* workaround silicon bug */
1758  .present = 1,
1759  .size_bytes = 256 * 1024,
1760  .nsectors = 16,
1761  .sector_size = 16384,
1762  .page_size = 256,
1763 
1764  },
1765  },
1766  },
1767  /*at91sam3x8h - ES2 and up uses the correct CIDR of 0x286E0A60*/
1768  {
1769  .chipid_cidr = 0x286E0A60,
1770  .name = "at91sam3x8h",
1771  .total_flash_size = 512 * 1024,
1772  .total_sram_size = 96 * 1024,
1773  .n_gpnvms = 3,
1774  .n_banks = 2,
1775  {
1776 /* .bank[0] = { */
1777  {
1778  .probed = false,
1779  .chip = NULL,
1780  .bank = NULL,
1781  .bank_number = 0,
1782  .base_address = FLASH_BANK0_BASE_AX,
1783  .controller_address = 0x400e0a00,
1784  .flash_wait_states = 6, /* workaround silicon bug */
1785  .present = 1,
1786  .size_bytes = 256 * 1024,
1787  .nsectors = 16,
1788  .sector_size = 16384,
1789  .page_size = 256,
1790  },
1791 /* .bank[1] = { */
1792  {
1793  .probed = false,
1794  .chip = NULL,
1795  .bank = NULL,
1796  .bank_number = 1,
1797  .base_address = FLASH_BANK1_BASE_512K_AX,
1798  .controller_address = 0x400e0c00,
1799  .flash_wait_states = 6, /* workaround silicon bug */
1800  .present = 1,
1801  .size_bytes = 256 * 1024,
1802  .nsectors = 16,
1803  .sector_size = 16384,
1804  .page_size = 256,
1805 
1806  },
1807  },
1808  },
1809  {
1810  .chipid_cidr = 0x285E0A60,
1811  .name = "at91sam3x8e",
1812  .total_flash_size = 512 * 1024,
1813  .total_sram_size = 96 * 1024,
1814  .n_gpnvms = 3,
1815  .n_banks = 2,
1816  {
1817 /* .bank[0] = { */
1818  {
1819  .probed = false,
1820  .chip = NULL,
1821  .bank = NULL,
1822  .bank_number = 0,
1823  .base_address = FLASH_BANK0_BASE_AX,
1824  .controller_address = 0x400e0a00,
1825  .flash_wait_states = 6, /* workaround silicon bug */
1826  .present = 1,
1827  .size_bytes = 256 * 1024,
1828  .nsectors = 16,
1829  .sector_size = 16384,
1830  .page_size = 256,
1831  },
1832 /* .bank[1] = { */
1833  {
1834  .probed = false,
1835  .chip = NULL,
1836  .bank = NULL,
1837  .bank_number = 1,
1838  .base_address = FLASH_BANK1_BASE_512K_AX,
1839  .controller_address = 0x400e0c00,
1840  .flash_wait_states = 6, /* workaround silicon bug */
1841  .present = 1,
1842  .size_bytes = 256 * 1024,
1843  .nsectors = 16,
1844  .sector_size = 16384,
1845  .page_size = 256,
1846 
1847  },
1848  },
1849  },
1850  {
1851  .chipid_cidr = 0x284E0A60,
1852  .name = "at91sam3x8c",
1853  .total_flash_size = 512 * 1024,
1854  .total_sram_size = 96 * 1024,
1855  .n_gpnvms = 3,
1856  .n_banks = 2,
1857  {
1858 /* .bank[0] = { */
1859  {
1860  .probed = false,
1861  .chip = NULL,
1862  .bank = NULL,
1863  .bank_number = 0,
1864  .base_address = FLASH_BANK0_BASE_AX,
1865  .controller_address = 0x400e0a00,
1866  .flash_wait_states = 6, /* workaround silicon bug */
1867  .present = 1,
1868  .size_bytes = 256 * 1024,
1869  .nsectors = 16,
1870  .sector_size = 16384,
1871  .page_size = 256,
1872  },
1873 /* .bank[1] = { */
1874  {
1875  .probed = false,
1876  .chip = NULL,
1877  .bank = NULL,
1878  .bank_number = 1,
1879  .base_address = FLASH_BANK1_BASE_512K_AX,
1880  .controller_address = 0x400e0c00,
1881  .flash_wait_states = 6, /* workaround silicon bug */
1882  .present = 1,
1883  .size_bytes = 256 * 1024,
1884  .nsectors = 16,
1885  .sector_size = 16384,
1886  .page_size = 256,
1887 
1888  },
1889  },
1890  },
1891  {
1892  .chipid_cidr = 0x285B0960,
1893  .name = "at91sam3x4e",
1894  .total_flash_size = 256 * 1024,
1895  .total_sram_size = 64 * 1024,
1896  .n_gpnvms = 3,
1897  .n_banks = 2,
1898  {
1899 /* .bank[0] = { */
1900  {
1901  .probed = false,
1902  .chip = NULL,
1903  .bank = NULL,
1904  .bank_number = 0,
1905  .base_address = FLASH_BANK0_BASE_AX,
1906  .controller_address = 0x400e0a00,
1907  .flash_wait_states = 6, /* workaround silicon bug */
1908  .present = 1,
1909  .size_bytes = 128 * 1024,
1910  .nsectors = 8,
1911  .sector_size = 16384,
1912  .page_size = 256,
1913  },
1914 /* .bank[1] = { */
1915  {
1916  .probed = false,
1917  .chip = NULL,
1918  .bank = NULL,
1919  .bank_number = 1,
1920  .base_address = FLASH_BANK1_BASE_256K_AX,
1921  .controller_address = 0x400e0c00,
1922  .flash_wait_states = 6, /* workaround silicon bug */
1923  .present = 1,
1924  .size_bytes = 128 * 1024,
1925  .nsectors = 8,
1926  .sector_size = 16384,
1927  .page_size = 256,
1928 
1929  },
1930  },
1931  },
1932  {
1933  .chipid_cidr = 0x284B0960,
1934  .name = "at91sam3x4c",
1935  .total_flash_size = 256 * 1024,
1936  .total_sram_size = 64 * 1024,
1937  .n_gpnvms = 3,
1938  .n_banks = 2,
1939  {
1940 /* .bank[0] = { */
1941  {
1942  .probed = false,
1943  .chip = NULL,
1944  .bank = NULL,
1945  .bank_number = 0,
1946  .base_address = FLASH_BANK0_BASE_AX,
1947  .controller_address = 0x400e0a00,
1948  .flash_wait_states = 6, /* workaround silicon bug */
1949  .present = 1,
1950  .size_bytes = 128 * 1024,
1951  .nsectors = 8,
1952  .sector_size = 16384,
1953  .page_size = 256,
1954  },
1955 /* .bank[1] = { */
1956  {
1957  .probed = false,
1958  .chip = NULL,
1959  .bank = NULL,
1960  .bank_number = 1,
1961  .base_address = FLASH_BANK1_BASE_256K_AX,
1962  .controller_address = 0x400e0c00,
1963  .flash_wait_states = 6, /* workaround silicon bug */
1964  .present = 1,
1965  .size_bytes = 128 * 1024,
1966  .nsectors = 8,
1967  .sector_size = 16384,
1968  .page_size = 256,
1969 
1970  },
1971  },
1972  },
1973  /* terminate */
1974  {
1975  .chipid_cidr = 0,
1976  .name = NULL,
1977  }
1978 };
1979 
1980 /* Globals above */
1981 /***********************************************************************
1982  **********************************************************************
1983  **********************************************************************
1984  **********************************************************************
1985  **********************************************************************
1986  **********************************************************************/
1987 /* *ATMEL* style code - from the SAM3 driver code */
1988 
1995 static int efc_get_status(struct sam3_bank_private *private, uint32_t *v)
1996 {
1997  int r;
1998  r = target_read_u32(private->chip->target,
1999  private->controller_address + OFFSET_EFC_FSR,
2000  v);
2001  LOG_DEBUG("Status: 0x%08x (lockerror: %d, cmderror: %d, ready: %d)",
2002  (unsigned int)(*v),
2003  ((unsigned int)((*v >> 2) & 1)),
2004  ((unsigned int)((*v >> 1) & 1)),
2005  ((unsigned int)((*v >> 0) & 1)));
2006 
2007  return r;
2008 }
2009 
2015 static int efc_get_result(struct sam3_bank_private *private, uint32_t *v)
2016 {
2017  int r;
2018  uint32_t rv;
2019  r = target_read_u32(private->chip->target,
2020  private->controller_address + OFFSET_EFC_FRR,
2021  &rv);
2022  if (v)
2023  *v = rv;
2024  LOG_DEBUG("Result: 0x%08x", ((unsigned int)(rv)));
2025  return r;
2026 }
2027 
2028 static int efc_start_command(struct sam3_bank_private *private,
2029  unsigned int command, unsigned int argument)
2030 {
2031  uint32_t n, v;
2032  int r;
2033  int retry;
2034 
2035  retry = 0;
2036 do_retry:
2037 
2038  /* Check command & argument */
2039  switch (command) {
2040  case AT91C_EFC_FCMD_WP:
2041  case AT91C_EFC_FCMD_WPL:
2042  case AT91C_EFC_FCMD_EWP:
2043  case AT91C_EFC_FCMD_EWPL:
2044  /* case AT91C_EFC_FCMD_EPL: */
2045  /* case AT91C_EFC_FCMD_EPA: */
2046  case AT91C_EFC_FCMD_SLB:
2047  case AT91C_EFC_FCMD_CLB:
2048  n = (private->size_bytes / private->page_size);
2049  if (argument >= n)
2050  LOG_ERROR("*BUG*: Embedded flash has only %" PRIu32 " pages", n);
2051  break;
2052 
2053  case AT91C_EFC_FCMD_SFB:
2054  case AT91C_EFC_FCMD_CFB:
2055  if (argument >= private->chip->details.n_gpnvms) {
2056  LOG_ERROR("*BUG*: Embedded flash has only %d GPNVMs",
2057  private->chip->details.n_gpnvms);
2058  }
2059  break;
2060 
2061  case AT91C_EFC_FCMD_GETD:
2062  case AT91C_EFC_FCMD_EA:
2063  case AT91C_EFC_FCMD_GLB:
2064  case AT91C_EFC_FCMD_GFB:
2065  case AT91C_EFC_FCMD_STUI:
2066  case AT91C_EFC_FCMD_SPUI:
2067  if (argument != 0)
2068  LOG_ERROR("Argument is meaningless for cmd: %d", command);
2069  break;
2070  default:
2071  LOG_ERROR("Unknown command %d", command);
2072  break;
2073  }
2074 
2075  if (command == AT91C_EFC_FCMD_SPUI) {
2076  /* this is a very special situation. */
2077  /* Situation (1) - error/retry - see below */
2078  /* And we are being called recursively */
2079  /* Situation (2) - normal, finished reading unique id */
2080  } else {
2081  /* it should be "ready" */
2082  efc_get_status(private, &v);
2083  if (v & 1) {
2084  /* then it is ready */
2085  /* we go on */
2086  } else {
2087  if (retry) {
2088  /* we have done this before */
2089  /* the controller is not responding. */
2090  LOG_ERROR("flash controller(%d) is not ready! Error",
2091  private->bank_number);
2092  return ERROR_FAIL;
2093  } else {
2094  retry++;
2095  LOG_ERROR("Flash controller(%d) is not ready, attempting reset",
2096  private->bank_number);
2097  /* we do that by issuing the *STOP* command */
2098  efc_start_command(private, AT91C_EFC_FCMD_SPUI, 0);
2099  /* above is recursive, and further recursion is blocked by */
2100  /* if (command == AT91C_EFC_FCMD_SPUI) above */
2101  goto do_retry;
2102  }
2103  }
2104  }
2105 
2106  v = (0x5A << 24) | (argument << 8) | command;
2107  LOG_DEBUG("Command: 0x%08x", ((unsigned int)(v)));
2108  r = target_write_u32(private->bank->target,
2109  private->controller_address + OFFSET_EFC_FCR, v);
2110  if (r != ERROR_OK)
2111  LOG_DEBUG("Error Write failed");
2112  return r;
2113 }
2114 
2122 static int efc_perform_command(struct sam3_bank_private *private,
2123  unsigned int command,
2124  unsigned int argument,
2125  uint32_t *status)
2126 {
2127 
2128  int r;
2129  uint32_t v;
2130  int64_t ms_now, ms_end;
2131 
2132  /* default */
2133  if (status)
2134  *status = 0;
2135 
2136  r = efc_start_command(private, command, argument);
2137  if (r != ERROR_OK)
2138  return r;
2139 
2140  ms_end = 500 + timeval_ms();
2141 
2142  do {
2143  r = efc_get_status(private, &v);
2144  if (r != ERROR_OK)
2145  return r;
2146  ms_now = timeval_ms();
2147  if (ms_now > ms_end) {
2148  /* error */
2149  LOG_ERROR("Command timeout");
2150  return ERROR_FAIL;
2151  }
2152  } while ((v & 1) == 0);
2153 
2154  /* error bits.. */
2155  if (status)
2156  *status = (v & 0x6);
2157  return ERROR_OK;
2158 
2159 }
2160 
2166 static int flashd_read_uid(struct sam3_bank_private *private)
2167 {
2168  int r;
2169  uint32_t v;
2170  int x;
2171  /* assume 0 */
2172  private->chip->cfg.unique_id[0] = 0;
2173  private->chip->cfg.unique_id[1] = 0;
2174  private->chip->cfg.unique_id[2] = 0;
2175  private->chip->cfg.unique_id[3] = 0;
2176 
2177  LOG_DEBUG("Begin");
2178  r = efc_start_command(private, AT91C_EFC_FCMD_STUI, 0);
2179  if (r < 0)
2180  return r;
2181 
2182  for (x = 0; x < 4; x++) {
2183  r = target_read_u32(private->chip->target,
2184  private->bank->base + (x * 4),
2185  &v);
2186  if (r < 0)
2187  return r;
2188  private->chip->cfg.unique_id[x] = v;
2189  }
2190 
2191  r = efc_perform_command(private, AT91C_EFC_FCMD_SPUI, 0, NULL);
2192  LOG_DEBUG("End: R=%d, id = 0x%08x, 0x%08x, 0x%08x, 0x%08x",
2193  r,
2194  (unsigned int)(private->chip->cfg.unique_id[0]),
2195  (unsigned int)(private->chip->cfg.unique_id[1]),
2196  (unsigned int)(private->chip->cfg.unique_id[2]),
2197  (unsigned int)(private->chip->cfg.unique_id[3]));
2198  return r;
2199 
2200 }
2201 
2206 static int flashd_erase_entire_bank(struct sam3_bank_private *private)
2207 {
2208  LOG_DEBUG("Here");
2209  return efc_perform_command(private, AT91C_EFC_FCMD_EA, 0, NULL);
2210 }
2211 
2218 /* ------------------------------------------------------------------------------ */
2219 static int flashd_get_gpnvm(struct sam3_bank_private *private, unsigned int gpnvm, unsigned int *puthere)
2220 {
2221  uint32_t v;
2222  int r;
2223 
2224  LOG_DEBUG("Here");
2225  if (private->bank_number != 0) {
2226  LOG_ERROR("GPNVM only works with Bank0");
2227  return ERROR_FAIL;
2228  }
2229 
2230  if (gpnvm >= private->chip->details.n_gpnvms) {
2231  LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
2232  gpnvm, private->chip->details.n_gpnvms);
2233  return ERROR_FAIL;
2234  }
2235 
2236  /* Get GPNVMs status */
2237  r = efc_perform_command(private, AT91C_EFC_FCMD_GFB, 0, NULL);
2238  if (r != ERROR_OK) {
2239  LOG_ERROR("Failed");
2240  return r;
2241  }
2242 
2243  r = efc_get_result(private, &v);
2244 
2245  if (puthere) {
2246  /* Check if GPNVM is set */
2247  /* get the bit and make it a 0/1 */
2248  *puthere = (v >> gpnvm) & 1;
2249  }
2250 
2251  return r;
2252 }
2253 
2260 static int flashd_clr_gpnvm(struct sam3_bank_private *private, unsigned int gpnvm)
2261 {
2262  int r;
2263  unsigned int v;
2264 
2265  LOG_DEBUG("Here");
2266  if (private->bank_number != 0) {
2267  LOG_ERROR("GPNVM only works with Bank0");
2268  return ERROR_FAIL;
2269  }
2270 
2271  if (gpnvm >= private->chip->details.n_gpnvms) {
2272  LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
2273  gpnvm, private->chip->details.n_gpnvms);
2274  return ERROR_FAIL;
2275  }
2276 
2277  r = flashd_get_gpnvm(private, gpnvm, &v);
2278  if (r != ERROR_OK) {
2279  LOG_DEBUG("Failed: %d", r);
2280  return r;
2281  }
2282  r = efc_perform_command(private, AT91C_EFC_FCMD_CFB, gpnvm, NULL);
2283  LOG_DEBUG("End: %d", r);
2284  return r;
2285 }
2286 
2292 static int flashd_set_gpnvm(struct sam3_bank_private *private, unsigned int gpnvm)
2293 {
2294  int r;
2295  unsigned int v;
2296 
2297  if (private->bank_number != 0) {
2298  LOG_ERROR("GPNVM only works with Bank0");
2299  return ERROR_FAIL;
2300  }
2301 
2302  if (gpnvm >= private->chip->details.n_gpnvms) {
2303  LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
2304  gpnvm, private->chip->details.n_gpnvms);
2305  return ERROR_FAIL;
2306  }
2307 
2308  r = flashd_get_gpnvm(private, gpnvm, &v);
2309  if (r != ERROR_OK)
2310  return r;
2311  if (v) {
2312  /* already set */
2313  r = ERROR_OK;
2314  } else {
2315  /* set it */
2316  r = efc_perform_command(private, AT91C_EFC_FCMD_SFB, gpnvm, NULL);
2317  }
2318  return r;
2319 }
2320 
2326 static int flashd_get_lock_bits(struct sam3_bank_private *private, uint32_t *v)
2327 {
2328  int r;
2329  LOG_DEBUG("Here");
2330  r = efc_perform_command(private, AT91C_EFC_FCMD_GLB, 0, NULL);
2331  if (r == ERROR_OK)
2332  r = efc_get_result(private, v);
2333  LOG_DEBUG("End: %d", r);
2334  return r;
2335 }
2336 
2344 static int flashd_unlock(struct sam3_bank_private *private,
2345  unsigned int start_sector,
2346  unsigned int end_sector)
2347 {
2348  int r;
2349  uint32_t status;
2350  uint32_t pg;
2351  uint32_t pages_per_sector;
2352 
2353  pages_per_sector = private->sector_size / private->page_size;
2354 
2355  /* Unlock all pages */
2356  while (start_sector <= end_sector) {
2357  pg = start_sector * pages_per_sector;
2358 
2359  r = efc_perform_command(private, AT91C_EFC_FCMD_CLB, pg, &status);
2360  if (r != ERROR_OK)
2361  return r;
2362  start_sector++;
2363  }
2364 
2365  return ERROR_OK;
2366 }
2367 
2374 static int flashd_lock(struct sam3_bank_private *private,
2375  unsigned int start_sector,
2376  unsigned int end_sector)
2377 {
2378  uint32_t status;
2379  uint32_t pg;
2380  uint32_t pages_per_sector;
2381  int r;
2382 
2383  pages_per_sector = private->sector_size / private->page_size;
2384 
2385  /* Lock all pages */
2386  while (start_sector <= end_sector) {
2387  pg = start_sector * pages_per_sector;
2388 
2389  r = efc_perform_command(private, AT91C_EFC_FCMD_SLB, pg, &status);
2390  if (r != ERROR_OK)
2391  return r;
2392  start_sector++;
2393  }
2394  return ERROR_OK;
2395 }
2396 
2397 /****** END SAM3 CODE ********/
2398 
2399 /* begin helpful debug code */
2400 /* print the fieldname, the field value, in dec & hex, and return field value */
2401 static uint32_t sam3_reg_fieldname(struct sam3_chip *chip,
2402  const char *regname,
2403  uint32_t value,
2404  unsigned int shift,
2405  unsigned int width)
2406 {
2407  uint32_t v;
2408  int hwidth, dwidth;
2409 
2410 
2411  /* extract the field */
2412  v = value >> shift;
2413  v = v & ((1 << width)-1);
2414  if (width <= 16) {
2415  hwidth = 4;
2416  dwidth = 5;
2417  } else {
2418  hwidth = 8;
2419  dwidth = 12;
2420  }
2421 
2422  /* show the basics */
2423  LOG_USER_N("\t%*s: %*" PRIu32 " [0x%0*" PRIx32 "] ",
2424  REG_NAME_WIDTH, regname,
2425  dwidth, v,
2426  hwidth, v);
2427  return v;
2428 }
2429 
2430 static const char _unknown[] = "unknown";
2431 static const char *const eproc_names[] = {
2432  _unknown, /* 0 */
2433  "arm946es", /* 1 */
2434  "arm7tdmi", /* 2 */
2435  "Cortex-M3", /* 3 */
2436  "arm920t", /* 4 */
2437  "arm926ejs", /* 5 */
2438  _unknown, /* 6 */
2439  _unknown, /* 7 */
2440  _unknown, /* 8 */
2441  _unknown, /* 9 */
2442  _unknown, /* 10 */
2443  _unknown, /* 11 */
2444  _unknown, /* 12 */
2445  _unknown, /* 13 */
2446  _unknown, /* 14 */
2447  _unknown, /* 15 */
2448 };
2449 
2450 #define nvpsize2 nvpsize /* these two tables are identical */
2451 static const char *const nvpsize[] = {
2452  "none", /* 0 */
2453  "8K bytes", /* 1 */
2454  "16K bytes", /* 2 */
2455  "32K bytes", /* 3 */
2456  _unknown, /* 4 */
2457  "64K bytes", /* 5 */
2458  _unknown, /* 6 */
2459  "128K bytes", /* 7 */
2460  _unknown, /* 8 */
2461  "256K bytes", /* 9 */
2462  "512K bytes", /* 10 */
2463  _unknown, /* 11 */
2464  "1024K bytes", /* 12 */
2465  _unknown, /* 13 */
2466  "2048K bytes", /* 14 */
2467  _unknown, /* 15 */
2468 };
2469 
2470 static const char *const sramsize[] = {
2471  "48K Bytes", /* 0 */
2472  "1K Bytes", /* 1 */
2473  "2K Bytes", /* 2 */
2474  "6K Bytes", /* 3 */
2475  "112K Bytes", /* 4 */
2476  "4K Bytes", /* 5 */
2477  "80K Bytes", /* 6 */
2478  "160K Bytes", /* 7 */
2479  "8K Bytes", /* 8 */
2480  "16K Bytes", /* 9 */
2481  "32K Bytes", /* 10 */
2482  "64K Bytes", /* 11 */
2483  "128K Bytes", /* 12 */
2484  "256K Bytes", /* 13 */
2485  "96K Bytes", /* 14 */
2486  "512K Bytes", /* 15 */
2487 
2488 };
2489 
2490 static const struct archnames { unsigned int value; const char *name; } archnames[] = {
2491  { 0x19, "AT91SAM9xx Series" },
2492  { 0x29, "AT91SAM9XExx Series" },
2493  { 0x34, "AT91x34 Series" },
2494  { 0x37, "CAP7 Series" },
2495  { 0x39, "CAP9 Series" },
2496  { 0x3B, "CAP11 Series" },
2497  { 0x40, "AT91x40 Series" },
2498  { 0x42, "AT91x42 Series" },
2499  { 0x55, "AT91x55 Series" },
2500  { 0x60, "AT91SAM7Axx Series" },
2501  { 0x61, "AT91SAM7AQxx Series" },
2502  { 0x63, "AT91x63 Series" },
2503  { 0x70, "AT91SAM7Sxx Series" },
2504  { 0x71, "AT91SAM7XCxx Series" },
2505  { 0x72, "AT91SAM7SExx Series" },
2506  { 0x73, "AT91SAM7Lxx Series" },
2507  { 0x75, "AT91SAM7Xxx Series" },
2508  { 0x76, "AT91SAM7SLxx Series" },
2509  { 0x80, "ATSAM3UxC Series (100-pin version)" },
2510  { 0x81, "ATSAM3UxE Series (144-pin version)" },
2511  { 0x83, "ATSAM3AxC Series (100-pin version)" },
2512  { 0x84, "ATSAM3XxC Series (100-pin version)" },
2513  { 0x85, "ATSAM3XxE Series (144-pin version)" },
2514  { 0x86, "ATSAM3XxG Series (208/217-pin version)" },
2515  { 0x88, "ATSAM3SxA Series (48-pin version)" },
2516  { 0x89, "ATSAM3SxB Series (64-pin version)" },
2517  { 0x8A, "ATSAM3SxC Series (100-pin version)" },
2518  { 0x92, "AT91x92 Series" },
2519  { 0x93, "ATSAM3NxA Series (48-pin version)" },
2520  { 0x94, "ATSAM3NxB Series (64-pin version)" },
2521  { 0x95, "ATSAM3NxC Series (100-pin version)" },
2522  { 0x98, "ATSAM3SDxA Series (48-pin version)" },
2523  { 0x99, "ATSAM3SDxB Series (64-pin version)" },
2524  { 0x9A, "ATSAM3SDxC Series (100-pin version)" },
2525  { 0xA5, "ATSAM5A" },
2526  { 0xF0, "AT75Cxx Series" },
2527  { -1, NULL },
2528 };
2529 
2530 static const char *const nvptype[] = {
2531  "rom", /* 0 */
2532  "romless or onchip flash", /* 1 */
2533  "embedded flash memory",/* 2 */
2534  "rom(nvpsiz) + embedded flash (nvpsiz2)", /* 3 */
2535  "sram emulating flash", /* 4 */
2536  _unknown, /* 5 */
2537  _unknown, /* 6 */
2538  _unknown, /* 7 */
2539 };
2540 
2541 static const char *_yes_or_no(uint32_t v)
2542 {
2543  if (v)
2544  return "YES";
2545  else
2546  return "NO";
2547 }
2548 
2549 static const char *const _rc_freq[] = {
2550  "4 MHz", "8 MHz", "12 MHz", "reserved"
2551 };
2552 
2553 static void sam3_explain_ckgr_mor(struct sam3_chip *chip)
2554 {
2555  uint32_t v;
2556  uint32_t rcen;
2557 
2558  v = sam3_reg_fieldname(chip, "MOSCXTEN", chip->cfg.CKGR_MOR, 0, 1);
2559  LOG_USER("(main xtal enabled: %s)", _yes_or_no(v));
2560  v = sam3_reg_fieldname(chip, "MOSCXTBY", chip->cfg.CKGR_MOR, 1, 1);
2561  LOG_USER("(main osc bypass: %s)", _yes_or_no(v));
2562  rcen = sam3_reg_fieldname(chip, "MOSCRCEN", chip->cfg.CKGR_MOR, 3, 1);
2563  LOG_USER("(onchip RC-OSC enabled: %s)", _yes_or_no(rcen));
2564  v = sam3_reg_fieldname(chip, "MOSCRCF", chip->cfg.CKGR_MOR, 4, 3);
2565  LOG_USER("(onchip RC-OSC freq: %s)", _rc_freq[v]);
2566 
2567  chip->cfg.rc_freq = 0;
2568  if (rcen) {
2569  switch (v) {
2570  case 0:
2571  chip->cfg.rc_freq = 4 * 1000 * 1000;
2572  break;
2573  case 1:
2574  chip->cfg.rc_freq = 8 * 1000 * 1000;
2575  break;
2576  case 2:
2577  chip->cfg.rc_freq = 12 * 1000 * 1000;
2578  break;
2579  default:
2580  chip->cfg.rc_freq = 0;
2581  break;
2582  }
2583  }
2584 
2585  v = sam3_reg_fieldname(chip, "MOSCXTST", chip->cfg.CKGR_MOR, 8, 8);
2586  LOG_USER("(startup clks, time= %f uSecs)",
2587  ((float)(v * 1000000)) / ((float)(chip->cfg.slow_freq)));
2588  v = sam3_reg_fieldname(chip, "MOSCSEL", chip->cfg.CKGR_MOR, 24, 1);
2589  LOG_USER("(mainosc source: %s)",
2590  v ? "external xtal" : "internal RC");
2591 
2592  v = sam3_reg_fieldname(chip, "CFDEN", chip->cfg.CKGR_MOR, 25, 1);
2593  LOG_USER("(clock failure enabled: %s)",
2594  _yes_or_no(v));
2595 }
2596 
2597 static void sam3_explain_chipid_cidr(struct sam3_chip *chip)
2598 {
2599  int x;
2600  uint32_t v;
2601  const char *cp;
2602 
2603  sam3_reg_fieldname(chip, "Version", chip->cfg.CHIPID_CIDR, 0, 5);
2604  LOG_USER_N("\n");
2605 
2606  v = sam3_reg_fieldname(chip, "EPROC", chip->cfg.CHIPID_CIDR, 5, 3);
2607  LOG_USER("%s", eproc_names[v]);
2608 
2609  v = sam3_reg_fieldname(chip, "NVPSIZE", chip->cfg.CHIPID_CIDR, 8, 4);
2610  LOG_USER("%s", nvpsize[v]);
2611 
2612  v = sam3_reg_fieldname(chip, "NVPSIZE2", chip->cfg.CHIPID_CIDR, 12, 4);
2613  LOG_USER("%s", nvpsize2[v]);
2614 
2615  v = sam3_reg_fieldname(chip, "SRAMSIZE", chip->cfg.CHIPID_CIDR, 16, 4);
2616  LOG_USER("%s", sramsize[v]);
2617 
2618  v = sam3_reg_fieldname(chip, "ARCH", chip->cfg.CHIPID_CIDR, 20, 8);
2619  cp = _unknown;
2620  for (x = 0; archnames[x].name; x++) {
2621  if (v == archnames[x].value) {
2622  cp = archnames[x].name;
2623  break;
2624  }
2625  }
2626 
2627  LOG_USER("%s", cp);
2628 
2629  v = sam3_reg_fieldname(chip, "NVPTYP", chip->cfg.CHIPID_CIDR, 28, 3);
2630  LOG_USER("%s", nvptype[v]);
2631 
2632  v = sam3_reg_fieldname(chip, "EXTID", chip->cfg.CHIPID_CIDR, 31, 1);
2633  LOG_USER("(exists: %s)", _yes_or_no(v));
2634 }
2635 
2636 static void sam3_explain_ckgr_mcfr(struct sam3_chip *chip)
2637 {
2638  uint32_t v;
2639 
2640  v = sam3_reg_fieldname(chip, "MAINFRDY", chip->cfg.CKGR_MCFR, 16, 1);
2641  LOG_USER("(main ready: %s)", _yes_or_no(v));
2642 
2643  v = sam3_reg_fieldname(chip, "MAINF", chip->cfg.CKGR_MCFR, 0, 16);
2644 
2645  v = (v * chip->cfg.slow_freq) / 16;
2646  chip->cfg.mainosc_freq = v;
2647 
2648  LOG_USER("(%3.03f Mhz (%" PRIu32 ".%03" PRIu32 "khz slowclk)",
2649  _tomhz(v),
2650  (uint32_t)(chip->cfg.slow_freq / 1000),
2651  (uint32_t)(chip->cfg.slow_freq % 1000));
2652 }
2653 
2654 static void sam3_explain_ckgr_plla(struct sam3_chip *chip)
2655 {
2656  uint32_t mula, diva;
2657 
2658  diva = sam3_reg_fieldname(chip, "DIVA", chip->cfg.CKGR_PLLAR, 0, 8);
2659  LOG_USER_N("\n");
2660  mula = sam3_reg_fieldname(chip, "MULA", chip->cfg.CKGR_PLLAR, 16, 11);
2661  LOG_USER_N("\n");
2662  chip->cfg.plla_freq = 0;
2663  if (mula == 0)
2664  LOG_USER("\tPLLA Freq: (Disabled,mula = 0)");
2665  else if (diva == 0)
2666  LOG_USER("\tPLLA Freq: (Disabled,diva = 0)");
2667  else if (diva >= 1) {
2668  chip->cfg.plla_freq = (chip->cfg.mainosc_freq * (mula + 1) / diva);
2669  LOG_USER("\tPLLA Freq: %3.03f MHz",
2670  _tomhz(chip->cfg.plla_freq));
2671  }
2672 }
2673 
2674 static void sam3_explain_mckr(struct sam3_chip *chip)
2675 {
2676  uint32_t css, pres, fin = 0;
2677  int pdiv = 0;
2678  const char *cp = NULL;
2679 
2680  css = sam3_reg_fieldname(chip, "CSS", chip->cfg.PMC_MCKR, 0, 2);
2681  switch (css & 3) {
2682  case 0:
2683  fin = chip->cfg.slow_freq;
2684  cp = "slowclk";
2685  break;
2686  case 1:
2687  fin = chip->cfg.mainosc_freq;
2688  cp = "mainosc";
2689  break;
2690  case 2:
2691  fin = chip->cfg.plla_freq;
2692  cp = "plla";
2693  break;
2694  case 3:
2695  if (chip->cfg.CKGR_UCKR & (1 << 16)) {
2696  fin = 480 * 1000 * 1000;
2697  cp = "upll";
2698  } else {
2699  fin = 0;
2700  cp = "upll (*ERROR* UPLL is disabled)";
2701  }
2702  break;
2703  default:
2704  assert(0);
2705  break;
2706  }
2707 
2708  LOG_USER("%s (%3.03f Mhz)",
2709  cp,
2710  _tomhz(fin));
2711  pres = sam3_reg_fieldname(chip, "PRES", chip->cfg.PMC_MCKR, 4, 3);
2712  switch (pres & 0x07) {
2713  case 0:
2714  pdiv = 1;
2715  cp = "selected clock";
2716  break;
2717  case 1:
2718  pdiv = 2;
2719  cp = "clock/2";
2720  break;
2721  case 2:
2722  pdiv = 4;
2723  cp = "clock/4";
2724  break;
2725  case 3:
2726  pdiv = 8;
2727  cp = "clock/8";
2728  break;
2729  case 4:
2730  pdiv = 16;
2731  cp = "clock/16";
2732  break;
2733  case 5:
2734  pdiv = 32;
2735  cp = "clock/32";
2736  break;
2737  case 6:
2738  pdiv = 64;
2739  cp = "clock/64";
2740  break;
2741  case 7:
2742  pdiv = 6;
2743  cp = "clock/6";
2744  break;
2745  default:
2746  assert(0);
2747  break;
2748  }
2749  LOG_USER("(%s)", cp);
2750  fin = fin / pdiv;
2751  /* sam3 has a *SINGLE* clock - */
2752  /* other at91 series parts have divisors for these. */
2753  chip->cfg.cpu_freq = fin;
2754  chip->cfg.mclk_freq = fin;
2755  chip->cfg.fclk_freq = fin;
2756  LOG_USER("\t\tResult CPU Freq: %3.03f",
2757  _tomhz(fin));
2758 }
2759 
2760 #if 0
2761 static struct sam3_chip *target2sam3(struct target *target)
2762 {
2763  struct sam3_chip *chip;
2764 
2765  if (!target)
2766  return NULL;
2767 
2768  chip = all_sam3_chips;
2769  while (chip) {
2770  if (chip->target == target)
2771  break; /* return below */
2772  else
2773  chip = chip->next;
2774  }
2775  return chip;
2776 }
2777 #endif
2778 
2779 static uint32_t *sam3_get_reg_ptr(struct sam3_cfg *cfg, const struct sam3_reg_list *list)
2780 {
2781  /* this function exists to help */
2782  /* keep funky offsetof() errors */
2783  /* and casting from causing bugs */
2784 
2785  /* By using prototypes - we can detect what would */
2786  /* be casting errors. */
2787 
2788  return (uint32_t *)(void *)(((char *)(cfg)) + list->struct_offset);
2789 }
2790 
2791 
2792 #define SAM3_ENTRY(NAME, FUNC) { .address = SAM3_ ## NAME, .struct_offset = offsetof( \
2793  struct sam3_cfg, \
2794  NAME), # NAME, FUNC }
2795 static const struct sam3_reg_list sam3_all_regs[] = {
2796  SAM3_ENTRY(CKGR_MOR, sam3_explain_ckgr_mor),
2797  SAM3_ENTRY(CKGR_MCFR, sam3_explain_ckgr_mcfr),
2798  SAM3_ENTRY(CKGR_PLLAR, sam3_explain_ckgr_plla),
2799  SAM3_ENTRY(CKGR_UCKR, NULL),
2800  SAM3_ENTRY(PMC_FSMR, NULL),
2801  SAM3_ENTRY(PMC_FSPR, NULL),
2802  SAM3_ENTRY(PMC_IMR, NULL),
2803  SAM3_ENTRY(PMC_MCKR, sam3_explain_mckr),
2804  SAM3_ENTRY(PMC_PCK0, NULL),
2805  SAM3_ENTRY(PMC_PCK1, NULL),
2806  SAM3_ENTRY(PMC_PCK2, NULL),
2807  SAM3_ENTRY(PMC_PCSR, NULL),
2808  SAM3_ENTRY(PMC_SCSR, NULL),
2809  SAM3_ENTRY(PMC_SR, NULL),
2810  SAM3_ENTRY(CHIPID_CIDR, sam3_explain_chipid_cidr),
2811  SAM3_ENTRY(CHIPID_CIDR2, sam3_explain_chipid_cidr),
2812  SAM3_ENTRY(CHIPID_EXID, NULL),
2813  SAM3_ENTRY(CHIPID_EXID2, NULL),
2814  /* TERMINATE THE LIST */
2815  { .name = NULL }
2816 };
2817 #undef SAM3_ENTRY
2818 
2819 static struct sam3_bank_private *get_sam3_bank_private(struct flash_bank *bank)
2820 {
2821  return bank->driver_priv;
2822 }
2823 
2828 static const struct sam3_reg_list *sam3_get_reg(struct sam3_chip *chip, uint32_t *goes_here)
2829 {
2830  const struct sam3_reg_list *reg;
2831 
2832  reg = &(sam3_all_regs[0]);
2833  while (reg->name) {
2834  uint32_t *possible;
2835 
2836  /* calculate where this one go.. */
2837  /* it is "possibly" this register. */
2838 
2839  possible = ((uint32_t *)(void *)(((char *)(&(chip->cfg))) + reg->struct_offset));
2840 
2841  /* well? Is it this register */
2842  if (possible == goes_here) {
2843  /* Jump for joy! */
2844  return reg;
2845  }
2846 
2847  /* next... */
2848  reg++;
2849  }
2850  /* This is *TOTAL*PANIC* - we are totally screwed. */
2851  LOG_ERROR("INVALID SAM3 REGISTER");
2852  return NULL;
2853 }
2854 
2855 static int sam3_read_this_reg(struct sam3_chip *chip, uint32_t *goes_here)
2856 {
2857  const struct sam3_reg_list *reg;
2858  int r;
2859 
2860  reg = sam3_get_reg(chip, goes_here);
2861  if (!reg)
2862  return ERROR_FAIL;
2863 
2864  r = target_read_u32(chip->target, reg->address, goes_here);
2865  if (r != ERROR_OK) {
2866  LOG_ERROR("Cannot read SAM3 register: %s @ 0x%08" PRIx32 ", Err: %d",
2867  reg->name, reg->address, r);
2868  }
2869  return r;
2870 }
2871 
2872 static int sam3_read_all_regs(struct sam3_chip *chip)
2873 {
2874  int r;
2875  const struct sam3_reg_list *reg;
2876 
2877  reg = &(sam3_all_regs[0]);
2878  while (reg->name) {
2879  r = sam3_read_this_reg(chip,
2880  sam3_get_reg_ptr(&(chip->cfg), reg));
2881  if (r != ERROR_OK) {
2882  LOG_ERROR("Cannot read SAM3 register: %s @ 0x%08" PRIx32 ", Error: %d",
2883  reg->name, reg->address, r);
2884  return r;
2885  }
2886  reg++;
2887  }
2888 
2889  /* Chip identification register
2890  *
2891  * Unfortunately, the chip identification register is not at
2892  * a constant address across all of the SAM3 series'. As a
2893  * consequence, a simple heuristic is used to find where it's
2894  * at...
2895  *
2896  * If the contents at the first address is zero, then we know
2897  * that the second address is where the chip id register is.
2898  * We can deduce this because for those SAM's that have the
2899  * chip id @ 0x400e0940, the first address, 0x400e0740, is
2900  * located in the memory map of the Power Management Controller
2901  * (PMC). Furthermore, the address is not used by the PMC.
2902  * So when read, the memory controller returns zero.*/
2903  if (chip->cfg.CHIPID_CIDR == 0) {
2904  /*Put the correct CIDR and EXID values in the chip structure */
2905  chip->cfg.CHIPID_CIDR = chip->cfg.CHIPID_CIDR2;
2906  chip->cfg.CHIPID_EXID = chip->cfg.CHIPID_EXID2;
2907  }
2908  return ERROR_OK;
2909 }
2910 
2911 static int sam3_get_info(struct sam3_chip *chip)
2912 {
2913  const struct sam3_reg_list *reg;
2914  uint32_t regval;
2915 
2916  reg = &(sam3_all_regs[0]);
2917  while (reg->name) {
2918  /* display all regs */
2919  LOG_DEBUG("Start: %s", reg->name);
2920  regval = *sam3_get_reg_ptr(&(chip->cfg), reg);
2921  LOG_USER("%*s: [0x%08" PRIx32 "] -> 0x%08" PRIx32,
2922  REG_NAME_WIDTH,
2923  reg->name,
2924  reg->address,
2925  regval);
2926  if (reg->explain_func)
2927  (*(reg->explain_func))(chip);
2928  LOG_DEBUG("End: %s", reg->name);
2929  reg++;
2930  }
2931  LOG_USER(" rc-osc: %3.03f MHz", _tomhz(chip->cfg.rc_freq));
2932  LOG_USER(" mainosc: %3.03f MHz", _tomhz(chip->cfg.mainosc_freq));
2933  LOG_USER(" plla: %3.03f MHz", _tomhz(chip->cfg.plla_freq));
2934  LOG_USER(" cpu-freq: %3.03f MHz", _tomhz(chip->cfg.cpu_freq));
2935  LOG_USER("mclk-freq: %3.03f MHz", _tomhz(chip->cfg.mclk_freq));
2936 
2937  LOG_USER(" UniqueId: 0x%08" PRIx32 " 0x%08" PRIx32 " 0x%08" PRIx32 " 0x%08" PRIx32,
2938  chip->cfg.unique_id[0],
2939  chip->cfg.unique_id[1],
2940  chip->cfg.unique_id[2],
2941  chip->cfg.unique_id[3]);
2942 
2943  return ERROR_OK;
2944 }
2945 
2946 static int sam3_protect_check(struct flash_bank *bank)
2947 {
2948  int r;
2949  uint32_t v = 0;
2950  unsigned int x;
2951  struct sam3_bank_private *private;
2952 
2953  LOG_DEBUG("Begin");
2954  if (bank->target->state != TARGET_HALTED) {
2955  LOG_ERROR("Target not halted");
2956  return ERROR_TARGET_NOT_HALTED;
2957  }
2958 
2959  private = get_sam3_bank_private(bank);
2960  if (!private) {
2961  LOG_ERROR("no private for this bank?");
2962  return ERROR_FAIL;
2963  }
2964  if (!(private->probed))
2965  return ERROR_FLASH_BANK_NOT_PROBED;
2966 
2967  r = flashd_get_lock_bits(private, &v);
2968  if (r != ERROR_OK) {
2969  LOG_DEBUG("Failed: %d", r);
2970  return r;
2971  }
2972 
2973  for (x = 0; x < private->nsectors; x++)
2974  bank->sectors[x].is_protected = (!!(v & (1 << x)));
2975  LOG_DEBUG("Done");
2976  return ERROR_OK;
2977 }
2978 
2979 FLASH_BANK_COMMAND_HANDLER(sam3_flash_bank_command)
2980 {
2981  struct sam3_chip *chip;
2982 
2983  chip = all_sam3_chips;
2984 
2985  /* is this an existing chip? */
2986  while (chip) {
2987  if (chip->target == bank->target)
2988  break;
2989  chip = chip->next;
2990  }
2991 
2992  if (!chip) {
2993  /* this is a *NEW* chip */
2994  chip = calloc(1, sizeof(struct sam3_chip));
2995  if (!chip) {
2996  LOG_ERROR("NO RAM!");
2997  return ERROR_FAIL;
2998  }
2999  chip->target = bank->target;
3000  /* insert at head */
3001  chip->next = all_sam3_chips;
3002  all_sam3_chips = chip;
3003  chip->target = bank->target;
3004  /* assumption is this runs at 32khz */
3005  chip->cfg.slow_freq = 32768;
3006  chip->probed = false;
3007  }
3008 
3009  switch (bank->base) {
3010  /* at91sam3s and at91sam3n series only has bank 0*/
3011  /* at91sam3u and at91sam3ax series has the same address for bank 0*/
3012  case FLASH_BANK_BASE_S:
3013  case FLASH_BANK0_BASE_U:
3014  bank->driver_priv = &chip->details.bank[0];
3015  bank->bank_number = 0;
3016  chip->details.bank[0].chip = chip;
3017  chip->details.bank[0].bank = bank;
3018  break;
3019 
3020  /* Bank 1 of at91sam3u or at91sam3ax series */
3021  case FLASH_BANK1_BASE_U:
3022  case FLASH_BANK1_BASE_256K_AX:
3023  case FLASH_BANK1_BASE_512K_AX:
3024  bank->driver_priv = &chip->details.bank[1];
3025  bank->bank_number = 1;
3026  chip->details.bank[1].chip = chip;
3027  chip->details.bank[1].bank = bank;
3028  break;
3029 
3030  default:
3031  LOG_ERROR("Address " TARGET_ADDR_FMT " invalid bank address (try 0x%08x or 0x%08x "
3032  "[at91sam3u series] or 0x%08x [at91sam3s series] or "
3033  "0x%08x [at91sam3n series] or 0x%08x or 0x%08x or 0x%08x[at91sam3ax series] )",
3034  bank->base,
3035  FLASH_BANK0_BASE_U,
3036  FLASH_BANK1_BASE_U,
3037  FLASH_BANK_BASE_S,
3038  FLASH_BANK_BASE_N,
3039  FLASH_BANK0_BASE_AX,
3040  FLASH_BANK1_BASE_256K_AX,
3041  FLASH_BANK1_BASE_512K_AX);
3042  return ERROR_FAIL;
3043  }
3044 
3045  /* we initialize after probing. */
3046  return ERROR_OK;
3047 }
3048 
3054 static void sam3_free_driver_priv(struct flash_bank *bank)
3055 {
3056  struct sam3_chip *chip = all_sam3_chips;
3057  while (chip) {
3058  struct sam3_chip *next = chip->next;
3059  free(chip);
3060  chip = next;
3061  }
3062  all_sam3_chips = NULL;
3063 }
3064 
3065 static int sam3_get_details(struct sam3_bank_private *private)
3066 {
3067  const struct sam3_chip_details *details;
3068  struct sam3_chip *chip;
3069  struct flash_bank *saved_banks[SAM3_MAX_FLASH_BANKS];
3070  unsigned int x;
3071 
3072  LOG_DEBUG("Begin");
3073  details = all_sam3_details;
3074  while (details->name) {
3075  /* Compare cidr without version bits */
3076  if (((details->chipid_cidr ^ private->chip->cfg.CHIPID_CIDR) & 0xFFFFFFE0) == 0)
3077  break;
3078  else
3079  details++;
3080  }
3081  if (!details->name) {
3082  LOG_ERROR("SAM3 ChipID 0x%08x not found in table (perhaps you can ID this chip?)",
3083  (unsigned int)(private->chip->cfg.CHIPID_CIDR));
3084  /* Help the victim, print details about the chip */
3085  LOG_INFO("SAM3 CHIPID_CIDR: 0x%08" PRIx32 " decodes as follows",
3086  private->chip->cfg.CHIPID_CIDR);
3087  sam3_explain_chipid_cidr(private->chip);
3088  return ERROR_FAIL;
3089  }
3090 
3091  /* DANGER: THERE ARE DRAGONS HERE */
3092 
3093  /* get our chip - it is going */
3094  /* to be over-written shortly */
3095  chip = private->chip;
3096 
3097  /* Note that, in reality: */
3098  /* */
3099  /* private = &(chip->details.bank[0]) */
3100  /* or private = &(chip->details.bank[1]) */
3101  /* */
3102 
3103  /* save the "bank" pointers */
3104  for (x = 0; x < SAM3_MAX_FLASH_BANKS; x++)
3105  saved_banks[x] = chip->details.bank[x].bank;
3106 
3107  /* Overwrite the "details" structure. */
3108  memcpy(&(private->chip->details),
3109  details,
3110  sizeof(private->chip->details));
3111 
3112  /* now fix the ghosted pointers */
3113  for (x = 0; x < SAM3_MAX_FLASH_BANKS; x++) {
3114  chip->details.bank[x].chip = chip;
3115  chip->details.bank[x].bank = saved_banks[x];
3116  }
3117 
3118  /* update the *BANK*SIZE* */
3119 
3120  LOG_DEBUG("End");
3121  return ERROR_OK;
3122 }
3123 
3124 static int _sam3_probe(struct flash_bank *bank, int noise)
3125 {
3126  int r;
3127  struct sam3_bank_private *private;
3128 
3129 
3130  LOG_DEBUG("Begin: Bank: %u, Noise: %d", bank->bank_number, noise);
3131  if (bank->target->state != TARGET_HALTED) {
3132  LOG_ERROR("Target not halted");
3133  return ERROR_TARGET_NOT_HALTED;
3134  }
3135 
3136  private = get_sam3_bank_private(bank);
3137  if (!private) {
3138  LOG_ERROR("Invalid/unknown bank number");
3139  return ERROR_FAIL;
3140  }
3141 
3142  r = sam3_read_all_regs(private->chip);
3143  if (r != ERROR_OK)
3144  return r;
3145 
3146  LOG_DEBUG("Here");
3147  if (private->chip->probed)
3148  r = sam3_get_info(private->chip);
3149  else
3150  r = sam3_get_details(private);
3151  if (r != ERROR_OK)
3152  return r;
3153 
3154  /* update the flash bank size */
3155  for (unsigned int x = 0; x < SAM3_MAX_FLASH_BANKS; x++) {
3156  if (bank->base == private->chip->details.bank[x].base_address) {
3157  bank->size = private->chip->details.bank[x].size_bytes;
3158  break;
3159  }
3160  }
3161 
3162  if (!bank->sectors) {
3163  bank->sectors = calloc(private->nsectors, (sizeof((bank->sectors)[0])));
3164  if (!bank->sectors) {
3165  LOG_ERROR("No memory!");
3166  return ERROR_FAIL;
3167  }
3168  bank->num_sectors = private->nsectors;
3169 
3170  for (unsigned int x = 0; x < bank->num_sectors; x++) {
3171  bank->sectors[x].size = private->sector_size;
3172  bank->sectors[x].offset = x * (private->sector_size);
3173  /* mark as unknown */
3174  bank->sectors[x].is_erased = -1;
3175  bank->sectors[x].is_protected = -1;
3176  }
3177  }
3178 
3179  private->probed = true;
3180 
3181  r = sam3_protect_check(bank);
3182  if (r != ERROR_OK)
3183  return r;
3184 
3185  LOG_DEBUG("Bank = %d, nbanks = %d",
3186  private->bank_number, private->chip->details.n_banks);
3187  if ((private->bank_number + 1) == private->chip->details.n_banks) {
3188  /* read unique id, */
3189  /* it appears to be associated with the *last* flash bank. */
3190  flashd_read_uid(private);
3191  }
3192 
3193  return r;
3194 }
3195 
3196 static int sam3_probe(struct flash_bank *bank)
3197 {
3198  return _sam3_probe(bank, 1);
3199 }
3200 
3201 static int sam3_auto_probe(struct flash_bank *bank)
3202 {
3203  return _sam3_probe(bank, 0);
3204 }
3205 
3206 static int sam3_erase(struct flash_bank *bank, unsigned int first,
3207  unsigned int last)
3208 {
3209  struct sam3_bank_private *private;
3210  int r;
3211 
3212  LOG_DEBUG("Here");
3213  if (bank->target->state != TARGET_HALTED) {
3214  LOG_ERROR("Target not halted");
3215  return ERROR_TARGET_NOT_HALTED;
3216  }
3217 
3218  r = sam3_auto_probe(bank);
3219  if (r != ERROR_OK) {
3220  LOG_DEBUG("Here,r=%d", r);
3221  return r;
3222  }
3223 
3224  private = get_sam3_bank_private(bank);
3225  if (!(private->probed))
3226  return ERROR_FLASH_BANK_NOT_PROBED;
3227 
3228  if ((first == 0) && ((last + 1) == private->nsectors)) {
3229  /* whole chip */
3230  LOG_DEBUG("Here");
3231  return flashd_erase_entire_bank(private);
3232  }
3233  LOG_INFO("sam3 auto-erases while programming (request ignored)");
3234  return ERROR_OK;
3235 }
3236 
3237 static int sam3_protect(struct flash_bank *bank, int set, unsigned int first,
3238  unsigned int last)
3239 {
3240  struct sam3_bank_private *private;
3241  int r;
3242 
3243  LOG_DEBUG("Here");
3244  if (bank->target->state != TARGET_HALTED) {
3245  LOG_ERROR("Target not halted");
3246  return ERROR_TARGET_NOT_HALTED;
3247  }
3248 
3249  private = get_sam3_bank_private(bank);
3250  if (!(private->probed))
3251  return ERROR_FLASH_BANK_NOT_PROBED;
3252 
3253  if (set)
3254  r = flashd_lock(private, first, last);
3255  else
3256  r = flashd_unlock(private, first, last);
3257  LOG_DEBUG("End: r=%d", r);
3258 
3259  return r;
3260 
3261 }
3262 
3263 static int sam3_page_read(struct sam3_bank_private *private, unsigned int pagenum, uint8_t *buf)
3264 {
3265  uint32_t adr;
3266  int r;
3267 
3268  adr = pagenum * private->page_size;
3269  adr += private->base_address;
3270 
3271  r = target_read_memory(private->chip->target,
3272  adr,
3273  4, /* THIS*MUST*BE* in 32bit values */
3274  private->page_size / 4,
3275  buf);
3276  if (r != ERROR_OK)
3277  LOG_ERROR("SAM3: Flash program failed to read page phys address: 0x%08x",
3278  (unsigned int)(adr));
3279  return r;
3280 }
3281 
3282 static int sam3_page_write(struct sam3_bank_private *private, unsigned int pagenum, const uint8_t *buf)
3283 {
3284  uint32_t adr;
3285  uint32_t status;
3286  uint32_t fmr; /* EEFC Flash Mode Register */
3287  int r;
3288 
3289  adr = pagenum * private->page_size;
3290  adr += private->base_address;
3291 
3292  /* Get flash mode register value */
3293  r = target_read_u32(private->chip->target, private->controller_address, &fmr);
3294  if (r != ERROR_OK)
3295  LOG_DEBUG("Error Read failed: read flash mode register");
3296 
3297  /* Clear flash wait state field */
3298  fmr &= 0xfffff0ff;
3299 
3300  /* set FWS (flash wait states) field in the FMR (flash mode register) */
3301  fmr |= (private->flash_wait_states << 8);
3302 
3303  LOG_DEBUG("Flash Mode: 0x%08x", ((unsigned int)(fmr)));
3304  r = target_write_u32(private->bank->target, private->controller_address, fmr);
3305  if (r != ERROR_OK)
3306  LOG_DEBUG("Error Write failed: set flash mode register");
3307 
3308  LOG_DEBUG("Wr Page %u @ phys address: 0x%08x", pagenum, (unsigned int)(adr));
3309  r = target_write_memory(private->chip->target,
3310  adr,
3311  4, /* THIS*MUST*BE* in 32bit values */
3312  private->page_size / 4,
3313  buf);
3314  if (r != ERROR_OK) {
3315  LOG_ERROR("SAM3: Failed to write (buffer) page at phys address 0x%08x",
3316  (unsigned int)(adr));
3317  return r;
3318  }
3319 
3320  r = efc_perform_command(private,
3321  /* send Erase & Write Page */
3322  AT91C_EFC_FCMD_EWP,
3323  pagenum,
3324  &status);
3325 
3326  if (r != ERROR_OK)
3327  LOG_ERROR("SAM3: Error performing Erase & Write page @ phys address 0x%08x",
3328  (unsigned int)(adr));
3329  if (status & (1 << 2)) {
3330  LOG_ERROR("SAM3: Page @ Phys address 0x%08x is locked", (unsigned int)(adr));
3331  return ERROR_FAIL;
3332  }
3333  if (status & (1 << 1)) {
3334  LOG_ERROR("SAM3: Flash Command error @phys address 0x%08x", (unsigned int)(adr));
3335  return ERROR_FAIL;
3336  }
3337  return ERROR_OK;
3338 }
3339 
3340 static int sam3_write(struct flash_bank *bank,
3341  const uint8_t *buffer,
3342  uint32_t offset,
3343  uint32_t count)
3344 {
3345  int n;
3346  unsigned int page_cur;
3347  unsigned int page_end;
3348  int r;
3349  unsigned int page_offset;
3350  struct sam3_bank_private *private;
3351  uint8_t *pagebuffer;
3352 
3353  /* in case we bail further below, set this to null */
3354  pagebuffer = NULL;
3355 
3356  /* ignore dumb requests */
3357  if (count == 0) {
3358  r = ERROR_OK;
3359  goto done;
3360  }
3361 
3362  if (bank->target->state != TARGET_HALTED) {
3363  LOG_ERROR("Target not halted");
3364  r = ERROR_TARGET_NOT_HALTED;
3365  goto done;
3366  }
3367 
3368  private = get_sam3_bank_private(bank);
3369  if (!(private->probed)) {
3370  r = ERROR_FLASH_BANK_NOT_PROBED;
3371  goto done;
3372  }
3373 
3374  if ((offset + count) > private->size_bytes) {
3375  LOG_ERROR("Flash write error - past end of bank");
3376  LOG_ERROR(" offset: 0x%08x, count 0x%08x, BankEnd: 0x%08x",
3377  (unsigned int)(offset),
3378  (unsigned int)(count),
3379  (unsigned int)(private->size_bytes));
3380  r = ERROR_FAIL;
3381  goto done;
3382  }
3383 
3384  pagebuffer = malloc(private->page_size);
3385  if (!pagebuffer) {
3386  LOG_ERROR("No memory for %d Byte page buffer", (int)(private->page_size));
3387  r = ERROR_FAIL;
3388  goto done;
3389  }
3390 
3391  /* what page do we start & end in? */
3392  page_cur = offset / private->page_size;
3393  page_end = (offset + count - 1) / private->page_size;
3394 
3395  LOG_DEBUG("Offset: 0x%08x, Count: 0x%08x", (unsigned int)(offset), (unsigned int)(count));
3396  LOG_DEBUG("Page start: %d, Page End: %d", (int)(page_cur), (int)(page_end));
3397 
3398  /* Special case: all one page */
3399  /* */
3400  /* Otherwise: */
3401  /* (1) non-aligned start */
3402  /* (2) body pages */
3403  /* (3) non-aligned end. */
3404 
3405  /* Handle special case - all one page. */
3406  if (page_cur == page_end) {
3407  LOG_DEBUG("Special case, all in one page");
3408  r = sam3_page_read(private, page_cur, pagebuffer);
3409  if (r != ERROR_OK)
3410  goto done;
3411 
3412  page_offset = (offset & (private->page_size-1));
3413  memcpy(pagebuffer + page_offset,
3414  buffer,
3415  count);
3416 
3417  r = sam3_page_write(private, page_cur, pagebuffer);
3418  if (r != ERROR_OK)
3419  goto done;
3420  r = ERROR_OK;
3421  goto done;
3422  }
3423 
3424  /* non-aligned start */
3425  page_offset = offset & (private->page_size - 1);
3426  if (page_offset) {
3427  LOG_DEBUG("Not-Aligned start");
3428  /* read the partial */
3429  r = sam3_page_read(private, page_cur, pagebuffer);
3430  if (r != ERROR_OK)
3431  goto done;
3432 
3433  /* over-write with new data */
3434  n = (private->page_size - page_offset);
3435  memcpy(pagebuffer + page_offset,
3436  buffer,
3437  n);
3438 
3439  r = sam3_page_write(private, page_cur, pagebuffer);
3440  if (r != ERROR_OK)
3441  goto done;
3442 
3443  count -= n;
3444  offset += n;
3445  buffer += n;
3446  page_cur++;
3447  }
3448 
3449  /* By checking that offset is correct here, we also
3450  fix a clang warning */
3451  assert(offset % private->page_size == 0);
3452 
3453  /* intermediate large pages */
3454  /* also - the final *terminal* */
3455  /* if that terminal page is a full page */
3456  LOG_DEBUG("Full Page Loop: cur=%d, end=%d, count = 0x%08x",
3457  (int)page_cur, (int)page_end, (unsigned int)(count));
3458 
3459  while ((page_cur < page_end) &&
3460  (count >= private->page_size)) {
3461  r = sam3_page_write(private, page_cur, buffer);
3462  if (r != ERROR_OK)
3463  goto done;
3464  count -= private->page_size;
3465  buffer += private->page_size;
3466  page_cur += 1;
3467  }
3468 
3469  /* terminal partial page? */
3470  if (count) {
3471  LOG_DEBUG("Terminal partial page, count = 0x%08x", (unsigned int)(count));
3472  /* we have a partial page */
3473  r = sam3_page_read(private, page_cur, pagebuffer);
3474  if (r != ERROR_OK)
3475  goto done;
3476  /* data goes at start */
3477  memcpy(pagebuffer, buffer, count);
3478  r = sam3_page_write(private, page_cur, pagebuffer);
3479  if (r != ERROR_OK)
3480  goto done;
3481  }
3482  LOG_DEBUG("Done!");
3483  r = ERROR_OK;
3484 done:
3485  free(pagebuffer);
3486  return r;
3487 }
3488 
3489 COMMAND_HANDLER(sam3_handle_info_command)
3490 {
3491  struct sam3_chip *chip;
3492  chip = get_current_sam3(CMD);
3493  if (!chip)
3494  return ERROR_OK;
3495 
3496  unsigned int x;
3497  int r;
3498 
3499  /* bank0 must exist before we can do anything */
3500  if (!chip->details.bank[0].bank) {
3501  x = 0;
3502 need_define:
3503  command_print(CMD,
3504  "Please define bank %d via command: flash bank %s ... ",
3505  x,
3506  at91sam3_flash.name);
3507  return ERROR_FAIL;
3508  }
3509 
3510  /* if bank 0 is not probed, then probe it */
3511  if (!(chip->details.bank[0].probed)) {
3512  r = sam3_auto_probe(chip->details.bank[0].bank);
3513  if (r != ERROR_OK)
3514  return ERROR_FAIL;
3515  }
3516  /* above guarantees the "chip details" structure is valid */
3517  /* and thus, bank private areas are valid */
3518  /* and we have a SAM3 chip, what a concept! */
3519 
3520  /* auto-probe other banks, 0 done above */
3521  for (x = 1; x < SAM3_MAX_FLASH_BANKS; x++) {
3522  /* skip banks not present */
3523  if (!(chip->details.bank[x].present))
3524  continue;
3525 
3526  if (!chip->details.bank[x].bank)
3527  goto need_define;
3528 
3529  if (chip->details.bank[x].probed)
3530  continue;
3531 
3532  r = sam3_auto_probe(chip->details.bank[x].bank);
3533  if (r != ERROR_OK)
3534  return r;
3535  }
3536 
3537  r = sam3_get_info(chip);
3538  if (r != ERROR_OK) {
3539  LOG_DEBUG("Sam3Info, Failed %d", r);
3540  return r;
3541  }
3542 
3543  return ERROR_OK;
3544 }
3545 
3546 COMMAND_HANDLER(sam3_handle_gpnvm_command)
3547 {
3548  unsigned int x, v;
3549  int r, who;
3550  struct sam3_chip *chip;
3551 
3552  chip = get_current_sam3(CMD);
3553  if (!chip)
3554  return ERROR_OK;
3555 
3556  if (chip->target->state != TARGET_HALTED) {
3557  LOG_ERROR("sam3 - target not halted");
3558  return ERROR_TARGET_NOT_HALTED;
3559  }
3560 
3561  if (!chip->details.bank[0].bank) {
3562  command_print(CMD, "Bank0 must be defined first via: flash bank %s ...",
3563  at91sam3_flash.name);
3564  return ERROR_FAIL;
3565  }
3566  if (!chip->details.bank[0].probed) {
3567  r = sam3_auto_probe(chip->details.bank[0].bank);
3568  if (r != ERROR_OK)
3569  return r;
3570  }
3571 
3572  switch (CMD_ARGC) {
3573  case 0:
3574  goto showall;
3575  case 1:
3576  who = -1;
3577  break;
3578  case 2:
3579  if ((strcmp(CMD_ARGV[0], "show") == 0) && (strcmp(CMD_ARGV[1], "all") == 0)) {
3580  who = -1;
3581  } else {
3582  uint32_t v32;
3583  COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], v32);
3584  who = v32;
3585  }
3586  break;
3587  default:
3588  return ERROR_COMMAND_SYNTAX_ERROR;
3589  }
3590 
3591  if (strcmp("show", CMD_ARGV[0]) == 0) {
3592  if (who == -1) {
3593 showall:
3594  r = ERROR_OK;
3595  for (x = 0; x < chip->details.n_gpnvms; x++) {
3596  r = flashd_get_gpnvm(&(chip->details.bank[0]), x, &v);
3597  if (r != ERROR_OK)
3598  break;
3599  command_print(CMD, "sam3-gpnvm%u: %u", x, v);
3600  }
3601  return r;
3602  }
3603  if ((who >= 0) && (((unsigned)(who)) < chip->details.n_gpnvms)) {
3604  r = flashd_get_gpnvm(&(chip->details.bank[0]), who, &v);
3605  if (r == ERROR_OK)
3606  command_print(CMD, "sam3-gpnvm%u: %u", who, v);
3607  return r;
3608  } else {
3609  command_print(CMD, "sam3-gpnvm invalid GPNVM: %u", who);
3610  return ERROR_COMMAND_SYNTAX_ERROR;
3611  }
3612  }
3613 
3614  if (who == -1) {
3615  command_print(CMD, "Missing GPNVM number");
3616  return ERROR_COMMAND_SYNTAX_ERROR;
3617  }
3618 
3619  if (strcmp("set", CMD_ARGV[0]) == 0)
3620  r = flashd_set_gpnvm(&(chip->details.bank[0]), who);
3621  else if ((strcmp("clr", CMD_ARGV[0]) == 0) ||
3622  (strcmp("clear", CMD_ARGV[0]) == 0)) /* quietly accept both */
3623  r = flashd_clr_gpnvm(&(chip->details.bank[0]), who);
3624  else {
3625  command_print(CMD, "Unknown command: %s", CMD_ARGV[0]);
3626  r = ERROR_COMMAND_SYNTAX_ERROR;
3627  }
3628  return r;
3629 }
3630 
3631 COMMAND_HANDLER(sam3_handle_slowclk_command)
3632 {
3633  struct sam3_chip *chip;
3634 
3635  chip = get_current_sam3(CMD);
3636  if (!chip)
3637  return ERROR_OK;
3638 
3639  switch (CMD_ARGC) {
3640  case 0:
3641  /* show */
3642  break;
3643  case 1:
3644  {
3645  /* set */
3646  uint32_t v;
3647  COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], v);
3648  if (v > 200000) {
3649  /* absurd slow clock of 200Khz? */
3650  command_print(CMD, "Absurd/illegal slow clock freq: %d\n", (int)(v));
3651  return ERROR_COMMAND_SYNTAX_ERROR;
3652  }
3653  chip->cfg.slow_freq = v;
3654  break;
3655  }
3656  default:
3657  /* error */
3658  command_print(CMD, "Too many parameters");
3659  return ERROR_COMMAND_SYNTAX_ERROR;
3660  }
3661  command_print(CMD, "Slowclk freq: %d.%03dkhz",
3662  (int)(chip->cfg.slow_freq / 1000),
3663  (int)(chip->cfg.slow_freq % 1000));
3664  return ERROR_OK;
3665 }
3666 
3667 static const struct command_registration at91sam3_exec_command_handlers[] = {
3668  {
3669  .name = "gpnvm",
3670  .handler = sam3_handle_gpnvm_command,
3671  .mode = COMMAND_EXEC,
3672  .usage = "[('clr'|'set'|'show') bitnum]",
3673  .help = "Without arguments, shows all bits in the gpnvm "
3674  "register. Otherwise, clears, sets, or shows one "
3675  "General Purpose Non-Volatile Memory (gpnvm) bit.",
3676  },
3677  {
3678  .name = "info",
3679  .handler = sam3_handle_info_command,
3680  .mode = COMMAND_EXEC,
3681  .help = "Print information about the current at91sam3 chip "
3682  "and its flash configuration.",
3683  .usage = "",
3684  },
3685  {
3686  .name = "slowclk",
3687  .handler = sam3_handle_slowclk_command,
3688  .mode = COMMAND_EXEC,
3689  .usage = "[clock_hz]",
3690  .help = "Display or set the slowclock frequency "
3691  "(default 32768 Hz).",
3692  },
3693  COMMAND_REGISTRATION_DONE
3694 };
3695 static const struct command_registration at91sam3_command_handlers[] = {
3696  {
3697  .name = "at91sam3",
3698  .mode = COMMAND_ANY,
3699  .help = "at91sam3 flash command group",
3700  .usage = "",
3701  .chain = at91sam3_exec_command_handlers,
3702  },
3703  COMMAND_REGISTRATION_DONE
3704 };
3705 
3706 const struct flash_driver at91sam3_flash = {
3707  .name = "at91sam3",
3708  .commands = at91sam3_command_handlers,
3709  .flash_bank_command = sam3_flash_bank_command,
3710  .erase = sam3_erase,
3711  .protect = sam3_protect,
3712  .write = sam3_write,
3713  .read = default_flash_read,
3714  .probe = sam3_probe,
3715  .auto_probe = sam3_auto_probe,
3716  .erase_check = default_flash_blank_check,
3717  .protect_check = sam3_protect_check,
3718  .free_driver_priv = sam3_free_driver_priv,
3719 };
FLASH_BANK1_BASE_512K_AX
#define FLASH_BANK1_BASE_512K_AX
Definition: at91sam3.c:44
FLASH_BANK0_BASE_U
#define FLASH_BANK0_BASE_U
Definition: at91sam3.c:26
FLASH_BANK1_BASE_256K_AX
#define FLASH_BANK1_BASE_256K_AX
Definition: at91sam3.c:43
sam3_get_info
static int sam3_get_info(struct sam3_chip *chip)
Definition: at91sam3.c:2911
SAM3_N_NVM_BITS
#define SAM3_N_NVM_BITS
Definition: at91sam3.c:177
get_current_sam3
static struct sam3_chip * get_current_sam3(struct command_invocation *cmd)
Definition: at91sam3.c:205
sam3_explain_ckgr_mcfr
static void sam3_explain_ckgr_mcfr(struct sam3_chip *chip)
Definition: at91sam3.c:2636
sam3_explain_mckr
static void sam3_explain_mckr(struct sam3_chip *chip)
Definition: at91sam3.c:2674
AT91C_EFC_FCMD_WPL
#define AT91C_EFC_FCMD_WPL
Definition: at91sam3.c:48
AT91C_EFC_FCMD_GLB
#define AT91C_EFC_FCMD_GLB
Definition: at91sam3.c:58
FLASH_BANK_BASE_S
#define FLASH_BANK_BASE_S
Definition: at91sam3.c:30
sam3_read_this_reg
static int sam3_read_this_reg(struct sam3_chip *chip, uint32_t *goes_here)
Definition: at91sam3.c:2855
sam3_explain_ckgr_plla
static void sam3_explain_ckgr_plla(struct sam3_chip *chip)
Definition: at91sam3.c:2654
eproc_names
static const char *const eproc_names[]
Definition: at91sam3.c:2431
AT91C_EFC_FCMD_EWPL
#define AT91C_EFC_FCMD_EWPL
Definition: at91sam3.c:50
REG_NAME_WIDTH
#define REG_NAME_WIDTH
Definition: at91sam3.c:23
_unknown
static const char _unknown[]
Definition: at91sam3.c:2430
FLASH_BANK1_BASE_512K_SD
#define FLASH_BANK1_BASE_512K_SD
Definition: at91sam3.c:34
efc_perform_command
static int efc_perform_command(struct sam3_bank_private *private, unsigned int command, unsigned int argument, uint32_t *status)
Performs the given command and wait until its completion (or an error).
Definition: at91sam3.c:2122
OFFSET_EFC_FRR
#define OFFSET_EFC_FRR
Definition: at91sam3.c:68
_yes_or_no
static const char * _yes_or_no(uint32_t v)
Definition: at91sam3.c:2541
flashd_get_gpnvm
static int flashd_get_gpnvm(struct sam3_bank_private *private, unsigned int gpnvm, unsigned int *puthere)
Gets current GPNVM state.
Definition: at91sam3.c:2219
AT91C_EFC_FCMD_SFB
#define AT91C_EFC_FCMD_SFB
Definition: at91sam3.c:59
sam3_write
static int sam3_write(struct flash_bank *bank, const uint8_t *buffer, uint32_t offset, uint32_t count)
Definition: at91sam3.c:3340
sam3_probe
static int sam3_probe(struct flash_bank *bank)
Definition: at91sam3.c:3196
flashd_get_lock_bits
static int flashd_get_lock_bits(struct sam3_bank_private *private, uint32_t *v)
Returns a bit field (at most 64) of locked regions within a page.
Definition: at91sam3.c:2326
AT91C_EFC_FCMD_EA
#define AT91C_EFC_FCMD_EA
Definition: at91sam3.c:51
sam3_reg_fieldname
static uint32_t sam3_reg_fieldname(struct sam3_chip *chip, const char *regname, uint32_t value, unsigned int shift, unsigned int width)
Definition: at91sam3.c:2401
all_sam3_details
static const struct sam3_chip_details all_sam3_details[]
Definition: at91sam3.c:234
sam3_get_reg
static const struct sam3_reg_list * sam3_get_reg(struct sam3_chip *chip, uint32_t *goes_here)
Given a pointer to where it goes in the structure, determine the register name, address from the all ...
Definition: at91sam3.c:2828
flashd_read_uid
static int flashd_read_uid(struct sam3_bank_private *private)
Read the unique ID.
Definition: at91sam3.c:2166
get_sam3_bank_private
static struct sam3_bank_private * get_sam3_bank_private(struct flash_bank *bank)
Definition: at91sam3.c:2819
at91sam3_exec_command_handlers
static const struct command_registration at91sam3_exec_command_handlers[]
Definition: at91sam3.c:3667
flashd_unlock
static int flashd_unlock(struct sam3_bank_private *private, unsigned int start_sector, unsigned int end_sector)
Unlocks all the regions in the given address range.
Definition: at91sam3.c:2344
AT91C_EFC_FCMD_GFB
#define AT91C_EFC_FCMD_GFB
Definition: at91sam3.c:61
sam3_protect
static int sam3_protect(struct flash_bank *bank, int set, unsigned int first, unsigned int last)
Definition: at91sam3.c:3237
sam3_page_write
static int sam3_page_write(struct sam3_bank_private *private, unsigned int pagenum, const uint8_t *buf)
Definition: at91sam3.c:3282
flashd_clr_gpnvm
static int flashd_clr_gpnvm(struct sam3_bank_private *private, unsigned int gpnvm)
Clears the selected GPNVM bit.
Definition: at91sam3.c:2260
flashd_set_gpnvm
static int flashd_set_gpnvm(struct sam3_bank_private *private, unsigned int gpnvm)
Sets the selected GPNVM bit.
Definition: at91sam3.c:2292
efc_start_command
static int efc_start_command(struct sam3_bank_private *private, unsigned int command, unsigned int argument)
Definition: at91sam3.c:2028
nvpsize
static const char *const nvpsize[]
Definition: at91sam3.c:2451
AT91C_EFC_FCMD_EWP
#define AT91C_EFC_FCMD_EWP
Definition: at91sam3.c:49
at91sam3_flash
const struct flash_driver at91sam3_flash
Definition: at91sam3.c:3706
FLASH_BANK_BASE_N
#define FLASH_BANK_BASE_N
Definition: at91sam3.c:38
_tomhz
static float _tomhz(uint32_t freq_hz)
Definition: at91sam3.c:70
AT91C_EFC_FCMD_WP
#define AT91C_EFC_FCMD_WP
Definition: at91sam3.c:47
all_sam3_chips
static struct sam3_chip * all_sam3_chips
Definition: at91sam3.c:203
_sam3_probe
static int _sam3_probe(struct flash_bank *bank, int noise)
Definition: at91sam3.c:3124
at91sam3_command_handlers
static const struct command_registration at91sam3_command_handlers[]
Definition: at91sam3.c:3695
sam3_free_driver_priv
static void sam3_free_driver_priv(struct flash_bank *bank)
Remove all chips from the internal list without distinguishing which one is owned by this bank.
Definition: at91sam3.c:3054
sam3_get_details
static int sam3_get_details(struct sam3_bank_private *private)
Definition: at91sam3.c:3065
nvptype
static const char *const nvptype[]
Definition: at91sam3.c:2530
efc_get_result
static int efc_get_result(struct sam3_bank_private *private, uint32_t *v)
Get the result of the last executed command.
Definition: at91sam3.c:2015
sam3_explain_chipid_cidr
static void sam3_explain_chipid_cidr(struct sam3_chip *chip)
Definition: at91sam3.c:2597
sam3_page_read
static int sam3_page_read(struct sam3_bank_private *private, unsigned int pagenum, uint8_t *buf)
Definition: at91sam3.c:3263
OFFSET_EFC_FCR
#define OFFSET_EFC_FCR
Definition: at91sam3.c:66
FLASH_BANK0_BASE_SD
#define FLASH_BANK0_BASE_SD
Definition: at91sam3.c:33
nvpsize2
#define nvpsize2
Definition: at91sam3.c:2450
flashd_lock
static int flashd_lock(struct sam3_bank_private *private, unsigned int start_sector, unsigned int end_sector)
Locks regions.
Definition: at91sam3.c:2374
sam3_get_reg_ptr
static uint32_t * sam3_get_reg_ptr(struct sam3_cfg *cfg, const struct sam3_reg_list *list)
Definition: at91sam3.c:2779
sam3_all_regs
static const struct sam3_reg_list sam3_all_regs[]
Definition: at91sam3.c:2795
OFFSET_EFC_FSR
#define OFFSET_EFC_FSR
Definition: at91sam3.c:67
FLASH_BANK0_BASE_AX
#define FLASH_BANK0_BASE_AX
Definition: at91sam3.c:41
sam3_explain_ckgr_mor
static void sam3_explain_ckgr_mor(struct sam3_chip *chip)
Definition: at91sam3.c:2553
SAM3_ENTRY
#define SAM3_ENTRY(NAME, FUNC)
Definition: at91sam3.c:2792
AT91C_EFC_FCMD_STUI
#define AT91C_EFC_FCMD_STUI
Definition: at91sam3.c:62
AT91C_EFC_FCMD_GETD
#define AT91C_EFC_FCMD_GETD
Definition: at91sam3.c:46
sam3_auto_probe
static int sam3_auto_probe(struct flash_bank *bank)
Definition: at91sam3.c:3201
efc_get_status
static int efc_get_status(struct sam3_bank_private *private, uint32_t *v)
Get the current status of the EEFC and the value of some status bits (LOCKE, PROGE).
Definition: at91sam3.c:1995
sam3_erase
static int sam3_erase(struct flash_bank *bank, unsigned int first, unsigned int last)
Definition: at91sam3.c:3206
sam3_read_all_regs
static int sam3_read_all_regs(struct sam3_chip *chip)
Definition: at91sam3.c:2872
FLASH_BANK_COMMAND_HANDLER
FLASH_BANK_COMMAND_HANDLER(sam3_flash_bank_command)
Definition: at91sam3.c:2979
sramsize
static const char *const sramsize[]
Definition: at91sam3.c:2470
AT91C_EFC_FCMD_SPUI
#define AT91C_EFC_FCMD_SPUI
Definition: at91sam3.c:63
FLASH_BANK1_BASE_U
#define FLASH_BANK1_BASE_U
Definition: at91sam3.c:27
AT91C_EFC_FCMD_CLB
#define AT91C_EFC_FCMD_CLB
Definition: at91sam3.c:57
flashd_erase_entire_bank
static int flashd_erase_entire_bank(struct sam3_bank_private *private)
Erases the entire flash.
Definition: at91sam3.c:2206
sam3_protect_check
static int sam3_protect_check(struct flash_bank *bank)
Definition: at91sam3.c:2946
AT91C_EFC_FCMD_SLB
#define AT91C_EFC_FCMD_SLB
Definition: at91sam3.c:56
_rc_freq
static const char *const _rc_freq[]
Definition: at91sam3.c:2549
AT91C_EFC_FCMD_CFB
#define AT91C_EFC_FCMD_CFB
Definition: at91sam3.c:60
SAM3_MAX_FLASH_BANKS
#define SAM3_MAX_FLASH_BANKS
Definition: at91sam3.c:182
COMMAND_HANDLER
COMMAND_HANDLER(sam3_handle_info_command)
Definition: at91sam3.c:3489
CKGR_MOR
#define CKGR_MOR
Definition: at91sam7.c:45
PMC_MCKR
#define PMC_MCKR
Definition: at91sam7.c:50
CKGR_MCFR
#define CKGR_MCFR
Definition: at91sam7.c:44
command_print_sameline
void command_print_sameline(struct command_invocation *cmd, const char *format,...)
Definition: command.c:378
command_print
void command_print(struct command_invocation *cmd, const char *format,...)
Definition: command.c:389
CMD
#define CMD
Use this macro to access the command being handled, rather than accessing the variable directly.
Definition: command.h:146
CMD_ARGV
#define CMD_ARGV
Use this macro to access the arguments for the command being handled, rather than accessing the varia...
Definition: command.h:161
ERROR_COMMAND_SYNTAX_ERROR
#define ERROR_COMMAND_SYNTAX_ERROR
Definition: command.h:405
CMD_ARGC
#define CMD_ARGC
Use this macro to access the number of arguments for the command being handled, rather than accessing...
Definition: command.h:156
COMMAND_PARSE_NUMBER
#define COMMAND_PARSE_NUMBER(type, in, out)
parses the string in into out as a type, or prints a command error and passes the error code to the c...
Definition: command.h:445
COMMAND_REGISTRATION_DONE
#define COMMAND_REGISTRATION_DONE
Use this as the last entry in an array of command_registration records.
Definition: command.h:256
COMMAND_ANY
@ COMMAND_ANY
Definition: command.h:42
COMMAND_EXEC
@ COMMAND_EXEC
Definition: command.h:40
buffer
uint64_t buffer
Pointer to data buffer to send over SPI.
Definition: dw-spi-helper.h:0
width
unsigned short width
Definition: embeddedice.c:47
bank
uint8_t bank
Definition: esirisc.c:135
ERROR_FLASH_BANK_NOT_PROBED
#define ERROR_FLASH_BANK_NOT_PROBED
Definition: flash/common.h:35
default_flash_blank_check
int default_flash_blank_check(struct flash_bank *bank)
Provides default erased-bank check handling.
Definition: flash/nor/core.c:377
default_flash_read
int default_flash_read(struct flash_bank *bank, uint8_t *buffer, uint32_t offset, uint32_t count)
Provides default read implementation for flash memory.
Definition: flash/nor/core.c:121
LOG_USER
#define LOG_USER(expr ...)
Definition: log.h:150
ERROR_FAIL
#define ERROR_FAIL
Definition: log.h:188
LOG_USER_N
#define LOG_USER_N(expr ...)
Definition: log.h:153
LOG_ERROR
#define LOG_ERROR(expr ...)
Definition: log.h:147
LOG_INFO
#define LOG_INFO(expr ...)
Definition: log.h:141
LOG_DEBUG
#define LOG_DEBUG(expr ...)
Definition: log.h:124
ERROR_OK
#define ERROR_OK
Definition: log.h:182
archnames::name
const char * name
Definition: at91sam3.c:2490
archnames::value
unsigned int value
Definition: at91sam3.c:2490
command_invocation
When run_command is called, a new instance will be created on the stack, filled with the proper value...
Definition: command.h:76
command_registration
Definition: command.h:238
command_registration::name
const char * name
Definition: command.h:239
flash_bank
Provides details of a flash bank, available either on-chip or through a major interface.
Definition: nor/core.h:75
flash_driver
Provides the implementation-independent structure that defines all of the callbacks required by OpenO...
Definition: nor/driver.h:39
flash_driver::name
const char * name
Gives a human-readable name of this flash driver, This field is used to select and initialize the dri...
Definition: nor/driver.h:44
reg
Definition: register.h:111
reg::name
const char * name
Definition: register.h:113
sam3_bank_private
Definition: at91sam3.c:142
sam3_bank_private::controller_address
uint32_t controller_address
Definition: at91sam3.c:155
sam3_bank_private::probed
bool probed
Definition: at91sam3.c:143
sam3_bank_private::sector_size
unsigned int sector_size
Definition: at91sam3.c:161
sam3_bank_private::bank
struct flash_bank * bank
Definition: at91sam3.c:153
sam3_bank_private::present
bool present
Definition: at91sam3.c:158
sam3_bank_private::size_bytes
unsigned int size_bytes
Definition: at91sam3.c:159
sam3_bank_private::bank_number
unsigned int bank_number
Definition: at91sam3.c:154
sam3_bank_private::page_size
unsigned int page_size
Definition: at91sam3.c:162
sam3_bank_private::flash_wait_states
uint32_t flash_wait_states
Definition: at91sam3.c:157
sam3_bank_private::nsectors
unsigned int nsectors
Definition: at91sam3.c:160
sam3_bank_private::chip
struct sam3_chip * chip
Definition: at91sam3.c:151
sam3_bank_private::base_address
uint32_t base_address
Definition: at91sam3.c:156
sam3_cfg
Definition: at91sam3.c:76
sam3_cfg::PMC_IMR
uint32_t PMC_IMR
Definition: at91sam3.c:125
sam3_cfg::PMC_SCSR
uint32_t PMC_SCSR
Definition: at91sam3.c:103
sam3_cfg::CKGR_PLLAR
uint32_t CKGR_PLLAR
Definition: at91sam3.c:113
sam3_cfg::pclk0_freq
uint32_t pclk0_freq
Definition: at91sam3.c:86
sam3_cfg::PMC_MCKR
uint32_t PMC_MCKR
Definition: at91sam3.c:115
sam3_cfg::CHIPID_CIDR2
uint32_t CHIPID_CIDR2
Definition: at91sam3.c:94
sam3_cfg::PMC_SR
uint32_t PMC_SR
Definition: at91sam3.c:123
sam3_cfg::unique_id
uint32_t unique_id[4]
Definition: at91sam3.c:77
sam3_cfg::pclk1_freq
uint32_t pclk1_freq
Definition: at91sam3.c:87
sam3_cfg::PMC_FSPR
uint32_t PMC_FSPR
Definition: at91sam3.c:129
sam3_cfg::slow_freq
uint32_t slow_freq
Definition: at91sam3.c:79
sam3_cfg::PMC_PCSR
uint32_t PMC_PCSR
Definition: at91sam3.c:105
sam3_cfg::mclk_freq
uint32_t mclk_freq
Definition: at91sam3.c:83
sam3_cfg::mainosc_freq
uint32_t mainosc_freq
Definition: at91sam3.c:81
sam3_cfg::pclk2_freq
uint32_t pclk2_freq
Definition: at91sam3.c:88
sam3_cfg::CKGR_UCKR
uint32_t CKGR_UCKR
Definition: at91sam3.c:107
sam3_cfg::CHIPID_EXID2
uint32_t CHIPID_EXID2
Definition: at91sam3.c:98
sam3_cfg::CKGR_MOR
uint32_t CKGR_MOR
Definition: at91sam3.c:109
sam3_cfg::plla_freq
uint32_t plla_freq
Definition: at91sam3.c:82
sam3_cfg::cpu_freq
uint32_t cpu_freq
Definition: at91sam3.c:84
sam3_cfg::fclk_freq
uint32_t fclk_freq
Definition: at91sam3.c:85
sam3_cfg::CKGR_MCFR
uint32_t CKGR_MCFR
Definition: at91sam3.c:111
sam3_cfg::CHIPID_EXID
uint32_t CHIPID_EXID
Definition: at91sam3.c:96
sam3_cfg::PMC_PCK0
uint32_t PMC_PCK0
Definition: at91sam3.c:117
sam3_cfg::CHIPID_CIDR
uint32_t CHIPID_CIDR
Definition: at91sam3.c:92
sam3_cfg::PMC_FSMR
uint32_t PMC_FSMR
Definition: at91sam3.c:127
sam3_cfg::rc_freq
uint32_t rc_freq
Definition: at91sam3.c:80
sam3_cfg::PMC_PCK2
uint32_t PMC_PCK2
Definition: at91sam3.c:121
sam3_cfg::PMC_PCK1
uint32_t PMC_PCK1
Definition: at91sam3.c:119
sam3_chip_details
Definition: at91sam3.c:165
sam3_chip_details::n_banks
unsigned int n_banks
Definition: at91sam3.c:181
sam3_chip_details::total_flash_size
unsigned int total_flash_size
Definition: at91sam3.c:179
sam3_chip_details::n_gpnvms
unsigned int n_gpnvms
Definition: at91sam3.c:176
sam3_chip_details::name
const char * name
Definition: at91sam3.c:174
sam3_chip_details::gpnvm
unsigned int gpnvm[SAM3_N_NVM_BITS]
Definition: at91sam3.c:178
sam3_chip_details::bank
struct sam3_bank_private bank[SAM3_MAX_FLASH_BANKS]
Definition: at91sam3.c:184
sam3_chip_details::total_sram_size
unsigned int total_sram_size
Definition: at91sam3.c:180
sam3_chip_details::chipid_cidr
uint32_t chipid_cidr
Definition: at91sam3.c:173
sam3_chip
Definition: at91sam3.c:187
sam3_chip::next
struct sam3_chip * next
Definition: at91sam3.c:188
sam3_chip::probed
bool probed
Definition: at91sam3.c:189
sam3_chip::target
struct target * target
Definition: at91sam3.c:193
sam3_chip::details
struct sam3_chip_details details
Definition: at91sam3.c:192
sam3_chip::cfg
struct sam3_cfg cfg
Definition: at91sam3.c:194
sam3_reg_list
Definition: at91sam3.c:198
sam3_reg_list::name
const char * name
Definition: at91sam3.c:199
sam3_reg_list::address
uint32_t address
Definition: at91sam3.c:199
sam3_reg_list::struct_offset
size_t struct_offset
Definition: at91sam3.c:199
sam3_reg_list::explain_func
void(* explain_func)(struct sam3_chip *chip)
Definition: at91sam3.c:200
target
Definition: target.h:119
target::state
enum target_state state
Definition: target.h:167
target_write_memory
int target_write_memory(struct target *target, target_addr_t address, uint32_t size, uint32_t count, const uint8_t *buffer)
Write count items of size bytes to the memory of target at the address given.
Definition: target.c:1288
target_write_u32
int target_write_u32(struct target *target, target_addr_t address, uint32_t value)
Definition: target.c:2635
target_read_u32
int target_read_u32(struct target *target, target_addr_t address, uint32_t *value)
Definition: target.c:2561
target_read_memory
int target_read_memory(struct target *target, target_addr_t address, uint32_t size, uint32_t count, uint8_t *buffer)
Read count items of size bytes from the memory of target at the address given.
Definition: target.c:1260
get_current_target
struct target * get_current_target(struct command_context *cmd_ctx)
Definition: target.c:468
ERROR_TARGET_NOT_HALTED
#define ERROR_TARGET_NOT_HALTED
Definition: target.h:817
TARGET_HALTED
@ TARGET_HALTED
Definition: target.h:58
time_support.h
timeval_ms
int64_t timeval_ms(void)
Definition: time_support_common.c:23
TARGET_ADDR_FMT
#define TARGET_ADDR_FMT
Definition: types.h:286
NULL
#define NULL
Definition: usb.h:16
status
uint8_t status[4]
Definition: vdebug.c:17
cmd
uint8_t cmd
Definition: vdebug.c:1
offset
uint8_t offset[4]
Definition: vdebug.c:9
count
uint8_t count[4]
Definition: vdebug.c:22