OpenOCD
at91sam3.c
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1 // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-Source-Code)
2 
3 /*
4  * Copyright (C) 2009 by Duane Ellis <openocd@duaneellis.com>
5  *
6  * at91sam3s* support
7  * Copyright (C) 2010 by Olaf Lüke <olaf@uni-paderborn.de>
8  * Copyright (C) 2011 by Olivier Schonken and Jim Norris
9  *
10  * Some of the lower level code was based on code supplied by
11  * ATMEL under BSD-Source-Code License and this copyright.
12  * ATMEL Microcontroller Software Support
13  * Copyright (c) 2009, Atmel Corporation. All rights reserved.
14  */
15 
16 #ifdef HAVE_CONFIG_H
17 #include "config.h"
18 #endif
19 
20 #include "imp.h"
21 #include <helper/time_support.h>
22 
23 #define REG_NAME_WIDTH (12)
24 
25 /* at91sam3u series (has one or two flash banks) */
26 #define FLASH_BANK0_BASE_U 0x00080000
27 #define FLASH_BANK1_BASE_U 0x00100000
28 
29 /* at91sam3s series (has always one flash bank) */
30 #define FLASH_BANK_BASE_S 0x00400000
31 
32 /* at91sam3sd series (has always two flash banks) */
33 #define FLASH_BANK0_BASE_SD FLASH_BANK_BASE_S
34 #define FLASH_BANK1_BASE_512K_SD (FLASH_BANK0_BASE_SD+(512*1024/2))
35 
36 
37 /* at91sam3n series (has always one flash bank) */
38 #define FLASH_BANK_BASE_N 0x00400000
39 
40 /* at91sam3a/x series has two flash banks*/
41 #define FLASH_BANK0_BASE_AX 0x00080000
42 /*Bank 1 of the at91sam3a/x series starts at 0x00080000 + half flash size*/
43 #define FLASH_BANK1_BASE_256K_AX 0x000A0000
44 #define FLASH_BANK1_BASE_512K_AX 0x000C0000
45 
46 #define AT91C_EFC_FCMD_GETD (0x0) /* (EFC) Get Flash Descriptor */
47 #define AT91C_EFC_FCMD_WP (0x1) /* (EFC) Write Page */
48 #define AT91C_EFC_FCMD_WPL (0x2) /* (EFC) Write Page and Lock */
49 #define AT91C_EFC_FCMD_EWP (0x3) /* (EFC) Erase Page and Write Page */
50 #define AT91C_EFC_FCMD_EWPL (0x4) /* (EFC) Erase Page and Write Page then Lock */
51 #define AT91C_EFC_FCMD_EA (0x5) /* (EFC) Erase All */
52 /* cmd6 is not present in the at91sam3u4/2/1 data sheet table 17-2 */
53 /* #define AT91C_EFC_FCMD_EPL (0x6) // (EFC) Erase plane? */
54 /* cmd7 is not present in the at91sam3u4/2/1 data sheet table 17-2 */
55 /* #define AT91C_EFC_FCMD_EPA (0x7) // (EFC) Erase pages? */
56 #define AT91C_EFC_FCMD_SLB (0x8) /* (EFC) Set Lock Bit */
57 #define AT91C_EFC_FCMD_CLB (0x9) /* (EFC) Clear Lock Bit */
58 #define AT91C_EFC_FCMD_GLB (0xA) /* (EFC) Get Lock Bit */
59 #define AT91C_EFC_FCMD_SFB (0xB) /* (EFC) Set Fuse Bit */
60 #define AT91C_EFC_FCMD_CFB (0xC) /* (EFC) Clear Fuse Bit */
61 #define AT91C_EFC_FCMD_GFB (0xD) /* (EFC) Get Fuse Bit */
62 #define AT91C_EFC_FCMD_STUI (0xE) /* (EFC) Start Read Unique ID */
63 #define AT91C_EFC_FCMD_SPUI (0xF) /* (EFC) Stop Read Unique ID */
64 
65 #define OFFSET_EFC_FMR 0
66 #define OFFSET_EFC_FCR 4
67 #define OFFSET_EFC_FSR 8
68 #define OFFSET_EFC_FRR 12
69 
70 static float _tomhz(uint32_t freq_hz)
71 {
72  float f;
73 
74  f = ((float)(freq_hz)) / 1000000.0;
75  return f;
76 }
77 
78 /* How the chip is configured. */
79 struct sam3_cfg {
80  uint32_t unique_id[4];
81 
82  uint32_t slow_freq;
83  uint32_t rc_freq;
84  uint32_t mainosc_freq;
85  uint32_t plla_freq;
86  uint32_t mclk_freq;
87  uint32_t cpu_freq;
88  uint32_t fclk_freq;
89  uint32_t pclk0_freq;
90  uint32_t pclk1_freq;
91  uint32_t pclk2_freq;
92 
93 
94 #define SAM3_CHIPID_CIDR (0x400E0740)
95  uint32_t CHIPID_CIDR;
96 #define SAM3_CHIPID_CIDR2 (0x400E0940) /*SAM3X and SAM3A cidr at this address*/
97  uint32_t CHIPID_CIDR2;
98 #define SAM3_CHIPID_EXID (0x400E0744)
99  uint32_t CHIPID_EXID;
100 #define SAM3_CHIPID_EXID2 (0x400E0944) /*SAM3X and SAM3A cidr at this address*/
101  uint32_t CHIPID_EXID2;
102 
103 
104 #define SAM3_PMC_BASE (0x400E0400)
105 #define SAM3_PMC_SCSR (SAM3_PMC_BASE + 0x0008)
106  uint32_t PMC_SCSR;
107 #define SAM3_PMC_PCSR (SAM3_PMC_BASE + 0x0018)
108  uint32_t PMC_PCSR;
109 #define SAM3_CKGR_UCKR (SAM3_PMC_BASE + 0x001c)
110  uint32_t CKGR_UCKR;
111 #define SAM3_CKGR_MOR (SAM3_PMC_BASE + 0x0020)
112  uint32_t CKGR_MOR;
113 #define SAM3_CKGR_MCFR (SAM3_PMC_BASE + 0x0024)
114  uint32_t CKGR_MCFR;
115 #define SAM3_CKGR_PLLAR (SAM3_PMC_BASE + 0x0028)
116  uint32_t CKGR_PLLAR;
117 #define SAM3_PMC_MCKR (SAM3_PMC_BASE + 0x0030)
118  uint32_t PMC_MCKR;
119 #define SAM3_PMC_PCK0 (SAM3_PMC_BASE + 0x0040)
120  uint32_t PMC_PCK0;
121 #define SAM3_PMC_PCK1 (SAM3_PMC_BASE + 0x0044)
122  uint32_t PMC_PCK1;
123 #define SAM3_PMC_PCK2 (SAM3_PMC_BASE + 0x0048)
124  uint32_t PMC_PCK2;
125 #define SAM3_PMC_SR (SAM3_PMC_BASE + 0x0068)
126  uint32_t PMC_SR;
127 #define SAM3_PMC_IMR (SAM3_PMC_BASE + 0x006c)
128  uint32_t PMC_IMR;
129 #define SAM3_PMC_FSMR (SAM3_PMC_BASE + 0x0070)
130  uint32_t PMC_FSMR;
131 #define SAM3_PMC_FSPR (SAM3_PMC_BASE + 0x0074)
132  uint32_t PMC_FSPR;
133 };
134 
135 /*
136  * The AT91SAM3N data sheet 04-Oct-2010, AT91SAM3U data sheet 22-Aug-2011
137  * and AT91SAM3S data sheet 09-Feb-2011 state that for flash writes
138  * the flash wait state (FWS) should be set to 6. It seems like that the
139  * cause of the problem is not the flash itself, but the flash write
140  * buffer. Ie the wait states have to be set before writing into the
141  * buffer.
142  * Tested and confirmed with SAM3N and SAM3U
143  */
144 
145 struct sam3_bank_private {
146  bool probed;
147  /* DANGER: THERE ARE DRAGONS HERE.. */
148  /* NOTE: If you add more 'ghost' pointers */
149  /* be aware that you must *manually* update */
150  /* these pointers in the function sam3_get_details() */
151  /* See the comment "Here there be dragons" */
152 
153  /* so we can find the chip we belong to */
154  struct sam3_chip *chip;
155  /* so we can find the original bank pointer */
156  struct flash_bank *bank;
157  unsigned int bank_number;
158  uint32_t controller_address;
159  uint32_t base_address;
160  uint32_t flash_wait_states;
161  bool present;
162  unsigned int size_bytes;
163  unsigned int nsectors;
164  unsigned int sector_size;
165  unsigned int page_size;
166 };
167 
168 struct sam3_chip_details {
169  /* THERE ARE DRAGONS HERE.. */
170  /* note: If you add pointers here */
171  /* be careful about them as they */
172  /* may need to be updated inside */
173  /* the function: "sam3_get_details() */
174  /* which copy/overwrites the */
175  /* 'runtime' copy of this structure */
176  uint32_t chipid_cidr;
177  const char *name;
178 
179  unsigned int n_gpnvms;
180 #define SAM3_N_NVM_BITS 3
181  unsigned int gpnvm[SAM3_N_NVM_BITS];
182  unsigned int total_flash_size;
183  unsigned int total_sram_size;
184  unsigned int n_banks;
185 #define SAM3_MAX_FLASH_BANKS 2
186  /* these are "initialized" from the global const data */
187  struct sam3_bank_private bank[SAM3_MAX_FLASH_BANKS];
188 };
189 
190 struct sam3_chip {
191  struct sam3_chip *next;
192  bool probed;
193 
194  /* this is "initialized" from the global const structure */
195  struct sam3_chip_details details;
196  struct target *target;
197  struct sam3_cfg cfg;
198 };
199 
200 
201 struct sam3_reg_list {
202  uint32_t address; size_t struct_offset; const char *name;
203  void (*explain_func)(struct sam3_chip *chip);
204 };
205 
206 static struct sam3_chip *all_sam3_chips;
207 
208 static struct sam3_chip *get_current_sam3(struct command_invocation *cmd)
209 {
210  struct target *t;
211  static struct sam3_chip *p;
212 
213  t = get_current_target(cmd->ctx);
214  if (!t) {
215  command_print_sameline(cmd, "No current target?\n");
216  return NULL;
217  }
218 
219  p = all_sam3_chips;
220  if (!p) {
221  /* this should not happen */
222  /* the command is not registered until the chip is created? */
223  command_print_sameline(cmd, "No SAM3 chips exist?\n");
224  return NULL;
225  }
226 
227  while (p) {
228  if (p->target == t)
229  return p;
230  p = p->next;
231  }
232  command_print_sameline(cmd, "Cannot find SAM3 chip?\n");
233  return NULL;
234 }
235 
236 /* these are used to *initialize* the "chip->details" structure. */
237 static const struct sam3_chip_details all_sam3_details[] = {
238  /* Start at91sam3u* series */
239  {
240  .chipid_cidr = 0x28100960,
241  .name = "at91sam3u4e",
242  .total_flash_size = 256 * 1024,
243  .total_sram_size = 52 * 1024,
244  .n_gpnvms = 3,
245  .n_banks = 2,
246 
247  /* System boots at address 0x0 */
248  /* gpnvm[1] = selects boot code */
249  /* if gpnvm[1] == 0 */
250  /* boot is via "SAMBA" (rom) */
251  /* else */
252  /* boot is via FLASH */
253  /* Selection is via gpnvm[2] */
254  /* endif */
255  /* */
256  /* NOTE: banks 0 & 1 switch places */
257  /* if gpnvm[2] == 0 */
258  /* Bank0 is the boot rom */
259  /* else */
260  /* Bank1 is the boot rom */
261  /* endif */
262 /* .bank[0] = { */
263  {
264  {
265  .probed = false,
266  .chip = NULL,
267  .bank = NULL,
268  .bank_number = 0,
269  .base_address = FLASH_BANK0_BASE_U,
270  .controller_address = 0x400e0800,
271  .flash_wait_states = 6, /* workaround silicon bug */
272  .present = 1,
273  .size_bytes = 128 * 1024,
274  .nsectors = 16,
275  .sector_size = 8192,
276  .page_size = 256,
277  },
278 
279 /* .bank[1] = { */
280  {
281  .probed = false,
282  .chip = NULL,
283  .bank = NULL,
284  .bank_number = 1,
285  .base_address = FLASH_BANK1_BASE_U,
286  .controller_address = 0x400e0a00,
287  .flash_wait_states = 6, /* workaround silicon bug */
288  .present = 1,
289  .size_bytes = 128 * 1024,
290  .nsectors = 16,
291  .sector_size = 8192,
292  .page_size = 256,
293  },
294  },
295  },
296 
297  {
298  .chipid_cidr = 0x281a0760,
299  .name = "at91sam3u2e",
300  .total_flash_size = 128 * 1024,
301  .total_sram_size = 36 * 1024,
302  .n_gpnvms = 2,
303  .n_banks = 1,
304 
305  /* System boots at address 0x0 */
306  /* gpnvm[1] = selects boot code */
307  /* if gpnvm[1] == 0 */
308  /* boot is via "SAMBA" (rom) */
309  /* else */
310  /* boot is via FLASH */
311  /* Selection is via gpnvm[2] */
312  /* endif */
313 /* .bank[0] = { */
314  {
315  {
316  .probed = false,
317  .chip = NULL,
318  .bank = NULL,
319  .bank_number = 0,
320  .base_address = FLASH_BANK0_BASE_U,
321  .controller_address = 0x400e0800,
322  .flash_wait_states = 6, /* workaround silicon bug */
323  .present = 1,
324  .size_bytes = 128 * 1024,
325  .nsectors = 16,
326  .sector_size = 8192,
327  .page_size = 256,
328  },
329 /* .bank[1] = { */
330  {
331  .present = 0,
332  .probed = false,
333  .bank_number = 1,
334  },
335  },
336  },
337  {
338  .chipid_cidr = 0x28190560,
339  .name = "at91sam3u1e",
340  .total_flash_size = 64 * 1024,
341  .total_sram_size = 20 * 1024,
342  .n_gpnvms = 2,
343  .n_banks = 1,
344 
345  /* System boots at address 0x0 */
346  /* gpnvm[1] = selects boot code */
347  /* if gpnvm[1] == 0 */
348  /* boot is via "SAMBA" (rom) */
349  /* else */
350  /* boot is via FLASH */
351  /* Selection is via gpnvm[2] */
352  /* endif */
353  /* */
354 
355 /* .bank[0] = { */
356  {
357  {
358  .probed = false,
359  .chip = NULL,
360  .bank = NULL,
361  .bank_number = 0,
362  .base_address = FLASH_BANK0_BASE_U,
363  .controller_address = 0x400e0800,
364  .flash_wait_states = 6, /* workaround silicon bug */
365  .present = 1,
366  .size_bytes = 64 * 1024,
367  .nsectors = 8,
368  .sector_size = 8192,
369  .page_size = 256,
370  },
371 
372 /* .bank[1] = { */
373  {
374  .present = 0,
375  .probed = false,
376  .bank_number = 1,
377  },
378  },
379  },
380 
381  {
382  .chipid_cidr = 0x28000960,
383  .name = "at91sam3u4c",
384  .total_flash_size = 256 * 1024,
385  .total_sram_size = 52 * 1024,
386  .n_gpnvms = 3,
387  .n_banks = 2,
388 
389  /* System boots at address 0x0 */
390  /* gpnvm[1] = selects boot code */
391  /* if gpnvm[1] == 0 */
392  /* boot is via "SAMBA" (rom) */
393  /* else */
394  /* boot is via FLASH */
395  /* Selection is via gpnvm[2] */
396  /* endif */
397  /* */
398  /* NOTE: banks 0 & 1 switch places */
399  /* if gpnvm[2] == 0 */
400  /* Bank0 is the boot rom */
401  /* else */
402  /* Bank1 is the boot rom */
403  /* endif */
404  {
405  {
406 /* .bank[0] = { */
407  .probed = false,
408  .chip = NULL,
409  .bank = NULL,
410  .bank_number = 0,
411  .base_address = FLASH_BANK0_BASE_U,
412  .controller_address = 0x400e0800,
413  .flash_wait_states = 6, /* workaround silicon bug */
414  .present = 1,
415  .size_bytes = 128 * 1024,
416  .nsectors = 16,
417  .sector_size = 8192,
418  .page_size = 256,
419  },
420 /* .bank[1] = { */
421  {
422  .probed = false,
423  .chip = NULL,
424  .bank = NULL,
425  .bank_number = 1,
426  .base_address = FLASH_BANK1_BASE_U,
427  .controller_address = 0x400e0a00,
428  .flash_wait_states = 6, /* workaround silicon bug */
429  .present = 1,
430  .size_bytes = 128 * 1024,
431  .nsectors = 16,
432  .sector_size = 8192,
433  .page_size = 256,
434  },
435  },
436  },
437 
438  {
439  .chipid_cidr = 0x280a0760,
440  .name = "at91sam3u2c",
441  .total_flash_size = 128 * 1024,
442  .total_sram_size = 36 * 1024,
443  .n_gpnvms = 2,
444  .n_banks = 1,
445 
446  /* System boots at address 0x0 */
447  /* gpnvm[1] = selects boot code */
448  /* if gpnvm[1] == 0 */
449  /* boot is via "SAMBA" (rom) */
450  /* else */
451  /* boot is via FLASH */
452  /* Selection is via gpnvm[2] */
453  /* endif */
454  {
455 /* .bank[0] = { */
456  {
457  .probed = false,
458  .chip = NULL,
459  .bank = NULL,
460  .bank_number = 0,
461  .base_address = FLASH_BANK0_BASE_U,
462  .controller_address = 0x400e0800,
463  .flash_wait_states = 6, /* workaround silicon bug */
464  .present = 1,
465  .size_bytes = 128 * 1024,
466  .nsectors = 16,
467  .sector_size = 8192,
468  .page_size = 256,
469  },
470 /* .bank[1] = { */
471  {
472  .present = 0,
473  .probed = false,
474  .bank_number = 1,
475  },
476  },
477  },
478  {
479  .chipid_cidr = 0x28090560,
480  .name = "at91sam3u1c",
481  .total_flash_size = 64 * 1024,
482  .total_sram_size = 20 * 1024,
483  .n_gpnvms = 2,
484  .n_banks = 1,
485 
486  /* System boots at address 0x0 */
487  /* gpnvm[1] = selects boot code */
488  /* if gpnvm[1] == 0 */
489  /* boot is via "SAMBA" (rom) */
490  /* else */
491  /* boot is via FLASH */
492  /* Selection is via gpnvm[2] */
493  /* endif */
494  /* */
495 
496  {
497 /* .bank[0] = { */
498  {
499  .probed = false,
500  .chip = NULL,
501  .bank = NULL,
502  .bank_number = 0,
503  .base_address = FLASH_BANK0_BASE_U,
504  .controller_address = 0x400e0800,
505  .flash_wait_states = 6, /* workaround silicon bug */
506  .present = 1,
507  .size_bytes = 64 * 1024,
508  .nsectors = 8,
509  .sector_size = 8192,
510  .page_size = 256,
511  },
512 /* .bank[1] = { */
513  {
514  .present = 0,
515  .probed = false,
516  .bank_number = 1,
517 
518  },
519  },
520  },
521 
522  /* Start at91sam3s* series */
523 
524  /* Note: The preliminary at91sam3s datasheet says on page 302 */
525  /* that the flash controller is at address 0x400E0800. */
526  /* This is _not_ the case, the controller resides at address 0x400e0a00. */
527  {
528  .chipid_cidr = 0x28A00960,
529  .name = "at91sam3s4c",
530  .total_flash_size = 256 * 1024,
531  .total_sram_size = 48 * 1024,
532  .n_gpnvms = 2,
533  .n_banks = 1,
534  {
535 /* .bank[0] = { */
536  {
537  .probed = false,
538  .chip = NULL,
539  .bank = NULL,
540  .bank_number = 0,
541  .base_address = FLASH_BANK_BASE_S,
542  .controller_address = 0x400e0a00,
543  .flash_wait_states = 6, /* workaround silicon bug */
544  .present = 1,
545  .size_bytes = 256 * 1024,
546  .nsectors = 16,
547  .sector_size = 16384,
548  .page_size = 256,
549  },
550 /* .bank[1] = { */
551  {
552  .present = 0,
553  .probed = false,
554  .bank_number = 1,
555 
556  },
557  },
558  },
559 
560  {
561  .chipid_cidr = 0x28900960,
562  .name = "at91sam3s4b",
563  .total_flash_size = 256 * 1024,
564  .total_sram_size = 48 * 1024,
565  .n_gpnvms = 2,
566  .n_banks = 1,
567  {
568 /* .bank[0] = { */
569  {
570  .probed = false,
571  .chip = NULL,
572  .bank = NULL,
573  .bank_number = 0,
574  .base_address = FLASH_BANK_BASE_S,
575  .controller_address = 0x400e0a00,
576  .flash_wait_states = 6, /* workaround silicon bug */
577  .present = 1,
578  .size_bytes = 256 * 1024,
579  .nsectors = 16,
580  .sector_size = 16384,
581  .page_size = 256,
582  },
583 /* .bank[1] = { */
584  {
585  .present = 0,
586  .probed = false,
587  .bank_number = 1,
588 
589  },
590  },
591  },
592  {
593  .chipid_cidr = 0x28800960,
594  .name = "at91sam3s4a",
595  .total_flash_size = 256 * 1024,
596  .total_sram_size = 48 * 1024,
597  .n_gpnvms = 2,
598  .n_banks = 1,
599  {
600 /* .bank[0] = { */
601  {
602  .probed = false,
603  .chip = NULL,
604  .bank = NULL,
605  .bank_number = 0,
606  .base_address = FLASH_BANK_BASE_S,
607  .controller_address = 0x400e0a00,
608  .flash_wait_states = 6, /* workaround silicon bug */
609  .present = 1,
610  .size_bytes = 256 * 1024,
611  .nsectors = 16,
612  .sector_size = 16384,
613  .page_size = 256,
614  },
615 /* .bank[1] = { */
616  {
617  .present = 0,
618  .probed = false,
619  .bank_number = 1,
620 
621  },
622  },
623  },
624  {
625  .chipid_cidr = 0x28AA0760,
626  .name = "at91sam3s2c",
627  .total_flash_size = 128 * 1024,
628  .total_sram_size = 32 * 1024,
629  .n_gpnvms = 2,
630  .n_banks = 1,
631  {
632 /* .bank[0] = { */
633  {
634  .probed = false,
635  .chip = NULL,
636  .bank = NULL,
637  .bank_number = 0,
638  .base_address = FLASH_BANK_BASE_S,
639  .controller_address = 0x400e0a00,
640  .flash_wait_states = 6, /* workaround silicon bug */
641  .present = 1,
642  .size_bytes = 128 * 1024,
643  .nsectors = 8,
644  .sector_size = 16384,
645  .page_size = 256,
646  },
647 /* .bank[1] = { */
648  {
649  .present = 0,
650  .probed = false,
651  .bank_number = 1,
652 
653  },
654  },
655  },
656  {
657  .chipid_cidr = 0x289A0760,
658  .name = "at91sam3s2b",
659  .total_flash_size = 128 * 1024,
660  .total_sram_size = 32 * 1024,
661  .n_gpnvms = 2,
662  .n_banks = 1,
663  {
664 /* .bank[0] = { */
665  {
666  .probed = false,
667  .chip = NULL,
668  .bank = NULL,
669  .bank_number = 0,
670  .base_address = FLASH_BANK_BASE_S,
671  .controller_address = 0x400e0a00,
672  .flash_wait_states = 6, /* workaround silicon bug */
673  .present = 1,
674  .size_bytes = 128 * 1024,
675  .nsectors = 8,
676  .sector_size = 16384,
677  .page_size = 256,
678  },
679 /* .bank[1] = { */
680  {
681  .present = 0,
682  .probed = false,
683  .bank_number = 1,
684 
685  },
686  },
687  },
688  {
689  .chipid_cidr = 0x298B0A60,
690  .name = "at91sam3sd8a",
691  .total_flash_size = 512 * 1024,
692  .total_sram_size = 64 * 1024,
693  .n_gpnvms = 3,
694  .n_banks = 2,
695  {
696 /* .bank[0] = { */
697  {
698  .probed = false,
699  .chip = NULL,
700  .bank = NULL,
701  .bank_number = 0,
702  .base_address = FLASH_BANK0_BASE_SD,
703  .controller_address = 0x400e0a00,
704  .flash_wait_states = 6, /* workaround silicon bug */
705  .present = 1,
706  .size_bytes = 256 * 1024,
707  .nsectors = 16,
708  .sector_size = 32768,
709  .page_size = 256,
710  },
711 /* .bank[1] = { */
712  {
713  .probed = false,
714  .chip = NULL,
715  .bank = NULL,
716  .bank_number = 1,
717  .base_address = FLASH_BANK1_BASE_512K_SD,
718  .controller_address = 0x400e0a00,
719  .flash_wait_states = 6, /* workaround silicon bug */
720  .present = 1,
721  .size_bytes = 256 * 1024,
722  .nsectors = 16,
723  .sector_size = 32768,
724  .page_size = 256,
725  },
726  },
727  },
728  {
729  .chipid_cidr = 0x299B0A60,
730  .name = "at91sam3sd8b",
731  .total_flash_size = 512 * 1024,
732  .total_sram_size = 64 * 1024,
733  .n_gpnvms = 3,
734  .n_banks = 2,
735  {
736 /* .bank[0] = { */
737  {
738  .probed = false,
739  .chip = NULL,
740  .bank = NULL,
741  .bank_number = 0,
742  .base_address = FLASH_BANK0_BASE_SD,
743  .controller_address = 0x400e0a00,
744  .flash_wait_states = 6, /* workaround silicon bug */
745  .present = 1,
746  .size_bytes = 256 * 1024,
747  .nsectors = 16,
748  .sector_size = 32768,
749  .page_size = 256,
750  },
751 /* .bank[1] = { */
752  {
753  .probed = false,
754  .chip = NULL,
755  .bank = NULL,
756  .bank_number = 1,
757  .base_address = FLASH_BANK1_BASE_512K_SD,
758  .controller_address = 0x400e0a00,
759  .flash_wait_states = 6, /* workaround silicon bug */
760  .present = 1,
761  .size_bytes = 256 * 1024,
762  .nsectors = 16,
763  .sector_size = 32768,
764  .page_size = 256,
765  },
766  },
767  },
768  {
769  .chipid_cidr = 0x29ab0a60,
770  .name = "at91sam3sd8c",
771  .total_flash_size = 512 * 1024,
772  .total_sram_size = 64 * 1024,
773  .n_gpnvms = 3,
774  .n_banks = 2,
775  {
776 /* .bank[0] = { */
777  {
778  .probed = false,
779  .chip = NULL,
780  .bank = NULL,
781  .bank_number = 0,
782  .base_address = FLASH_BANK0_BASE_SD,
783  .controller_address = 0x400e0a00,
784  .flash_wait_states = 6, /* workaround silicon bug */
785  .present = 1,
786  .size_bytes = 256 * 1024,
787  .nsectors = 16,
788  .sector_size = 32768,
789  .page_size = 256,
790  },
791 /* .bank[1] = { */
792  {
793  .probed = false,
794  .chip = NULL,
795  .bank = NULL,
796  .bank_number = 1,
797  .base_address = FLASH_BANK1_BASE_512K_SD,
798  .controller_address = 0x400e0a00,
799  .flash_wait_states = 6, /* workaround silicon bug */
800  .present = 1,
801  .size_bytes = 256 * 1024,
802  .nsectors = 16,
803  .sector_size = 32768,
804  .page_size = 256,
805  },
806  },
807  },
808  {
809  .chipid_cidr = 0x288A0760,
810  .name = "at91sam3s2a",
811  .total_flash_size = 128 * 1024,
812  .total_sram_size = 32 * 1024,
813  .n_gpnvms = 2,
814  .n_banks = 1,
815  {
816 /* .bank[0] = { */
817  {
818  .probed = false,
819  .chip = NULL,
820  .bank = NULL,
821  .bank_number = 0,
822  .base_address = FLASH_BANK_BASE_S,
823  .controller_address = 0x400e0a00,
824  .flash_wait_states = 6, /* workaround silicon bug */
825  .present = 1,
826  .size_bytes = 128 * 1024,
827  .nsectors = 8,
828  .sector_size = 16384,
829  .page_size = 256,
830  },
831 /* .bank[1] = { */
832  {
833  .present = 0,
834  .probed = false,
835  .bank_number = 1,
836 
837  },
838  },
839  },
840  {
841  .chipid_cidr = 0x28A90560,
842  .name = "at91sam3s1c",
843  .total_flash_size = 64 * 1024,
844  .total_sram_size = 16 * 1024,
845  .n_gpnvms = 2,
846  .n_banks = 1,
847  {
848 /* .bank[0] = { */
849  {
850  .probed = false,
851  .chip = NULL,
852  .bank = NULL,
853  .bank_number = 0,
854  .base_address = FLASH_BANK_BASE_S,
855  .controller_address = 0x400e0a00,
856  .flash_wait_states = 6, /* workaround silicon bug */
857  .present = 1,
858  .size_bytes = 64 * 1024,
859  .nsectors = 4,
860  .sector_size = 16384,
861  .page_size = 256,
862  },
863 /* .bank[1] = { */
864  {
865  .present = 0,
866  .probed = false,
867  .bank_number = 1,
868 
869  },
870  },
871  },
872  {
873  .chipid_cidr = 0x28990560,
874  .name = "at91sam3s1b",
875  .total_flash_size = 64 * 1024,
876  .total_sram_size = 16 * 1024,
877  .n_gpnvms = 2,
878  .n_banks = 1,
879  {
880 /* .bank[0] = { */
881  {
882  .probed = false,
883  .chip = NULL,
884  .bank = NULL,
885  .bank_number = 0,
886  .base_address = FLASH_BANK_BASE_S,
887  .controller_address = 0x400e0a00,
888  .flash_wait_states = 6, /* workaround silicon bug */
889  .present = 1,
890  .size_bytes = 64 * 1024,
891  .nsectors = 4,
892  .sector_size = 16384,
893  .page_size = 256,
894  },
895 /* .bank[1] = { */
896  {
897  .present = 0,
898  .probed = false,
899  .bank_number = 1,
900 
901  },
902  },
903  },
904  {
905  .chipid_cidr = 0x28890560,
906  .name = "at91sam3s1a",
907  .total_flash_size = 64 * 1024,
908  .total_sram_size = 16 * 1024,
909  .n_gpnvms = 2,
910  .n_banks = 1,
911  {
912 /* .bank[0] = { */
913  {
914  .probed = false,
915  .chip = NULL,
916  .bank = NULL,
917  .bank_number = 0,
918  .base_address = FLASH_BANK_BASE_S,
919  .controller_address = 0x400e0a00,
920  .flash_wait_states = 6, /* workaround silicon bug */
921  .present = 1,
922  .size_bytes = 64 * 1024,
923  .nsectors = 4,
924  .sector_size = 16384,
925  .page_size = 256,
926  },
927 /* .bank[1] = { */
928  {
929  .present = 0,
930  .probed = false,
931  .bank_number = 1,
932 
933  },
934  },
935  },
936  {
937  .chipid_cidr = 0x288B0A60,
938  .name = "at91sam3s8a",
939  .total_flash_size = 256 * 2048,
940  .total_sram_size = 64 * 1024,
941  .n_gpnvms = 2,
942  .n_banks = 1,
943  {
944 /* .bank[0] = { */
945  {
946  .probed = false,
947  .chip = NULL,
948  .bank = NULL,
949  .bank_number = 0,
950  .base_address = FLASH_BANK_BASE_S,
951  .controller_address = 0x400e0a00,
952  .flash_wait_states = 6, /* workaround silicon bug */
953  .present = 1,
954  .size_bytes = 256 * 2048,
955  .nsectors = 16,
956  .sector_size = 32768,
957  .page_size = 256,
958  },
959 /* .bank[1] = { */
960  {
961  .present = 0,
962  .probed = false,
963  .bank_number = 1,
964 
965  },
966  },
967  },
968  {
969  .chipid_cidr = 0x289B0A60,
970  .name = "at91sam3s8b",
971  .total_flash_size = 256 * 2048,
972  .total_sram_size = 64 * 1024,
973  .n_gpnvms = 2,
974  .n_banks = 1,
975  {
976 /* .bank[0] = { */
977  {
978  .probed = false,
979  .chip = NULL,
980  .bank = NULL,
981  .bank_number = 0,
982  .base_address = FLASH_BANK_BASE_S,
983  .controller_address = 0x400e0a00,
984  .flash_wait_states = 6, /* workaround silicon bug */
985  .present = 1,
986  .size_bytes = 256 * 2048,
987  .nsectors = 16,
988  .sector_size = 32768,
989  .page_size = 256,
990  },
991 /* .bank[1] = { */
992  {
993  .present = 0,
994  .probed = false,
995  .bank_number = 1,
996 
997  },
998  },
999  },
1000  {
1001  .chipid_cidr = 0x28AB0A60,
1002  .name = "at91sam3s8c",
1003  .total_flash_size = 256 * 2048,
1004  .total_sram_size = 64 * 1024,
1005  .n_gpnvms = 2,
1006  .n_banks = 1,
1007  {
1008 /* .bank[0] = { */
1009  {
1010  .probed = false,
1011  .chip = NULL,
1012  .bank = NULL,
1013  .bank_number = 0,
1014  .base_address = FLASH_BANK_BASE_S,
1015  .controller_address = 0x400e0a00,
1016  .flash_wait_states = 6, /* workaround silicon bug */
1017  .present = 1,
1018  .size_bytes = 256 * 2048,
1019  .nsectors = 16,
1020  .sector_size = 32768,
1021  .page_size = 256,
1022  },
1023 /* .bank[1] = { */
1024  {
1025  .present = 0,
1026  .probed = false,
1027  .bank_number = 1,
1028 
1029  },
1030  },
1031  },
1032 
1033  /* Start at91sam3n* series */
1034  {
1035  .chipid_cidr = 0x29540960,
1036  .name = "at91sam3n4c",
1037  .total_flash_size = 256 * 1024,
1038  .total_sram_size = 24 * 1024,
1039  .n_gpnvms = 3,
1040  .n_banks = 1,
1041 
1042  /* System boots at address 0x0 */
1043  /* gpnvm[1] = selects boot code */
1044  /* if gpnvm[1] == 0 */
1045  /* boot is via "SAMBA" (rom) */
1046  /* else */
1047  /* boot is via FLASH */
1048  /* Selection is via gpnvm[2] */
1049  /* endif */
1050  /* */
1051  /* NOTE: banks 0 & 1 switch places */
1052  /* if gpnvm[2] == 0 */
1053  /* Bank0 is the boot rom */
1054  /* else */
1055  /* Bank1 is the boot rom */
1056  /* endif */
1057 /* .bank[0] = { */
1058  {
1059  {
1060  .probed = false,
1061  .chip = NULL,
1062  .bank = NULL,
1063  .bank_number = 0,
1064  .base_address = FLASH_BANK_BASE_N,
1065  .controller_address = 0x400e0A00,
1066  .flash_wait_states = 6, /* workaround silicon bug */
1067  .present = 1,
1068  .size_bytes = 256 * 1024,
1069  .nsectors = 16,
1070  .sector_size = 16384,
1071  .page_size = 256,
1072  },
1073 
1074 /* .bank[1] = { */
1075  {
1076  .present = 0,
1077  .probed = false,
1078  .bank_number = 1,
1079  },
1080  },
1081  },
1082 
1083  {
1084  .chipid_cidr = 0x29440960,
1085  .name = "at91sam3n4b",
1086  .total_flash_size = 256 * 1024,
1087  .total_sram_size = 24 * 1024,
1088  .n_gpnvms = 3,
1089  .n_banks = 1,
1090 
1091  /* System boots at address 0x0 */
1092  /* gpnvm[1] = selects boot code */
1093  /* if gpnvm[1] == 0 */
1094  /* boot is via "SAMBA" (rom) */
1095  /* else */
1096  /* boot is via FLASH */
1097  /* Selection is via gpnvm[2] */
1098  /* endif */
1099  /* */
1100  /* NOTE: banks 0 & 1 switch places */
1101  /* if gpnvm[2] == 0 */
1102  /* Bank0 is the boot rom */
1103  /* else */
1104  /* Bank1 is the boot rom */
1105  /* endif */
1106 /* .bank[0] = { */
1107  {
1108  {
1109  .probed = false,
1110  .chip = NULL,
1111  .bank = NULL,
1112  .bank_number = 0,
1113  .base_address = FLASH_BANK_BASE_N,
1114  .controller_address = 0x400e0A00,
1115  .flash_wait_states = 6, /* workaround silicon bug */
1116  .present = 1,
1117  .size_bytes = 256 * 1024,
1118  .nsectors = 16,
1119  .sector_size = 16384,
1120  .page_size = 256,
1121  },
1122 
1123 /* .bank[1] = { */
1124  {
1125  .present = 0,
1126  .probed = false,
1127  .bank_number = 1,
1128  },
1129  },
1130  },
1131 
1132  {
1133  .chipid_cidr = 0x29340960,
1134  .name = "at91sam3n4a",
1135  .total_flash_size = 256 * 1024,
1136  .total_sram_size = 24 * 1024,
1137  .n_gpnvms = 3,
1138  .n_banks = 1,
1139 
1140  /* System boots at address 0x0 */
1141  /* gpnvm[1] = selects boot code */
1142  /* if gpnvm[1] == 0 */
1143  /* boot is via "SAMBA" (rom) */
1144  /* else */
1145  /* boot is via FLASH */
1146  /* Selection is via gpnvm[2] */
1147  /* endif */
1148  /* */
1149  /* NOTE: banks 0 & 1 switch places */
1150  /* if gpnvm[2] == 0 */
1151  /* Bank0 is the boot rom */
1152  /* else */
1153  /* Bank1 is the boot rom */
1154  /* endif */
1155 /* .bank[0] = { */
1156  {
1157  {
1158  .probed = false,
1159  .chip = NULL,
1160  .bank = NULL,
1161  .bank_number = 0,
1162  .base_address = FLASH_BANK_BASE_N,
1163  .controller_address = 0x400e0A00,
1164  .flash_wait_states = 6, /* workaround silicon bug */
1165  .present = 1,
1166  .size_bytes = 256 * 1024,
1167  .nsectors = 16,
1168  .sector_size = 16384,
1169  .page_size = 256,
1170  },
1171 
1172 /* .bank[1] = { */
1173  {
1174  .present = 0,
1175  .probed = false,
1176  .bank_number = 1,
1177  },
1178  },
1179  },
1180 
1181  {
1182  .chipid_cidr = 0x29590760,
1183  .name = "at91sam3n2c",
1184  .total_flash_size = 128 * 1024,
1185  .total_sram_size = 16 * 1024,
1186  .n_gpnvms = 3,
1187  .n_banks = 1,
1188 
1189  /* System boots at address 0x0 */
1190  /* gpnvm[1] = selects boot code */
1191  /* if gpnvm[1] == 0 */
1192  /* boot is via "SAMBA" (rom) */
1193  /* else */
1194  /* boot is via FLASH */
1195  /* Selection is via gpnvm[2] */
1196  /* endif */
1197  /* */
1198  /* NOTE: banks 0 & 1 switch places */
1199  /* if gpnvm[2] == 0 */
1200  /* Bank0 is the boot rom */
1201  /* else */
1202  /* Bank1 is the boot rom */
1203  /* endif */
1204 /* .bank[0] = { */
1205  {
1206  {
1207  .probed = false,
1208  .chip = NULL,
1209  .bank = NULL,
1210  .bank_number = 0,
1211  .base_address = FLASH_BANK_BASE_N,
1212  .controller_address = 0x400e0A00,
1213  .flash_wait_states = 6, /* workaround silicon bug */
1214  .present = 1,
1215  .size_bytes = 128 * 1024,
1216  .nsectors = 8,
1217  .sector_size = 16384,
1218  .page_size = 256,
1219  },
1220 
1221 /* .bank[1] = { */
1222  {
1223  .present = 0,
1224  .probed = false,
1225  .bank_number = 1,
1226  },
1227  },
1228  },
1229 
1230  {
1231  .chipid_cidr = 0x29490760,
1232  .name = "at91sam3n2b",
1233  .total_flash_size = 128 * 1024,
1234  .total_sram_size = 16 * 1024,
1235  .n_gpnvms = 3,
1236  .n_banks = 1,
1237 
1238  /* System boots at address 0x0 */
1239  /* gpnvm[1] = selects boot code */
1240  /* if gpnvm[1] == 0 */
1241  /* boot is via "SAMBA" (rom) */
1242  /* else */
1243  /* boot is via FLASH */
1244  /* Selection is via gpnvm[2] */
1245  /* endif */
1246  /* */
1247  /* NOTE: banks 0 & 1 switch places */
1248  /* if gpnvm[2] == 0 */
1249  /* Bank0 is the boot rom */
1250  /* else */
1251  /* Bank1 is the boot rom */
1252  /* endif */
1253 /* .bank[0] = { */
1254  {
1255  {
1256  .probed = false,
1257  .chip = NULL,
1258  .bank = NULL,
1259  .bank_number = 0,
1260  .base_address = FLASH_BANK_BASE_N,
1261  .controller_address = 0x400e0A00,
1262  .flash_wait_states = 6, /* workaround silicon bug */
1263  .present = 1,
1264  .size_bytes = 128 * 1024,
1265  .nsectors = 8,
1266  .sector_size = 16384,
1267  .page_size = 256,
1268  },
1269 
1270 /* .bank[1] = { */
1271  {
1272  .present = 0,
1273  .probed = false,
1274  .bank_number = 1,
1275  },
1276  },
1277  },
1278 
1279  {
1280  .chipid_cidr = 0x29390760,
1281  .name = "at91sam3n2a",
1282  .total_flash_size = 128 * 1024,
1283  .total_sram_size = 16 * 1024,
1284  .n_gpnvms = 3,
1285  .n_banks = 1,
1286 
1287  /* System boots at address 0x0 */
1288  /* gpnvm[1] = selects boot code */
1289  /* if gpnvm[1] == 0 */
1290  /* boot is via "SAMBA" (rom) */
1291  /* else */
1292  /* boot is via FLASH */
1293  /* Selection is via gpnvm[2] */
1294  /* endif */
1295  /* */
1296  /* NOTE: banks 0 & 1 switch places */
1297  /* if gpnvm[2] == 0 */
1298  /* Bank0 is the boot rom */
1299  /* else */
1300  /* Bank1 is the boot rom */
1301  /* endif */
1302 /* .bank[0] = { */
1303  {
1304  {
1305  .probed = false,
1306  .chip = NULL,
1307  .bank = NULL,
1308  .bank_number = 0,
1309  .base_address = FLASH_BANK_BASE_N,
1310  .controller_address = 0x400e0A00,
1311  .flash_wait_states = 6, /* workaround silicon bug */
1312  .present = 1,
1313  .size_bytes = 128 * 1024,
1314  .nsectors = 8,
1315  .sector_size = 16384,
1316  .page_size = 256,
1317  },
1318 
1319 /* .bank[1] = { */
1320  {
1321  .present = 0,
1322  .probed = false,
1323  .bank_number = 1,
1324  },
1325  },
1326  },
1327 
1328  {
1329  .chipid_cidr = 0x29580560,
1330  .name = "at91sam3n1c",
1331  .total_flash_size = 64 * 1024,
1332  .total_sram_size = 8 * 1024,
1333  .n_gpnvms = 3,
1334  .n_banks = 1,
1335 
1336  /* System boots at address 0x0 */
1337  /* gpnvm[1] = selects boot code */
1338  /* if gpnvm[1] == 0 */
1339  /* boot is via "SAMBA" (rom) */
1340  /* else */
1341  /* boot is via FLASH */
1342  /* Selection is via gpnvm[2] */
1343  /* endif */
1344  /* */
1345  /* NOTE: banks 0 & 1 switch places */
1346  /* if gpnvm[2] == 0 */
1347  /* Bank0 is the boot rom */
1348  /* else */
1349  /* Bank1 is the boot rom */
1350  /* endif */
1351 /* .bank[0] = { */
1352  {
1353  {
1354  .probed = false,
1355  .chip = NULL,
1356  .bank = NULL,
1357  .bank_number = 0,
1358  .base_address = FLASH_BANK_BASE_N,
1359  .controller_address = 0x400e0A00,
1360  .flash_wait_states = 6, /* workaround silicon bug */
1361  .present = 1,
1362  .size_bytes = 64 * 1024,
1363  .nsectors = 4,
1364  .sector_size = 16384,
1365  .page_size = 256,
1366  },
1367 
1368 /* .bank[1] = { */
1369  {
1370  .present = 0,
1371  .probed = false,
1372  .bank_number = 1,
1373  },
1374  },
1375  },
1376 
1377  {
1378  .chipid_cidr = 0x29480560,
1379  .name = "at91sam3n1b",
1380  .total_flash_size = 64 * 1024,
1381  .total_sram_size = 8 * 1024,
1382  .n_gpnvms = 3,
1383  .n_banks = 1,
1384 
1385  /* System boots at address 0x0 */
1386  /* gpnvm[1] = selects boot code */
1387  /* if gpnvm[1] == 0 */
1388  /* boot is via "SAMBA" (rom) */
1389  /* else */
1390  /* boot is via FLASH */
1391  /* Selection is via gpnvm[2] */
1392  /* endif */
1393  /* */
1394  /* NOTE: banks 0 & 1 switch places */
1395  /* if gpnvm[2] == 0 */
1396  /* Bank0 is the boot rom */
1397  /* else */
1398  /* Bank1 is the boot rom */
1399  /* endif */
1400 /* .bank[0] = { */
1401  {
1402  {
1403  .probed = false,
1404  .chip = NULL,
1405  .bank = NULL,
1406  .bank_number = 0,
1407  .base_address = FLASH_BANK_BASE_N,
1408  .controller_address = 0x400e0A00,
1409  .flash_wait_states = 6, /* workaround silicon bug */
1410  .present = 1,
1411  .size_bytes = 64 * 1024,
1412  .nsectors = 4,
1413  .sector_size = 16384,
1414  .page_size = 256,
1415  },
1416 
1417 /* .bank[1] = { */
1418  {
1419  .present = 0,
1420  .probed = false,
1421  .bank_number = 1,
1422  },
1423  },
1424  },
1425 
1426  {
1427  .chipid_cidr = 0x29380560,
1428  .name = "at91sam3n1a",
1429  .total_flash_size = 64 * 1024,
1430  .total_sram_size = 8 * 1024,
1431  .n_gpnvms = 3,
1432  .n_banks = 1,
1433 
1434  /* System boots at address 0x0 */
1435  /* gpnvm[1] = selects boot code */
1436  /* if gpnvm[1] == 0 */
1437  /* boot is via "SAMBA" (rom) */
1438  /* else */
1439  /* boot is via FLASH */
1440  /* Selection is via gpnvm[2] */
1441  /* endif */
1442  /* */
1443  /* NOTE: banks 0 & 1 switch places */
1444  /* if gpnvm[2] == 0 */
1445  /* Bank0 is the boot rom */
1446  /* else */
1447  /* Bank1 is the boot rom */
1448  /* endif */
1449 /* .bank[0] = { */
1450  {
1451  {
1452  .probed = false,
1453  .chip = NULL,
1454  .bank = NULL,
1455  .bank_number = 0,
1456  .base_address = FLASH_BANK_BASE_N,
1457  .controller_address = 0x400e0A00,
1458  .flash_wait_states = 6, /* workaround silicon bug */
1459  .present = 1,
1460  .size_bytes = 64 * 1024,
1461  .nsectors = 4,
1462  .sector_size = 16384,
1463  .page_size = 256,
1464  },
1465 
1466 /* .bank[1] = { */
1467  {
1468  .present = 0,
1469  .probed = false,
1470  .bank_number = 1,
1471  },
1472  },
1473  },
1474 
1475  {
1476  .chipid_cidr = 0x29480360,
1477  .name = "at91sam3n0b",
1478  .total_flash_size = 32 * 1024,
1479  .total_sram_size = 8 * 1024,
1480  .n_gpnvms = 3,
1481  .n_banks = 1,
1482 
1483 /* .bank[0] = { */
1484  {
1485  {
1486  .probed = false,
1487  .chip = NULL,
1488  .bank = NULL,
1489  .bank_number = 0,
1490  .base_address = FLASH_BANK_BASE_N,
1491  .controller_address = 0x400e0A00,
1492  .flash_wait_states = 6, /* workaround silicon bug */
1493  .present = 1,
1494  .size_bytes = 32 * 1024,
1495  .nsectors = 2,
1496  .sector_size = 16384,
1497  .page_size = 256,
1498  },
1499 
1500 /* .bank[1] = { */
1501  {
1502  .present = 0,
1503  .probed = false,
1504  .bank_number = 1,
1505  },
1506  },
1507  },
1508 
1509  {
1510  .chipid_cidr = 0x29380360,
1511  .name = "at91sam3n0a",
1512  .total_flash_size = 32 * 1024,
1513  .total_sram_size = 8 * 1024,
1514  .n_gpnvms = 3,
1515  .n_banks = 1,
1516 
1517 /* .bank[0] = { */
1518  {
1519  {
1520  .probed = false,
1521  .chip = NULL,
1522  .bank = NULL,
1523  .bank_number = 0,
1524  .base_address = FLASH_BANK_BASE_N,
1525  .controller_address = 0x400e0A00,
1526  .flash_wait_states = 6, /* workaround silicon bug */
1527  .present = 1,
1528  .size_bytes = 32 * 1024,
1529  .nsectors = 2,
1530  .sector_size = 16384,
1531  .page_size = 256,
1532  },
1533 
1534 /* .bank[1] = { */
1535  {
1536  .present = 0,
1537  .probed = false,
1538  .bank_number = 1,
1539  },
1540  },
1541  },
1542 
1543  {
1544  .chipid_cidr = 0x29450260,
1545  .name = "at91sam3n00b",
1546  .total_flash_size = 16 * 1024,
1547  .total_sram_size = 4 * 1024,
1548  .n_gpnvms = 3,
1549  .n_banks = 1,
1550 
1551 /* .bank[0] = { */
1552  {
1553  {
1554  .probed = false,
1555  .chip = NULL,
1556  .bank = NULL,
1557  .bank_number = 0,
1558  .base_address = FLASH_BANK_BASE_N,
1559  .controller_address = 0x400e0A00,
1560  .flash_wait_states = 6, /* workaround silicon bug */
1561  .present = 1,
1562  .size_bytes = 16 * 1024,
1563  .nsectors = 1,
1564  .sector_size = 16384,
1565  .page_size = 256,
1566  },
1567 
1568 /* .bank[1] = { */
1569  {
1570  .present = 0,
1571  .probed = false,
1572  .bank_number = 1,
1573  },
1574  },
1575  },
1576 
1577  {
1578  .chipid_cidr = 0x29350260,
1579  .name = "at91sam3n00a",
1580  .total_flash_size = 16 * 1024,
1581  .total_sram_size = 4 * 1024,
1582  .n_gpnvms = 3,
1583  .n_banks = 1,
1584 
1585 /* .bank[0] = { */
1586  {
1587  {
1588  .probed = false,
1589  .chip = NULL,
1590  .bank = NULL,
1591  .bank_number = 0,
1592  .base_address = FLASH_BANK_BASE_N,
1593  .controller_address = 0x400e0A00,
1594  .flash_wait_states = 6, /* workaround silicon bug */
1595  .present = 1,
1596  .size_bytes = 16 * 1024,
1597  .nsectors = 1,
1598  .sector_size = 16384,
1599  .page_size = 256,
1600  },
1601 
1602 /* .bank[1] = { */
1603  {
1604  .present = 0,
1605  .probed = false,
1606  .bank_number = 1,
1607  },
1608  },
1609  },
1610 
1611 
1612  /* Start at91sam3a series*/
1613  /* System boots at address 0x0 */
1614  /* gpnvm[1] = selects boot code */
1615  /* if gpnvm[1] == 0 */
1616  /* boot is via "SAMBA" (rom) */
1617  /* else */
1618  /* boot is via FLASH */
1619  /* Selection is via gpnvm[2] */
1620  /* endif */
1621  /* */
1622  /* NOTE: banks 0 & 1 switch places */
1623  /* if gpnvm[2] == 0 */
1624  /* Bank0 is the boot rom */
1625  /* else */
1626  /* Bank1 is the boot rom */
1627  /* endif */
1628 
1629  {
1630  .chipid_cidr = 0x283E0A60,
1631  .name = "at91sam3a8c",
1632  .total_flash_size = 512 * 1024,
1633  .total_sram_size = 96 * 1024,
1634  .n_gpnvms = 3,
1635  .n_banks = 2,
1636  {
1637 /* .bank[0] = { */
1638  {
1639  .probed = false,
1640  .chip = NULL,
1641  .bank = NULL,
1642  .bank_number = 0,
1643  .base_address = FLASH_BANK0_BASE_AX,
1644  .controller_address = 0x400e0a00,
1645  .flash_wait_states = 6, /* workaround silicon bug */
1646  .present = 1,
1647  .size_bytes = 256 * 1024,
1648  .nsectors = 16,
1649  .sector_size = 16384,
1650  .page_size = 256,
1651  },
1652 /* .bank[1] = { */
1653  {
1654  .probed = false,
1655  .chip = NULL,
1656  .bank = NULL,
1657  .bank_number = 1,
1658  .base_address = FLASH_BANK1_BASE_512K_AX,
1659  .controller_address = 0x400e0c00,
1660  .flash_wait_states = 6, /* workaround silicon bug */
1661  .present = 1,
1662  .size_bytes = 256 * 1024,
1663  .nsectors = 16,
1664  .sector_size = 16384,
1665  .page_size = 256,
1666 
1667  },
1668  },
1669  },
1670  {
1671  .chipid_cidr = 0x283B0960,
1672  .name = "at91sam3a4c",
1673  .total_flash_size = 256 * 1024,
1674  .total_sram_size = 64 * 1024,
1675  .n_gpnvms = 3,
1676  .n_banks = 2,
1677  {
1678 /* .bank[0] = { */
1679  {
1680  .probed = false,
1681  .chip = NULL,
1682  .bank = NULL,
1683  .bank_number = 0,
1684  .base_address = FLASH_BANK0_BASE_AX,
1685  .controller_address = 0x400e0a00,
1686  .flash_wait_states = 6, /* workaround silicon bug */
1687  .present = 1,
1688  .size_bytes = 128 * 1024,
1689  .nsectors = 8,
1690  .sector_size = 16384,
1691  .page_size = 256,
1692  },
1693 /* .bank[1] = { */
1694  {
1695  .probed = false,
1696  .chip = NULL,
1697  .bank = NULL,
1698  .bank_number = 1,
1699  .base_address = FLASH_BANK1_BASE_256K_AX,
1700  .controller_address = 0x400e0c00,
1701  .flash_wait_states = 6, /* workaround silicon bug */
1702  .present = 1,
1703  .size_bytes = 128 * 1024,
1704  .nsectors = 8,
1705  .sector_size = 16384,
1706  .page_size = 256,
1707 
1708  },
1709  },
1710  },
1711 
1712  /* Start at91sam3x* series */
1713  /* System boots at address 0x0 */
1714  /* gpnvm[1] = selects boot code */
1715  /* if gpnvm[1] == 0 */
1716  /* boot is via "SAMBA" (rom) */
1717  /* else */
1718  /* boot is via FLASH */
1719  /* Selection is via gpnvm[2] */
1720  /* endif */
1721  /* */
1722  /* NOTE: banks 0 & 1 switch places */
1723  /* if gpnvm[2] == 0 */
1724  /* Bank0 is the boot rom */
1725  /* else */
1726  /* Bank1 is the boot rom */
1727  /* endif */
1728  /*at91sam3x8h - ES has an incorrect CIDR of 0x286E0A20*/
1729  {
1730  .chipid_cidr = 0x286E0A20,
1731  .name = "at91sam3x8h - ES",
1732  .total_flash_size = 512 * 1024,
1733  .total_sram_size = 96 * 1024,
1734  .n_gpnvms = 3,
1735  .n_banks = 2,
1736  {
1737 /* .bank[0] = { */
1738  {
1739  .probed = false,
1740  .chip = NULL,
1741  .bank = NULL,
1742  .bank_number = 0,
1743  .base_address = FLASH_BANK0_BASE_AX,
1744  .controller_address = 0x400e0a00,
1745  .flash_wait_states = 6, /* workaround silicon bug */
1746  .present = 1,
1747  .size_bytes = 256 * 1024,
1748  .nsectors = 16,
1749  .sector_size = 16384,
1750  .page_size = 256,
1751  },
1752 /* .bank[1] = { */
1753  {
1754  .probed = false,
1755  .chip = NULL,
1756  .bank = NULL,
1757  .bank_number = 1,
1758  .base_address = FLASH_BANK1_BASE_512K_AX,
1759  .controller_address = 0x400e0c00,
1760  .flash_wait_states = 6, /* workaround silicon bug */
1761  .present = 1,
1762  .size_bytes = 256 * 1024,
1763  .nsectors = 16,
1764  .sector_size = 16384,
1765  .page_size = 256,
1766 
1767  },
1768  },
1769  },
1770  /*at91sam3x8h - ES2 and up uses the correct CIDR of 0x286E0A60*/
1771  {
1772  .chipid_cidr = 0x286E0A60,
1773  .name = "at91sam3x8h",
1774  .total_flash_size = 512 * 1024,
1775  .total_sram_size = 96 * 1024,
1776  .n_gpnvms = 3,
1777  .n_banks = 2,
1778  {
1779 /* .bank[0] = { */
1780  {
1781  .probed = false,
1782  .chip = NULL,
1783  .bank = NULL,
1784  .bank_number = 0,
1785  .base_address = FLASH_BANK0_BASE_AX,
1786  .controller_address = 0x400e0a00,
1787  .flash_wait_states = 6, /* workaround silicon bug */
1788  .present = 1,
1789  .size_bytes = 256 * 1024,
1790  .nsectors = 16,
1791  .sector_size = 16384,
1792  .page_size = 256,
1793  },
1794 /* .bank[1] = { */
1795  {
1796  .probed = false,
1797  .chip = NULL,
1798  .bank = NULL,
1799  .bank_number = 1,
1800  .base_address = FLASH_BANK1_BASE_512K_AX,
1801  .controller_address = 0x400e0c00,
1802  .flash_wait_states = 6, /* workaround silicon bug */
1803  .present = 1,
1804  .size_bytes = 256 * 1024,
1805  .nsectors = 16,
1806  .sector_size = 16384,
1807  .page_size = 256,
1808 
1809  },
1810  },
1811  },
1812  {
1813  .chipid_cidr = 0x285E0A60,
1814  .name = "at91sam3x8e",
1815  .total_flash_size = 512 * 1024,
1816  .total_sram_size = 96 * 1024,
1817  .n_gpnvms = 3,
1818  .n_banks = 2,
1819  {
1820 /* .bank[0] = { */
1821  {
1822  .probed = false,
1823  .chip = NULL,
1824  .bank = NULL,
1825  .bank_number = 0,
1826  .base_address = FLASH_BANK0_BASE_AX,
1827  .controller_address = 0x400e0a00,
1828  .flash_wait_states = 6, /* workaround silicon bug */
1829  .present = 1,
1830  .size_bytes = 256 * 1024,
1831  .nsectors = 16,
1832  .sector_size = 16384,
1833  .page_size = 256,
1834  },
1835 /* .bank[1] = { */
1836  {
1837  .probed = false,
1838  .chip = NULL,
1839  .bank = NULL,
1840  .bank_number = 1,
1841  .base_address = FLASH_BANK1_BASE_512K_AX,
1842  .controller_address = 0x400e0c00,
1843  .flash_wait_states = 6, /* workaround silicon bug */
1844  .present = 1,
1845  .size_bytes = 256 * 1024,
1846  .nsectors = 16,
1847  .sector_size = 16384,
1848  .page_size = 256,
1849 
1850  },
1851  },
1852  },
1853  {
1854  .chipid_cidr = 0x284E0A60,
1855  .name = "at91sam3x8c",
1856  .total_flash_size = 512 * 1024,
1857  .total_sram_size = 96 * 1024,
1858  .n_gpnvms = 3,
1859  .n_banks = 2,
1860  {
1861 /* .bank[0] = { */
1862  {
1863  .probed = false,
1864  .chip = NULL,
1865  .bank = NULL,
1866  .bank_number = 0,
1867  .base_address = FLASH_BANK0_BASE_AX,
1868  .controller_address = 0x400e0a00,
1869  .flash_wait_states = 6, /* workaround silicon bug */
1870  .present = 1,
1871  .size_bytes = 256 * 1024,
1872  .nsectors = 16,
1873  .sector_size = 16384,
1874  .page_size = 256,
1875  },
1876 /* .bank[1] = { */
1877  {
1878  .probed = false,
1879  .chip = NULL,
1880  .bank = NULL,
1881  .bank_number = 1,
1882  .base_address = FLASH_BANK1_BASE_512K_AX,
1883  .controller_address = 0x400e0c00,
1884  .flash_wait_states = 6, /* workaround silicon bug */
1885  .present = 1,
1886  .size_bytes = 256 * 1024,
1887  .nsectors = 16,
1888  .sector_size = 16384,
1889  .page_size = 256,
1890 
1891  },
1892  },
1893  },
1894  {
1895  .chipid_cidr = 0x285B0960,
1896  .name = "at91sam3x4e",
1897  .total_flash_size = 256 * 1024,
1898  .total_sram_size = 64 * 1024,
1899  .n_gpnvms = 3,
1900  .n_banks = 2,
1901  {
1902 /* .bank[0] = { */
1903  {
1904  .probed = false,
1905  .chip = NULL,
1906  .bank = NULL,
1907  .bank_number = 0,
1908  .base_address = FLASH_BANK0_BASE_AX,
1909  .controller_address = 0x400e0a00,
1910  .flash_wait_states = 6, /* workaround silicon bug */
1911  .present = 1,
1912  .size_bytes = 128 * 1024,
1913  .nsectors = 8,
1914  .sector_size = 16384,
1915  .page_size = 256,
1916  },
1917 /* .bank[1] = { */
1918  {
1919  .probed = false,
1920  .chip = NULL,
1921  .bank = NULL,
1922  .bank_number = 1,
1923  .base_address = FLASH_BANK1_BASE_256K_AX,
1924  .controller_address = 0x400e0c00,
1925  .flash_wait_states = 6, /* workaround silicon bug */
1926  .present = 1,
1927  .size_bytes = 128 * 1024,
1928  .nsectors = 8,
1929  .sector_size = 16384,
1930  .page_size = 256,
1931 
1932  },
1933  },
1934  },
1935  {
1936  .chipid_cidr = 0x284B0960,
1937  .name = "at91sam3x4c",
1938  .total_flash_size = 256 * 1024,
1939  .total_sram_size = 64 * 1024,
1940  .n_gpnvms = 3,
1941  .n_banks = 2,
1942  {
1943 /* .bank[0] = { */
1944  {
1945  .probed = false,
1946  .chip = NULL,
1947  .bank = NULL,
1948  .bank_number = 0,
1949  .base_address = FLASH_BANK0_BASE_AX,
1950  .controller_address = 0x400e0a00,
1951  .flash_wait_states = 6, /* workaround silicon bug */
1952  .present = 1,
1953  .size_bytes = 128 * 1024,
1954  .nsectors = 8,
1955  .sector_size = 16384,
1956  .page_size = 256,
1957  },
1958 /* .bank[1] = { */
1959  {
1960  .probed = false,
1961  .chip = NULL,
1962  .bank = NULL,
1963  .bank_number = 1,
1964  .base_address = FLASH_BANK1_BASE_256K_AX,
1965  .controller_address = 0x400e0c00,
1966  .flash_wait_states = 6, /* workaround silicon bug */
1967  .present = 1,
1968  .size_bytes = 128 * 1024,
1969  .nsectors = 8,
1970  .sector_size = 16384,
1971  .page_size = 256,
1972 
1973  },
1974  },
1975  },
1976  /* terminate */
1977  {
1978  .chipid_cidr = 0,
1979  .name = NULL,
1980  }
1981 };
1982 
1983 /* Globals above */
1984 /***********************************************************************
1985  **********************************************************************
1986  **********************************************************************
1987  **********************************************************************
1988  **********************************************************************
1989  **********************************************************************/
1990 /* *ATMEL* style code - from the SAM3 driver code */
1991 
1998 static int efc_get_status(struct sam3_bank_private *private, uint32_t *v)
1999 {
2000  int r;
2001  r = target_read_u32(private->chip->target,
2002  private->controller_address + OFFSET_EFC_FSR,
2003  v);
2004  LOG_DEBUG("Status: 0x%08x (lockerror: %d, cmderror: %d, ready: %d)",
2005  (unsigned int)(*v),
2006  ((unsigned int)((*v >> 2) & 1)),
2007  ((unsigned int)((*v >> 1) & 1)),
2008  ((unsigned int)((*v >> 0) & 1)));
2009 
2010  return r;
2011 }
2012 
2018 static int efc_get_result(struct sam3_bank_private *private, uint32_t *v)
2019 {
2020  int r;
2021  uint32_t rv;
2022  r = target_read_u32(private->chip->target,
2023  private->controller_address + OFFSET_EFC_FRR,
2024  &rv);
2025  if (v)
2026  *v = rv;
2027  LOG_DEBUG("Result: 0x%08x", ((unsigned int)(rv)));
2028  return r;
2029 }
2030 
2031 static int efc_start_command(struct sam3_bank_private *private,
2032  unsigned int command, unsigned int argument)
2033 {
2034  uint32_t n, v;
2035  int r;
2036  int retry;
2037 
2038  retry = 0;
2039 do_retry:
2040 
2041  /* Check command & argument */
2042  switch (command) {
2043 
2044  case AT91C_EFC_FCMD_WP:
2045  case AT91C_EFC_FCMD_WPL:
2046  case AT91C_EFC_FCMD_EWP:
2047  case AT91C_EFC_FCMD_EWPL:
2048  /* case AT91C_EFC_FCMD_EPL: */
2049  /* case AT91C_EFC_FCMD_EPA: */
2050  case AT91C_EFC_FCMD_SLB:
2051  case AT91C_EFC_FCMD_CLB:
2052  n = (private->size_bytes / private->page_size);
2053  if (argument >= n)
2054  LOG_ERROR("*BUG*: Embedded flash has only %" PRIu32 " pages", n);
2055  break;
2056 
2057  case AT91C_EFC_FCMD_SFB:
2058  case AT91C_EFC_FCMD_CFB:
2059  if (argument >= private->chip->details.n_gpnvms) {
2060  LOG_ERROR("*BUG*: Embedded flash has only %d GPNVMs",
2061  private->chip->details.n_gpnvms);
2062  }
2063  break;
2064 
2065  case AT91C_EFC_FCMD_GETD:
2066  case AT91C_EFC_FCMD_EA:
2067  case AT91C_EFC_FCMD_GLB:
2068  case AT91C_EFC_FCMD_GFB:
2069  case AT91C_EFC_FCMD_STUI:
2070  case AT91C_EFC_FCMD_SPUI:
2071  if (argument != 0)
2072  LOG_ERROR("Argument is meaningless for cmd: %d", command);
2073  break;
2074  default:
2075  LOG_ERROR("Unknown command %d", command);
2076  break;
2077  }
2078 
2079  if (command == AT91C_EFC_FCMD_SPUI) {
2080  /* this is a very special situation. */
2081  /* Situation (1) - error/retry - see below */
2082  /* And we are being called recursively */
2083  /* Situation (2) - normal, finished reading unique id */
2084  } else {
2085  /* it should be "ready" */
2086  efc_get_status(private, &v);
2087  if (v & 1) {
2088  /* then it is ready */
2089  /* we go on */
2090  } else {
2091  if (retry) {
2092  /* we have done this before */
2093  /* the controller is not responding. */
2094  LOG_ERROR("flash controller(%d) is not ready! Error",
2095  private->bank_number);
2096  return ERROR_FAIL;
2097  } else {
2098  retry++;
2099  LOG_ERROR("Flash controller(%d) is not ready, attempting reset",
2100  private->bank_number);
2101  /* we do that by issuing the *STOP* command */
2102  efc_start_command(private, AT91C_EFC_FCMD_SPUI, 0);
2103  /* above is recursive, and further recursion is blocked by */
2104  /* if (command == AT91C_EFC_FCMD_SPUI) above */
2105  goto do_retry;
2106  }
2107  }
2108  }
2109 
2110  v = (0x5A << 24) | (argument << 8) | command;
2111  LOG_DEBUG("Command: 0x%08x", ((unsigned int)(v)));
2112  r = target_write_u32(private->bank->target,
2113  private->controller_address + OFFSET_EFC_FCR, v);
2114  if (r != ERROR_OK)
2115  LOG_DEBUG("Error Write failed");
2116  return r;
2117 }
2118 
2126 static int efc_perform_command(struct sam3_bank_private *private,
2127  unsigned int command,
2128  unsigned int argument,
2129  uint32_t *status)
2130 {
2131 
2132  int r;
2133  uint32_t v;
2134  int64_t ms_now, ms_end;
2135 
2136  /* default */
2137  if (status)
2138  *status = 0;
2139 
2140  r = efc_start_command(private, command, argument);
2141  if (r != ERROR_OK)
2142  return r;
2143 
2144  ms_end = 500 + timeval_ms();
2145 
2146  do {
2147  r = efc_get_status(private, &v);
2148  if (r != ERROR_OK)
2149  return r;
2150  ms_now = timeval_ms();
2151  if (ms_now > ms_end) {
2152  /* error */
2153  LOG_ERROR("Command timeout");
2154  return ERROR_FAIL;
2155  }
2156  } while ((v & 1) == 0);
2157 
2158  /* error bits.. */
2159  if (status)
2160  *status = (v & 0x6);
2161  return ERROR_OK;
2162 
2163 }
2164 
2170 static int flashd_read_uid(struct sam3_bank_private *private)
2171 {
2172  int r;
2173  uint32_t v;
2174  int x;
2175  /* assume 0 */
2176  private->chip->cfg.unique_id[0] = 0;
2177  private->chip->cfg.unique_id[1] = 0;
2178  private->chip->cfg.unique_id[2] = 0;
2179  private->chip->cfg.unique_id[3] = 0;
2180 
2181  LOG_DEBUG("Begin");
2182  r = efc_start_command(private, AT91C_EFC_FCMD_STUI, 0);
2183  if (r < 0)
2184  return r;
2185 
2186  for (x = 0; x < 4; x++) {
2187  r = target_read_u32(private->chip->target,
2188  private->bank->base + (x * 4),
2189  &v);
2190  if (r < 0)
2191  return r;
2192  private->chip->cfg.unique_id[x] = v;
2193  }
2194 
2195  r = efc_perform_command(private, AT91C_EFC_FCMD_SPUI, 0, NULL);
2196  LOG_DEBUG("End: R=%d, id = 0x%08x, 0x%08x, 0x%08x, 0x%08x",
2197  r,
2198  (unsigned int)(private->chip->cfg.unique_id[0]),
2199  (unsigned int)(private->chip->cfg.unique_id[1]),
2200  (unsigned int)(private->chip->cfg.unique_id[2]),
2201  (unsigned int)(private->chip->cfg.unique_id[3]));
2202  return r;
2203 
2204 }
2205 
2210 static int flashd_erase_entire_bank(struct sam3_bank_private *private)
2211 {
2212  LOG_DEBUG("Here");
2213  return efc_perform_command(private, AT91C_EFC_FCMD_EA, 0, NULL);
2214 }
2215 
2222 /* ------------------------------------------------------------------------------ */
2223 static int flashd_get_gpnvm(struct sam3_bank_private *private, unsigned int gpnvm, unsigned int *puthere)
2224 {
2225  uint32_t v;
2226  int r;
2227 
2228  LOG_DEBUG("Here");
2229  if (private->bank_number != 0) {
2230  LOG_ERROR("GPNVM only works with Bank0");
2231  return ERROR_FAIL;
2232  }
2233 
2234  if (gpnvm >= private->chip->details.n_gpnvms) {
2235  LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
2236  gpnvm, private->chip->details.n_gpnvms);
2237  return ERROR_FAIL;
2238  }
2239 
2240  /* Get GPNVMs status */
2241  r = efc_perform_command(private, AT91C_EFC_FCMD_GFB, 0, NULL);
2242  if (r != ERROR_OK) {
2243  LOG_ERROR("Failed");
2244  return r;
2245  }
2246 
2247  r = efc_get_result(private, &v);
2248 
2249  if (puthere) {
2250  /* Check if GPNVM is set */
2251  /* get the bit and make it a 0/1 */
2252  *puthere = (v >> gpnvm) & 1;
2253  }
2254 
2255  return r;
2256 }
2257 
2264 static int flashd_clr_gpnvm(struct sam3_bank_private *private, unsigned int gpnvm)
2265 {
2266  int r;
2267  unsigned int v;
2268 
2269  LOG_DEBUG("Here");
2270  if (private->bank_number != 0) {
2271  LOG_ERROR("GPNVM only works with Bank0");
2272  return ERROR_FAIL;
2273  }
2274 
2275  if (gpnvm >= private->chip->details.n_gpnvms) {
2276  LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
2277  gpnvm, private->chip->details.n_gpnvms);
2278  return ERROR_FAIL;
2279  }
2280 
2281  r = flashd_get_gpnvm(private, gpnvm, &v);
2282  if (r != ERROR_OK) {
2283  LOG_DEBUG("Failed: %d", r);
2284  return r;
2285  }
2286  r = efc_perform_command(private, AT91C_EFC_FCMD_CFB, gpnvm, NULL);
2287  LOG_DEBUG("End: %d", r);
2288  return r;
2289 }
2290 
2296 static int flashd_set_gpnvm(struct sam3_bank_private *private, unsigned int gpnvm)
2297 {
2298  int r;
2299  unsigned int v;
2300 
2301  if (private->bank_number != 0) {
2302  LOG_ERROR("GPNVM only works with Bank0");
2303  return ERROR_FAIL;
2304  }
2305 
2306  if (gpnvm >= private->chip->details.n_gpnvms) {
2307  LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
2308  gpnvm, private->chip->details.n_gpnvms);
2309  return ERROR_FAIL;
2310  }
2311 
2312  r = flashd_get_gpnvm(private, gpnvm, &v);
2313  if (r != ERROR_OK)
2314  return r;
2315  if (v) {
2316  /* already set */
2317  r = ERROR_OK;
2318  } else {
2319  /* set it */
2320  r = efc_perform_command(private, AT91C_EFC_FCMD_SFB, gpnvm, NULL);
2321  }
2322  return r;
2323 }
2324 
2330 static int flashd_get_lock_bits(struct sam3_bank_private *private, uint32_t *v)
2331 {
2332  int r;
2333  LOG_DEBUG("Here");
2334  r = efc_perform_command(private, AT91C_EFC_FCMD_GLB, 0, NULL);
2335  if (r == ERROR_OK)
2336  r = efc_get_result(private, v);
2337  LOG_DEBUG("End: %d", r);
2338  return r;
2339 }
2340 
2348 static int flashd_unlock(struct sam3_bank_private *private,
2349  unsigned int start_sector,
2350  unsigned int end_sector)
2351 {
2352  int r;
2353  uint32_t status;
2354  uint32_t pg;
2355  uint32_t pages_per_sector;
2356 
2357  pages_per_sector = private->sector_size / private->page_size;
2358 
2359  /* Unlock all pages */
2360  while (start_sector <= end_sector) {
2361  pg = start_sector * pages_per_sector;
2362 
2363  r = efc_perform_command(private, AT91C_EFC_FCMD_CLB, pg, &status);
2364  if (r != ERROR_OK)
2365  return r;
2366  start_sector++;
2367  }
2368 
2369  return ERROR_OK;
2370 }
2371 
2378 static int flashd_lock(struct sam3_bank_private *private,
2379  unsigned int start_sector,
2380  unsigned int end_sector)
2381 {
2382  uint32_t status;
2383  uint32_t pg;
2384  uint32_t pages_per_sector;
2385  int r;
2386 
2387  pages_per_sector = private->sector_size / private->page_size;
2388 
2389  /* Lock all pages */
2390  while (start_sector <= end_sector) {
2391  pg = start_sector * pages_per_sector;
2392 
2393  r = efc_perform_command(private, AT91C_EFC_FCMD_SLB, pg, &status);
2394  if (r != ERROR_OK)
2395  return r;
2396  start_sector++;
2397  }
2398  return ERROR_OK;
2399 }
2400 
2401 /****** END SAM3 CODE ********/
2402 
2403 /* begin helpful debug code */
2404 /* print the fieldname, the field value, in dec & hex, and return field value */
2405 static uint32_t sam3_reg_fieldname(struct sam3_chip *chip,
2406  const char *regname,
2407  uint32_t value,
2408  unsigned int shift,
2409  unsigned int width)
2410 {
2411  uint32_t v;
2412  int hwidth, dwidth;
2413 
2414 
2415  /* extract the field */
2416  v = value >> shift;
2417  v = v & ((1 << width)-1);
2418  if (width <= 16) {
2419  hwidth = 4;
2420  dwidth = 5;
2421  } else {
2422  hwidth = 8;
2423  dwidth = 12;
2424  }
2425 
2426  /* show the basics */
2427  LOG_USER_N("\t%*s: %*" PRIu32 " [0x%0*" PRIx32 "] ",
2428  REG_NAME_WIDTH, regname,
2429  dwidth, v,
2430  hwidth, v);
2431  return v;
2432 }
2433 
2434 static const char _unknown[] = "unknown";
2435 static const char *const eproc_names[] = {
2436  _unknown, /* 0 */
2437  "arm946es", /* 1 */
2438  "arm7tdmi", /* 2 */
2439  "Cortex-M3", /* 3 */
2440  "arm920t", /* 4 */
2441  "arm926ejs", /* 5 */
2442  _unknown, /* 6 */
2443  _unknown, /* 7 */
2444  _unknown, /* 8 */
2445  _unknown, /* 9 */
2446  _unknown, /* 10 */
2447  _unknown, /* 11 */
2448  _unknown, /* 12 */
2449  _unknown, /* 13 */
2450  _unknown, /* 14 */
2451  _unknown, /* 15 */
2452 };
2453 
2454 #define nvpsize2 nvpsize /* these two tables are identical */
2455 static const char *const nvpsize[] = {
2456  "none", /* 0 */
2457  "8K bytes", /* 1 */
2458  "16K bytes", /* 2 */
2459  "32K bytes", /* 3 */
2460  _unknown, /* 4 */
2461  "64K bytes", /* 5 */
2462  _unknown, /* 6 */
2463  "128K bytes", /* 7 */
2464  _unknown, /* 8 */
2465  "256K bytes", /* 9 */
2466  "512K bytes", /* 10 */
2467  _unknown, /* 11 */
2468  "1024K bytes", /* 12 */
2469  _unknown, /* 13 */
2470  "2048K bytes", /* 14 */
2471  _unknown, /* 15 */
2472 };
2473 
2474 static const char *const sramsize[] = {
2475  "48K Bytes", /* 0 */
2476  "1K Bytes", /* 1 */
2477  "2K Bytes", /* 2 */
2478  "6K Bytes", /* 3 */
2479  "112K Bytes", /* 4 */
2480  "4K Bytes", /* 5 */
2481  "80K Bytes", /* 6 */
2482  "160K Bytes", /* 7 */
2483  "8K Bytes", /* 8 */
2484  "16K Bytes", /* 9 */
2485  "32K Bytes", /* 10 */
2486  "64K Bytes", /* 11 */
2487  "128K Bytes", /* 12 */
2488  "256K Bytes", /* 13 */
2489  "96K Bytes", /* 14 */
2490  "512K Bytes", /* 15 */
2491 
2492 };
2493 
2494 static const struct archnames { unsigned int value; const char *name; } archnames[] = {
2495  { 0x19, "AT91SAM9xx Series" },
2496  { 0x29, "AT91SAM9XExx Series" },
2497  { 0x34, "AT91x34 Series" },
2498  { 0x37, "CAP7 Series" },
2499  { 0x39, "CAP9 Series" },
2500  { 0x3B, "CAP11 Series" },
2501  { 0x40, "AT91x40 Series" },
2502  { 0x42, "AT91x42 Series" },
2503  { 0x55, "AT91x55 Series" },
2504  { 0x60, "AT91SAM7Axx Series" },
2505  { 0x61, "AT91SAM7AQxx Series" },
2506  { 0x63, "AT91x63 Series" },
2507  { 0x70, "AT91SAM7Sxx Series" },
2508  { 0x71, "AT91SAM7XCxx Series" },
2509  { 0x72, "AT91SAM7SExx Series" },
2510  { 0x73, "AT91SAM7Lxx Series" },
2511  { 0x75, "AT91SAM7Xxx Series" },
2512  { 0x76, "AT91SAM7SLxx Series" },
2513  { 0x80, "ATSAM3UxC Series (100-pin version)" },
2514  { 0x81, "ATSAM3UxE Series (144-pin version)" },
2515  { 0x83, "ATSAM3AxC Series (100-pin version)" },
2516  { 0x84, "ATSAM3XxC Series (100-pin version)" },
2517  { 0x85, "ATSAM3XxE Series (144-pin version)" },
2518  { 0x86, "ATSAM3XxG Series (208/217-pin version)" },
2519  { 0x88, "ATSAM3SxA Series (48-pin version)" },
2520  { 0x89, "ATSAM3SxB Series (64-pin version)" },
2521  { 0x8A, "ATSAM3SxC Series (100-pin version)" },
2522  { 0x92, "AT91x92 Series" },
2523  { 0x93, "ATSAM3NxA Series (48-pin version)" },
2524  { 0x94, "ATSAM3NxB Series (64-pin version)" },
2525  { 0x95, "ATSAM3NxC Series (100-pin version)" },
2526  { 0x98, "ATSAM3SDxA Series (48-pin version)" },
2527  { 0x99, "ATSAM3SDxB Series (64-pin version)" },
2528  { 0x9A, "ATSAM3SDxC Series (100-pin version)" },
2529  { 0xA5, "ATSAM5A" },
2530  { 0xF0, "AT75Cxx Series" },
2531  { -1, NULL },
2532 };
2533 
2534 static const char *const nvptype[] = {
2535  "rom", /* 0 */
2536  "romless or onchip flash", /* 1 */
2537  "embedded flash memory",/* 2 */
2538  "rom(nvpsiz) + embedded flash (nvpsiz2)", /* 3 */
2539  "sram emulating flash", /* 4 */
2540  _unknown, /* 5 */
2541  _unknown, /* 6 */
2542  _unknown, /* 7 */
2543 };
2544 
2545 static const char *_yes_or_no(uint32_t v)
2546 {
2547  if (v)
2548  return "YES";
2549  else
2550  return "NO";
2551 }
2552 
2553 static const char *const _rc_freq[] = {
2554  "4 MHz", "8 MHz", "12 MHz", "reserved"
2555 };
2556 
2557 static void sam3_explain_ckgr_mor(struct sam3_chip *chip)
2558 {
2559  uint32_t v;
2560  uint32_t rcen;
2561 
2562  v = sam3_reg_fieldname(chip, "MOSCXTEN", chip->cfg.CKGR_MOR, 0, 1);
2563  LOG_USER("(main xtal enabled: %s)", _yes_or_no(v));
2564  v = sam3_reg_fieldname(chip, "MOSCXTBY", chip->cfg.CKGR_MOR, 1, 1);
2565  LOG_USER("(main osc bypass: %s)", _yes_or_no(v));
2566  rcen = sam3_reg_fieldname(chip, "MOSCRCEN", chip->cfg.CKGR_MOR, 3, 1);
2567  LOG_USER("(onchip RC-OSC enabled: %s)", _yes_or_no(rcen));
2568  v = sam3_reg_fieldname(chip, "MOSCRCF", chip->cfg.CKGR_MOR, 4, 3);
2569  LOG_USER("(onchip RC-OSC freq: %s)", _rc_freq[v]);
2570 
2571  chip->cfg.rc_freq = 0;
2572  if (rcen) {
2573  switch (v) {
2574  default:
2575  chip->cfg.rc_freq = 0;
2576  break;
2577  case 0:
2578  chip->cfg.rc_freq = 4 * 1000 * 1000;
2579  break;
2580  case 1:
2581  chip->cfg.rc_freq = 8 * 1000 * 1000;
2582  break;
2583  case 2:
2584  chip->cfg.rc_freq = 12 * 1000 * 1000;
2585  break;
2586  }
2587  }
2588 
2589  v = sam3_reg_fieldname(chip, "MOSCXTST", chip->cfg.CKGR_MOR, 8, 8);
2590  LOG_USER("(startup clks, time= %f uSecs)",
2591  ((float)(v * 1000000)) / ((float)(chip->cfg.slow_freq)));
2592  v = sam3_reg_fieldname(chip, "MOSCSEL", chip->cfg.CKGR_MOR, 24, 1);
2593  LOG_USER("(mainosc source: %s)",
2594  v ? "external xtal" : "internal RC");
2595 
2596  v = sam3_reg_fieldname(chip, "CFDEN", chip->cfg.CKGR_MOR, 25, 1);
2597  LOG_USER("(clock failure enabled: %s)",
2598  _yes_or_no(v));
2599 }
2600 
2601 static void sam3_explain_chipid_cidr(struct sam3_chip *chip)
2602 {
2603  int x;
2604  uint32_t v;
2605  const char *cp;
2606 
2607  sam3_reg_fieldname(chip, "Version", chip->cfg.CHIPID_CIDR, 0, 5);
2608  LOG_USER_N("\n");
2609 
2610  v = sam3_reg_fieldname(chip, "EPROC", chip->cfg.CHIPID_CIDR, 5, 3);
2611  LOG_USER("%s", eproc_names[v]);
2612 
2613  v = sam3_reg_fieldname(chip, "NVPSIZE", chip->cfg.CHIPID_CIDR, 8, 4);
2614  LOG_USER("%s", nvpsize[v]);
2615 
2616  v = sam3_reg_fieldname(chip, "NVPSIZE2", chip->cfg.CHIPID_CIDR, 12, 4);
2617  LOG_USER("%s", nvpsize2[v]);
2618 
2619  v = sam3_reg_fieldname(chip, "SRAMSIZE", chip->cfg.CHIPID_CIDR, 16, 4);
2620  LOG_USER("%s", sramsize[v]);
2621 
2622  v = sam3_reg_fieldname(chip, "ARCH", chip->cfg.CHIPID_CIDR, 20, 8);
2623  cp = _unknown;
2624  for (x = 0; archnames[x].name; x++) {
2625  if (v == archnames[x].value) {
2626  cp = archnames[x].name;
2627  break;
2628  }
2629  }
2630 
2631  LOG_USER("%s", cp);
2632 
2633  v = sam3_reg_fieldname(chip, "NVPTYP", chip->cfg.CHIPID_CIDR, 28, 3);
2634  LOG_USER("%s", nvptype[v]);
2635 
2636  v = sam3_reg_fieldname(chip, "EXTID", chip->cfg.CHIPID_CIDR, 31, 1);
2637  LOG_USER("(exists: %s)", _yes_or_no(v));
2638 }
2639 
2640 static void sam3_explain_ckgr_mcfr(struct sam3_chip *chip)
2641 {
2642  uint32_t v;
2643 
2644  v = sam3_reg_fieldname(chip, "MAINFRDY", chip->cfg.CKGR_MCFR, 16, 1);
2645  LOG_USER("(main ready: %s)", _yes_or_no(v));
2646 
2647  v = sam3_reg_fieldname(chip, "MAINF", chip->cfg.CKGR_MCFR, 0, 16);
2648 
2649  v = (v * chip->cfg.slow_freq) / 16;
2650  chip->cfg.mainosc_freq = v;
2651 
2652  LOG_USER("(%3.03f Mhz (%" PRIu32 ".%03" PRIu32 "khz slowclk)",
2653  _tomhz(v),
2654  (uint32_t)(chip->cfg.slow_freq / 1000),
2655  (uint32_t)(chip->cfg.slow_freq % 1000));
2656 }
2657 
2658 static void sam3_explain_ckgr_plla(struct sam3_chip *chip)
2659 {
2660  uint32_t mula, diva;
2661 
2662  diva = sam3_reg_fieldname(chip, "DIVA", chip->cfg.CKGR_PLLAR, 0, 8);
2663  LOG_USER_N("\n");
2664  mula = sam3_reg_fieldname(chip, "MULA", chip->cfg.CKGR_PLLAR, 16, 11);
2665  LOG_USER_N("\n");
2666  chip->cfg.plla_freq = 0;
2667  if (mula == 0)
2668  LOG_USER("\tPLLA Freq: (Disabled,mula = 0)");
2669  else if (diva == 0)
2670  LOG_USER("\tPLLA Freq: (Disabled,diva = 0)");
2671  else if (diva >= 1) {
2672  chip->cfg.plla_freq = (chip->cfg.mainosc_freq * (mula + 1) / diva);
2673  LOG_USER("\tPLLA Freq: %3.03f MHz",
2674  _tomhz(chip->cfg.plla_freq));
2675  }
2676 }
2677 
2678 static void sam3_explain_mckr(struct sam3_chip *chip)
2679 {
2680  uint32_t css, pres, fin = 0;
2681  int pdiv = 0;
2682  const char *cp = NULL;
2683 
2684  css = sam3_reg_fieldname(chip, "CSS", chip->cfg.PMC_MCKR, 0, 2);
2685  switch (css & 3) {
2686  case 0:
2687  fin = chip->cfg.slow_freq;
2688  cp = "slowclk";
2689  break;
2690  case 1:
2691  fin = chip->cfg.mainosc_freq;
2692  cp = "mainosc";
2693  break;
2694  case 2:
2695  fin = chip->cfg.plla_freq;
2696  cp = "plla";
2697  break;
2698  case 3:
2699  if (chip->cfg.CKGR_UCKR & (1 << 16)) {
2700  fin = 480 * 1000 * 1000;
2701  cp = "upll";
2702  } else {
2703  fin = 0;
2704  cp = "upll (*ERROR* UPLL is disabled)";
2705  }
2706  break;
2707  default:
2708  assert(0);
2709  break;
2710  }
2711 
2712  LOG_USER("%s (%3.03f Mhz)",
2713  cp,
2714  _tomhz(fin));
2715  pres = sam3_reg_fieldname(chip, "PRES", chip->cfg.PMC_MCKR, 4, 3);
2716  switch (pres & 0x07) {
2717  case 0:
2718  pdiv = 1;
2719  cp = "selected clock";
2720  break;
2721  case 1:
2722  pdiv = 2;
2723  cp = "clock/2";
2724  break;
2725  case 2:
2726  pdiv = 4;
2727  cp = "clock/4";
2728  break;
2729  case 3:
2730  pdiv = 8;
2731  cp = "clock/8";
2732  break;
2733  case 4:
2734  pdiv = 16;
2735  cp = "clock/16";
2736  break;
2737  case 5:
2738  pdiv = 32;
2739  cp = "clock/32";
2740  break;
2741  case 6:
2742  pdiv = 64;
2743  cp = "clock/64";
2744  break;
2745  case 7:
2746  pdiv = 6;
2747  cp = "clock/6";
2748  break;
2749  default:
2750  assert(0);
2751  break;
2752  }
2753  LOG_USER("(%s)", cp);
2754  fin = fin / pdiv;
2755  /* sam3 has a *SINGLE* clock - */
2756  /* other at91 series parts have divisors for these. */
2757  chip->cfg.cpu_freq = fin;
2758  chip->cfg.mclk_freq = fin;
2759  chip->cfg.fclk_freq = fin;
2760  LOG_USER("\t\tResult CPU Freq: %3.03f",
2761  _tomhz(fin));
2762 }
2763 
2764 #if 0
2765 static struct sam3_chip *target2sam3(struct target *target)
2766 {
2767  struct sam3_chip *chip;
2768 
2769  if (!target)
2770  return NULL;
2771 
2772  chip = all_sam3_chips;
2773  while (chip) {
2774  if (chip->target == target)
2775  break; /* return below */
2776  else
2777  chip = chip->next;
2778  }
2779  return chip;
2780 }
2781 #endif
2782 
2783 static uint32_t *sam3_get_reg_ptr(struct sam3_cfg *cfg, const struct sam3_reg_list *list)
2784 {
2785  /* this function exists to help */
2786  /* keep funky offsetof() errors */
2787  /* and casting from causing bugs */
2788 
2789  /* By using prototypes - we can detect what would */
2790  /* be casting errors. */
2791 
2792  return (uint32_t *)(void *)(((char *)(cfg)) + list->struct_offset);
2793 }
2794 
2795 
2796 #define SAM3_ENTRY(NAME, FUNC) { .address = SAM3_ ## NAME, .struct_offset = offsetof( \
2797  struct sam3_cfg, \
2798  NAME), # NAME, FUNC }
2799 static const struct sam3_reg_list sam3_all_regs[] = {
2800  SAM3_ENTRY(CKGR_MOR, sam3_explain_ckgr_mor),
2801  SAM3_ENTRY(CKGR_MCFR, sam3_explain_ckgr_mcfr),
2802  SAM3_ENTRY(CKGR_PLLAR, sam3_explain_ckgr_plla),
2803  SAM3_ENTRY(CKGR_UCKR, NULL),
2804  SAM3_ENTRY(PMC_FSMR, NULL),
2805  SAM3_ENTRY(PMC_FSPR, NULL),
2806  SAM3_ENTRY(PMC_IMR, NULL),
2807  SAM3_ENTRY(PMC_MCKR, sam3_explain_mckr),
2808  SAM3_ENTRY(PMC_PCK0, NULL),
2809  SAM3_ENTRY(PMC_PCK1, NULL),
2810  SAM3_ENTRY(PMC_PCK2, NULL),
2811  SAM3_ENTRY(PMC_PCSR, NULL),
2812  SAM3_ENTRY(PMC_SCSR, NULL),
2813  SAM3_ENTRY(PMC_SR, NULL),
2814  SAM3_ENTRY(CHIPID_CIDR, sam3_explain_chipid_cidr),
2815  SAM3_ENTRY(CHIPID_CIDR2, sam3_explain_chipid_cidr),
2816  SAM3_ENTRY(CHIPID_EXID, NULL),
2817  SAM3_ENTRY(CHIPID_EXID2, NULL),
2818  /* TERMINATE THE LIST */
2819  { .name = NULL }
2820 };
2821 #undef SAM3_ENTRY
2822 
2823 static struct sam3_bank_private *get_sam3_bank_private(struct flash_bank *bank)
2824 {
2825  return bank->driver_priv;
2826 }
2827 
2832 static const struct sam3_reg_list *sam3_get_reg(struct sam3_chip *chip, uint32_t *goes_here)
2833 {
2834  const struct sam3_reg_list *reg;
2835 
2836  reg = &(sam3_all_regs[0]);
2837  while (reg->name) {
2838  uint32_t *possible;
2839 
2840  /* calculate where this one go.. */
2841  /* it is "possibly" this register. */
2842 
2843  possible = ((uint32_t *)(void *)(((char *)(&(chip->cfg))) + reg->struct_offset));
2844 
2845  /* well? Is it this register */
2846  if (possible == goes_here) {
2847  /* Jump for joy! */
2848  return reg;
2849  }
2850 
2851  /* next... */
2852  reg++;
2853  }
2854  /* This is *TOTAL*PANIC* - we are totally screwed. */
2855  LOG_ERROR("INVALID SAM3 REGISTER");
2856  return NULL;
2857 }
2858 
2859 static int sam3_read_this_reg(struct sam3_chip *chip, uint32_t *goes_here)
2860 {
2861  const struct sam3_reg_list *reg;
2862  int r;
2863 
2864  reg = sam3_get_reg(chip, goes_here);
2865  if (!reg)
2866  return ERROR_FAIL;
2867 
2868  r = target_read_u32(chip->target, reg->address, goes_here);
2869  if (r != ERROR_OK) {
2870  LOG_ERROR("Cannot read SAM3 register: %s @ 0x%08" PRIx32 ", Err: %d",
2871  reg->name, reg->address, r);
2872  }
2873  return r;
2874 }
2875 
2876 static int sam3_read_all_regs(struct sam3_chip *chip)
2877 {
2878  int r;
2879  const struct sam3_reg_list *reg;
2880 
2881  reg = &(sam3_all_regs[0]);
2882  while (reg->name) {
2883  r = sam3_read_this_reg(chip,
2884  sam3_get_reg_ptr(&(chip->cfg), reg));
2885  if (r != ERROR_OK) {
2886  LOG_ERROR("Cannot read SAM3 register: %s @ 0x%08" PRIx32 ", Error: %d",
2887  reg->name, reg->address, r);
2888  return r;
2889  }
2890  reg++;
2891  }
2892 
2893  /* Chip identification register
2894  *
2895  * Unfortunately, the chip identification register is not at
2896  * a constant address across all of the SAM3 series'. As a
2897  * consequence, a simple heuristic is used to find where it's
2898  * at...
2899  *
2900  * If the contents at the first address is zero, then we know
2901  * that the second address is where the chip id register is.
2902  * We can deduce this because for those SAM's that have the
2903  * chip id @ 0x400e0940, the first address, 0x400e0740, is
2904  * located in the memory map of the Power Management Controller
2905  * (PMC). Furthermore, the address is not used by the PMC.
2906  * So when read, the memory controller returns zero.*/
2907  if (chip->cfg.CHIPID_CIDR == 0) {
2908  /*Put the correct CIDR and EXID values in the chip structure */
2909  chip->cfg.CHIPID_CIDR = chip->cfg.CHIPID_CIDR2;
2910  chip->cfg.CHIPID_EXID = chip->cfg.CHIPID_EXID2;
2911  }
2912  return ERROR_OK;
2913 }
2914 
2915 static int sam3_get_info(struct sam3_chip *chip)
2916 {
2917  const struct sam3_reg_list *reg;
2918  uint32_t regval;
2919 
2920  reg = &(sam3_all_regs[0]);
2921  while (reg->name) {
2922  /* display all regs */
2923  LOG_DEBUG("Start: %s", reg->name);
2924  regval = *sam3_get_reg_ptr(&(chip->cfg), reg);
2925  LOG_USER("%*s: [0x%08" PRIx32 "] -> 0x%08" PRIx32,
2926  REG_NAME_WIDTH,
2927  reg->name,
2928  reg->address,
2929  regval);
2930  if (reg->explain_func)
2931  (*(reg->explain_func))(chip);
2932  LOG_DEBUG("End: %s", reg->name);
2933  reg++;
2934  }
2935  LOG_USER(" rc-osc: %3.03f MHz", _tomhz(chip->cfg.rc_freq));
2936  LOG_USER(" mainosc: %3.03f MHz", _tomhz(chip->cfg.mainosc_freq));
2937  LOG_USER(" plla: %3.03f MHz", _tomhz(chip->cfg.plla_freq));
2938  LOG_USER(" cpu-freq: %3.03f MHz", _tomhz(chip->cfg.cpu_freq));
2939  LOG_USER("mclk-freq: %3.03f MHz", _tomhz(chip->cfg.mclk_freq));
2940 
2941  LOG_USER(" UniqueId: 0x%08" PRIx32 " 0x%08" PRIx32 " 0x%08" PRIx32 " 0x%08" PRIx32,
2942  chip->cfg.unique_id[0],
2943  chip->cfg.unique_id[1],
2944  chip->cfg.unique_id[2],
2945  chip->cfg.unique_id[3]);
2946 
2947  return ERROR_OK;
2948 }
2949 
2950 static int sam3_protect_check(struct flash_bank *bank)
2951 {
2952  int r;
2953  uint32_t v = 0;
2954  unsigned int x;
2955  struct sam3_bank_private *private;
2956 
2957  LOG_DEBUG("Begin");
2958  if (bank->target->state != TARGET_HALTED) {
2959  LOG_ERROR("Target not halted");
2960  return ERROR_TARGET_NOT_HALTED;
2961  }
2962 
2963  private = get_sam3_bank_private(bank);
2964  if (!private) {
2965  LOG_ERROR("no private for this bank?");
2966  return ERROR_FAIL;
2967  }
2968  if (!(private->probed))
2969  return ERROR_FLASH_BANK_NOT_PROBED;
2970 
2971  r = flashd_get_lock_bits(private, &v);
2972  if (r != ERROR_OK) {
2973  LOG_DEBUG("Failed: %d", r);
2974  return r;
2975  }
2976 
2977  for (x = 0; x < private->nsectors; x++)
2978  bank->sectors[x].is_protected = (!!(v & (1 << x)));
2979  LOG_DEBUG("Done");
2980  return ERROR_OK;
2981 }
2982 
2983 FLASH_BANK_COMMAND_HANDLER(sam3_flash_bank_command)
2984 {
2985  struct sam3_chip *chip;
2986 
2987  chip = all_sam3_chips;
2988 
2989  /* is this an existing chip? */
2990  while (chip) {
2991  if (chip->target == bank->target)
2992  break;
2993  chip = chip->next;
2994  }
2995 
2996  if (!chip) {
2997  /* this is a *NEW* chip */
2998  chip = calloc(1, sizeof(struct sam3_chip));
2999  if (!chip) {
3000  LOG_ERROR("NO RAM!");
3001  return ERROR_FAIL;
3002  }
3003  chip->target = bank->target;
3004  /* insert at head */
3005  chip->next = all_sam3_chips;
3006  all_sam3_chips = chip;
3007  chip->target = bank->target;
3008  /* assumption is this runs at 32khz */
3009  chip->cfg.slow_freq = 32768;
3010  chip->probed = false;
3011  }
3012 
3013  switch (bank->base) {
3014  default:
3015  LOG_ERROR("Address 0x%08x invalid bank address (try 0x%08x or 0x%08x "
3016  "[at91sam3u series] or 0x%08x [at91sam3s series] or "
3017  "0x%08x [at91sam3n series] or 0x%08x or 0x%08x or 0x%08x[at91sam3ax series] )",
3018  ((unsigned int)(bank->base)),
3019  ((unsigned int)(FLASH_BANK0_BASE_U)),
3020  ((unsigned int)(FLASH_BANK1_BASE_U)),
3021  ((unsigned int)(FLASH_BANK_BASE_S)),
3022  ((unsigned int)(FLASH_BANK_BASE_N)),
3023  ((unsigned int)(FLASH_BANK0_BASE_AX)),
3024  ((unsigned int)(FLASH_BANK1_BASE_256K_AX)),
3025  ((unsigned int)(FLASH_BANK1_BASE_512K_AX)));
3026  return ERROR_FAIL;
3027 
3028  /* at91sam3s and at91sam3n series only has bank 0*/
3029  /* at91sam3u and at91sam3ax series has the same address for bank 0*/
3030  case FLASH_BANK_BASE_S:
3031  case FLASH_BANK0_BASE_U:
3032  bank->driver_priv = &(chip->details.bank[0]);
3033  bank->bank_number = 0;
3034  chip->details.bank[0].chip = chip;
3035  chip->details.bank[0].bank = bank;
3036  break;
3037 
3038  /* Bank 1 of at91sam3u or at91sam3ax series */
3039  case FLASH_BANK1_BASE_U:
3040  case FLASH_BANK1_BASE_256K_AX:
3041  case FLASH_BANK1_BASE_512K_AX:
3042  bank->driver_priv = &(chip->details.bank[1]);
3043  bank->bank_number = 1;
3044  chip->details.bank[1].chip = chip;
3045  chip->details.bank[1].bank = bank;
3046  break;
3047  }
3048 
3049  /* we initialize after probing. */
3050  return ERROR_OK;
3051 }
3052 
3058 static void sam3_free_driver_priv(struct flash_bank *bank)
3059 {
3060  struct sam3_chip *chip = all_sam3_chips;
3061  while (chip) {
3062  struct sam3_chip *next = chip->next;
3063  free(chip);
3064  chip = next;
3065  }
3066  all_sam3_chips = NULL;
3067 }
3068 
3069 static int sam3_get_details(struct sam3_bank_private *private)
3070 {
3071  const struct sam3_chip_details *details;
3072  struct sam3_chip *chip;
3073  struct flash_bank *saved_banks[SAM3_MAX_FLASH_BANKS];
3074  unsigned int x;
3075 
3076  LOG_DEBUG("Begin");
3077  details = all_sam3_details;
3078  while (details->name) {
3079  /* Compare cidr without version bits */
3080  if (((details->chipid_cidr ^ private->chip->cfg.CHIPID_CIDR) & 0xFFFFFFE0) == 0)
3081  break;
3082  else
3083  details++;
3084  }
3085  if (!details->name) {
3086  LOG_ERROR("SAM3 ChipID 0x%08x not found in table (perhaps you can ID this chip?)",
3087  (unsigned int)(private->chip->cfg.CHIPID_CIDR));
3088  /* Help the victim, print details about the chip */
3089  LOG_INFO("SAM3 CHIPID_CIDR: 0x%08" PRIx32 " decodes as follows",
3090  private->chip->cfg.CHIPID_CIDR);
3091  sam3_explain_chipid_cidr(private->chip);
3092  return ERROR_FAIL;
3093  }
3094 
3095  /* DANGER: THERE ARE DRAGONS HERE */
3096 
3097  /* get our chip - it is going */
3098  /* to be over-written shortly */
3099  chip = private->chip;
3100 
3101  /* Note that, in reality: */
3102  /* */
3103  /* private = &(chip->details.bank[0]) */
3104  /* or private = &(chip->details.bank[1]) */
3105  /* */
3106 
3107  /* save the "bank" pointers */
3108  for (x = 0; x < SAM3_MAX_FLASH_BANKS; x++)
3109  saved_banks[x] = chip->details.bank[x].bank;
3110 
3111  /* Overwrite the "details" structure. */
3112  memcpy(&(private->chip->details),
3113  details,
3114  sizeof(private->chip->details));
3115 
3116  /* now fix the ghosted pointers */
3117  for (x = 0; x < SAM3_MAX_FLASH_BANKS; x++) {
3118  chip->details.bank[x].chip = chip;
3119  chip->details.bank[x].bank = saved_banks[x];
3120  }
3121 
3122  /* update the *BANK*SIZE* */
3123 
3124  LOG_DEBUG("End");
3125  return ERROR_OK;
3126 }
3127 
3128 static int _sam3_probe(struct flash_bank *bank, int noise)
3129 {
3130  int r;
3131  struct sam3_bank_private *private;
3132 
3133 
3134  LOG_DEBUG("Begin: Bank: %u, Noise: %d", bank->bank_number, noise);
3135  if (bank->target->state != TARGET_HALTED) {
3136  LOG_ERROR("Target not halted");
3137  return ERROR_TARGET_NOT_HALTED;
3138  }
3139 
3140  private = get_sam3_bank_private(bank);
3141  if (!private) {
3142  LOG_ERROR("Invalid/unknown bank number");
3143  return ERROR_FAIL;
3144  }
3145 
3146  r = sam3_read_all_regs(private->chip);
3147  if (r != ERROR_OK)
3148  return r;
3149 
3150  LOG_DEBUG("Here");
3151  if (private->chip->probed)
3152  r = sam3_get_info(private->chip);
3153  else
3154  r = sam3_get_details(private);
3155  if (r != ERROR_OK)
3156  return r;
3157 
3158  /* update the flash bank size */
3159  for (unsigned int x = 0; x < SAM3_MAX_FLASH_BANKS; x++) {
3160  if (bank->base == private->chip->details.bank[x].base_address) {
3161  bank->size = private->chip->details.bank[x].size_bytes;
3162  break;
3163  }
3164  }
3165 
3166  if (!bank->sectors) {
3167  bank->sectors = calloc(private->nsectors, (sizeof((bank->sectors)[0])));
3168  if (!bank->sectors) {
3169  LOG_ERROR("No memory!");
3170  return ERROR_FAIL;
3171  }
3172  bank->num_sectors = private->nsectors;
3173 
3174  for (unsigned int x = 0; x < bank->num_sectors; x++) {
3175  bank->sectors[x].size = private->sector_size;
3176  bank->sectors[x].offset = x * (private->sector_size);
3177  /* mark as unknown */
3178  bank->sectors[x].is_erased = -1;
3179  bank->sectors[x].is_protected = -1;
3180  }
3181  }
3182 
3183  private->probed = true;
3184 
3185  r = sam3_protect_check(bank);
3186  if (r != ERROR_OK)
3187  return r;
3188 
3189  LOG_DEBUG("Bank = %d, nbanks = %d",
3190  private->bank_number, private->chip->details.n_banks);
3191  if ((private->bank_number + 1) == private->chip->details.n_banks) {
3192  /* read unique id, */
3193  /* it appears to be associated with the *last* flash bank. */
3194  flashd_read_uid(private);
3195  }
3196 
3197  return r;
3198 }
3199 
3200 static int sam3_probe(struct flash_bank *bank)
3201 {
3202  return _sam3_probe(bank, 1);
3203 }
3204 
3205 static int sam3_auto_probe(struct flash_bank *bank)
3206 {
3207  return _sam3_probe(bank, 0);
3208 }
3209 
3210 static int sam3_erase(struct flash_bank *bank, unsigned int first,
3211  unsigned int last)
3212 {
3213  struct sam3_bank_private *private;
3214  int r;
3215 
3216  LOG_DEBUG("Here");
3217  if (bank->target->state != TARGET_HALTED) {
3218  LOG_ERROR("Target not halted");
3219  return ERROR_TARGET_NOT_HALTED;
3220  }
3221 
3222  r = sam3_auto_probe(bank);
3223  if (r != ERROR_OK) {
3224  LOG_DEBUG("Here,r=%d", r);
3225  return r;
3226  }
3227 
3228  private = get_sam3_bank_private(bank);
3229  if (!(private->probed))
3230  return ERROR_FLASH_BANK_NOT_PROBED;
3231 
3232  if ((first == 0) && ((last + 1) == private->nsectors)) {
3233  /* whole chip */
3234  LOG_DEBUG("Here");
3235  return flashd_erase_entire_bank(private);
3236  }
3237  LOG_INFO("sam3 auto-erases while programming (request ignored)");
3238  return ERROR_OK;
3239 }
3240 
3241 static int sam3_protect(struct flash_bank *bank, int set, unsigned int first,
3242  unsigned int last)
3243 {
3244  struct sam3_bank_private *private;
3245  int r;
3246 
3247  LOG_DEBUG("Here");
3248  if (bank->target->state != TARGET_HALTED) {
3249  LOG_ERROR("Target not halted");
3250  return ERROR_TARGET_NOT_HALTED;
3251  }
3252 
3253  private = get_sam3_bank_private(bank);
3254  if (!(private->probed))
3255  return ERROR_FLASH_BANK_NOT_PROBED;
3256 
3257  if (set)
3258  r = flashd_lock(private, first, last);
3259  else
3260  r = flashd_unlock(private, first, last);
3261  LOG_DEBUG("End: r=%d", r);
3262 
3263  return r;
3264 
3265 }
3266 
3267 static int sam3_page_read(struct sam3_bank_private *private, unsigned int pagenum, uint8_t *buf)
3268 {
3269  uint32_t adr;
3270  int r;
3271 
3272  adr = pagenum * private->page_size;
3273  adr += private->base_address;
3274 
3275  r = target_read_memory(private->chip->target,
3276  adr,
3277  4, /* THIS*MUST*BE* in 32bit values */
3278  private->page_size / 4,
3279  buf);
3280  if (r != ERROR_OK)
3281  LOG_ERROR("SAM3: Flash program failed to read page phys address: 0x%08x",
3282  (unsigned int)(adr));
3283  return r;
3284 }
3285 
3286 static int sam3_page_write(struct sam3_bank_private *private, unsigned int pagenum, const uint8_t *buf)
3287 {
3288  uint32_t adr;
3289  uint32_t status;
3290  uint32_t fmr; /* EEFC Flash Mode Register */
3291  int r;
3292 
3293  adr = pagenum * private->page_size;
3294  adr += private->base_address;
3295 
3296  /* Get flash mode register value */
3297  r = target_read_u32(private->chip->target, private->controller_address, &fmr);
3298  if (r != ERROR_OK)
3299  LOG_DEBUG("Error Read failed: read flash mode register");
3300 
3301  /* Clear flash wait state field */
3302  fmr &= 0xfffff0ff;
3303 
3304  /* set FWS (flash wait states) field in the FMR (flash mode register) */
3305  fmr |= (private->flash_wait_states << 8);
3306 
3307  LOG_DEBUG("Flash Mode: 0x%08x", ((unsigned int)(fmr)));
3308  r = target_write_u32(private->bank->target, private->controller_address, fmr);
3309  if (r != ERROR_OK)
3310  LOG_DEBUG("Error Write failed: set flash mode register");
3311 
3312  LOG_DEBUG("Wr Page %u @ phys address: 0x%08x", pagenum, (unsigned int)(adr));
3313  r = target_write_memory(private->chip->target,
3314  adr,
3315  4, /* THIS*MUST*BE* in 32bit values */
3316  private->page_size / 4,
3317  buf);
3318  if (r != ERROR_OK) {
3319  LOG_ERROR("SAM3: Failed to write (buffer) page at phys address 0x%08x",
3320  (unsigned int)(adr));
3321  return r;
3322  }
3323 
3324  r = efc_perform_command(private,
3325  /* send Erase & Write Page */
3326  AT91C_EFC_FCMD_EWP,
3327  pagenum,
3328  &status);
3329 
3330  if (r != ERROR_OK)
3331  LOG_ERROR("SAM3: Error performing Erase & Write page @ phys address 0x%08x",
3332  (unsigned int)(adr));
3333  if (status & (1 << 2)) {
3334  LOG_ERROR("SAM3: Page @ Phys address 0x%08x is locked", (unsigned int)(adr));
3335  return ERROR_FAIL;
3336  }
3337  if (status & (1 << 1)) {
3338  LOG_ERROR("SAM3: Flash Command error @phys address 0x%08x", (unsigned int)(adr));
3339  return ERROR_FAIL;
3340  }
3341  return ERROR_OK;
3342 }
3343 
3344 static int sam3_write(struct flash_bank *bank,
3345  const uint8_t *buffer,
3346  uint32_t offset,
3347  uint32_t count)
3348 {
3349  int n;
3350  unsigned int page_cur;
3351  unsigned int page_end;
3352  int r;
3353  unsigned int page_offset;
3354  struct sam3_bank_private *private;
3355  uint8_t *pagebuffer;
3356 
3357  /* in case we bail further below, set this to null */
3358  pagebuffer = NULL;
3359 
3360  /* ignore dumb requests */
3361  if (count == 0) {
3362  r = ERROR_OK;
3363  goto done;
3364  }
3365 
3366  if (bank->target->state != TARGET_HALTED) {
3367  LOG_ERROR("Target not halted");
3368  r = ERROR_TARGET_NOT_HALTED;
3369  goto done;
3370  }
3371 
3372  private = get_sam3_bank_private(bank);
3373  if (!(private->probed)) {
3374  r = ERROR_FLASH_BANK_NOT_PROBED;
3375  goto done;
3376  }
3377 
3378  if ((offset + count) > private->size_bytes) {
3379  LOG_ERROR("Flash write error - past end of bank");
3380  LOG_ERROR(" offset: 0x%08x, count 0x%08x, BankEnd: 0x%08x",
3381  (unsigned int)(offset),
3382  (unsigned int)(count),
3383  (unsigned int)(private->size_bytes));
3384  r = ERROR_FAIL;
3385  goto done;
3386  }
3387 
3388  pagebuffer = malloc(private->page_size);
3389  if (!pagebuffer) {
3390  LOG_ERROR("No memory for %d Byte page buffer", (int)(private->page_size));
3391  r = ERROR_FAIL;
3392  goto done;
3393  }
3394 
3395  /* what page do we start & end in? */
3396  page_cur = offset / private->page_size;
3397  page_end = (offset + count - 1) / private->page_size;
3398 
3399  LOG_DEBUG("Offset: 0x%08x, Count: 0x%08x", (unsigned int)(offset), (unsigned int)(count));
3400  LOG_DEBUG("Page start: %d, Page End: %d", (int)(page_cur), (int)(page_end));
3401 
3402  /* Special case: all one page */
3403  /* */
3404  /* Otherwise: */
3405  /* (1) non-aligned start */
3406  /* (2) body pages */
3407  /* (3) non-aligned end. */
3408 
3409  /* Handle special case - all one page. */
3410  if (page_cur == page_end) {
3411  LOG_DEBUG("Special case, all in one page");
3412  r = sam3_page_read(private, page_cur, pagebuffer);
3413  if (r != ERROR_OK)
3414  goto done;
3415 
3416  page_offset = (offset & (private->page_size-1));
3417  memcpy(pagebuffer + page_offset,
3418  buffer,
3419  count);
3420 
3421  r = sam3_page_write(private, page_cur, pagebuffer);
3422  if (r != ERROR_OK)
3423  goto done;
3424  r = ERROR_OK;
3425  goto done;
3426  }
3427 
3428  /* non-aligned start */
3429  page_offset = offset & (private->page_size - 1);
3430  if (page_offset) {
3431  LOG_DEBUG("Not-Aligned start");
3432  /* read the partial */
3433  r = sam3_page_read(private, page_cur, pagebuffer);
3434  if (r != ERROR_OK)
3435  goto done;
3436 
3437  /* over-write with new data */
3438  n = (private->page_size - page_offset);
3439  memcpy(pagebuffer + page_offset,
3440  buffer,
3441  n);
3442 
3443  r = sam3_page_write(private, page_cur, pagebuffer);
3444  if (r != ERROR_OK)
3445  goto done;
3446 
3447  count -= n;
3448  offset += n;
3449  buffer += n;
3450  page_cur++;
3451  }
3452 
3453  /* By checking that offset is correct here, we also
3454  fix a clang warning */
3455  assert(offset % private->page_size == 0);
3456 
3457  /* intermediate large pages */
3458  /* also - the final *terminal* */
3459  /* if that terminal page is a full page */
3460  LOG_DEBUG("Full Page Loop: cur=%d, end=%d, count = 0x%08x",
3461  (int)page_cur, (int)page_end, (unsigned int)(count));
3462 
3463  while ((page_cur < page_end) &&
3464  (count >= private->page_size)) {
3465  r = sam3_page_write(private, page_cur, buffer);
3466  if (r != ERROR_OK)
3467  goto done;
3468  count -= private->page_size;
3469  buffer += private->page_size;
3470  page_cur += 1;
3471  }
3472 
3473  /* terminal partial page? */
3474  if (count) {
3475  LOG_DEBUG("Terminal partial page, count = 0x%08x", (unsigned int)(count));
3476  /* we have a partial page */
3477  r = sam3_page_read(private, page_cur, pagebuffer);
3478  if (r != ERROR_OK)
3479  goto done;
3480  /* data goes at start */
3481  memcpy(pagebuffer, buffer, count);
3482  r = sam3_page_write(private, page_cur, pagebuffer);
3483  if (r != ERROR_OK)
3484  goto done;
3485  }
3486  LOG_DEBUG("Done!");
3487  r = ERROR_OK;
3488 done:
3489  free(pagebuffer);
3490  return r;
3491 }
3492 
3493 COMMAND_HANDLER(sam3_handle_info_command)
3494 {
3495  struct sam3_chip *chip;
3496  chip = get_current_sam3(CMD);
3497  if (!chip)
3498  return ERROR_OK;
3499 
3500  unsigned int x;
3501  int r;
3502 
3503  /* bank0 must exist before we can do anything */
3504  if (!chip->details.bank[0].bank) {
3505  x = 0;
3506 need_define:
3507  command_print(CMD,
3508  "Please define bank %d via command: flash bank %s ... ",
3509  x,
3510  at91sam3_flash.name);
3511  return ERROR_FAIL;
3512  }
3513 
3514  /* if bank 0 is not probed, then probe it */
3515  if (!(chip->details.bank[0].probed)) {
3516  r = sam3_auto_probe(chip->details.bank[0].bank);
3517  if (r != ERROR_OK)
3518  return ERROR_FAIL;
3519  }
3520  /* above guarantees the "chip details" structure is valid */
3521  /* and thus, bank private areas are valid */
3522  /* and we have a SAM3 chip, what a concept! */
3523 
3524  /* auto-probe other banks, 0 done above */
3525  for (x = 1; x < SAM3_MAX_FLASH_BANKS; x++) {
3526  /* skip banks not present */
3527  if (!(chip->details.bank[x].present))
3528  continue;
3529 
3530  if (!chip->details.bank[x].bank)
3531  goto need_define;
3532 
3533  if (chip->details.bank[x].probed)
3534  continue;
3535 
3536  r = sam3_auto_probe(chip->details.bank[x].bank);
3537  if (r != ERROR_OK)
3538  return r;
3539  }
3540 
3541  r = sam3_get_info(chip);
3542  if (r != ERROR_OK) {
3543  LOG_DEBUG("Sam3Info, Failed %d", r);
3544  return r;
3545  }
3546 
3547  return ERROR_OK;
3548 }
3549 
3550 COMMAND_HANDLER(sam3_handle_gpnvm_command)
3551 {
3552  unsigned int x, v;
3553  int r, who;
3554  struct sam3_chip *chip;
3555 
3556  chip = get_current_sam3(CMD);
3557  if (!chip)
3558  return ERROR_OK;
3559 
3560  if (chip->target->state != TARGET_HALTED) {
3561  LOG_ERROR("sam3 - target not halted");
3562  return ERROR_TARGET_NOT_HALTED;
3563  }
3564 
3565  if (!chip->details.bank[0].bank) {
3566  command_print(CMD, "Bank0 must be defined first via: flash bank %s ...",
3567  at91sam3_flash.name);
3568  return ERROR_FAIL;
3569  }
3570  if (!chip->details.bank[0].probed) {
3571  r = sam3_auto_probe(chip->details.bank[0].bank);
3572  if (r != ERROR_OK)
3573  return r;
3574  }
3575 
3576  switch (CMD_ARGC) {
3577  default:
3578  return ERROR_COMMAND_SYNTAX_ERROR;
3579  case 0:
3580  goto showall;
3581  case 1:
3582  who = -1;
3583  break;
3584  case 2:
3585  if ((strcmp(CMD_ARGV[0], "show") == 0) && (strcmp(CMD_ARGV[1], "all") == 0))
3586  who = -1;
3587  else {
3588  uint32_t v32;
3589  COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], v32);
3590  who = v32;
3591  }
3592  break;
3593  }
3594 
3595  if (strcmp("show", CMD_ARGV[0]) == 0) {
3596  if (who == -1) {
3597 showall:
3598  r = ERROR_OK;
3599  for (x = 0; x < chip->details.n_gpnvms; x++) {
3600  r = flashd_get_gpnvm(&(chip->details.bank[0]), x, &v);
3601  if (r != ERROR_OK)
3602  break;
3603  command_print(CMD, "sam3-gpnvm%u: %u", x, v);
3604  }
3605  return r;
3606  }
3607  if ((who >= 0) && (((unsigned)(who)) < chip->details.n_gpnvms)) {
3608  r = flashd_get_gpnvm(&(chip->details.bank[0]), who, &v);
3609  if (r == ERROR_OK)
3610  command_print(CMD, "sam3-gpnvm%u: %u", who, v);
3611  return r;
3612  } else {
3613  command_print(CMD, "sam3-gpnvm invalid GPNVM: %u", who);
3614  return ERROR_COMMAND_SYNTAX_ERROR;
3615  }
3616  }
3617 
3618  if (who == -1) {
3619  command_print(CMD, "Missing GPNVM number");
3620  return ERROR_COMMAND_SYNTAX_ERROR;
3621  }
3622 
3623  if (strcmp("set", CMD_ARGV[0]) == 0)
3624  r = flashd_set_gpnvm(&(chip->details.bank[0]), who);
3625  else if ((strcmp("clr", CMD_ARGV[0]) == 0) ||
3626  (strcmp("clear", CMD_ARGV[0]) == 0)) /* quietly accept both */
3627  r = flashd_clr_gpnvm(&(chip->details.bank[0]), who);
3628  else {
3629  command_print(CMD, "Unknown command: %s", CMD_ARGV[0]);
3630  r = ERROR_COMMAND_SYNTAX_ERROR;
3631  }
3632  return r;
3633 }
3634 
3635 COMMAND_HANDLER(sam3_handle_slowclk_command)
3636 {
3637  struct sam3_chip *chip;
3638 
3639  chip = get_current_sam3(CMD);
3640  if (!chip)
3641  return ERROR_OK;
3642 
3643  switch (CMD_ARGC) {
3644  case 0:
3645  /* show */
3646  break;
3647  case 1:
3648  {
3649  /* set */
3650  uint32_t v;
3651  COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], v);
3652  if (v > 200000) {
3653  /* absurd slow clock of 200Khz? */
3654  command_print(CMD, "Absurd/illegal slow clock freq: %d\n", (int)(v));
3655  return ERROR_COMMAND_SYNTAX_ERROR;
3656  }
3657  chip->cfg.slow_freq = v;
3658  break;
3659  }
3660  default:
3661  /* error */
3662  command_print(CMD, "Too many parameters");
3663  return ERROR_COMMAND_SYNTAX_ERROR;
3664  }
3665  command_print(CMD, "Slowclk freq: %d.%03dkhz",
3666  (int)(chip->cfg.slow_freq / 1000),
3667  (int)(chip->cfg.slow_freq % 1000));
3668  return ERROR_OK;
3669 }
3670 
3671 static const struct command_registration at91sam3_exec_command_handlers[] = {
3672  {
3673  .name = "gpnvm",
3674  .handler = sam3_handle_gpnvm_command,
3675  .mode = COMMAND_EXEC,
3676  .usage = "[('clr'|'set'|'show') bitnum]",
3677  .help = "Without arguments, shows all bits in the gpnvm "
3678  "register. Otherwise, clears, sets, or shows one "
3679  "General Purpose Non-Volatile Memory (gpnvm) bit.",
3680  },
3681  {
3682  .name = "info",
3683  .handler = sam3_handle_info_command,
3684  .mode = COMMAND_EXEC,
3685  .help = "Print information about the current at91sam3 chip "
3686  "and its flash configuration.",
3687  .usage = "",
3688  },
3689  {
3690  .name = "slowclk",
3691  .handler = sam3_handle_slowclk_command,
3692  .mode = COMMAND_EXEC,
3693  .usage = "[clock_hz]",
3694  .help = "Display or set the slowclock frequency "
3695  "(default 32768 Hz).",
3696  },
3697  COMMAND_REGISTRATION_DONE
3698 };
3699 static const struct command_registration at91sam3_command_handlers[] = {
3700  {
3701  .name = "at91sam3",
3702  .mode = COMMAND_ANY,
3703  .help = "at91sam3 flash command group",
3704  .usage = "",
3705  .chain = at91sam3_exec_command_handlers,
3706  },
3707  COMMAND_REGISTRATION_DONE
3708 };
3709 
3710 const struct flash_driver at91sam3_flash = {
3711  .name = "at91sam3",
3712  .commands = at91sam3_command_handlers,
3713  .flash_bank_command = sam3_flash_bank_command,
3714  .erase = sam3_erase,
3715  .protect = sam3_protect,
3716  .write = sam3_write,
3717  .read = default_flash_read,
3718  .probe = sam3_probe,
3719  .auto_probe = sam3_auto_probe,
3720  .erase_check = default_flash_blank_check,
3721  .protect_check = sam3_protect_check,
3722  .free_driver_priv = sam3_free_driver_priv,
3723 };
FLASH_BANK1_BASE_512K_AX
#define FLASH_BANK1_BASE_512K_AX
Definition: at91sam3.c:44
FLASH_BANK0_BASE_U
#define FLASH_BANK0_BASE_U
Definition: at91sam3.c:26
FLASH_BANK1_BASE_256K_AX
#define FLASH_BANK1_BASE_256K_AX
Definition: at91sam3.c:43
sam3_get_info
static int sam3_get_info(struct sam3_chip *chip)
Definition: at91sam3.c:2915
SAM3_N_NVM_BITS
#define SAM3_N_NVM_BITS
Definition: at91sam3.c:180
get_current_sam3
static struct sam3_chip * get_current_sam3(struct command_invocation *cmd)
Definition: at91sam3.c:208
sam3_explain_ckgr_mcfr
static void sam3_explain_ckgr_mcfr(struct sam3_chip *chip)
Definition: at91sam3.c:2640
sam3_explain_mckr
static void sam3_explain_mckr(struct sam3_chip *chip)
Definition: at91sam3.c:2678
AT91C_EFC_FCMD_WPL
#define AT91C_EFC_FCMD_WPL
Definition: at91sam3.c:48
AT91C_EFC_FCMD_GLB
#define AT91C_EFC_FCMD_GLB
Definition: at91sam3.c:58
FLASH_BANK_BASE_S
#define FLASH_BANK_BASE_S
Definition: at91sam3.c:30
sam3_read_this_reg
static int sam3_read_this_reg(struct sam3_chip *chip, uint32_t *goes_here)
Definition: at91sam3.c:2859
sam3_explain_ckgr_plla
static void sam3_explain_ckgr_plla(struct sam3_chip *chip)
Definition: at91sam3.c:2658
eproc_names
static const char *const eproc_names[]
Definition: at91sam3.c:2435
AT91C_EFC_FCMD_EWPL
#define AT91C_EFC_FCMD_EWPL
Definition: at91sam3.c:50
REG_NAME_WIDTH
#define REG_NAME_WIDTH
Definition: at91sam3.c:23
_unknown
static const char _unknown[]
Definition: at91sam3.c:2434
FLASH_BANK1_BASE_512K_SD
#define FLASH_BANK1_BASE_512K_SD
Definition: at91sam3.c:34
efc_perform_command
static int efc_perform_command(struct sam3_bank_private *private, unsigned int command, unsigned int argument, uint32_t *status)
Performs the given command and wait until its completion (or an error).
Definition: at91sam3.c:2126
OFFSET_EFC_FRR
#define OFFSET_EFC_FRR
Definition: at91sam3.c:68
_yes_or_no
static const char * _yes_or_no(uint32_t v)
Definition: at91sam3.c:2545
flashd_get_gpnvm
static int flashd_get_gpnvm(struct sam3_bank_private *private, unsigned int gpnvm, unsigned int *puthere)
Gets current GPNVM state.
Definition: at91sam3.c:2223
AT91C_EFC_FCMD_SFB
#define AT91C_EFC_FCMD_SFB
Definition: at91sam3.c:59
sam3_write
static int sam3_write(struct flash_bank *bank, const uint8_t *buffer, uint32_t offset, uint32_t count)
Definition: at91sam3.c:3344
sam3_probe
static int sam3_probe(struct flash_bank *bank)
Definition: at91sam3.c:3200
flashd_get_lock_bits
static int flashd_get_lock_bits(struct sam3_bank_private *private, uint32_t *v)
Returns a bit field (at most 64) of locked regions within a page.
Definition: at91sam3.c:2330
AT91C_EFC_FCMD_EA
#define AT91C_EFC_FCMD_EA
Definition: at91sam3.c:51
sam3_reg_fieldname
static uint32_t sam3_reg_fieldname(struct sam3_chip *chip, const char *regname, uint32_t value, unsigned int shift, unsigned int width)
Definition: at91sam3.c:2405
all_sam3_details
static const struct sam3_chip_details all_sam3_details[]
Definition: at91sam3.c:237
sam3_get_reg
static const struct sam3_reg_list * sam3_get_reg(struct sam3_chip *chip, uint32_t *goes_here)
Given a pointer to where it goes in the structure, determine the register name, address from the all ...
Definition: at91sam3.c:2832
flashd_read_uid
static int flashd_read_uid(struct sam3_bank_private *private)
Read the unique ID.
Definition: at91sam3.c:2170
get_sam3_bank_private
static struct sam3_bank_private * get_sam3_bank_private(struct flash_bank *bank)
Definition: at91sam3.c:2823
at91sam3_exec_command_handlers
static const struct command_registration at91sam3_exec_command_handlers[]
Definition: at91sam3.c:3671
flashd_unlock
static int flashd_unlock(struct sam3_bank_private *private, unsigned int start_sector, unsigned int end_sector)
Unlocks all the regions in the given address range.
Definition: at91sam3.c:2348
AT91C_EFC_FCMD_GFB
#define AT91C_EFC_FCMD_GFB
Definition: at91sam3.c:61
sam3_protect
static int sam3_protect(struct flash_bank *bank, int set, unsigned int first, unsigned int last)
Definition: at91sam3.c:3241
sam3_page_write
static int sam3_page_write(struct sam3_bank_private *private, unsigned int pagenum, const uint8_t *buf)
Definition: at91sam3.c:3286
flashd_clr_gpnvm
static int flashd_clr_gpnvm(struct sam3_bank_private *private, unsigned int gpnvm)
Clears the selected GPNVM bit.
Definition: at91sam3.c:2264
flashd_set_gpnvm
static int flashd_set_gpnvm(struct sam3_bank_private *private, unsigned int gpnvm)
Sets the selected GPNVM bit.
Definition: at91sam3.c:2296
efc_start_command
static int efc_start_command(struct sam3_bank_private *private, unsigned int command, unsigned int argument)
Definition: at91sam3.c:2031
nvpsize
static const char *const nvpsize[]
Definition: at91sam3.c:2455
AT91C_EFC_FCMD_EWP
#define AT91C_EFC_FCMD_EWP
Definition: at91sam3.c:49
at91sam3_flash
const struct flash_driver at91sam3_flash
Definition: at91sam3.c:3710
FLASH_BANK_BASE_N
#define FLASH_BANK_BASE_N
Definition: at91sam3.c:38
_tomhz
static float _tomhz(uint32_t freq_hz)
Definition: at91sam3.c:70
AT91C_EFC_FCMD_WP
#define AT91C_EFC_FCMD_WP
Definition: at91sam3.c:47
all_sam3_chips
static struct sam3_chip * all_sam3_chips
Definition: at91sam3.c:206
_sam3_probe
static int _sam3_probe(struct flash_bank *bank, int noise)
Definition: at91sam3.c:3128
at91sam3_command_handlers
static const struct command_registration at91sam3_command_handlers[]
Definition: at91sam3.c:3699
sam3_free_driver_priv
static void sam3_free_driver_priv(struct flash_bank *bank)
Remove all chips from the internal list without distinguishing which one is owned by this bank.
Definition: at91sam3.c:3058
sam3_get_details
static int sam3_get_details(struct sam3_bank_private *private)
Definition: at91sam3.c:3069
nvptype
static const char *const nvptype[]
Definition: at91sam3.c:2534
efc_get_result
static int efc_get_result(struct sam3_bank_private *private, uint32_t *v)
Get the result of the last executed command.
Definition: at91sam3.c:2018
sam3_explain_chipid_cidr
static void sam3_explain_chipid_cidr(struct sam3_chip *chip)
Definition: at91sam3.c:2601
sam3_page_read
static int sam3_page_read(struct sam3_bank_private *private, unsigned int pagenum, uint8_t *buf)
Definition: at91sam3.c:3267
OFFSET_EFC_FCR
#define OFFSET_EFC_FCR
Definition: at91sam3.c:66
FLASH_BANK0_BASE_SD
#define FLASH_BANK0_BASE_SD
Definition: at91sam3.c:33
nvpsize2
#define nvpsize2
Definition: at91sam3.c:2454
flashd_lock
static int flashd_lock(struct sam3_bank_private *private, unsigned int start_sector, unsigned int end_sector)
Locks regions.
Definition: at91sam3.c:2378
sam3_get_reg_ptr
static uint32_t * sam3_get_reg_ptr(struct sam3_cfg *cfg, const struct sam3_reg_list *list)
Definition: at91sam3.c:2783
sam3_all_regs
static const struct sam3_reg_list sam3_all_regs[]
Definition: at91sam3.c:2799
OFFSET_EFC_FSR
#define OFFSET_EFC_FSR
Definition: at91sam3.c:67
FLASH_BANK0_BASE_AX
#define FLASH_BANK0_BASE_AX
Definition: at91sam3.c:41
sam3_explain_ckgr_mor
static void sam3_explain_ckgr_mor(struct sam3_chip *chip)
Definition: at91sam3.c:2557
SAM3_ENTRY
#define SAM3_ENTRY(NAME, FUNC)
Definition: at91sam3.c:2796
AT91C_EFC_FCMD_STUI
#define AT91C_EFC_FCMD_STUI
Definition: at91sam3.c:62
AT91C_EFC_FCMD_GETD
#define AT91C_EFC_FCMD_GETD
Definition: at91sam3.c:46
sam3_auto_probe
static int sam3_auto_probe(struct flash_bank *bank)
Definition: at91sam3.c:3205
efc_get_status
static int efc_get_status(struct sam3_bank_private *private, uint32_t *v)
Get the current status of the EEFC and the value of some status bits (LOCKE, PROGE).
Definition: at91sam3.c:1998
sam3_erase
static int sam3_erase(struct flash_bank *bank, unsigned int first, unsigned int last)
Definition: at91sam3.c:3210
sam3_read_all_regs
static int sam3_read_all_regs(struct sam3_chip *chip)
Definition: at91sam3.c:2876
FLASH_BANK_COMMAND_HANDLER
FLASH_BANK_COMMAND_HANDLER(sam3_flash_bank_command)
Definition: at91sam3.c:2983
sramsize
static const char *const sramsize[]
Definition: at91sam3.c:2474
AT91C_EFC_FCMD_SPUI
#define AT91C_EFC_FCMD_SPUI
Definition: at91sam3.c:63
FLASH_BANK1_BASE_U
#define FLASH_BANK1_BASE_U
Definition: at91sam3.c:27
AT91C_EFC_FCMD_CLB
#define AT91C_EFC_FCMD_CLB
Definition: at91sam3.c:57
flashd_erase_entire_bank
static int flashd_erase_entire_bank(struct sam3_bank_private *private)
Erases the entire flash.
Definition: at91sam3.c:2210
sam3_protect_check
static int sam3_protect_check(struct flash_bank *bank)
Definition: at91sam3.c:2950
AT91C_EFC_FCMD_SLB
#define AT91C_EFC_FCMD_SLB
Definition: at91sam3.c:56
_rc_freq
static const char *const _rc_freq[]
Definition: at91sam3.c:2553
AT91C_EFC_FCMD_CFB
#define AT91C_EFC_FCMD_CFB
Definition: at91sam3.c:60
SAM3_MAX_FLASH_BANKS
#define SAM3_MAX_FLASH_BANKS
Definition: at91sam3.c:185
COMMAND_HANDLER
COMMAND_HANDLER(sam3_handle_info_command)
Definition: at91sam3.c:3493
CKGR_MOR
#define CKGR_MOR
Definition: at91sam7.c:45
PMC_MCKR
#define PMC_MCKR
Definition: at91sam7.c:50
CKGR_MCFR
#define CKGR_MCFR
Definition: at91sam7.c:44
command_print_sameline
void command_print_sameline(struct command_invocation *cmd, const char *format,...)
Definition: command.c:420
command_print
void command_print(struct command_invocation *cmd, const char *format,...)
Definition: command.c:443
CMD
#define CMD
Use this macro to access the command being handled, rather than accessing the variable directly.
Definition: command.h:141
CMD_ARGV
#define CMD_ARGV
Use this macro to access the arguments for the command being handled, rather than accessing the varia...
Definition: command.h:156
ERROR_COMMAND_SYNTAX_ERROR
#define ERROR_COMMAND_SYNTAX_ERROR
Definition: command.h:402
CMD_ARGC
#define CMD_ARGC
Use this macro to access the number of arguments for the command being handled, rather than accessing...
Definition: command.h:151
COMMAND_PARSE_NUMBER
#define COMMAND_PARSE_NUMBER(type, in, out)
parses the string in into out as a type, or prints a command error and passes the error code to the c...
Definition: command.h:442
COMMAND_REGISTRATION_DONE
#define COMMAND_REGISTRATION_DONE
Use this as the last entry in an array of command_registration records.
Definition: command.h:253
COMMAND_ANY
@ COMMAND_ANY
Definition: command.h:42
COMMAND_EXEC
@ COMMAND_EXEC
Definition: command.h:40
width
unsigned short width
Definition: embeddedice.c:47
bank
uint8_t bank
Definition: esirisc.c:135
ERROR_FLASH_BANK_NOT_PROBED
#define ERROR_FLASH_BANK_NOT_PROBED
Definition: flash/common.h:35
default_flash_blank_check
int default_flash_blank_check(struct flash_bank *bank)
Provides default erased-bank check handling.
Definition: flash/nor/core.c:380
default_flash_read
int default_flash_read(struct flash_bank *bank, uint8_t *buffer, uint32_t offset, uint32_t count)
Provides default read implementation for flash memory.
Definition: flash/nor/core.c:121
LOG_USER
#define LOG_USER(expr ...)
Definition: log.h:135
ERROR_FAIL
#define ERROR_FAIL
Definition: log.h:170
LOG_USER_N
#define LOG_USER_N(expr ...)
Definition: log.h:138
LOG_ERROR
#define LOG_ERROR(expr ...)
Definition: log.h:132
LOG_INFO
#define LOG_INFO(expr ...)
Definition: log.h:126
LOG_DEBUG
#define LOG_DEBUG(expr ...)
Definition: log.h:109
ERROR_OK
#define ERROR_OK
Definition: log.h:164
archnames::name
const char * name
Definition: at91sam3.c:2494
archnames::value
unsigned int value
Definition: at91sam3.c:2494
command_invocation
When run_command is called, a new instance will be created on the stack, filled with the proper value...
Definition: command.h:76
command_registration
Definition: command.h:234
command_registration::name
const char * name
Definition: command.h:235
flash_bank
Provides details of a flash bank, available either on-chip or through a major interface.
Definition: nor/core.h:75
flash_driver
Provides the implementation-independent structure that defines all of the callbacks required by OpenO...
Definition: nor/driver.h:39
flash_driver::name
const char * name
Gives a human-readable name of this flash driver, This field is used to select and initialize the dri...
Definition: nor/driver.h:44
reg
Definition: register.h:111
reg::name
const char * name
Definition: register.h:113
sam3_bank_private
Definition: at91sam3.c:145
sam3_bank_private::controller_address
uint32_t controller_address
Definition: at91sam3.c:158
sam3_bank_private::probed
bool probed
Definition: at91sam3.c:146
sam3_bank_private::sector_size
unsigned int sector_size
Definition: at91sam3.c:164
sam3_bank_private::bank
struct flash_bank * bank
Definition: at91sam3.c:156
sam3_bank_private::present
bool present
Definition: at91sam3.c:161
sam3_bank_private::size_bytes
unsigned int size_bytes
Definition: at91sam3.c:162
sam3_bank_private::bank_number
unsigned int bank_number
Definition: at91sam3.c:157
sam3_bank_private::page_size
unsigned int page_size
Definition: at91sam3.c:165
sam3_bank_private::flash_wait_states
uint32_t flash_wait_states
Definition: at91sam3.c:160
sam3_bank_private::nsectors
unsigned int nsectors
Definition: at91sam3.c:163
sam3_bank_private::chip
struct sam3_chip * chip
Definition: at91sam3.c:154
sam3_bank_private::base_address
uint32_t base_address
Definition: at91sam3.c:159
sam3_cfg
Definition: at91sam3.c:79
sam3_cfg::PMC_IMR
uint32_t PMC_IMR
Definition: at91sam3.c:128
sam3_cfg::PMC_SCSR
uint32_t PMC_SCSR
Definition: at91sam3.c:106
sam3_cfg::CKGR_PLLAR
uint32_t CKGR_PLLAR
Definition: at91sam3.c:116
sam3_cfg::pclk0_freq
uint32_t pclk0_freq
Definition: at91sam3.c:89
sam3_cfg::PMC_MCKR
uint32_t PMC_MCKR
Definition: at91sam3.c:118
sam3_cfg::CHIPID_CIDR2
uint32_t CHIPID_CIDR2
Definition: at91sam3.c:97
sam3_cfg::PMC_SR
uint32_t PMC_SR
Definition: at91sam3.c:126
sam3_cfg::unique_id
uint32_t unique_id[4]
Definition: at91sam3.c:80
sam3_cfg::pclk1_freq
uint32_t pclk1_freq
Definition: at91sam3.c:90
sam3_cfg::PMC_FSPR
uint32_t PMC_FSPR
Definition: at91sam3.c:132
sam3_cfg::slow_freq
uint32_t slow_freq
Definition: at91sam3.c:82
sam3_cfg::PMC_PCSR
uint32_t PMC_PCSR
Definition: at91sam3.c:108
sam3_cfg::mclk_freq
uint32_t mclk_freq
Definition: at91sam3.c:86
sam3_cfg::mainosc_freq
uint32_t mainosc_freq
Definition: at91sam3.c:84
sam3_cfg::pclk2_freq
uint32_t pclk2_freq
Definition: at91sam3.c:91
sam3_cfg::CKGR_UCKR
uint32_t CKGR_UCKR
Definition: at91sam3.c:110
sam3_cfg::CHIPID_EXID2
uint32_t CHIPID_EXID2
Definition: at91sam3.c:101
sam3_cfg::CKGR_MOR
uint32_t CKGR_MOR
Definition: at91sam3.c:112
sam3_cfg::plla_freq
uint32_t plla_freq
Definition: at91sam3.c:85
sam3_cfg::cpu_freq
uint32_t cpu_freq
Definition: at91sam3.c:87
sam3_cfg::fclk_freq
uint32_t fclk_freq
Definition: at91sam3.c:88
sam3_cfg::CKGR_MCFR
uint32_t CKGR_MCFR
Definition: at91sam3.c:114
sam3_cfg::CHIPID_EXID
uint32_t CHIPID_EXID
Definition: at91sam3.c:99
sam3_cfg::PMC_PCK0
uint32_t PMC_PCK0
Definition: at91sam3.c:120
sam3_cfg::CHIPID_CIDR
uint32_t CHIPID_CIDR
Definition: at91sam3.c:95
sam3_cfg::PMC_FSMR
uint32_t PMC_FSMR
Definition: at91sam3.c:130
sam3_cfg::rc_freq
uint32_t rc_freq
Definition: at91sam3.c:83
sam3_cfg::PMC_PCK2
uint32_t PMC_PCK2
Definition: at91sam3.c:124
sam3_cfg::PMC_PCK1
uint32_t PMC_PCK1
Definition: at91sam3.c:122
sam3_chip_details
Definition: at91sam3.c:168
sam3_chip_details::n_banks
unsigned int n_banks
Definition: at91sam3.c:184
sam3_chip_details::total_flash_size
unsigned int total_flash_size
Definition: at91sam3.c:182
sam3_chip_details::n_gpnvms
unsigned int n_gpnvms
Definition: at91sam3.c:179
sam3_chip_details::name
const char * name
Definition: at91sam3.c:177
sam3_chip_details::gpnvm
unsigned int gpnvm[SAM3_N_NVM_BITS]
Definition: at91sam3.c:181
sam3_chip_details::bank
struct sam3_bank_private bank[SAM3_MAX_FLASH_BANKS]
Definition: at91sam3.c:187
sam3_chip_details::total_sram_size
unsigned int total_sram_size
Definition: at91sam3.c:183
sam3_chip_details::chipid_cidr
uint32_t chipid_cidr
Definition: at91sam3.c:176
sam3_chip
Definition: at91sam3.c:190
sam3_chip::next
struct sam3_chip * next
Definition: at91sam3.c:191
sam3_chip::probed
bool probed
Definition: at91sam3.c:192
sam3_chip::target
struct target * target
Definition: at91sam3.c:196
sam3_chip::details
struct sam3_chip_details details
Definition: at91sam3.c:195
sam3_chip::cfg
struct sam3_cfg cfg
Definition: at91sam3.c:197
sam3_reg_list
Definition: at91sam3.c:201
sam3_reg_list::name
const char * name
Definition: at91sam3.c:202
sam3_reg_list::address
uint32_t address
Definition: at91sam3.c:202
sam3_reg_list::struct_offset
size_t struct_offset
Definition: at91sam3.c:202
sam3_reg_list::explain_func
void(* explain_func)(struct sam3_chip *chip)
Definition: at91sam3.c:203
target
Definition: target.h:116
target::state
enum target_state state
Definition: target.h:157
target_write_memory
int target_write_memory(struct target *target, target_addr_t address, uint32_t size, uint32_t count, const uint8_t *buffer)
Write count items of size bytes to the memory of target at the address given.
Definition: target.c:1265
target_write_u32
int target_write_u32(struct target *target, target_addr_t address, uint32_t value)
Definition: target.c:2641
target_read_u32
int target_read_u32(struct target *target, target_addr_t address, uint32_t *value)
Definition: target.c:2550
target_read_memory
int target_read_memory(struct target *target, target_addr_t address, uint32_t size, uint32_t count, uint8_t *buffer)
Read count items of size bytes from the memory of target at the address given.
Definition: target.c:1237
get_current_target
struct target * get_current_target(struct command_context *cmd_ctx)
Definition: target.c:458
ERROR_TARGET_NOT_HALTED
#define ERROR_TARGET_NOT_HALTED
Definition: target.h:790
TARGET_HALTED
@ TARGET_HALTED
Definition: target.h:56
time_support.h
timeval_ms
int64_t timeval_ms(void)
Definition: time_support_common.c:23
NULL
#define NULL
Definition: usb.h:16
status
uint8_t status[4]
Definition: vdebug.c:17
cmd
uint8_t cmd
Definition: vdebug.c:1
offset
uint8_t offset[4]
Definition: vdebug.c:9
count
uint8_t count[4]
Definition: vdebug.c:22