Hold common code supporting the ARM7 and ARM9 core generations. More...

Include dependency graph for arm7_9_common.c:

Functions
int	arm7_9_add_breakpoint (struct target target, struct breakpoint breakpoint)
	Add a breakpoint to an ARM7/9 target. More...

int	arm7_9_add_watchpoint (struct target target, struct watchpoint watchpoint)
	Add a watchpoint to an ARM7/9 target. More...

int	arm7_9_assert_reset (struct target *target)
	Asserts the reset (SRST) on an ARM7/9 target. More...

static void	arm7_9_assign_wp (struct arm7_9_common arm7_9, struct breakpoint breakpoint)
	Assign a watchpoint to one of the two available hardware comparators in an ARM7 or ARM9 target. More...

int	arm7_9_bulk_write_memory (struct target target, target_addr_t address, uint32_t count, const uint8_t buffer)

int	arm7_9_check_reset (struct target *target)

static int	arm7_9_clear_halt (struct target *target)
	Clears the halt condition for an ARM7/9 target. More...

static int	arm7_9_clear_watchpoints (struct arm7_9_common *arm7_9)
	Clear watchpoints for an ARM7/9 target. More...

static int	arm7_9_dcc_completion (struct target target, uint32_t exit_point, unsigned int timeout_ms, void arch_info)

int	arm7_9_deassert_reset (struct target *target)
	Deassert the reset (SRST) signal on an ARM7/9 target. More...

static int	arm7_9_debug_entry (struct target *target)
	Handle an ARM7/9 target's entry into debug mode. More...

void	arm7_9_deinit (struct target *target)

void	arm7_9_disable_eice_step (struct target *target)

static void	arm7_9_enable_breakpoints (struct target *target)
	Enable the breakpoints on an ARM7/9 target. More...

void	arm7_9_enable_eice_step (struct target *target, uint32_t next_pc)

static void	arm7_9_enable_watchpoints (struct target *target)
	Enable the watchpoints on an ARM7/9 target. More...

int	arm7_9_endianness_callback (jtag_callback_data_t pu8_in, jtag_callback_data_t i_size, jtag_callback_data_t i_be, jtag_callback_data_t i_flip)

int	arm7_9_examine (struct target *target)
	Perform per-target setup that requires JTAG access. More...

static int	arm7_9_execute_fast_sys_speed (struct target *target)
	Restarts the target by sending a RESTART instruction and moving the JTAG state to IDLE. More...

int	arm7_9_execute_sys_speed (struct target *target)
	Restarts the target by sending a RESTART instruction and moving the JTAG state to IDLE. More...

static int	arm7_9_full_context (struct target *target)
	Validate the full context for an ARM7/9 target in all processor modes. More...

int	arm7_9_halt (struct target *target)
	Halt an ARM7/9 target. More...

static int	arm7_9_handle_target_request (void *priv)
	Handles requests to an ARM7/9 target. More...

int	arm7_9_init_arch_info (struct target target, struct arm7_9_common arm7_9)

int	arm7_9_poll (struct target *target)
	Polls an ARM7/9 target for its current status. More...

static int	arm7_9_read_core_reg (struct target target, struct reg r, int num, enum arm_mode mode)

int	arm7_9_read_memory (struct target target, target_addr_t address, uint32_t size, uint32_t count, uint8_t buffer)

int	arm7_9_remove_breakpoint (struct target target, struct breakpoint breakpoint)
	Removes a breakpoint from an ARM7/9 target. More...

int	arm7_9_remove_watchpoint (struct target target, struct watchpoint watchpoint)
	Remove a watchpoint from an ARM7/9 target. More...

static int	arm7_9_restart_core (struct target *target)
	Restart the core of an ARM7/9 target. More...

static int	arm7_9_restore_context (struct target *target)
	Restore the processor context on an ARM7/9 target. More...

int	arm7_9_resume (struct target *target, int current, target_addr_t address, int handle_breakpoints, int debug_execution)

static int	arm7_9_set_breakpoint (struct target target, struct breakpoint breakpoint)
	Set either a hardware or software breakpoint on an ARM7/9 target. More...

static int	arm7_9_set_software_breakpoints (struct arm7_9_common *arm7_9)
	Setup an ARM7/9 target's embedded ICE registers for software breakpoints. More...

static int	arm7_9_set_watchpoint (struct target target, struct watchpoint watchpoint)
	Sets a watchpoint for an ARM7/9 target in one of the watchpoint units. More...

static int	arm7_9_setup (struct target *target)
	Setup the common pieces for an ARM7/9 target after reset or on startup. More...

static int	arm7_9_setup_semihosting (struct target *target, int enable)

int	arm7_9_soft_reset_halt (struct target *target)
	Issue a software reset and halt to an ARM7/9 target. More...

int	arm7_9_step (struct target *target, int current, target_addr_t address, int handle_breakpoints)

int	arm7_9_target_request_data (struct target target, uint32_t size, uint8_t buffer)
	Get some data from the ARM7/9 target. More...

static int	arm7_9_unset_breakpoint (struct target target, struct breakpoint breakpoint)
	Unsets an existing breakpoint on an ARM7/9 target. More...

static int	arm7_9_unset_watchpoint (struct target target, struct watchpoint watchpoint)
	Unset an existing watchpoint and clear the used watchpoint unit. More...

static int	arm7_9_write_core_reg (struct target target, struct reg r, int num, enum arm_mode mode, uint8_t *value)

int	arm7_9_write_memory (struct target target, target_addr_t address, uint32_t size, uint32_t count, const uint8_t buffer)

int	arm7_9_write_memory_no_opt (struct target target, uint32_t address, uint32_t size, uint32_t count, const uint8_t buffer)

int	arm7_9_write_memory_opt (struct target target, target_addr_t address, uint32_t size, uint32_t count, const uint8_t buffer)

	COMMAND_HANDLER (handle_arm7_9_dbgrq_command)

	COMMAND_HANDLER (handle_arm7_9_dcc_downloads_command)

	COMMAND_HANDLER (handle_arm7_9_fast_memory_access_command)

Variables
static const struct command_registration	arm7_9_any_command_handlers []

const struct command_registration	arm7_9_command_handlers []

static const uint8_t *	dcc_buffer

static const uint32_t	dcc_code []

static int	dcc_count

Detailed Description

Hold common code supporting the ARM7 and ARM9 core generations.

While the ARM core implementations evolved substantially during these two generations, they look quite similar from the JTAG perspective. Both have similar debug facilities, based on the same two scan chains providing access to the core and to an EmbeddedICE module. Both can support similar ETM and ETB modules, for tracing. And both expose what could be viewed as "ARM Classic", with multiple processor modes, shadowed registers, and support for the Thumb instruction set.

Processor differences include things like presence or absence of MMU and cache, pipeline sizes, use of a modified Harvard Architecture (with separate instruction and data buses from the CPU), support for cpu clock gating during idle, and more.

Definition in file arm7_9_common.c.

Function Documentation

◆ arm7_9_add_breakpoint()

int arm7_9_add_breakpoint	(	struct target *	target,
		struct breakpoint *	breakpoint
	)

Add a breakpoint to an ARM7/9 target.

This makes sure that there are no dangling breakpoints and that the desired breakpoint can be added.

Parameters

target	Pointer to the target ARM7/9 device to add a breakpoint to
breakpoint	Pointer to the breakpoint to be added

Returns: An error status if there is a problem adding the breakpoint or the result of setting the breakpoint

Definition at line 376 of file arm7_9_common.c.

References arm7_9_assign_wp(), arm7_9_clear_watchpoints(), arm7_9_set_breakpoint(), BKPT_HARD, arm7_9_common::breakpoint_count, ERROR_TARGET_RESOURCE_NOT_AVAILABLE, breakpoint::length, LOG_INFO, target_to_arm7_9(), breakpoint::type, and arm7_9_common::wp_available.

◆ arm7_9_add_watchpoint()

int arm7_9_add_watchpoint	(	struct target *	target,
		struct watchpoint *	watchpoint
	)

Add a watchpoint to an ARM7/9 target.

If there are no watchpoint units available, an error response is returned.

Parameters

target	Pointer to the ARM7/9 target to add a watchpoint to
watchpoint	Pointer to the watchpoint to be added

Returns: Error status while trying to add the watchpoint

Definition at line 563 of file arm7_9_common.c.

References ERROR_OK, ERROR_TARGET_RESOURCE_NOT_AVAILABLE, watchpoint::length, target_to_arm7_9(), and arm7_9_common::wp_available.

◆ arm7_9_assert_reset()

int arm7_9_assert_reset ( struct target * target )

Asserts the reset (SRST) on an ARM7/9 target.

Some -S targets (ARM966E-S in the STR912 isn't affected, ARM926EJ-S in the LPC3180 and AT91SAM9260 is affected) completely stop the JTAG clock while the core is held in reset (SRST). It isn't possible to program the halt condition once reset is asserted, hence a hook that allows the target to set up its reset-halt condition is setup prior to asserting reset.

Parameters

target Pointer to an ARM7/9 target to assert reset on

Returns: ERROR_FAIL if the JTAG device does not have SRST, otherwise ERROR_OK

Definition at line 862 of file arm7_9_common.c.

References arm7_9_common::arm, arm::core_cache, DBG_REASON_DBGRQ, target::debug_reason, arm7_9_common::eice_cache, EICE_VEC_CATCH, EICE_W0_ADDR_MASK, EICE_W0_ADDR_VALUE, EICE_W0_CONTROL_MASK, EICE_W0_CONTROL_VALUE, EICE_W0_DATA_MASK, EICE_W_CTRL_ENABLE, EICE_W_CTRL_NOPC, embeddedice_write_reg(), ERROR_FAIL, ERROR_OK, ERROR_TARGET_NOT_EXAMINED, arm7_9_common::has_vector_catch, jtag_add_reset(), jtag_add_runtest(), jtag_add_sleep(), jtag_get_reset_config(), jtag_reset_config, LOG_DEBUG, LOG_ERROR, LOG_WARNING, reg_cache::reg_list, register_cache_invalidate(), target::reset_halt, RESET_HAS_SRST, RESET_SRST_NO_GATING, RESET_SRST_PULLS_TRST, srst_asserted, target::state, TAP_IDLE, TARGET_EVENT_RESET_ASSERT, target_handle_event(), target_has_event_action(), target_name(), TARGET_RESET, target_state_name(), target_to_arm7_9(), and target_was_examined().

Referenced by feroceon_assert_reset().

◆ arm7_9_assign_wp()

static void arm7_9_assign_wp	(	struct arm7_9_common *	arm7_9,
		struct breakpoint *	breakpoint
	)

static

Assign a watchpoint to one of the two available hardware comparators in an ARM7 or ARM9 target.

Parameters

arm7_9	Pointer to the common struct for an ARM7/9 target
breakpoint	Pointer to the breakpoint to be used as a watchpoint

Definition at line 81 of file arm7_9_common.c.

References breakpoint::address, breakpoint_hw_set(), LOG_DEBUG, LOG_ERROR, breakpoint::number, TARGET_PRIxADDR, breakpoint::unique_id, arm7_9_common::wp0_used, arm7_9_common::wp1_used, and arm7_9_common::wp_available.

Referenced by arm7_9_add_breakpoint(), and arm7_9_set_breakpoint().

◆ arm7_9_bulk_write_memory()

int arm7_9_bulk_write_memory	(	struct target *	target,
		target_addr_t	address,
		uint32_t	count,
		const uint8_t *	buffer
	)

Definition at line 2586 of file arm7_9_common.c.

References working_area::address, arm7_9_dcc_completion(), arm7_9_write_memory_no_opt(), ARM_COMMON_MAGIC, ARM_MODE_SVC, ARM_STATE_ARM, armv4_5_run_algorithm_inner(), ARRAY_SIZE, buf_get_u32(), buf_set_u32(), buffer, arm_algorithm::common_magic, arm_algorithm::core_mode, arm_algorithm::core_state, count, dcc_buffer, dcc_code, dcc_count, arm7_9_common::dcc_downloads, arm7_9_common::dcc_working_area, destroy_reg_param(), ERROR_FAIL, ERROR_OK, ERROR_TARGET_RESOURCE_NOT_AVAILABLE, ERROR_TARGET_UNALIGNED_ACCESS, init_reg_param(), LOG_ERROR, LOG_INFO, NULL, PARAM_IN_OUT, target_alloc_working_area(), target_buffer_set_u32_array(), TARGET_PRIxADDR, target_to_arm7_9(), and reg_param::value.

Referenced by arm7tdmi_init_arch_info(), arm9tdmi_init_arch_info(), and fa526_init_arch_info_2().

◆ arm7_9_check_reset()

int arm7_9_check_reset ( struct target * target )

Definition at line 2700 of file arm7_9_common.c.

References arm7_9_common::dcc_downloads, ERROR_OK, arm7_9_common::fast_memory_access, get_target_reset_nag(), LOG_WARNING, target_to_arm7_9(), and target::working_area_size.

◆ arm7_9_clear_halt()

static int arm7_9_clear_halt ( struct target * target )

static

Clears the halt condition for an ARM7/9 target.

If it isn't coming out of reset and if DBGRQ is used, it is programmed to be deasserted. If the reset vector catch was used, it is restored. Otherwise, the control value is restored and the watchpoint unit is restored if it was in use.

Parameters

target Pointer to the ARM7/9 target to have halt cleared

Returns: Always ERROR_OK

Definition at line 1010 of file arm7_9_common.c.

References buf_set_u32(), arm7_9_common::debug_entry_from_reset, arm7_9_common::eice_cache, EICE_DBG_CONTROL_DBGRQ, EICE_DBG_CTRL, EICE_VEC_CATCH, EICE_W0_ADDR_MASK, EICE_W0_ADDR_VALUE, EICE_W0_CONTROL_MASK, EICE_W0_CONTROL_VALUE, EICE_W0_DATA_MASK, embeddedice_store_reg(), ERROR_OK, arm7_9_common::has_vector_catch, reg_cache::reg_list, target_to_arm7_9(), arm7_9_common::use_dbgrq, reg::value, and arm7_9_common::wp0_used.

Referenced by arm7_9_debug_entry(), and arm7_9_soft_reset_halt().

◆ arm7_9_clear_watchpoints()

static int arm7_9_clear_watchpoints ( struct arm7_9_common * arm7_9 )

static

Clear watchpoints for an ARM7/9 target.

Parameters

arm7_9 Pointer to the common struct for an ARM7/9 target

Returns: JTAG error status after executing queue

Definition at line 60 of file arm7_9_common.c.

References arm7_9_common::eice_cache, EICE_W0_CONTROL_VALUE, EICE_W1_CONTROL_VALUE, embeddedice_write_reg(), jtag_execute_queue(), LOG_DEBUG, reg_cache::reg_list, arm7_9_common::sw_breakpoint_count, arm7_9_common::sw_breakpoints_added, arm7_9_common::wp0_used, arm7_9_common::wp1_used, arm7_9_common::wp1_used_default, arm7_9_common::wp_available, and arm7_9_common::wp_available_max.

Referenced by arm7_9_add_breakpoint(), arm7_9_remove_breakpoint(), and arm7_9_setup().

◆ arm7_9_dcc_completion()

static int arm7_9_dcc_completion	(	struct target *	target,
		uint32_t	exit_point,
		unsigned int	timeout_ms,
		void *	arch_info
	)

static

Definition at line 2520 of file arm7_9_common.c.

References embeddedice_reg::addr, reg::arch_info, buffer, count, dcc_buffer, dcc_count, arm7_9_common::eice_cache, EICE_COMMS_DATA, embeddedice_write_dcc(), embeddedice_write_reg(), target::endianness, ERROR_OK, fast_target_buffer_get_u32(), embeddedice_reg::jtag_info, reg_cache::reg_list, arm_jtag::tap, TARGET_DEBUG_RUNNING, target_halt(), TARGET_HALTED, TARGET_LITTLE_ENDIAN, target_to_arm7_9(), and target_wait_state().

Referenced by arm7_9_bulk_write_memory().

◆ arm7_9_deassert_reset()

int arm7_9_deassert_reset ( struct target * target )

Deassert the reset (SRST) signal on an ARM7/9 target.

If SRST pulls TRST and the target is being reset into a halt, a warning will be triggered because it is not possible to reset into a halted mode in this case. The target is halted using the target's functions.

Parameters

target Pointer to the target to have the reset deasserted

Returns: ERROR_OK or an error from polling or halting the target

Definition at line 967 of file arm7_9_common.c.

References ERROR_OK, jtag_add_reset(), jtag_get_reset_config(), jtag_reset_config, LOG_DEBUG, LOG_WARNING, target::reset_halt, RESET_SRST_PULLS_TRST, target_examine_one(), target_halt(), target_poll(), and target_state_name().

◆ arm7_9_debug_entry()

static int arm7_9_debug_entry ( struct target * target )

static

Handle an ARM7/9 target's entry into debug mode.

The halt is cleared on the ARM. The JTAG queue is then executed and the reason for debug entry is examined. Once done, the target is verified to be halted and the processor is forced into ARM mode. The core registers are saved for the current core mode and the program counter (register 15) is updated as needed. The core registers and CPSR and SPSR are saved for restoration later.

Parameters

target Pointer to target that is entering debug mode

Returns: Error code if anything fails, otherwise ERROR_OK

Definition at line 1225 of file arm7_9_common.c.

References arm7_9_common::arm, arm7_9_clear_halt(), arm_mode_name(), arm_reg_current(), arm_set_cpsr(), ARM_STATE_ARM, ARM_STATE_JAZELLE, ARM_STATE_THUMB, buf_get_u32(), buf_set_u32(), arm7_9_common::change_to_arm, arm::core_mode, arm::core_state, DBG_REASON_DBGRQ, arm7_9_common::dbgreq_adjust_pc, target::debug_reason, reg::dirty, arm7_9_common::eice_cache, EICE_DBG_CONTROL_DBGACK, EICE_DBG_CONTROL_DBGRQ, EICE_DBG_CONTROL_INTDIS, EICE_DBG_CTRL, EICE_DBG_STAT, EICE_DBG_STATUS_ITBIT, embeddedice_store_reg(), ERROR_OK, ERROR_TARGET_FAILURE, ERROR_TARGET_NOT_HALTED, arm7_9_common::examine_debug_reason, is_arm_mode(), jtag_execute_queue(), LOG_DEBUG, LOG_ERROR, LOG_TARGET_ERROR, arm7_9_common::post_debug_entry, arm7_9_common::read_core_regs, arm7_9_common::read_xpsr, reg_cache::reg_list, arm::spsr, target::state, TARGET_HALTED, target_to_arm7_9(), TARGET_UNKNOWN, arm7_9_common::use_dbgrq, reg::valid, and reg::value.

Referenced by arm7_9_poll(), arm7_9_resume(), and arm7_9_step().

◆ arm7_9_deinit()

void arm7_9_deinit ( struct target * target )

Definition at line 2690 of file arm7_9_common.c.

References arm_jtag_close_connection(), arm7_9_common::eice_cache, embeddedice_free_reg_cache(), arm7_9_common::jtag_info, target_to_arm7_9(), and target_was_examined().

Referenced by arm920t_deinit_target(), arm926ejs_deinit_target(), arm946e_deinit_target(), arm966e_deinit_target(), arm9tdmi_deinit_target(), and fa526_deinit_target().

◆ arm7_9_disable_eice_step()

void arm7_9_disable_eice_step ( struct target * target )

Definition at line 1888 of file arm7_9_common.c.

References arm7_9_common::eice_cache, EICE_W0_ADDR_MASK, EICE_W0_CONTROL_MASK, EICE_W0_CONTROL_VALUE, EICE_W0_DATA_MASK, EICE_W1_ADDR_MASK, EICE_W1_ADDR_VALUE, EICE_W1_CONTROL_MASK, EICE_W1_CONTROL_VALUE, EICE_W1_DATA_MASK, embeddedice_store_reg(), reg_cache::reg_list, and target_to_arm7_9().

Referenced by arm7tdmi_init_arch_info(), and arm9tdmi_disable_single_step().

◆ arm7_9_enable_breakpoints()

static void arm7_9_enable_breakpoints ( struct target * target )

static

Enable the breakpoints on an ARM7/9 target.

The target's breakpoints are iterated through and are set on the target.

Parameters

target Pointer to the ARM7/9 target to enable breakpoints on

Definition at line 1688 of file arm7_9_common.c.

References arm7_9_set_breakpoint(), target::breakpoints, and breakpoint::next.

Referenced by arm7_9_resume().

◆ arm7_9_enable_eice_step()

void arm7_9_enable_eice_step	(	struct target *	target,
		uint32_t	next_pc
	)

Definition at line 1848 of file arm7_9_common.c.

References arm7_9_common::arm, buf_get_u32(), arm7_9_common::eice_cache, EICE_W0_ADDR_MASK, EICE_W0_CONTROL_MASK, EICE_W0_CONTROL_VALUE, EICE_W0_DATA_MASK, EICE_W1_ADDR_MASK, EICE_W1_ADDR_VALUE, EICE_W1_CONTROL_MASK, EICE_W1_CONTROL_VALUE, EICE_W1_DATA_MASK, EICE_W_CTRL_ENABLE, EICE_W_CTRL_NOPC, EICE_W_CTRL_RANGE, embeddedice_write_reg(), arm::pc, reg_cache::reg_list, target_to_arm7_9(), and reg::value.

Referenced by arm7tdmi_init_arch_info(), and arm9tdmi_enable_single_step().

◆ arm7_9_enable_watchpoints()

static void arm7_9_enable_watchpoints ( struct target * target )

static

Enable the watchpoints on an ARM7/9 target.

The target's watchpoints are iterated through and are set on the target if they aren't already set.

Parameters

target Pointer to the ARM7/9 target to enable watchpoints on

Definition at line 1671 of file arm7_9_common.c.

References arm7_9_set_watchpoint(), watchpoint::is_set, watchpoint::next, and target::watchpoints.

Referenced by arm7_9_resume().

◆ arm7_9_endianness_callback()

int arm7_9_endianness_callback	(	jtag_callback_data_t	pu8_in,
		jtag_callback_data_t	i_size,
		jtag_callback_data_t	i_be,
		jtag_callback_data_t	i_flip
	)

Definition at line 2718 of file arm7_9_common.c.

References ERROR_OK, flip_u32(), h_u16_to_be(), h_u16_to_le(), h_u32_to_be(), h_u32_to_le(), le_to_h_u16(), le_to_h_u32(), and size.

Referenced by arm7tdmi_clock_data_in_endianness(), and arm9tdmi_clock_data_in_endianness().

◆ arm7_9_examine()

int arm7_9_examine ( struct target * target )

Perform per-target setup that requires JTAG access.

Definition at line 2658 of file arm7_9_common.c.

References arm7_9_common::arm, arm7_9_setup(), arm7_9_common::eice_cache, embeddedice_build_reg_cache(), embeddedice_setup(), ERROR_FAIL, ERROR_OK, arm::etm, etm_build_reg_cache(), etm_setup(), arm7_9_common::jtag_info, reg_cache::next, target::reg_cache, register_get_last_cache_p(), target_set_examined(), target_to_arm7_9(), and target_was_examined().

◆ arm7_9_execute_fast_sys_speed()

static int arm7_9_execute_fast_sys_speed ( struct target * target )

static

Restarts the target by sending a RESTART instruction and moving the JTAG state to IDLE.

This validates that DBGACK and SYSCOMP are set without waiting until they are.

Parameters

target Pointer to the target to issue commands to

Returns: Always ERROR_OK

Definition at line 662 of file arm7_9_common.c.

References arm_jtag_set_instr(), buf_set_u32(), arm7_9_common::eice_cache, EICE_DBG_STAT, embeddedice_read_reg_w_check(), ERROR_OK, arm7_9_common::jtag_info, arm7_9_common::need_bypass_before_restart, NULL, reg_cache::reg_list, arm_jtag::tap, TAP_IDLE, and target_to_arm7_9().

Referenced by arm7_9_read_memory(), and arm7_9_write_memory().

◆ arm7_9_execute_sys_speed()

int arm7_9_execute_sys_speed ( struct target * target )

Restarts the target by sending a RESTART instruction and moving the JTAG state to IDLE.

This includes a timeout waiting for DBGACK and SYSCOMP to be asserted by the processor.

Parameters

target Pointer to target to issue commands to

Returns: Error status if there is a timeout or a problem while executing the JTAG queue

Definition at line 611 of file arm7_9_common.c.

References alive_sleep(), arm_jtag_set_instr(), buf_get_u32(), debug_level, arm7_9_common::eice_cache, EICE_DBG_STAT, EICE_DBG_STATUS_DBGACK, EICE_DBG_STATUS_SYSCOMP, embeddedice_read_reg(), ERROR_OK, ERROR_TARGET_TIMEOUT, jtag_execute_queue(), arm7_9_common::jtag_info, keep_alive(), LOG_ERROR, arm7_9_common::need_bypass_before_restart, NULL, reg_cache::reg_list, reg::size, arm_jtag::tap, TAP_IDLE, target_to_arm7_9(), timeval_ms(), and reg::value.

Referenced by arm7_9_read_memory(), arm7_9_resume(), arm7_9_step(), arm7_9_write_memory(), arm920t_execute_cp15(), feroceon_read_cp15(), and feroceon_write_cp15().

◆ arm7_9_full_context()

static int arm7_9_full_context ( struct target * target )

static

Validate the full context for an ARM7/9 target in all processor modes.

If there are any invalid registers for the target, they will all be read. This includes the PSR.

Parameters

target Pointer to the ARM7/9 target to capture the full context from

Returns: Error if the target is not halted, has an invalid core mode, or if the JTAG queue fails to execute

Definition at line 1379 of file arm7_9_common.c.

References arm7_9_common::arm, ARMV4_5_CORE_REG_MODE, armv4_5_number_to_mode(), buf_get_u32(), buf_set_u32(), arm::core_cache, arm::core_mode, arm::cpsr, ERROR_FAIL, ERROR_OK, ERROR_TARGET_NOT_HALTED, is_arm_mode(), jtag_execute_queue(), LOG_DEBUG, LOG_ERROR, LOG_TARGET_ERROR, mask, arm7_9_common::read_core_regs, arm7_9_common::read_xpsr, target::state, TARGET_HALTED, target_to_arm7_9(), reg::value, and arm7_9_common::write_xpsr_im8.

◆ arm7_9_halt()

int arm7_9_halt ( struct target * target )

Halt an ARM7/9 target.

This is accomplished by either asserting the DBGRQ line or by programming a watchpoint to trigger on any address. It is considered a bug to call this function while the target is in the TARGET_RESET state.

Parameters

target Pointer to the ARM7/9 target to be halted

Returns: Always ERROR_OK

Definition at line 1167 of file arm7_9_common.c.

References buf_set_u32(), DBG_REASON_DBGRQ, target::debug_reason, arm7_9_common::eice_cache, EICE_DBG_CONTROL_DBGRQ, EICE_DBG_CTRL, EICE_W0_ADDR_MASK, EICE_W0_CONTROL_MASK, EICE_W0_CONTROL_VALUE, EICE_W0_DATA_MASK, EICE_W_CTRL_ENABLE, EICE_W_CTRL_NOPC, embeddedice_store_reg(), embeddedice_write_reg(), ERROR_OK, LOG_DEBUG, LOG_ERROR, LOG_WARNING, reg_cache::reg_list, arm7_9_common::set_special_dbgrq, target::state, TARGET_HALTED, TARGET_RESET, target_state_name(), target_to_arm7_9(), TARGET_UNKNOWN, arm7_9_common::use_dbgrq, and reg::value.

Referenced by feroceon_assert_reset().

◆ arm7_9_handle_target_request()

static int arm7_9_handle_target_request ( void * priv )

static

Handles requests to an ARM7/9 target.

If debug messaging is enabled, the target is running and the DCC control register has the W bit high, this will execute the request on the target.

Parameters

priv	Void pointer expected to be a struct target pointer

Returns: ERROR_OK unless there are issues with the JTAG queue or when reading from the Embedded ICE unit

Definition at line 739 of file arm7_9_common.c.

References buf_get_u32(), target::dbg_msg_enabled, arm7_9_common::eice_cache, EICE_COMMS_CTRL, embeddedice_read_reg(), embeddedice_receive(), ERROR_OK, jtag_execute_queue(), arm7_9_common::jtag_info, priv, reg_cache::reg_list, target::state, target_request(), TARGET_RUNNING, target_to_arm7_9(), target_was_examined(), and reg::value.

◆ arm7_9_init_arch_info()

int arm7_9_init_arch_info	(	struct target *	target,
		struct arm7_9_common *	arm7_9
	)

Definition at line 2846 of file arm7_9_common.c.

Referenced by arm7tdmi_init_arch_info(), arm9tdmi_init_arch_info(), and fa526_init_arch_info_2().

◆ arm7_9_poll()

int arm7_9_poll ( struct target * target )

Polls an ARM7/9 target for its current status.

If DBGACK is set, the target is manipulated to the right halted state based on its current state. This is what happens:

State	Action
TARGET_RUNNING \| TARGET_RESET	Enters debug mode. If TARGET_RESET, pc may be checked
TARGET_UNKNOWN	Warning is logged
TARGET_DEBUG_RUNNING	Enters debug mode
TARGET_HALTED	Nothing

If the target does not end up in the halted state, a warning is produced. If DBGACK is cleared, then the target is expected to either be running or running in debug.

Parameters

target Pointer to the ARM7/9 target to poll

Returns: ERROR_OK or an error status if a command fails

Definition at line 796 of file arm7_9_common.c.

References arm7_9_debug_entry(), arm_semihosting(), buf_get_u32(), arm7_9_common::eice_cache, EICE_DBG_STAT, EICE_DBG_STATUS_DBGACK, embeddedice_read_reg(), ERROR_OK, jtag_execute_queue(), LOG_DEBUG, LOG_WARNING, reg_cache::reg_list, target::state, target_call_event_callbacks(), TARGET_DEBUG_RUNNING, TARGET_EVENT_DEBUG_HALTED, TARGET_EVENT_HALTED, TARGET_HALTED, TARGET_RESET, TARGET_RUNNING, target_to_arm7_9(), TARGET_UNKNOWN, and reg::value.

◆ arm7_9_read_core_reg()

static int arm7_9_read_core_reg	(	struct target *	target,
		struct reg *	r,
		int	num,
		enum arm_mode	mode
	)

static

Definition at line 1990 of file arm7_9_common.c.

References reg::arch_info, arm7_9_common::arm, ARM_MODE_ANY, buf_get_u32(), buf_set_u32(), arm::core_mode, arm::cpsr, reg::dirty, ERROR_COMMAND_SYNTAX_ERROR, ERROR_FAIL, ERROR_OK, is_arm_mode(), jtag_execute_queue(), arm_reg::mode, mode, arm7_9_common::read_core_regs, arm7_9_common::read_xpsr, target_to_arm7_9(), reg::valid, reg::value, and arm7_9_common::write_xpsr_im8.

◆ arm7_9_read_memory()

int arm7_9_read_memory	(	struct target *	target,
		target_addr_t	address,
		uint32_t	size,
		uint32_t	count,
		uint8_t *	buffer
	)

Definition at line 2102 of file arm7_9_common.c.

References arm7_9_common::arm, arm7_9_execute_fast_sys_speed(), arm7_9_execute_sys_speed(), ARM_MODE_ABT, arm_reg_current(), buf_get_u32(), buffer, arm::core_mode, count, arm::cpsr, reg::dirty, ERROR_COMMAND_SYNTAX_ERROR, ERROR_FAIL, ERROR_OK, ERROR_TARGET_DATA_ABORT, ERROR_TARGET_NOT_HALTED, ERROR_TARGET_UNALIGNED_ACCESS, arm7_9_common::fast_memory_access, is_arm_mode(), jtag_execute_queue(), keep_alive(), arm7_9_common::load_byte_reg, arm7_9_common::load_hword_reg, arm7_9_common::load_word_regs, LOG_DEBUG, LOG_ERROR, LOG_TARGET_ERROR, LOG_WARNING, arm7_9_common::read_core_regs_target_buffer, arm7_9_common::read_xpsr, size, target::state, TARGET_HALTED, TARGET_PRIxADDR, target_to_arm7_9(), reg::valid, reg::value, arm7_9_common::write_core_regs, and arm7_9_common::write_xpsr_im8.

Referenced by arm720t_init_arch_info(), arm720t_read_memory(), arm920t_init_arch_info(), arm920t_read_memory(), arm926ejs_init_arch_info(), arm946e_read_memory(), and fa526_init_arch_info().

◆ arm7_9_remove_breakpoint()

int arm7_9_remove_breakpoint	(	struct target *	target,
		struct breakpoint *	breakpoint
	)

Removes a breakpoint from an ARM7/9 target.

This will make sure there are no dangling breakpoints and updates available watchpoints if it is a hardware breakpoint.

Parameters

target	Pointer to the target to have a breakpoint removed
breakpoint	Pointer to the breakpoint to be removed

Returns: Error status if there was a problem unsetting the breakpoint or the watchpoints could not be cleared

Definition at line 415 of file arm7_9_common.c.

References arm7_9_clear_watchpoints(), arm7_9_unset_breakpoint(), BKPT_HARD, arm7_9_common::breakpoint_count, ERROR_OK, target_to_arm7_9(), breakpoint::type, and arm7_9_common::wp_available.

◆ arm7_9_remove_watchpoint()

int arm7_9_remove_watchpoint	(	struct target *	target,
		struct watchpoint *	watchpoint
	)

Remove a watchpoint from an ARM7/9 target.

The watchpoint will be unset and the used watchpoint unit will be reopened.

Parameters

target	Pointer to the target to remove a watchpoint from
watchpoint	Pointer to the watchpoint to be removed

Returns: Result of trying to unset the watchpoint

Definition at line 586 of file arm7_9_common.c.

References arm7_9_unset_watchpoint(), ERROR_OK, watchpoint::is_set, target_to_arm7_9(), and arm7_9_common::wp_available.

◆ arm7_9_restart_core()

static int arm7_9_restart_core ( struct target * target )

static

Restart the core of an ARM7/9 target.

A RESTART command is sent to the instruction register and the JTAG state is set to TAP_IDLE causing a core restart.

Parameters

target Pointer to the ARM7/9 target to be restarted

Returns: Result of executing the JTAG queue

Definition at line 1643 of file arm7_9_common.c.

References arm_jtag_set_instr(), ERROR_OK, jtag_add_runtest(), jtag_execute_queue(), arm7_9_common::jtag_info, arm7_9_common::need_bypass_before_restart, NULL, arm_jtag::tap, TAP_IDLE, and target_to_arm7_9().

Referenced by arm7_9_resume().

◆ arm7_9_restore_context()

static int arm7_9_restore_context ( struct target * target )

static

Restore the processor context on an ARM7/9 target.

The full processor context is analyzed to see if any of the registers are dirty on this end, but have a valid new value. If this is the case, the processor is changed to the appropriate mode and the new register values are written out to the processor. If there happens to be a dirty register with an invalid value, an error will be logged.

Parameters

target Pointer to the ARM7/9 target to have its context restored

Returns: Error status if the target is not halted or the core mode in the armv4_5 struct is invalid.

Definition at line 1497 of file arm7_9_common.c.

References reg::arch_info, arm7_9_common::arm, ARM_MODE_ANY, arm_mode_name(), ARM_MODE_SYS, ARM_MODE_USR, ARMV4_5_CORE_REG_MODE, armv4_5_number_to_mode(), buf_get_u32(), arm::core_cache, arm::core_mode, arm::cpsr, reg::dirty, ERROR_FAIL, ERROR_OK, ERROR_TARGET_NOT_HALTED, is_arm_mode(), LOG_DEBUG, LOG_ERROR, LOG_TARGET_ERROR, mask, arm_reg::mode, reg::name, arm::pc, arm7_9_common::pre_restore_context, regs, target::state, TARGET_HALTED, target_to_arm7_9(), reg::valid, reg::value, arm7_9_common::write_core_regs, arm7_9_common::write_pc, arm7_9_common::write_xpsr, and arm7_9_common::write_xpsr_im8.

Referenced by arm7_9_resume(), and arm7_9_step().

◆ arm7_9_resume()

int arm7_9_resume	(	struct target *	target,
		int	current,
		target_addr_t	address,
		int	handle_breakpoints,
		int	debug_execution
	)

Definition at line 1699 of file arm7_9_common.c.

References breakpoint::address, arm7_9_common::arm, arm7_9_debug_entry(), arm7_9_enable_breakpoints(), arm7_9_enable_watchpoints(), arm7_9_execute_sys_speed(), arm7_9_restart_core(), arm7_9_restore_context(), arm7_9_set_breakpoint(), arm7_9_unset_breakpoint(), arm_simulate_step(), ARM_STATE_ARM, ARM_STATE_THUMB, arm7_9_common::branch_resume, arm7_9_common::branch_resume_thumb, breakpoint_find(), buf_get_u32(), buf_set_u32(), arm::core_cache, arm::core_state, DBG_REASON_NOTHALTED, DBG_REASON_SINGLESTEP, target::debug_reason, arm7_9_common::disable_single_step, arm7_9_common::eice_cache, EICE_DBG_CONTROL_DBGACK, EICE_DBG_CONTROL_INTDIS, EICE_DBG_CTRL, embeddedice_write_reg(), arm7_9_common::enable_single_step, ERROR_FAIL, ERROR_OK, ERROR_TARGET_NOT_HALTED, LOG_DEBUG, LOG_ERROR, LOG_TARGET_ERROR, arm::pc, reg_cache::reg_list, register_cache_invalidate(), reg::size, target::state, target_call_event_callbacks(), TARGET_DEBUG_RUNNING, TARGET_EVENT_DEBUG_RESUMED, TARGET_EVENT_RESUMED, target_free_all_working_areas(), TARGET_HALTED, TARGET_PRIxADDR, target_read_u32(), TARGET_RUNNING, target_to_arm7_9(), TARGET_UNKNOWN, breakpoint::unique_id, and reg::value.

Referenced by feroceon_bulk_write_memory().

◆ arm7_9_set_breakpoint()

static int arm7_9_set_breakpoint	(	struct target *	target,
		struct breakpoint *	breakpoint
	)

static

Set either a hardware or software breakpoint on an ARM7/9 target.

The breakpoint is set up even if it is already set. Some actions, e.g. reset, might have erased the values in Embedded ICE.

Parameters

target	Pointer to the target device to set the breakpoints on
breakpoint	Pointer to the breakpoint to be set

Returns: For hardware breakpoints, this is the result of executing the JTAG queue. For software breakpoints, this will be the status of the required memory reads and writes

Definition at line 176 of file arm7_9_common.c.

References breakpoint::address, arm7_9_assign_wp(), arm7_9_set_software_breakpoints(), arm7_9_common::arm_bkpt, BKPT_HARD, BKPT_SOFT, arm7_9_common::eice_cache, EICE_W0_ADDR_MASK, EICE_W0_ADDR_VALUE, EICE_W0_CONTROL_MASK, EICE_W0_CONTROL_VALUE, EICE_W0_DATA_MASK, EICE_W1_ADDR_MASK, EICE_W1_ADDR_VALUE, EICE_W1_CONTROL_MASK, EICE_W1_CONTROL_VALUE, EICE_W1_DATA_MASK, EICE_W_CTRL_ENABLE, EICE_W_CTRL_NOPC, embeddedice_set_reg(), ERROR_OK, ERROR_TARGET_NOT_HALTED, breakpoint::is_set, jtag_execute_queue(), breakpoint::length, LOG_DEBUG, LOG_ERROR, LOG_TARGET_ERROR, mask, breakpoint::number, breakpoint::orig_instr, reg_cache::reg_list, target::state, arm7_9_common::sw_breakpoint_count, TARGET_HALTED, TARGET_PRIxADDR, target_read_memory(), target_read_u16(), target_read_u32(), target_to_arm7_9(), target_write_u16(), target_write_u32(), arm7_9_common::thumb_bkpt, breakpoint::type, and breakpoint::unique_id.

Referenced by arm7_9_add_breakpoint(), arm7_9_enable_breakpoints(), arm7_9_resume(), and arm7_9_step().

◆ arm7_9_set_software_breakpoints()

static int arm7_9_set_software_breakpoints ( struct arm7_9_common * arm7_9 )

static

Setup an ARM7/9 target's embedded ICE registers for software breakpoints.

Parameters

arm7_9 Pointer to common struct for ARM7/9 targets

Returns: Error codes if there is a problem finding a watchpoint or the result of executing the JTAG queue

Definition at line 108 of file arm7_9_common.c.

References arm7_9_common::arm_bkpt, arm7_9_common::eice_cache, EICE_W0_ADDR_MASK, EICE_W0_CONTROL_MASK, EICE_W0_CONTROL_VALUE, EICE_W0_DATA_MASK, EICE_W0_DATA_VALUE, EICE_W1_ADDR_MASK, EICE_W1_CONTROL_MASK, EICE_W1_CONTROL_VALUE, EICE_W1_DATA_MASK, EICE_W1_DATA_VALUE, EICE_W_CTRL_ENABLE, EICE_W_CTRL_NOPC, embeddedice_set_reg(), ERROR_FAIL, ERROR_OK, ERROR_TARGET_RESOURCE_NOT_AVAILABLE, jtag_execute_queue(), LOG_DEBUG, LOG_ERROR, LOG_WARNING, reg_cache::reg_list, arm7_9_common::sw_breakpoints_added, arm7_9_common::wp0_used, arm7_9_common::wp1_used, and arm7_9_common::wp_available.

Referenced by arm7_9_set_breakpoint().

◆ arm7_9_set_watchpoint()

static int arm7_9_set_watchpoint	(	struct target *	target,
		struct watchpoint *	watchpoint
	)

static

Sets a watchpoint for an ARM7/9 target in one of the watchpoint units.

It is considered a bug to call this function when there are no available watchpoint units.

Parameters

target	Pointer to an ARM7/9 target to set a watchpoint on
watchpoint	Pointer to the watchpoint to be set

Returns: Error status if watchpoint set fails or the result of executing the JTAG queue

Definition at line 448 of file arm7_9_common.c.

References watchpoint::address, arm7_9_common::eice_cache, EICE_W0_ADDR_MASK, EICE_W0_ADDR_VALUE, EICE_W0_CONTROL_MASK, EICE_W0_CONTROL_VALUE, EICE_W0_DATA_MASK, EICE_W0_DATA_VALUE, EICE_W1_ADDR_MASK, EICE_W1_ADDR_VALUE, EICE_W1_CONTROL_MASK, EICE_W1_CONTROL_VALUE, EICE_W1_DATA_MASK, EICE_W1_DATA_VALUE, EICE_W_CTRL_ENABLE, EICE_W_CTRL_NOPC, embeddedice_set_reg(), ERROR_OK, ERROR_TARGET_NOT_HALTED, jtag_execute_queue(), watchpoint::length, LOG_ERROR, LOG_TARGET_ERROR, watchpoint::mask, mask, reg_cache::reg_list, watchpoint::rw, target::state, TARGET_HALTED, target_to_arm7_9(), watchpoint::value, WATCHPOINT_IGNORE_DATA_VALUE_MASK, watchpoint_set(), arm7_9_common::wp0_used, arm7_9_common::wp1_used, and WPT_ACCESS.

Referenced by arm7_9_enable_watchpoints().

◆ arm7_9_setup()

static int arm7_9_setup ( struct target * target )

static

Setup the common pieces for an ARM7/9 target after reset or on startup.

Parameters

target Pointer to an ARM7/9 target to setup

Returns: Result of clearing the watchpoints on the target

Definition at line 158 of file arm7_9_common.c.

References arm7_9_clear_watchpoints(), and target_to_arm7_9().

Referenced by arm7_9_examine().

◆ arm7_9_setup_semihosting()

static int arm7_9_setup_semihosting	(	struct target *	target,
		int	enable
	)

static

Definition at line 2818 of file arm7_9_common.c.

References BKPT_SOFT, breakpoint_add(), breakpoint_remove(), buf_set_u32(), arm7_9_common::eice_cache, EICE_VEC_CATCH, embeddedice_read_reg(), embeddedice_store_reg(), ERROR_OK, ERROR_TARGET_INVALID, arm7_9_common::has_vector_catch, is_arm7_9(), LOG_USER, reg_cache::reg_list, target_to_arm7_9(), reg::valid, and reg::value.

◆ arm7_9_soft_reset_halt()

int arm7_9_soft_reset_halt ( struct target * target )

Issue a software reset and halt to an ARM7/9 target.

The target is halted and then there is a wait until the processor shows the halt. This wait can timeout and results in an error being returned. The software reset involves clearing the halt, updating the debug control register, changing to ARM mode, reset of the program counter, and reset of all of the registers.

Parameters

target Pointer to the ARM7/9 target to be reset and halted by software

Returns: Error status if any of the commands fail, otherwise ERROR_OK

Definition at line 1062 of file arm7_9_common.c.

References alive_sleep(), arm7_9_common::arm, arm7_9_clear_halt(), arm_reg_current(), arm_set_cpsr(), ARM_STATE_THUMB, buf_get_u32(), buf_set_u32(), arm7_9_common::change_to_arm, arm::core_cache, arm::core_state, arm::cpsr, debug_level, reg::dirty, arm7_9_common::eice_cache, EICE_DBG_CONTROL_DBGACK, EICE_DBG_CONTROL_DBGRQ, EICE_DBG_CONTROL_INTDIS, EICE_DBG_CTRL, EICE_DBG_STAT, EICE_DBG_STATUS_DBGACK, EICE_DBG_STATUS_ITBIT, embeddedice_read_reg(), embeddedice_store_reg(), ERROR_OK, ERROR_TARGET_TIMEOUT, jtag_execute_queue(), keep_alive(), LOG_DEBUG, LOG_ERROR, arm::pc, reg_cache::reg_list, register_cache_invalidate(), target::state, target_call_event_callbacks(), TARGET_EVENT_HALTED, target_halt(), TARGET_HALTED, target_to_arm7_9(), timeval_ms(), reg::valid, and reg::value.

◆ arm7_9_step()

int arm7_9_step	(	struct target *	target,
		int	current,
		target_addr_t	address,
		int	handle_breakpoints
	)

Definition at line 1903 of file arm7_9_common.c.

References breakpoint::address, arm7_9_common::arm, arm7_9_debug_entry(), arm7_9_execute_sys_speed(), arm7_9_restore_context(), arm7_9_set_breakpoint(), arm7_9_unset_breakpoint(), arm_simulate_step(), ARM_STATE_ARM, ARM_STATE_THUMB, arm7_9_common::branch_resume, arm7_9_common::branch_resume_thumb, breakpoint_find(), buf_get_u32(), buf_set_u32(), arm::core_cache, arm::core_state, DBG_REASON_SINGLESTEP, target::debug_reason, arm7_9_common::disable_single_step, arm7_9_common::enable_single_step, ERROR_FAIL, ERROR_OK, ERROR_TARGET_NOT_HALTED, LOG_DEBUG, LOG_ERROR, LOG_TARGET_ERROR, NULL, arm::pc, register_cache_invalidate(), target::state, target_call_event_callbacks(), TARGET_EVENT_HALTED, TARGET_EVENT_RESUMED, TARGET_HALTED, target_read_u32(), target_to_arm7_9(), TARGET_UNKNOWN, and reg::value.

◆ arm7_9_target_request_data()

int arm7_9_target_request_data	(	struct target *	target,
		uint32_t	size,
		uint8_t *	buffer
	)

Get some data from the ARM7/9 target.

Parameters

target	Pointer to the ARM7/9 target to read data from
size	The number of 32bit words to be read
buffer	Pointer to the buffer that will hold the data

Returns: The result of receiving data from the Embedded ICE unit

Definition at line 709 of file arm7_9_common.c.

References buffer, embeddedice_receive(), ERROR_OK, h_u32_to_le(), arm7_9_common::jtag_info, size, and target_to_arm7_9().

◆ arm7_9_unset_breakpoint()

static int arm7_9_unset_breakpoint	(	struct target *	target,
		struct breakpoint *	breakpoint
	)

static

Unsets an existing breakpoint on an ARM7/9 target.

If it is a hardware breakpoint, the watchpoint used will be freed and the Embedded ICE registers will be updated. Otherwise, the software breakpoint will be restored to its original instruction if it hasn't already been modified.

Parameters

target	Pointer to ARM7/9 target to unset the breakpoint from
breakpoint	Pointer to breakpoint to be unset

Returns: For hardware breakpoints, this is the result of executing the JTAG queue. For software breakpoints, this will be the status of the required memory reads and writes

Definition at line 288 of file arm7_9_common.c.

References breakpoint::address, arm7_9_common::arm_bkpt, BKPT_HARD, arm7_9_common::eice_cache, EICE_W0_CONTROL_VALUE, EICE_W1_CONTROL_VALUE, embeddedice_set_reg(), ERROR_OK, breakpoint::is_set, jtag_execute_queue(), breakpoint::length, LOG_DEBUG, LOG_WARNING, breakpoint::number, breakpoint::orig_instr, reg_cache::reg_list, arm7_9_common::sw_breakpoint_count, arm7_9_common::sw_breakpoints_added, target_buffer_get_u16(), target_buffer_get_u32(), TARGET_PRIxADDR, target_read_memory(), target_to_arm7_9(), target_write_memory(), arm7_9_common::thumb_bkpt, breakpoint::type, breakpoint::unique_id, arm7_9_common::wp0_used, arm7_9_common::wp1_used, and arm7_9_common::wp_available.

Referenced by arm7_9_remove_breakpoint(), arm7_9_resume(), and arm7_9_step().

◆ arm7_9_unset_watchpoint()

static int arm7_9_unset_watchpoint	(	struct target *	target,
		struct watchpoint *	watchpoint
	)

static

Unset an existing watchpoint and clear the used watchpoint unit.

Parameters

target	Pointer to the target to have the watchpoint removed
watchpoint	Pointer to the watchpoint to be removed

Returns: Error status while trying to unset the watchpoint or the result of executing the JTAG queue

Definition at line 522 of file arm7_9_common.c.

References arm7_9_common::eice_cache, EICE_W0_CONTROL_VALUE, EICE_W1_CONTROL_VALUE, embeddedice_set_reg(), ERROR_OK, ERROR_TARGET_NOT_HALTED, watchpoint::is_set, jtag_execute_queue(), LOG_TARGET_ERROR, LOG_WARNING, watchpoint::number, reg_cache::reg_list, target::state, TARGET_HALTED, target_to_arm7_9(), arm7_9_common::wp0_used, and arm7_9_common::wp1_used.

Referenced by arm7_9_remove_watchpoint().

◆ arm7_9_write_core_reg()

static int arm7_9_write_core_reg	(	struct target *	target,
		struct reg *	r,
		int	num,
		enum arm_mode	mode,
		uint8_t *	value
	)

static

Definition at line 2046 of file arm7_9_common.c.

References reg::arch_info, arm7_9_common::arm, ARM_MODE_ANY, buf_get_u32(), arm::core_mode, arm::cpsr, reg::dirty, ERROR_COMMAND_SYNTAX_ERROR, ERROR_FAIL, is_arm_mode(), jtag_execute_queue(), arm_reg::mode, mode, arm::spsr, target_to_arm7_9(), reg::valid, reg::value, arm7_9_common::write_core_regs, arm7_9_common::write_xpsr, and arm7_9_common::write_xpsr_im8.

◆ arm7_9_write_memory()

int arm7_9_write_memory	(	struct target *	target,
		target_addr_t	address,
		uint32_t	size,
		uint32_t	count,
		const uint8_t *	buffer
	)

Definition at line 2272 of file arm7_9_common.c.

References arm7_9_common::arm, arm7_9_execute_fast_sys_speed(), arm7_9_execute_sys_speed(), ARM_MODE_ABT, arm_reg_current(), buf_get_u32(), buf_set_u32(), buffer, arm::core_mode, count, arm::cpsr, reg::dirty, arm7_9_common::eice_cache, EICE_DBG_CONTROL_DBGACK, EICE_DBG_CTRL, embeddedice_store_reg(), ERROR_COMMAND_SYNTAX_ERROR, ERROR_FAIL, ERROR_OK, ERROR_TARGET_DATA_ABORT, ERROR_TARGET_NOT_HALTED, ERROR_TARGET_UNALIGNED_ACCESS, arm7_9_common::fast_memory_access, is_arm_mode(), jtag_execute_queue(), keep_alive(), LOG_DEBUG, LOG_ERROR, LOG_TARGET_ERROR, LOG_WARNING, arm7_9_common::read_xpsr, reg_cache::reg_list, size, target::state, arm7_9_common::store_byte_reg, arm7_9_common::store_hword_reg, arm7_9_common::store_word_regs, target_buffer_get_u16(), target_buffer_get_u32(), TARGET_HALTED, TARGET_PRIxADDR, target_to_arm7_9(), reg::valid, reg::value, arm7_9_common::write_core_regs, and arm7_9_common::write_xpsr_im8.

Referenced by arm720t_init_arch_info(), arm7tdmi_init_arch_info(), arm920t_init_arch_info(), arm920t_write_memory(), arm926ejs_init_arch_info(), arm926ejs_write_memory(), arm9tdmi_init_arch_info(), dragonite_target_create(), and fa526_init_arch_info().

◆ arm7_9_write_memory_no_opt()

int arm7_9_write_memory_no_opt	(	struct target *	target,
		uint32_t	address,
		uint32_t	size,
		uint32_t	count,
		const uint8_t *	buffer
	)

Definition at line 2506 of file arm7_9_common.c.

References buffer, count, size, target_to_arm7_9(), and arm7_9_common::write_memory.

Referenced by arm7_9_bulk_write_memory(), and feroceon_bulk_write_memory().

◆ arm7_9_write_memory_opt()

int arm7_9_write_memory_opt	(	struct target *	target,
		target_addr_t	address,
		uint32_t	size,
		uint32_t	count,
		const uint8_t *	buffer
	)

Definition at line 2486 of file arm7_9_common.c.

References buffer, arm7_9_common::bulk_write_memory, count, ERROR_OK, size, target_to_arm7_9(), and arm7_9_common::write_memory.

Referenced by arm946e_write_memory().

◆ COMMAND_HANDLER() [1/3]

COMMAND_HANDLER ( handle_arm7_9_dbgrq_command )

Definition at line 2758 of file arm7_9_common.c.

References CMD, CMD_ARGC, CMD_ARGV, CMD_CTX, COMMAND_PARSE_ENABLE, command_print(), ERROR_OK, ERROR_TARGET_INVALID, get_current_target(), is_arm7_9(), target_to_arm7_9(), and arm7_9_common::use_dbgrq.

◆ COMMAND_HANDLER() [2/3]

COMMAND_HANDLER ( handle_arm7_9_dcc_downloads_command )

Definition at line 2798 of file arm7_9_common.c.

References CMD, CMD_ARGC, CMD_ARGV, CMD_CTX, COMMAND_PARSE_ENABLE, command_print(), arm7_9_common::dcc_downloads, ERROR_OK, ERROR_TARGET_INVALID, get_current_target(), is_arm7_9(), and target_to_arm7_9().

◆ COMMAND_HANDLER() [3/3]

COMMAND_HANDLER ( handle_arm7_9_fast_memory_access_command )

Definition at line 2778 of file arm7_9_common.c.

References CMD, CMD_ARGC, CMD_ARGV, CMD_CTX, COMMAND_PARSE_ENABLE, command_print(), ERROR_OK, ERROR_TARGET_INVALID, arm7_9_common::fast_memory_access, get_current_target(), is_arm7_9(), and target_to_arm7_9().

Variable Documentation

◆ arm7_9_any_command_handlers

const struct command_registration arm7_9_any_command_handlers[]

static

Initial value:

= {
    {
        .name = "dbgrq",
        .handler = handle_arm7_9_dbgrq_command,
        .mode = COMMAND_ANY,
        .usage = "['enable'|'disable']",
        .help = "use EmbeddedICE dbgrq instead of breakpoint "
            "for target halt requests",
    },
    {
        .name = "fast_memory_access",
        .handler = handle_arm7_9_fast_memory_access_command,
        .mode = COMMAND_ANY,
        .usage = "['enable'|'disable']",
        .help = "use fast memory accesses instead of slower "
            "but potentially safer accesses",
    },
    {
        .name = "dcc_downloads",
        .handler = handle_arm7_9_dcc_downloads_command,
        .mode = COMMAND_ANY,
        .usage = "['enable'|'disable']",
        .help = "use DCC downloads for larger memory writes",
    },
    COMMAND_REGISTRATION_DONE
}

Definition at line 2846 of file arm7_9_common.c.

◆ arm7_9_command_handlers

const struct command_registration arm7_9_command_handlers[]

Initial value:

= {
    {
        .chain = arm_command_handlers,
    },
    {
        .chain = etm_command_handlers,
    },
    {
        .name = "arm7_9",
        .mode = COMMAND_ANY,
        .help = "arm7/9 specific commands",
        .usage = "",
        .chain = arm7_9_any_command_handlers,
    },
    COMMAND_REGISTRATION_DONE
}

Definition at line 2846 of file arm7_9_common.c.

◆ dcc_buffer

const uint8_t* dcc_buffer

static

Definition at line 2518 of file arm7_9_common.c.

Referenced by arm7_9_bulk_write_memory(), arm7_9_dcc_completion(), ocl_erase(), ocl_probe(), and ocl_write().

◆ dcc_code

const uint32_t dcc_code[]

static

Initial value:

= {
    
    0xee101e10, 
    0xe3110001, 
    0x0afffffc, 
 
    0xee111e10, 
    0xe4801004, 
 
    0xeafffff9  
}

Definition at line 2568 of file arm7_9_common.c.

Referenced by arm7_9_bulk_write_memory(), and feroceon_bulk_write_memory().

◆ dcc_count

int dcc_count

static

Definition at line 2517 of file arm7_9_common.c.

Referenced by arm7_9_bulk_write_memory(), and arm7_9_dcc_completion().

Functions

Variables

Detailed Description

Function Documentation

◆ arm7_9_add_breakpoint()

◆ arm7_9_add_watchpoint()

◆ arm7_9_assert_reset()

◆ arm7_9_assign_wp()

◆ arm7_9_bulk_write_memory()

◆ arm7_9_check_reset()

◆ arm7_9_clear_halt()

◆ arm7_9_clear_watchpoints()

◆ arm7_9_dcc_completion()

◆ arm7_9_deassert_reset()

◆ arm7_9_debug_entry()

◆ arm7_9_deinit()

◆ arm7_9_disable_eice_step()

◆ arm7_9_enable_breakpoints()

◆ arm7_9_enable_eice_step()

◆ arm7_9_enable_watchpoints()

◆ arm7_9_endianness_callback()

◆ arm7_9_examine()

◆ arm7_9_execute_fast_sys_speed()

◆ arm7_9_execute_sys_speed()

◆ arm7_9_full_context()

◆ arm7_9_halt()

◆ arm7_9_handle_target_request()

◆ arm7_9_init_arch_info()

◆ arm7_9_poll()

◆ arm7_9_read_core_reg()

◆ arm7_9_read_memory()

◆ arm7_9_remove_breakpoint()

◆ arm7_9_remove_watchpoint()

◆ arm7_9_restart_core()

◆ arm7_9_restore_context()

◆ arm7_9_resume()

◆ arm7_9_set_breakpoint()

◆ arm7_9_set_software_breakpoints()

◆ arm7_9_set_watchpoint()

◆ arm7_9_setup()

◆ arm7_9_setup_semihosting()

◆ arm7_9_soft_reset_halt()

◆ arm7_9_step()

◆ arm7_9_target_request_data()

◆ arm7_9_unset_breakpoint()

◆ arm7_9_unset_watchpoint()

◆ arm7_9_write_core_reg()

◆ arm7_9_write_memory()

◆ arm7_9_write_memory_no_opt()

◆ arm7_9_write_memory_opt()

◆ COMMAND_HANDLER() [1/3]

◆ COMMAND_HANDLER() [2/3]

◆ COMMAND_HANDLER() [3/3]

Variable Documentation

◆ arm7_9_any_command_handlers

◆ arm7_9_command_handlers

◆ dcc_buffer

◆ dcc_code

◆ dcc_count