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rtos_ucos_iii_stackings.c
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1 // SPDX-License-Identifier: GPL-2.0-or-later
2 
3 /***************************************************************************
4  * Copyright (C) 2017 by Square, Inc. *
5  * Steven Stallion <stallion@squareup.com> *
6  ***************************************************************************/
7 
8 #ifdef HAVE_CONFIG_H
9 #include "config.h"
10 #endif
11 
12 #include <helper/types.h>
13 #include <rtos/rtos.h>
15 #include <target/armv7m.h>
16 #include <target/esirisc.h>
17 
19  { ARMV7M_R0, 0x20, 32 }, /* r0 */
20  { ARMV7M_R1, 0x24, 32 }, /* r1 */
21  { ARMV7M_R2, 0x28, 32 }, /* r2 */
22  { ARMV7M_R3, 0x2c, 32 }, /* r3 */
23  { ARMV7M_R4, 0x00, 32 }, /* r4 */
24  { ARMV7M_R5, 0x04, 32 }, /* r5 */
25  { ARMV7M_R6, 0x08, 32 }, /* r6 */
26  { ARMV7M_R7, 0x0c, 32 }, /* r7 */
27  { ARMV7M_R8, 0x10, 32 }, /* r8 */
28  { ARMV7M_R9, 0x14, 32 }, /* r9 */
29  { ARMV7M_R10, 0x18, 32 }, /* r10 */
30  { ARMV7M_R11, 0x1c, 32 }, /* r11 */
31  { ARMV7M_R12, 0x30, 32 }, /* r12 */
32  { ARMV7M_R13, -2, 32 }, /* sp */
33  { ARMV7M_R14, 0x34, 32 }, /* lr */
34  { ARMV7M_PC, 0x38, 32 }, /* pc */
35  { ARMV7M_XPSR, 0x3c, 32 }, /* xPSR */
36 };
37 
39  { ESIRISC_SP, -2, 32 }, /* sp */
40  { ESIRISC_RA, 0x48, 32 }, /* ra */
41  { ESIRISC_R2, 0x44, 32 }, /* r2 */
42  { ESIRISC_R3, 0x40, 32 }, /* r3 */
43  { ESIRISC_R4, 0x3c, 32 }, /* r4 */
44  { ESIRISC_R5, 0x38, 32 }, /* r5 */
45  { ESIRISC_R6, 0x34, 32 }, /* r6 */
46  { ESIRISC_R7, 0x30, 32 }, /* r7 */
47  { ESIRISC_R8, 0x2c, 32 }, /* r8 */
48  { ESIRISC_R9, 0x28, 32 }, /* r9 */
49  { ESIRISC_R10, 0x24, 32 }, /* r10 */
50  { ESIRISC_R11, 0x20, 32 }, /* r11 */
51  { ESIRISC_R12, 0x1c, 32 }, /* r12 */
52  { ESIRISC_R13, 0x18, 32 }, /* r13 */
53  { ESIRISC_R14, 0x14, 32 }, /* r14 */
54  { ESIRISC_R15, 0x10, 32 }, /* r15 */
55  { ESIRISC_PC, 0x04, 32 }, /* PC */
56  { ESIRISC_CAS, 0x08, 32 }, /* CAS */
57 };
58 
60  .stack_registers_size = 0x40,
61  .stack_growth_direction = -1,
62  .num_output_registers = ARRAY_SIZE(rtos_ucos_iii_cortex_m_stack_offsets),
63  .calculate_process_stack = rtos_generic_stack_align8,
64  .register_offsets = rtos_ucos_iii_cortex_m_stack_offsets
65 };
66 
68  .stack_registers_size = 0x4c,
69  .stack_growth_direction = -1,
70  .num_output_registers = ARRAY_SIZE(rtos_ucos_iii_esi_risc_stack_offsets),
71  .register_offsets = rtos_ucos_iii_esi_risc_stack_offsets
72 };
@ ARMV7M_R1
Definition: armv7m.h:108
@ ARMV7M_R6
Definition: armv7m.h:114
@ ARMV7M_R2
Definition: armv7m.h:109
@ ARMV7M_R3
Definition: armv7m.h:110
@ ARMV7M_R14
Definition: armv7m.h:124
@ ARMV7M_R9
Definition: armv7m.h:118
@ ARMV7M_R12
Definition: armv7m.h:122
@ ARMV7M_R0
Definition: armv7m.h:107
@ ARMV7M_R13
Definition: armv7m.h:123
@ ARMV7M_PC
Definition: armv7m.h:125
@ ARMV7M_R7
Definition: armv7m.h:115
@ ARMV7M_R4
Definition: armv7m.h:112
@ ARMV7M_XPSR
Definition: armv7m.h:127
@ ARMV7M_R8
Definition: armv7m.h:117
@ ARMV7M_R11
Definition: armv7m.h:120
@ ARMV7M_R10
Definition: armv7m.h:119
@ ARMV7M_R5
Definition: armv7m.h:113
@ ESIRISC_R4
Definition: esirisc_regs.h:17
@ ESIRISC_R13
Definition: esirisc_regs.h:26
@ ESIRISC_R7
Definition: esirisc_regs.h:20
@ ESIRISC_SP
Definition: esirisc_regs.h:13
@ ESIRISC_R11
Definition: esirisc_regs.h:24
@ ESIRISC_R14
Definition: esirisc_regs.h:27
@ ESIRISC_CAS
Definition: esirisc_regs.h:89
@ ESIRISC_PC
Definition: esirisc_regs.h:88
@ ESIRISC_R10
Definition: esirisc_regs.h:23
@ ESIRISC_R9
Definition: esirisc_regs.h:22
@ ESIRISC_RA
Definition: esirisc_regs.h:14
@ ESIRISC_R12
Definition: esirisc_regs.h:25
@ ESIRISC_R15
Definition: esirisc_regs.h:28
@ ESIRISC_R3
Definition: esirisc_regs.h:16
@ ESIRISC_R8
Definition: esirisc_regs.h:21
@ ESIRISC_R2
Definition: esirisc_regs.h:15
@ ESIRISC_R6
Definition: esirisc_regs.h:19
@ ESIRISC_R5
Definition: esirisc_regs.h:18
target_addr_t rtos_generic_stack_align8(struct target *target, const uint8_t *stack_data, const struct rtos_register_stacking *stacking, target_addr_t stack_ptr)
static const struct stack_register_offset rtos_ucos_iii_esi_risc_stack_offsets[]
const struct rtos_register_stacking rtos_ucos_iii_cortex_m_stacking
static const struct stack_register_offset rtos_ucos_iii_cortex_m_stack_offsets[]
const struct rtos_register_stacking rtos_ucos_iii_esi_risc_stacking
unsigned char stack_registers_size
Definition: rtos.h:92
#define ARRAY_SIZE(x)
Compute the number of elements of a variable length array.
Definition: types.h:57