22 #define WATCHDOG_REFRESH_REGISTER 0x40010600
23 #define WATCHDOG_REFRESH_VALUE 0x6e524635
32 #define NRF5_FICR_REG(offset) (NRF5_FICR_BASE + offset)
84 #define NRF5_UICR_REG(offset) (NRF5_UICR_BASE + offset)
96 #define NRF5_NVMC_REG(offset) (NRF5_NVMC_BASE + offset)
157 #define NRF51_DEVICE_DEF(id, pt, var, bcode, fsize) \
162 .build_code = bcode, \
163 .flash_size_kb = (fsize), \
164 .features = NRF5_FEATURE_SERIES_51, \
167 #define NRF5_DEVICE_DEF(id, pt, var, bcode, fsize, features) \
172 .build_code = bcode, \
173 .flash_size_kb = (fsize), \
174 .features = features, \
284 struct nrf5_bank *nbank =
bank->driver_priv;
288 return nbank->probed;
299 struct nrf5_bank *nbank =
bank->driver_priv;
312 int timeout_ms = 340;
318 LOG_ERROR(
"Error waiting NVMC_READY: generic flash write/erase error (check protection etc...)");
322 if (ready == 0x00000001)
327 }
while ((
timeval_ms()-ts_start) < timeout_ms);
329 LOG_DEBUG(
"Timed out waiting for NVMC_READY");
341 LOG_ERROR(
"Failed to enable erase operation");
351 LOG_ERROR(
"Erase enable did not complete");
364 LOG_ERROR(
"Failed to enable write operation");
374 LOG_ERROR(
"Write enable did not complete");
387 LOG_ERROR(
"Failed to enable read-only operation");
396 LOG_ERROR(
"Read only enable did not complete");
402 uint32_t erase_register, uint32_t erase_value)
425 LOG_ERROR(
"Failed to erase reg: 0x%08"PRIx32
" val: 0x%08"PRIx32,
426 erase_register, erase_value);
434 struct nrf5_bank *nbank =
bank->driver_priv;
442 LOG_ERROR(
"Couldn't read code region 0 size[FICR]");
446 if (clenr0 == 0xFFFFFFFF) {
450 LOG_ERROR(
"Couldn't read code region 0 size[UICR]");
455 for (
unsigned int i = 0; i <
bank->num_sectors; i++)
456 bank->sectors[i].is_protected =
457 clenr0 != 0xFFFFFFFF &&
bank->sectors[i].offset < clenr0;
464 struct nrf5_bank *nbank =
bank->driver_priv;
469 static uint32_t nrf5_bprot_offsets[4] = { 0x600, 0x604, 0x610, 0x614 };
470 uint32_t bprot_reg = 0;
473 for (
unsigned int i = 0; i <
bank->num_sectors; i++) {
474 unsigned int bit = i % 32;
476 unsigned int n_reg = i / 32;
484 bank->sectors[i].is_protected = (bprot_reg & (1 <<
bit)) ? 1 : 0;
495 struct nrf5_bank *nbank =
bank->driver_priv;
506 LOG_WARNING(
"Flash protection of this nRF device is not supported");
514 uint32_t clenr0, ppfc;
515 struct nrf5_bank *nbank =
bank->driver_priv;
519 LOG_ERROR(
"Code region 0 must start at the beginning of the bank");
526 LOG_ERROR(
"Couldn't read PPFC register");
530 if ((ppfc & 0xFF) == 0x00) {
531 LOG_ERROR(
"Code region 0 size was pre-programmed at the factory, can't change flash protection settings");
538 LOG_ERROR(
"Couldn't read code region 0 size from UICR");
542 if (!set || clenr0 != 0xFFFFFFFF) {
543 LOG_ERROR(
"You need to perform chip erase before changing the protection settings");
551 clenr0 =
bank->sectors[last].offset +
bank->sectors[last].size;
560 LOG_INFO(
"A reset or power cycle is required for the new protection settings to take effect.");
562 LOG_ERROR(
"Couldn't write code region 0 size to UICR");
578 LOG_ERROR(
"UICR page does not support protection");
589 LOG_ERROR(
"Flash protection setting is not supported on this nRF5 device");
598 if (isalnum(b[0]) && isalnum(b[1]) && isalnum(b[2]) && isalnum(b[3])) {
621 res = snprintf(buf, buf_size,
"nRF%s-%s(build code: %s)",
626 res = snprintf(buf, buf_size,
"nRF%" PRIx32
"-%s%.2s(build code: %s)",
629 variant, &variant[2]);
631 res = snprintf(buf, buf_size,
"nRF51xxx (HWID 0x%04" PRIx16
")", chip->
hwid);
635 if (res <= 0 || (
unsigned int)res >= buf_size) {
636 LOG_ERROR(
"BUG: buffer problem in %s", __func__);
644 struct nrf5_bank *nbank =
bank->driver_priv;
647 char chip_type_str[256];
665 LOG_DEBUG(
"Couldn't read FICR INFO.PART register");
691 LOG_DEBUG(
"FICR INFO likely not implemented. Invalid PART value 0x%08"
728 uint32_t numramblock;
731 LOG_DEBUG(
"Couldn't read FICR NUMRAMBLOCK register");
735 if (numramblock < 1 || numramblock > 4) {
736 LOG_DEBUG(
"FICR NUMRAMBLOCK strange value %" PRIx32, numramblock);
740 for (
unsigned int i = 0; i < numramblock; i++) {
741 uint32_t sizeramblock;
744 LOG_DEBUG(
"Couldn't read FICR NUMRAMBLOCK register");
747 if (sizeramblock < 1024 || sizeramblock > 65536)
748 LOG_DEBUG(
"FICR SIZERAMBLOCK strange value %" PRIx32, sizeramblock);
750 *ram_size += sizeramblock;
758 struct nrf5_bank *nbank =
bank->driver_priv;
765 LOG_ERROR(
"Couldn't read CONFIGID register");
770 chip->
hwid = configid & 0xFFFF;
791 LOG_WARNING(
"HWID 0x%04" PRIx32
" mismatch: FICR INFO.PART %"
804 uint32_t flash_page_size;
808 LOG_ERROR(
"Couldn't read code page size");
814 uint32_t num_sectors;
817 LOG_ERROR(
"Couldn't read code memory size");
824 char chip_type_str[256];
828 LOG_INFO(
"%s%s %ukB Flash, %ukB RAM",
829 device_is_unknown ?
"Unknown device: " :
"",
840 LOG_WARNING(
"Chip's reported Flash capacity does not match expected one");
842 LOG_WARNING(
"Chip's reported Flash capacity does not match FICR INFO.FLASH");
844 bank->num_sectors = num_sectors;
845 bank->size = num_sectors * flash_page_size;
854 bank->num_sectors = 1;
855 bank->size = flash_page_size;
861 bank->sectors[0].is_protected = 0;
879 LOG_DEBUG(
"Erasing all non-volatile memory");
899 LOG_ERROR(
"Couldn't read PPFC register");
903 if ((ppfc & 0xFF) == 0xFF) {
910 LOG_ERROR(
"The chip was not pre-programmed with SoftDevice stack and UICR cannot be erased separately. Please issue mass erase before trying to write to this region");
933 uint32_t buffer_size = 8192;
940 static const uint8_t nrf5_flash_write_code[] = {
941 #include "../../../contrib/loaders/flash/nrf5/nrf5.inc"
944 LOG_DEBUG(
"Writing buffer to flash address=0x%"PRIx32
" bytes=0x%"PRIx32, address, bytes);
945 assert(bytes % 4 == 0);
950 LOG_WARNING(
"no working area available, falling back to slow memory writes");
952 for (; bytes > 0; bytes -= 4) {
969 sizeof(nrf5_flash_write_code),
970 nrf5_flash_write_code);
978 if (buffer_size <= 256) {
982 LOG_WARNING(
"No large enough working area available, can't do block memory writes");
1008 write_algorithm->
address, write_algorithm->
address +
sizeof(nrf5_flash_write_code) - 2,
1034 assert(
count % 4 == 0);
1050 for (
unsigned int sector = 0; sector <
bank->num_sectors; sector++) {
1058 LOG_ERROR(
"Write refused, sector %d is protected", sector);
1076 LOG_ERROR(
"Failed to write to nrf5 flash");
1104 for (
unsigned int s = first; s <= last && res ==
ERROR_OK; s++) {
1107 &&
bank->sectors[s].is_protected == 1) {
1108 LOG_ERROR(
"Flash sector %d is protected", s);
1114 LOG_ERROR(
"Error erasing sector %d", s);
1124 struct nrf5_bank *nbank =
bank->driver_priv;
1161 struct nrf5_bank *nbank =
NULL;
1163 switch (
bank->base) {
1175 chip = calloc(1,
sizeof(*chip));
1182 switch (
bank->base) {
1184 nbank = &chip->
bank[0];
1187 nbank = &chip->
bank[1];
1194 nbank->probed =
false;
1195 bank->driver_priv = nbank;
1196 bank->write_start_alignment =
bank->write_end_alignment = 4;
1224 LOG_ERROR(
"Couldn't read PPFC register");
1228 if ((ppfc & 0xFF) == 0x00) {
1229 LOG_ERROR(
"Code region 0 size was pre-programmed at the factory, "
1230 "mass erase command won't work.");
1239 LOG_INFO(
"A reset or power cycle is required if the flash was protected before.");
1267 const uint32_t address;
1311 for (
size_t i = 0; i <
ARRAY_SIZE(ficr); i++) {
1315 LOG_ERROR(
"Couldn't read %" PRIx32, ficr[i].address);
1320 for (
size_t i = 0; i <
ARRAY_SIZE(uicr); i++) {
1324 LOG_ERROR(
"Couldn't read %" PRIx32, uicr[i].address);
1330 "\n[factory information control block]\n\n"
1331 "code page size: %"PRIu32
"B\n"
1332 "code memory size: %"PRIu32
"kB\n"
1333 "code region 0 size: %"PRIu32
"kB\n"
1334 "pre-programmed code: %s\n"
1335 "number of ram blocks: %"PRIu32
"\n"
1336 "ram block 0 size: %"PRIu32
"B\n"
1337 "ram block 1 size: %"PRIu32
"B\n"
1338 "ram block 2 size: %"PRIu32
"B\n"
1339 "ram block 3 size: %"PRIu32
"B\n"
1340 "config id: %" PRIx32
"\n"
1341 "device id: 0x%"PRIx32
"%08"PRIx32
"\n"
1342 "encryption root: 0x%08"PRIx32
"%08"PRIx32
"%08"PRIx32
"%08"PRIx32
"\n"
1343 "identity root: 0x%08"PRIx32
"%08"PRIx32
"%08"PRIx32
"%08"PRIx32
"\n"
1344 "device address type: 0x%"PRIx32
"\n"
1345 "device address: 0x%"PRIx32
"%08"PRIx32
"\n"
1346 "override enable: %"PRIx32
"\n"
1347 "NRF_1MBIT values: %"PRIx32
" %"PRIx32
" %"PRIx32
" %"PRIx32
" %"PRIx32
"\n"
1348 "BLE_1MBIT values: %"PRIx32
" %"PRIx32
" %"PRIx32
" %"PRIx32
" %"PRIx32
"\n"
1349 "\n[user information control block]\n\n"
1350 "code region 0 size: %"PRIu32
"kB\n"
1351 "read back protection configuration: %"PRIx32
"\n"
1352 "reset value for XTALFREQ: %"PRIx32
"\n"
1353 "firmware id: 0x%04"PRIx32,
1355 (ficr[1].value * ficr[0].value) / 1024,
1356 (ficr[2].value == 0xFFFFFFFF) ? 0 : ficr[2].value / 1024,
1357 ((ficr[3].value & 0xFF) == 0x00) ?
"present" :
"not present",
1360 (ficr[6].value == 0xFFFFFFFF) ? 0 : ficr[6].value,
1361 (ficr[7].value == 0xFFFFFFFF) ? 0 : ficr[7].value,
1362 (ficr[8].value == 0xFFFFFFFF) ? 0 : ficr[8].value,
1364 ficr[10].value, ficr[11].value,
1365 ficr[12].value, ficr[13].value, ficr[14].value, ficr[15].value,
1366 ficr[16].value, ficr[17].value, ficr[18].value, ficr[19].value,
1368 ficr[21].value, ficr[22].value,
1370 ficr[24].value, ficr[25].value, ficr[26].value, ficr[27].value, ficr[28].value,
1371 ficr[29].value, ficr[30].value, ficr[31].value, ficr[32].value, ficr[33].value,
1372 (uicr[0].value == 0xFFFFFFFF) ? 0 : uicr[0].value / 1024,
1373 uicr[1].value & 0xFFFF,
1374 uicr[2].value & 0xFF,
1375 uicr[3].value & 0xFFFF);
1382 .
name =
"mass_erase",
1383 .handler = nrf5_handle_mass_erase_command,
1385 .help =
"Erase all flash contents of the chip.",
1390 .handler = nrf5_handle_info_command,
1392 .help =
"Show FICR and UICR info.",
1402 .help =
"nrf5 flash command group",
1409 .help =
"nrf51 flash command group",
1419 .flash_bank_command = nrf5_flash_bank_command,
1437 .flash_bank_command = nrf5_flash_bank_command,
void init_reg_param(struct reg_param *param, char *reg_name, uint32_t size, enum param_direction direction)
void destroy_reg_param(struct reg_param *param)
#define ARMV7M_COMMON_MAGIC
Support functions to access arbitrary bits in a byte array.
static void buf_set_u32(uint8_t *_buffer, unsigned first, unsigned num, uint32_t value)
Sets num bits in _buffer, starting at the first bit, using the bits in value.
void command_print_sameline(struct command_invocation *cmd, const char *format,...)
void command_print(struct command_invocation *cmd, const char *format,...)
#define CMD
Use this macro to access the command being handled, rather than accessing the variable directly.
#define CMD_CTX
Use this macro to access the context of the command being handled, rather than accessing the variable...
#define COMMAND_REGISTRATION_DONE
Use this as the last entry in an array of command_registration records.
#define ERROR_FLASH_OPER_UNSUPPORTED
#define ERROR_FLASH_PROTECTED
struct flash_sector * alloc_block_array(uint32_t offset, uint32_t size, unsigned int num_blocks)
Allocate and fill an array of sectors or protection blocks.
int default_flash_blank_check(struct flash_bank *bank)
Provides default erased-bank check handling.
int default_flash_read(struct flash_bank *bank, uint8_t *buffer, uint32_t offset, uint32_t count)
Provides default read implementation for flash memory.
int get_flash_bank_by_addr(struct target *target, target_addr_t addr, bool check, struct flash_bank **result_bank)
Returns the flash bank located at a specified address.
struct flash_bank * flash_bank_list(void)
#define LOG_WARNING(expr ...)
#define LOG_ERROR(expr ...)
#define LOG_INFO(expr ...)
#define LOG_DEBUG(expr ...)
static int nrf5_protect_clenr0(struct flash_bank *bank, int set, unsigned int first, unsigned int last)
static const struct nrf5_device_package nrf5_packages_table[]
static const char * nrf5_decode_info_package(uint32_t package)
static int nrf5_protect(struct flash_bank *bank, int set, unsigned int first, unsigned int last)
COMMAND_HANDLER(nrf5_handle_mass_erase_command)
#define NRF5_DEVICE_DEF(id, pt, var, bcode, fsize, features)
#define NRF5_FICR_REG(offset)
static const struct command_registration nrf5_exec_command_handlers[]
const struct flash_driver nrf5_flash
static bool nrf5_info_variant_to_str(uint32_t variant, char *bf)
static int nrf5_wait_for_nvmc(struct nrf5_info *chip)
static int nrf5_auto_probe(struct flash_bank *bank)
static int nrf5_probe(struct flash_bank *bank)
static int nrf5_erase_all(struct nrf5_info *chip)
#define WATCHDOG_REFRESH_REGISTER
#define WATCHDOG_REFRESH_VALUE
static const struct command_registration nrf5_command_handlers[]
static int nrf5_protect_check(struct flash_bank *bank)
static int nrf5_write(struct flash_bank *bank, const uint8_t *buffer, uint32_t offset, uint32_t count)
static int nrf5_nvmc_read_only(struct nrf5_info *chip)
static int nrf5_protect_check_clenr0(struct flash_bank *bank)
#define NRF5_NVMC_REG(offset)
static int nrf5_erase_page(struct flash_bank *bank, struct nrf5_info *chip, struct flash_sector *sector)
static int nrf5_read_ficr_info(struct nrf5_info *chip)
static int get_nrf5_chip_type_str(const struct nrf5_info *chip, char *buf, unsigned int buf_size)
static int nrf5_nvmc_write_enable(struct nrf5_info *chip)
static struct nrf5_info * nrf5_get_chip(struct target *target)
static int nrf5_info(struct flash_bank *bank, struct command_invocation *cmd)
static int nrf5_erase(struct flash_bank *bank, unsigned int first, unsigned int last)
#define NRF51_DEVICE_DEF(id, pt, var, bcode, fsize)
static void nrf5_free_driver_priv(struct flash_bank *bank)
static int nrf5_ll_flash_write(struct nrf5_info *chip, uint32_t address, const uint8_t *buffer, uint32_t bytes)
static int nrf5_protect_check_bprot(struct flash_bank *bank)
static int nrf5_nvmc_erase_enable(struct nrf5_info *chip)
static int nrf5_nvmc_generic_erase(struct nrf5_info *chip, uint32_t erase_register, uint32_t erase_value)
FLASH_BANK_COMMAND_HANDLER(nrf5_flash_bank_command)
static bool nrf5_bank_is_probed(const struct flash_bank *bank)
#define NRF5_UICR_REG(offset)
static int nrf5_get_ram_size(struct target *target, uint32_t *ram_size)
static const struct nrf5_device_spec nrf5_known_devices_table[]
const struct flash_driver nrf5_flash nrf51_flash
static int nrf5_get_probed_chip_if_halted(struct flash_bank *bank, struct nrf5_info **chip)
@ NRF51_FICR_SIZERAMBLOCK3
@ NRF51_FICR_SIZERAMBLOCK0
@ NRF5_FICR_DEVICEADDRTYPE
@ NRF51_FICR_SIZERAMBLOCK2
@ NRF51_FICR_SIZERAMBLOCK1
static uint32_t bit(uint32_t value, unsigned int b)
unsigned int common_magic
When run_command is called, a new instance will be created on the stack, filled with the proper value...
Provides details of a flash bank, available either on-chip or through a major interface.
const struct flash_driver * driver
Driver for this bank.
void * driver_priv
Private driver storage pointer.
struct flash_bank * next
The next flash bank on this chip.
struct target * target
Target to which this bank belongs.
Provides the implementation-independent structure that defines all of the callbacks required by OpenO...
const char * name
Gives a human-readable name of this flash driver, This field is used to select and initialize the dri...
Describes the geometry and status of a single flash sector within a flash bank.
int is_erased
Indication of erasure status: 0 = not erased, 1 = erased, other = unknown.
uint32_t offset
Bus offset from start of the flash chip (in bytes).
int is_protected
Indication of protection status: 0 = unprotected/unlocked, 1 = protected/locked, other = unknown.
uint32_t size
Number of bytes in this flash sector.
unsigned int flash_size_kb
enum nrf5_features features
unsigned int flash_size_kb
struct nrf52_ficr_info ficr_info
struct nrf5_info::nrf5_bank bank[2]
const struct nrf5_device_spec * spec
enum nrf5_features features
int target_write_buffer(struct target *target, target_addr_t address, uint32_t size, const uint8_t *buffer)
int target_write_memory(struct target *target, target_addr_t address, uint32_t size, uint32_t count, const uint8_t *buffer)
Write count items of size bytes to the memory of target at the address given.
int target_alloc_working_area(struct target *target, uint32_t size, struct working_area **area)
int target_write_u32(struct target *target, target_addr_t address, uint32_t value)
int target_free_working_area(struct target *target, struct working_area *area)
Free a working area.
int target_run_flash_async_algorithm(struct target *target, const uint8_t *buffer, uint32_t count, int block_size, int num_mem_params, struct mem_param *mem_params, int num_reg_params, struct reg_param *reg_params, uint32_t buffer_start, uint32_t buffer_size, uint32_t entry_point, uint32_t exit_point, void *arch_info)
Streams data to a circular buffer on target intended for consumption by code running asynchronously o...
int target_read_u32(struct target *target, target_addr_t address, uint32_t *value)
struct target * get_current_target(struct command_context *cmd_ctx)
#define ERROR_TARGET_NOT_HALTED
#define ERROR_TARGET_RESOURCE_NOT_AVAILABLE
static void h_u32_to_be(uint8_t *buf, uint32_t val)
#define ARRAY_SIZE(x)
Compute the number of elements of a variable length array.