Go to the source code of this file.
Macros | |
| #define | AMFAR(a, b) (0x60300060 | (a << 15) | b) |
| #define | AMFAR2(a, b) (0x60300260 | (a << 15) | b) |
| #define | AMTAR(a, b) (0x60300040 | (a << 15) | b) |
| #define | AMTAR2(a, b) (0x60300240 | (a << 15) | b) |
| #define | BEQ_MINUS_12 (0x4C000000 | 0x3FFA) |
| #define | DSB (0x64000008) |
| #define | FMFCFG (0x6A000301) |
| #define | FMFCSR (0x6A000701) |
| #define | FMFDR(a, b) (0x6A000041 | ((a) << 20) | ((b) << 15)) |
| #define | FMFSR(a, b) (0x6A000001 | ((a) << 20) | ((b) << 15)) |
| #define | FMTCSR (0x6A000709) |
| #define | FMTDR(a, b) (0x6A000049 | ((a) << 20) | ((b) << 15)) |
| #define | FMTSR(a, b) (0x6A000009 | ((a) << 20) | ((b) << 15)) |
| #define | IRET (0x64000004) |
| #define | ISB (0x64000009) |
| #define | ISYNC(a) (0x6400000d | ((a) << 20)) |
| #define | L1D_IX_INVAL(a) (0x64000001 | ((a) << 15)) |
| #define | L1D_IX_RTAG(a) (0x64000061 | ((a) << 15)) |
| #define | L1D_IX_RWD(a) (0x64000081 | ((a) << 15)) |
| #define | L1D_IX_WB(a) (0x64000021 | ((a) << 15)) |
| #define | L1D_VA_INVAL(a) (0x64000101 | ((a) << 15)) |
| #define | L1D_VA_WB(a) (0x64000121 | ((a) << 15)) |
| #define | L1I_IX_INVAL(a) (0x64000201 | ((a) << 15)) |
| #define | L1I_IX_RTAG(a) (0x64000261 | ((a) << 15)) |
| #define | L1I_IX_RWD(a) (0x64000281 | ((a) << 15)) |
| #define | L1I_VA_FILLCK(a) (0x64000361 | ((a) << 15)) |
| #define | L1I_VA_INVAL(a) (0x64000301 | ((a) << 15)) |
| #define | LBI_BI(a, b) (0x08000001 | (a << 20) | (b << 15)) |
| #define | LHI_BI(a, b) (0x0A000001 | (a << 20) | (b << 15)) |
| #define | LWI_BI(a, b) (0x0C000001 | (a << 20) | (b << 15)) |
| #define | MFCPD(a, b, c) (0x6A000041 | (a << 20) | (b << 8) | (c << 4)) |
| #define | MFCPW(a, b, c) (0x6A000001 | (a << 20) | (b << 8) | (c << 4)) |
| #define | MFSR(a, b) (0x64000002 | (b << 10) | (a << 20)) |
| #define | MFSR_DTR(a) (0x64000002 | (((0x03 << 7) | (0x08 << 3) | (0x00 << 0)) << 10) | (((a) & 0x1F) << 20)) |
| #define | MFUSR_G0(a, b) (0x42000020 | (a << 20) | (b << 15)) |
| #define | MOVI_(a, b) (0x44000000 | (a << 20) | (b & 0xFFFFF)) |
| #define | MSYNC_ALL (0x6400000c) |
| #define | MSYNC_STORE (0x6400002c) |
| #define | MTCPD(a, b, c) (0x6A000049 | (a << 20) | (b << 8) | (c << 4)) |
| #define | MTCPW(a, b, c) (0x6A000009 | (a << 20) | (b << 8) | (c << 4)) |
| #define | MTSR(a, b) (0x64000003 | (b << 10) | (a << 20)) |
| #define | MTSR_DTR(a) (0x64000003 | (((0x03 << 7) | (0x08 << 3) | (0x00 << 0)) << 10) | (((a) & 0x1F) << 20)) |
| #define | MTUSR_G0(a, b) (0x42000021 | (a << 20) | (b << 15)) |
| #define | NDS32_BREAK_16 (0x00EA) |
| #define | NDS32_BREAK_32 (0x0A000064) |
| #define | NOP (0x40000009) |
| #define | ORI(a, b, c) (0x58000000 | ((a) << 20) | ((b) << 15) | (c)) |
| #define | SBI_BI(a, b) (0x18000001 | (a << 20) | (b << 15)) |
| #define | SETHI(a, b) (0x46000000 | ((a) << 20) | (b)) |
| #define | SHI_BI(a, b) (0x1A000001 | (a << 20) | (b << 15)) |
| #define | SWI_BI(a, b) (0x1C000001 | (a << 20) | (b << 15)) |
| #define | TLBOP_TARGET_PROBE(a, b) (0x640000AE | ((a) << 20) | ((b) << 15)) |
| #define | TLBOP_TARGET_READ(a) (0x6400000e | ((a) << 15)) |
Macro Definition Documentation
◆ AMFAR
| #define AMFAR | ( | a, | |
| b | |||
| ) | (0x60300060 | (a << 15) | b) |
Definition at line 51 of file nds32_insn.h.
◆ AMFAR2
| #define AMFAR2 | ( | a, | |
| b | |||
| ) | (0x60300260 | (a << 15) | b) |
Definition at line 53 of file nds32_insn.h.
◆ AMTAR
| #define AMTAR | ( | a, | |
| b | |||
| ) | (0x60300040 | (a << 15) | b) |
Definition at line 52 of file nds32_insn.h.
◆ AMTAR2
| #define AMTAR2 | ( | a, | |
| b | |||
| ) | (0x60300240 | (a << 15) | b) |
Definition at line 54 of file nds32_insn.h.
◆ BEQ_MINUS_12
| #define BEQ_MINUS_12 (0x4C000000 | 0x3FFA) |
Definition at line 14 of file nds32_insn.h.
◆ DSB
| #define DSB (0x64000008) |
Definition at line 12 of file nds32_insn.h.
◆ FMFCFG
| #define FMFCFG (0x6A000301) |
Definition at line 57 of file nds32_insn.h.
◆ FMFCSR
| #define FMFCSR (0x6A000701) |
Definition at line 55 of file nds32_insn.h.
◆ FMFDR
| #define FMFDR | ( | a, | |
| b | |||
| ) | (0x6A000041 | ((a) << 20) | ((b) << 15)) |
Definition at line 60 of file nds32_insn.h.
◆ FMFSR
| #define FMFSR | ( | a, | |
| b | |||
| ) | (0x6A000001 | ((a) << 20) | ((b) << 15)) |
Definition at line 58 of file nds32_insn.h.
◆ FMTCSR
| #define FMTCSR (0x6A000709) |
Definition at line 56 of file nds32_insn.h.
◆ FMTDR
| #define FMTDR | ( | a, | |
| b | |||
| ) | (0x6A000049 | ((a) << 20) | ((b) << 15)) |
Definition at line 61 of file nds32_insn.h.
◆ FMTSR
| #define FMTSR | ( | a, | |
| b | |||
| ) | (0x6A000009 | ((a) << 20) | ((b) << 15)) |
Definition at line 59 of file nds32_insn.h.
◆ IRET
| #define IRET (0x64000004) |
Definition at line 25 of file nds32_insn.h.
◆ ISB
| #define ISB (0x64000009) |
Definition at line 13 of file nds32_insn.h.
◆ ISYNC
| #define ISYNC | ( | a | ) | (0x6400000d | ((a) << 20)) |
Definition at line 37 of file nds32_insn.h.
◆ L1D_IX_INVAL
| #define L1D_IX_INVAL | ( | a | ) | (0x64000001 | ((a) << 15)) |
Definition at line 27 of file nds32_insn.h.
◆ L1D_IX_RTAG
| #define L1D_IX_RTAG | ( | a | ) | (0x64000061 | ((a) << 15)) |
Definition at line 30 of file nds32_insn.h.
◆ L1D_IX_RWD
| #define L1D_IX_RWD | ( | a | ) | (0x64000081 | ((a) << 15)) |
Definition at line 31 of file nds32_insn.h.
◆ L1D_IX_WB
| #define L1D_IX_WB | ( | a | ) | (0x64000021 | ((a) << 15)) |
Definition at line 26 of file nds32_insn.h.
◆ L1D_VA_INVAL
| #define L1D_VA_INVAL | ( | a | ) | (0x64000101 | ((a) << 15)) |
Definition at line 28 of file nds32_insn.h.
◆ L1D_VA_WB
| #define L1D_VA_WB | ( | a | ) | (0x64000121 | ((a) << 15)) |
Definition at line 29 of file nds32_insn.h.
◆ L1I_IX_INVAL
| #define L1I_IX_INVAL | ( | a | ) | (0x64000201 | ((a) << 15)) |
Definition at line 32 of file nds32_insn.h.
◆ L1I_IX_RTAG
| #define L1I_IX_RTAG | ( | a | ) | (0x64000261 | ((a) << 15)) |
Definition at line 34 of file nds32_insn.h.
◆ L1I_IX_RWD
| #define L1I_IX_RWD | ( | a | ) | (0x64000281 | ((a) << 15)) |
Definition at line 35 of file nds32_insn.h.
◆ L1I_VA_FILLCK
| #define L1I_VA_FILLCK | ( | a | ) | (0x64000361 | ((a) << 15)) |
Definition at line 36 of file nds32_insn.h.
◆ L1I_VA_INVAL
| #define L1I_VA_INVAL | ( | a | ) | (0x64000301 | ((a) << 15)) |
Definition at line 33 of file nds32_insn.h.
◆ LBI_BI
| #define LBI_BI | ( | a, | |
| b | |||
| ) | (0x08000001 | (a << 20) | (b << 15)) |
Definition at line 21 of file nds32_insn.h.
◆ LHI_BI
| #define LHI_BI | ( | a, | |
| b | |||
| ) | (0x0A000001 | (a << 20) | (b << 15)) |
Definition at line 20 of file nds32_insn.h.
◆ LWI_BI
| #define LWI_BI | ( | a, | |
| b | |||
| ) | (0x0C000001 | (a << 20) | (b << 15)) |
Definition at line 19 of file nds32_insn.h.
◆ MFCPD
| #define MFCPD | ( | a, | |
| b, | |||
| c | |||
| ) | (0x6A000041 | (a << 20) | (b << 8) | (c << 4)) |
Definition at line 42 of file nds32_insn.h.
◆ MFCPW
| #define MFCPW | ( | a, | |
| b, | |||
| c | |||
| ) | (0x6A000001 | (a << 20) | (b << 8) | (c << 4)) |
Definition at line 43 of file nds32_insn.h.
◆ MFSR
| #define MFSR | ( | a, | |
| b | |||
| ) | (0x64000002 | (b << 10) | (a << 20)) |
Definition at line 49 of file nds32_insn.h.
◆ MFSR_DTR
| #define MFSR_DTR | ( | a | ) | (0x64000002 | (((0x03 << 7) | (0x08 << 3) | (0x00 << 0)) << 10) | (((a) & 0x1F) << 20)) |
Definition at line 16 of file nds32_insn.h.
◆ MFUSR_G0
| #define MFUSR_G0 | ( | a, | |
| b | |||
| ) | (0x42000020 | (a << 20) | (b << 15)) |
Definition at line 47 of file nds32_insn.h.
◆ MOVI_
| #define MOVI_ | ( | a, | |
| b | |||
| ) | (0x44000000 | (a << 20) | (b & 0xFFFFF)) |
Definition at line 46 of file nds32_insn.h.
◆ MSYNC_ALL
| #define MSYNC_ALL (0x6400000c) |
Definition at line 39 of file nds32_insn.h.
◆ MSYNC_STORE
| #define MSYNC_STORE (0x6400002c) |
Definition at line 38 of file nds32_insn.h.
◆ MTCPD
| #define MTCPD | ( | a, | |
| b, | |||
| c | |||
| ) | (0x6A000049 | (a << 20) | (b << 8) | (c << 4)) |
Definition at line 44 of file nds32_insn.h.
◆ MTCPW
| #define MTCPW | ( | a, | |
| b, | |||
| c | |||
| ) | (0x6A000009 | (a << 20) | (b << 8) | (c << 4)) |
Definition at line 45 of file nds32_insn.h.
◆ MTSR
| #define MTSR | ( | a, | |
| b | |||
| ) | (0x64000003 | (b << 10) | (a << 20)) |
Definition at line 50 of file nds32_insn.h.
◆ MTSR_DTR
| #define MTSR_DTR | ( | a | ) | (0x64000003 | (((0x03 << 7) | (0x08 << 3) | (0x00 << 0)) << 10) | (((a) & 0x1F) << 20)) |
Definition at line 15 of file nds32_insn.h.
◆ MTUSR_G0
| #define MTUSR_G0 | ( | a, | |
| b | |||
| ) | (0x42000021 | (a << 20) | (b << 15)) |
Definition at line 48 of file nds32_insn.h.
◆ NDS32_BREAK_16
| #define NDS32_BREAK_16 (0x00EA) |
Definition at line 64 of file nds32_insn.h.
◆ NDS32_BREAK_32
| #define NDS32_BREAK_32 (0x0A000064) |
Definition at line 65 of file nds32_insn.h.
◆ NOP
| #define NOP (0x40000009) |
Definition at line 11 of file nds32_insn.h.
◆ ORI
| #define ORI | ( | a, | |
| b, | |||
| c | |||
| ) | (0x58000000 | ((a) << 20) | ((b) << 15) | (c)) |
Definition at line 18 of file nds32_insn.h.
◆ SBI_BI
| #define SBI_BI | ( | a, | |
| b | |||
| ) | (0x18000001 | (a << 20) | (b << 15)) |
Definition at line 24 of file nds32_insn.h.
◆ SETHI
| #define SETHI | ( | a, | |
| b | |||
| ) | (0x46000000 | ((a) << 20) | (b)) |
Definition at line 17 of file nds32_insn.h.
◆ SHI_BI
| #define SHI_BI | ( | a, | |
| b | |||
| ) | (0x1A000001 | (a << 20) | (b << 15)) |
Definition at line 23 of file nds32_insn.h.
◆ SWI_BI
| #define SWI_BI | ( | a, | |
| b | |||
| ) | (0x1C000001 | (a << 20) | (b << 15)) |
Definition at line 22 of file nds32_insn.h.
◆ TLBOP_TARGET_PROBE
| #define TLBOP_TARGET_PROBE | ( | a, | |
| b | |||
| ) | (0x640000AE | ((a) << 20) | ((b) << 15)) |
Definition at line 41 of file nds32_insn.h.
◆ TLBOP_TARGET_READ
| #define TLBOP_TARGET_READ | ( | a | ) | (0x6400000e | ((a) << 15)) |
Definition at line 40 of file nds32_insn.h.
