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8 #ifndef OPENOCD_TARGET_NDS32_INSN_H
9 #define OPENOCD_TARGET_NDS32_INSN_H
11 #define NOP (0x40000009)
12 #define DSB (0x64000008)
13 #define ISB (0x64000009)
14 #define BEQ_MINUS_12 (0x4C000000 | 0x3FFA)
15 #define MTSR_DTR(a) (0x64000003 | (((0x03 << 7) | (0x08 << 3) | (0x00 << 0)) << 10) | (((a) & 0x1F) << 20))
16 #define MFSR_DTR(a) (0x64000002 | (((0x03 << 7) | (0x08 << 3) | (0x00 << 0)) << 10) | (((a) & 0x1F) << 20))
17 #define SETHI(a, b) (0x46000000 | ((a) << 20) | (b))
18 #define ORI(a, b, c) (0x58000000 | ((a) << 20) | ((b) << 15) | (c))
19 #define LWI_BI(a, b) (0x0C000001 | (a << 20) | (b << 15))
20 #define LHI_BI(a, b) (0x0A000001 | (a << 20) | (b << 15))
21 #define LBI_BI(a, b) (0x08000001 | (a << 20) | (b << 15))
22 #define SWI_BI(a, b) (0x1C000001 | (a << 20) | (b << 15))
23 #define SHI_BI(a, b) (0x1A000001 | (a << 20) | (b << 15))
24 #define SBI_BI(a, b) (0x18000001 | (a << 20) | (b << 15))
25 #define IRET (0x64000004)
26 #define L1D_IX_WB(a) (0x64000021 | ((a) << 15))
27 #define L1D_IX_INVAL(a) (0x64000001 | ((a) << 15))
28 #define L1D_VA_INVAL(a) (0x64000101 | ((a) << 15))
29 #define L1D_VA_WB(a) (0x64000121 | ((a) << 15))
30 #define L1D_IX_RTAG(a) (0x64000061 | ((a) << 15))
31 #define L1D_IX_RWD(a) (0x64000081 | ((a) << 15))
32 #define L1I_IX_INVAL(a) (0x64000201 | ((a) << 15))
33 #define L1I_VA_INVAL(a) (0x64000301 | ((a) << 15))
34 #define L1I_IX_RTAG(a) (0x64000261 | ((a) << 15))
35 #define L1I_IX_RWD(a) (0x64000281 | ((a) << 15))
36 #define L1I_VA_FILLCK(a) (0x64000361 | ((a) << 15))
37 #define ISYNC(a) (0x6400000d | ((a) << 20))
38 #define MSYNC_STORE (0x6400002c)
39 #define MSYNC_ALL (0x6400000c)
40 #define TLBOP_TARGET_READ(a) (0x6400000e | ((a) << 15))
41 #define TLBOP_TARGET_PROBE(a, b) (0x640000AE | ((a) << 20) | ((b) << 15))
42 #define MFCPD(a, b, c) (0x6A000041 | (a << 20) | (b << 8) | (c << 4))
43 #define MFCPW(a, b, c) (0x6A000001 | (a << 20) | (b << 8) | (c << 4))
44 #define MTCPD(a, b, c) (0x6A000049 | (a << 20) | (b << 8) | (c << 4))
45 #define MTCPW(a, b, c) (0x6A000009 | (a << 20) | (b << 8) | (c << 4))
46 #define MOVI_(a, b) (0x44000000 | (a << 20) | (b & 0xFFFFF))
47 #define MFUSR_G0(a, b) (0x42000020 | (a << 20) | (b << 15))
48 #define MTUSR_G0(a, b) (0x42000021 | (a << 20) | (b << 15))
49 #define MFSR(a, b) (0x64000002 | (b << 10) | (a << 20))
50 #define MTSR(a, b) (0x64000003 | (b << 10) | (a << 20))
51 #define AMFAR(a, b) (0x60300060 | (a << 15) | b)
52 #define AMTAR(a, b) (0x60300040 | (a << 15) | b)
53 #define AMFAR2(a, b) (0x60300260 | (a << 15) | b)
54 #define AMTAR2(a, b) (0x60300240 | (a << 15) | b)
55 #define FMFCSR (0x6A000701)
56 #define FMTCSR (0x6A000709)
57 #define FMFCFG (0x6A000301)
58 #define FMFSR(a, b) (0x6A000001 | ((a) << 20) | ((b) << 15))
59 #define FMTSR(a, b) (0x6A000009 | ((a) << 20) | ((b) << 15))
60 #define FMFDR(a, b) (0x6A000041 | ((a) << 20) | ((b) << 15))
61 #define FMTDR(a, b) (0x6A000049 | ((a) << 20) | ((b) << 15))
64 #define NDS32_BREAK_16 (0x00EA)
65 #define NDS32_BREAK_32 (0x0A000064)
1.9.1