21 #define _E "DSP5680XX_ERROR:%d\nAt:%s:%d:%s"
22 #define err_check(r, c, m) if (r != ERROR_OK) {LOG_ERROR(_E, c, __func__, __LINE__, m); return r; }
23 #define err_check_propagate(retval) if (retval != ERROR_OK) return retval;
24 #define DEBUG_MSG "Debug mode be enabled to read mem."
25 #define DEBUG_FAIL { err_check(ERROR_FAIL, DSP5680XX_ERROR_NOT_IN_DEBUG, DEBUG_MSG) }
26 #define CHECK_DBG if (!dsp5680xx_context.debug_mode_enabled) DEBUG_FAIL
27 #define HALT_MSG "Target must be halted."
28 #define HALT_FAIL { err_check(ERROR_FAIL, DSP5680XX_ERROR_TARGET_RUNNING, HALT_MSG) }
29 #define CHECK_HALT(target) if (target->state != TARGET_HALTED) HALT_FAIL
30 #define check_halt_and_debug(target) { CHECK_HALT(target); CHECK_DBG; }
49 const char *cp =
"RESET";
62 uint8_t *d_out,
int len)
85 "dr_len overflow, maximum is 32");
97 LOG_DEBUG(
"Data read (%d bits): 0x%04X", len, *d_out);
113 uint32_t *d_out, uint8_t ir_len)
133 || ((t->
enabled) && (ir_len != tap_ir_len))) {
153 uint32_t read_from_ir;
165 *
status = (uint8_t) read_from_ir;
172 uint32_t bogus_instr = 0;
177 LOG_DEBUG(
"Data read (%d bits): 0x%04X", num_bits, *data_read);
182 #define jtag_data_read8(target, data_read) jtag_data_read(target, data_read, 8)
183 #define jtag_data_read16(target, data_read) jtag_data_read(target, data_read, 16)
184 #define jtag_data_read32(target, data_read) jtag_data_read(target, data_read, 32)
202 #define jtag_data_write8(target, instr, data_read) jtag_data_write(target, instr, 8, data_read)
203 #define jtag_data_write16(target, instr, data_read) jtag_data_write(target, instr, 16, data_read)
204 #define jtag_data_write24(target, instr, data_read) jtag_data_write(target, instr, 24, data_read)
205 #define jtag_data_write32(target, instr, data_read) jtag_data_write(target, instr, 32, data_read)
220 uint8_t rw, uint8_t go, uint8_t ex,
221 uint8_t *eonce_status)
227 uint8_t instr_with_flags = instr | (rw << 7) | (go << 6) | (ex << 5);
232 *eonce_status = (uint8_t) dr_out_tmp;
237 #define dsp5680xx_exe_1(target, oc1, oc2, oc3) dsp5680xx_exe1(target, oc1)
238 #define dsp5680xx_exe_2(target, oc1, oc2, oc3) dsp5680xx_exe2(target, oc1, oc2)
239 #define dsp5680xx_exe_3(target, oc1, oc2, oc3) dsp5680xx_exe3(target, oc1, oc2, oc3)
240 #define dsp5680xx_exe_generic(t, words, oc1, oc2, oc3) dsp5680xx_exe_##words(t, oc1, oc2, oc3)
273 uint16_t opcode2, uint16_t opcode3)
306 uint32_t *eonce_status_low)
320 #define CMD1 eonce_instruction_exec_single(target, DSP5680XX_ONCE_ORX, 0, 0, 0, NULL);
321 #define CMD2 jtag_data_write16((t, data)
322 #define core_tx_lower_data(t, data) PT1\ PT2
368 #define exe(a, b, c, d, e) dsp5680xx_exe_generic(a, b, c, d, e)
371 #define core_move_long_to_r0(target, value) exe(target, 3, 0xe418, value&0xffff, value>>16)
374 #define core_move_long_to_n(target, value) exe(target, 3, 0xe41e, value&0xffff, value>>16)
377 #define core_move_at_r0_to_y0(target) exe(target, 1, 0xF514, 0, 0)
380 #define core_move_at_r0_to_y1(target) exe(target, 1, 0xF714, 0, 0)
383 #define core_move_long_at_r0_y(target) exe(target, 1, 0xF734, 0, 0)
386 #define core_move_y0_at_r0(target) exe(target, 1, 0xd514, 0, 0)
389 #define eonce_bfclr_at_r0(target, value) exe(target, 2, 0x8040, value, 0)
392 #define core_move_value_to_y0(target, value) exe(target, 2, 0x8745, value, 0)
395 #define core_move_y0_at_r0_inc(target) exe(target, 1, 0xd500, 0, 0)
398 #define core_move_y0_at_pr0_inc(target) exe(target, 1, 0x8560, 0, 0)
401 #define core_move_at_pr0_inc_to_y0(target) exe(target, 1, 0x8568, 0, 0)
404 #define core_move_at_pr0_inc_to_y1(target) exe(target, 1, 0x8768, 0, 0)
407 #define core_move_long_to_r2(target, value) exe(target, 3, 0xe41A, value&0xffff, value>>16)
410 #define core_move_y0_at_r2(target) exe(target, 1, 0xd516, 0, 0)
413 #define core_move_value_at_r2(target, value) exe(target, 2, 0x8642, value, 0)
416 #define core_move_value_at_r0(target, value) exe(target, 2, 0x8640, value, 0)
419 #define core_move_value_at_r2_disp(target, value, disp) exe(target, 3, 0x8646, value, disp)
422 #define core_move_at_r2_to_y0(target) exe(target, 1, 0xF516, 0, 0)
425 #define core_move_at_pr2_inc_to_y0(target) exe(target, 1, 0x856A, 0, 0)
428 #define core_move_long_to_r1(target, value) exe(target, 3, 0xE419, value&0xffff, value>>16)
431 #define core_move_long_to_r3(target, value) exe(target, 3, 0xE41B, value&0xffff, value>>16)
434 #define core_move_y0_at_pr3_inc(target) exe(target, 1, 0x8563, 0, 0)
437 #define core_move_y0_at_r3(target) exe(target, 1, 0xD503, 0, 0)
440 #define core_move_long_to_r4(target, value) exe(target, 3, 0xE41C, value&0xffff, value>>16)
443 #define core_move_pc_to_r4(target) exe(target, 1, 0xE716, 0, 0)
446 #define core_move_r4_to_y(target) exe(target, 1, 0xe764, 0, 0)
449 #define core_move_at_pr0_inc_to_y0(target) exe(target, 1, 0x8568, 0, 0)
452 #define core_move_at_r0_inc_to_y0(target) exe(target, 1, 0xf500, 0, 0)
455 #define core_move_at_r0_y0(target) exe(target, 1, 0xF514, 0, 0)
458 #define eonce_nop(target) exe(target, 1, 0xe700, 0, 0)
461 #define core_move_at_r2_disp_to_y0(target, disp) exe(target, 2, 0xF542, disp, 0)
464 #define core_move_y1_at_r2(target) exe(target, 1, 0xd716, 0, 0)
467 #define core_move_y1_at_r0(target) exe(target, 1, 0xd714, 0, 0)
470 #define core_move_byte_y0_at_r0(target) exe(target, 1, 0xd5a0, 0, 0)
473 #define core_move_y1_at_pr0_inc(target) exe(target, 1, 0x8760, 0, 0)
476 #define core_move_y1_at_r0_inc(target) exe(target, 1, 0xD700, 0, 0)
479 #define core_move_long_to_y(target, value) exe(target, 3, 0xe417, value&0xffff, value>>16)
521 uint32_t dummy_data_to_shift_into_dr;
527 (uint8_t *) data_read, 8);
529 LOG_DEBUG(
"Reg. data: 0x%02X.", *data_read);
573 const char *msg =
"Failed to get master tap.";
584 "Failed to get core tap.");
590 (
"Master:%d\nCore:%d\nOnly 1 should be enabled.\n",
603 (uint8_t *) &ir_out, 4);
616 (uint8_t *) &ir_out, 4);
639 uint16_t *eonce_status)
671 uint16_t data_read_from_dr;
675 if ((data_read_from_dr & 0x30) == 0x30) {
676 LOG_DEBUG(
"EOnCE successfully entered debug mode.");
688 *eonce_status = data_read_from_dr;
701 uint16_t *eonce_status)
726 "Failed to get master tap.");
732 "Failed to get master tap.");
774 (uint8_t *) &read_16, 8);
779 (uint8_t *) &read_16, 8);
787 for (
int i = 0; i < 3; i++) {
798 "Failed to halt target.");
801 for (
int i = 0; i < 3; i++) {
804 (uint8_t *) &read_16, 16);
807 (uint8_t *) &read_16, 16);
811 uint16_t data_read_from_dr;
815 if ((data_read_from_dr & 0x30) == 0x30) {
816 LOG_DEBUG(
"EOnCE successfully entered debug mode.");
820 const char *msg =
"Failed to set EOnCE module to debug mode";
826 *eonce_status = data_read_from_dr;
853 LOG_USER(
"PC value: 0x%X%X\n", tmp[1], tmp[0]);
880 LOG_USER(
"%s not implemented yet.", __func__);
900 uint16_t eonce_status = 0xbeef;
904 LOG_USER(
"Target already halted and in debug mode.");
909 (
"Target already halted, re attempting to enter debug mode.");
928 uint8_t eonce_status;
938 eonce_status = (uint8_t) read_tmp;
942 "%s: Failed to put EOnCE in debug mode.Flash locked?...";
959 "%s: JTAG running, but EOnCE run failed.Try resetting..";
970 eonce_status = (uint8_t) read_tmp;
974 (
"Inconsistent target status. Restart!");
983 (
"%s: Cannot communicate with JTAG. Check connection...",
989 LOG_ERROR(
"%s: Target status invalid - communication failure",
1000 LOG_USER(
"Target already running.");
1005 uint8_t eonce_status;
1007 uint8_t jtag_status;
1017 while (retry-- > 1) {
1026 "Failed to exit debug mode...");
1031 LOG_DEBUG(
"EOnCE status: 0x%02X.", eonce_status);
1043 "Failed to reset JTAG state machine");
1055 "Failed to resume target");
1080 if (((*address) & 0xff0000) != 0xff0000)
1087 uint8_t *data_read,
int r_pmem)
1091 uint32_t address = a;
1109 LOG_DEBUG(
"%s:Data read from 0x%06" PRIX32
": 0x%02X%02X", __func__, address,
1110 data_read[1], data_read[0]);
1115 uint8_t *data_read,
int r_pmem)
1119 uint32_t address = a;
1123 address = (address & 0xFFFFF);
1155 uint32_t
count, uint8_t *buf)
1159 uint32_t address = a;
1175 for (
unsigned i = 0; i <
count; i++) {
1176 if (--counter == 0) {
1199 LOG_USER(
"%s: Invalid read size.", __func__);
1214 uint16_t data, uint8_t w_pmem)
1218 uint32_t address = a;
1237 uint32_t data,
int w_pmem)
1241 uint32_t address = a;
1263 const uint8_t *d,
int pmem)
1267 uint32_t address = a;
1271 const uint8_t *data = d;
1281 for (iter = 0; iter <
count / 2; iter++) {
1282 if (--counter == 0) {
1286 data_16 = (data[2 * iter] | (data[2 * iter + 1] << 8));
1291 LOG_ERROR(
"%s: Could not write to p:0x%04" PRIX32, __func__,
1307 (uint8_t *) &data_old);
1310 data_old = (((data_old & 0xff) << 8) | data[0]);
1313 (((data_old & 0xff) << 8) | data[2 * iter + 1]);
1323 const uint8_t *d,
int pmem)
1327 uint32_t address = a;
1331 const uint8_t *data = d;
1339 for (iter = 0; iter <
count; iter++) {
1340 if (--counter == 0) {
1348 LOG_ERROR(
"%s: Could not write to p:0x%04" PRIX32, __func__,
1360 const uint8_t *d,
int pmem)
1364 uint32_t address = a;
1368 const uint8_t *data = d;
1376 for (iter = 0; iter <
count; iter++) {
1377 if (--counter == 0) {
1385 LOG_ERROR(
"%s: Could not write to p:0x%04" PRIX32, __func__,
1413 uint32_t address = a;
1415 uint8_t
const *
buffer = b;
1442 "Invalid data size.");
1502 static int perl_crc(
const uint8_t *buff8, uint32_t word_count)
1504 uint16_t checksum = 0xffff;
1506 uint16_t data, fbmisr;
1510 for (i = 0; i < word_count; i++) {
1511 data = (buff8[2 * i] | (buff8[2 * i + 1] << 8));
1513 (checksum & 2) >> 1 ^ (checksum & 4) >> 2 ^ (checksum & 16)
1514 >> 4 ^ (checksum & 0x8000) >> 15;
1515 checksum = (data ^ ((checksum << 1) | fbmisr));
1518 for (; !(i & 0x80000000); i--) {
1519 data = (buff8[2 * i] | (buff8[2 * i + 1] << 8));
1521 (checksum & 2) >> 1 ^ (checksum & 4) >> 2 ^ (checksum & 16)
1522 >> 4 ^ (checksum & 0x8000) >> 15;
1523 checksum = (data ^ ((checksum << 1) | fbmisr));
1547 (
const uint8_t *)&sim_cmd);
1578 const char *msg =
"NULL pointer not valid.";
1585 (uint8_t *)
protected, 0);
1604 uint16_t *hfm_ustat,
int pmem)
1624 if ((watchdog--) == 1) {
1627 "Timed out waiting for FM to finish old command.";
1630 }
while (!(i[0] & 0x40));
1683 if ((watchdog--) == 1) {
1686 "FM execution did not finish.");
1688 }
while (!(i[0] & 0x40));
1689 *hfm_ustat = ((i[0] << 8) | (i[1]));
1693 "pviol and/or accer bits set. HFM command execution error";
1728 unsigned int hfm_at_wrong_value = 0;
1731 LOG_DEBUG(
"HFM CLK divisor contained incorrect value (0x%02X).",
1733 hfm_at_wrong_value = 1;
1736 (
"HFM CLK divisor was already set to correct value (0x%02X).",
1753 "Unable to set HFM CLK divisor.");
1755 if (hfm_at_wrong_value)
1756 LOG_DEBUG(
"HFM CLK divisor set to 0x%02x.", i[0] & 0x7f);
1775 uint16_t *signature)
1787 "Failed to halt target.");
1795 (uint8_t *) signature, 0);
1885 int do_mass_erase = ((!(first | last))
1888 if (do_mass_erase) {
1893 for (
int i = first; i <= last; i++) {
1944 0x8A46, 0x0013, 0x807D, 0xE700,
1945 0xE700, 0x8A44, 0xFFFE, 0x017B,
1946 0xE700, 0xF514, 0x8563, 0x8646,
1947 0x0020, 0x0014, 0x8646, 0x0080,
1948 0x0013, 0xF042, 0x0013, 0x8B40,
1949 0x2004, 0x8246, 0x0013, 0x0020,
1950 0xA967, 0x8B40, 0x1065, 0x8246,
1951 0x0013, 0x0010, 0xA961
1961 uint32_t address = a;
1963 const uint8_t *
buffer = b;
1977 uint32_t ram_addr = 0x8700;
1983 if (!is_flash_lock) {
2034 const char *msg =
"Cannot handle odd number of words.";
2044 uint32_t drscan_data;
2060 if (--counter == 0) {
2073 if (!is_flash_lock) {
2085 if (pc_crc != signature) {
2088 "Flashed data failed CRC check, flash again!";
2099 uint16_t eonce_status;
2113 "Failed to get master tap.");
2119 "Failed to get master tap.");
2131 "Failed to reset JTAG state machine");
2170 "Failed to reset JTAG state machine");
2212 "Failed to reset JTAG state machine");
2221 "Failed to get master tap.");
2227 "Failed to get master tap.");
2238 int handle_breakpoints)
2241 "Not implemented yet.");
2246 .
name =
"dsp5680xx",
#define JTAG_INSTR_ENABLE_ONCE
#define JTAG_STATUS_DEBUG
#define JTAG_STATUS_NORMAL
#define JTAG_INSTR_DEBUG_REQUEST
static int core_tx_upper_data(struct target *target, uint16_t data, uint32_t *eonce_status_low)
static int dsp5680xx_read_buffer(struct target *target, target_addr_t address, uint32_t size, uint8_t *buffer)
This function is called by verify_image, it is used to read data from memory.
static int dsp5680xx_soft_reset_halt(struct target *target)
Halts the core and resets the SIM.
static uint32_t data_read_dummy
static int dsp5680xx_halt(struct target *target)
static int dsp5680xx_deassert_reset(struct target *target)
#define core_move_value_at_r2_disp(target, value, disp)
#define core_move_y0_at_pr0_inc(target)
static int dsp5680xx_read_32_single(struct target *t, uint32_t a, uint8_t *data_read, int r_pmem)
static int eonce_exit_debug_mode(struct target *target, uint8_t *eonce_status)
Takes the core out of debug mode.
static int core_load_tx_rx_high_addr_to_r0(struct target *target)
#define core_move_at_r2_disp_to_y0(target, disp)
#define core_move_pc_to_r4(target)
static int jtag_data_write(struct target *target, uint32_t instr, int num_bits, uint32_t *data_read)
static int dsp5680xx_exe2(struct target *target, uint16_t opcode1, uint16_t opcode2)
static int dsp5680xx_convert_address(uint32_t *address, int *pmem)
The value of address determines if it corresponds to P: (program) or X: (dat) memory.
static int dsp5680xx_write_16_single(struct target *t, uint32_t a, uint16_t data, uint8_t w_pmem)
static int eonce_instruction_exec_single(struct target *target, uint8_t instr, uint8_t rw, uint8_t go, uint8_t ex, uint8_t *eonce_status)
Executes EOnCE instruction.
#define core_move_at_r0_to_y0(target)
static const uint32_t pgm_write_pflash_length
int dsp5680xx_f_erase(struct target *target, int first, int last)
Erases either a sector or the complete flash array.
#define core_move_at_pr0_inc_to_y1(target)
#define core_move_at_pr0_inc_to_y0(target)
static int dsp5680xx_step(struct target *target, int current, target_addr_t address, int handle_breakpoints)
int dsp5680xx_f_lock(struct target *target)
Writes the flash security words with a specific value.
static int dsp5680xx_irscan(struct target *target, uint32_t *d_in, uint32_t *d_out, uint8_t ir_len)
Test func.
static int dsp5680xx_resume(struct target *target, int current, target_addr_t address, int hb, int d)
static int mass_erase(struct target *target, uint16_t *hfm_ustat)
Executes the FM mass erase command.
static int dsp5680xx_drscan(struct target *target, uint8_t *d_in, uint8_t *d_out, int len)
#define core_move_y0_at_r0(target)
#define core_move_y0_at_r0_inc(target)
static int dsp5680xx_target_create(struct target *target, Jim_Interp *interp)
#define core_move_y1_at_r0(target)
#define core_move_y1_at_pr0_inc(target)
#define err_check_propagate(retval)
static int jtag_data_read(struct target *target, uint8_t *data_read, int num_bits)
#define dsp5680xx_exe_generic(t, words, oc1, oc2, oc3)
static int dsp5680xx_write_8(struct target *t, uint32_t a, uint32_t c, const uint8_t *d, int pmem)
static int dsp5680xx_poll(struct target *target)
static int switch_tap(struct target *target, struct jtag_tap *master_tap, struct jtag_tap *core_tap)
static int dsp5680xx_f_signature(struct target *target, uint32_t address, uint32_t words, uint16_t *signature)
Executes the FM calculate signature command.
static int dsp5680xx_exe1(struct target *target, uint16_t opcode)
static int dsp5680xx_read_core_reg(struct target *target, uint8_t reg_addr, uint16_t *data_read)
#define jtag_data_write16(target, instr, data_read)
static int core_rx_lower_data(struct target *target, uint8_t *data_read)
#define err_check(r, c, m)
#define core_move_value_to_y0(target, value)
static int dsp5680xx_f_sim_reset(struct target *target)
Resets the SIM.
static int dsp5680xx_assert_reset(struct target *target)
#define core_move_y0_at_pr3_inc(target)
#define core_move_at_r2_to_y0(target)
#define core_move_at_r0_to_y1(target)
#define core_move_r4_to_y(target)
static int eonce_enter_debug_mode_without_reset(struct target *target, uint16_t *eonce_status)
Puts the core into debug mode, enabling the EOnCE module.
static int dsp5680xx_read(struct target *t, target_addr_t a, uint32_t size, uint32_t count, uint8_t *buf)
#define core_move_y1_at_r0_inc(target)
static int eonce_load_tx_rx_to_r0(struct target *target)
static int dsp5680xx_write_32_single(struct target *t, uint32_t a, uint32_t data, int w_pmem)
static int dsp5680xx_exe3(struct target *target, uint16_t opcode1, uint16_t opcode2, uint16_t opcode3)
static int dsp5680xx_jtag_status(struct target *target, uint8_t *status)
static int eonce_enter_debug_mode(struct target *target, uint16_t *eonce_status)
Puts the core into debug mode, enabling the EOnCE module.
static int dsp5680xx_init_target(struct command_context *cmd_ctx, struct target *target)
#define core_move_value_at_r2(target, value)
#define check_halt_and_debug(target)
static int dsp5680xx_write(struct target *target, target_addr_t a, uint32_t size, uint32_t count, const uint8_t *b)
Writes buffer to memory.
static int dsp5680xx_write_16(struct target *t, uint32_t a, uint32_t c, const uint8_t *d, int pmem)
static int dsp5680xx_execute_queue(void)
#define core_move_value_at_r0(target, value)
#define core_move_long_to_r3(target, value)
int dsp5680xx_f_unlock(struct target *target)
Executes a mass erase command.
static int core_move_value_to_pc(struct target *target, uint32_t value)
static int perl_crc(const uint8_t *buff8, uint32_t word_count)
Calculates a signature over word_count words in the data from buff8.
#define core_move_y0_at_r3(target)
static int set_fm_ck_div(struct target *target)
Prior to the execution of any Flash module command, the Flash module Clock Divider (CLKDIV) register ...
static int dsp5680xx_write_32(struct target *t, uint32_t a, uint32_t c, const uint8_t *d, int pmem)
static int dsp5680xx_checksum_memory(struct target *target, target_addr_t address, uint32_t size, uint32_t *checksum)
This function is not implemented.
static int dsp5680xx_read_16_single(struct target *t, uint32_t a, uint8_t *data_read, int r_pmem)
#define jtag_data_read16(target, data_read)
#define core_move_long_to_r2(target, value)
static int dsp5680xx_arch_state(struct target *target)
int dsp5680xx_f_wr(struct target *t, const uint8_t *b, uint32_t a, uint32_t count, int is_flash_lock)
Writes to flash memory.
#define core_move_at_r0_inc_to_y0(target)
static int core_rx_upper_data(struct target *target, uint8_t *data_read)
static int dsp5680xx_f_ex(struct target *target, uint16_t c, uint32_t address, uint32_t data, uint16_t *hfm_ustat, int pmem)
Executes a command on the FM module.
static int eonce_read_status_reg(struct target *target, uint16_t *data)
static struct dsp5680xx_common dsp5680xx_context
#define core_move_long_to_r0(target, value)
int dsp5680xx_f_protect_check(struct target *target, uint16_t *protected)
Reads the memory mapped protection register.
struct target_type dsp5680xx_target
Holds methods for dsp5680xx targets.
static int reset_jtag(void)
Reset state machine.
static const uint16_t pgm_write_pflash[]
int dsp5680xx_f_erase_check(struct target *target, uint8_t *erased, uint32_t sector)
The FM has the functionality of checking if the flash array is erased.
static int erase_sector(struct target *target, int sector, uint16_t *hfm_ustat)
Executes the FM page erase command.
#define core_move_long_to_y(target, value)
static int eonce_pc_store(struct target *target)
Reads the current value of the program counter and stores it.
static int dsp5680xx_write_buffer(struct target *t, target_addr_t a, uint32_t size, const uint8_t *b)
Basic support for the 5680xx DSP from Freescale. The chip has two taps in the JTAG chain,...
#define HFM_USTAT_MASK_BLANK
#define DSP5680XX_ERROR_JTAG_TAP_FIND_MASTER
#define DSP5680XX_ERROR_ENTER_DEBUG_MODE
#define DSP5680XX_ERROR_INVALID_IR_LEN
#define DSP5680XX_ERROR_FLASHING_INVALID_WORD_COUNT
#define FLUSH_COUNT_READ_WRITE
#define DSP5680XX_ERROR_RESUME
#define MASTER_TAP_CMD_FLASH_ERASE
#define DSP5680XX_ERROR_EXIT_DEBUG_MODE
#define DSP5680XX_ERROR_NOT_IMPLEMENTED_STEP
#define MC568013_EONCE_TX1_RX1_HIGH_ADDR
#define HFM_USTAT_MASK_PVIOL_ACCER
#define DSP5680XX_ERROR_JTAG_RESET
#define DSP5680XX_ERROR_HALT
#define HFM_CLK_DEFAULT
The value used on for the FM clock is important to prevent flashing errors and to prevent deteriorati...
#define MC568013_EONCE_OBASE_ADDR
#define DSP5680XX_ERROR_INVALID_DATA_SIZE_UNIT
#define DSP5680XX_ONCE_ORX1
#define FLUSH_COUNT_FLASH
#define DSP5680XX_ERROR_FM_EXEC
#define DSP5680XX_ERROR_FM_SET_CLK
#define DSP5680XX_ERROR_JTAG_TAP_FIND_CORE
#define DSP5680XX_ERROR_JTAG_IRSCAN
#define DSP5680XX_JTAG_MASTER_TAP_IRLEN
#define MC568013_SIM_BASE_ADDR
#define DSP5680XX_ERROR_PROTECT_CHECK_INVALID_ARGS
#define DSP5680XX_ONCE_OSCR_NORMAL_M
#define HFM_FLASH_BASE_ADDR
#define DSP5680XX_ONCE_OTX1
#define HFM_LOCK_FLASH
Writing HFM_LOCK_FLASH to HFM_LOCK_ADDR_L and HFM_LOCK_ADDR_H will enable security on flash after the...
#define DSP5680XX_ONCE_OSCR_DEBUG_M
#define DSP5680XX_ONCE_OTX
#define DSP5680XX_ONCE_OSR
#define MASTER_TAP_CMD_IDCODE
#define S_FILE_DATA_OFFSET
#define DSP5680XX_ERROR_JTAG_DRSCAN
#define DSP5680XX_ERROR_FM_BUSY
#define HFM_CALCULATE_DATA_SIGNATURE
#define TIME_DIV_FREESCALE
#define DSP5680XX_ERROR_FLASHING_CRC
#define DSP5680XX_ERROR_JTAG_TAP_ENABLE_MASTER
#define DSP5680XX_ERROR_JTAG_DR_LEN_OVERFLOW
#define DSP5680XX_ERROR_JTAG_INVALID_TAP
#define DSP5680XX_ERROR_FM_CMD_TIMED_OUT
#define DSP5680XX_ERROR_JTAG_TAP_ENABLE_CORE
#define MC568013_EONCE_TX_RX_ADDR
#define DSP5680XX_JTAG_CORE_TAP_IRLEN
tap_state_t tap_state_by_name(const char *name)
Provides user-friendly name lookup of TAP states.
struct jtag_tap * jtag_tap_by_string(const char *s)
void jtag_add_plain_dr_scan(int num_bits, const uint8_t *out_bits, uint8_t *in_bits, tap_state_t state)
Scan out the bits in ir scan mode.
void jtag_add_pathmove(int num_states, const tap_state_t *path)
Application code must assume that interfaces will implement transitions between states with different...
void jtag_add_reset(int req_tlr_or_trst, int req_srst)
A reset of the TAP state machine can be requested.
void jtag_add_plain_ir_scan(int num_bits, const uint8_t *out_bits, uint8_t *in_bits, tap_state_t state)
Scan out the bits in ir scan mode.
int jtag_execute_queue(void)
For software FIFO implementations, the queued commands can be executed during this call or earlier.
int jtag_add_statemove(tap_state_t goal_state)
jtag_add_statemove() moves from the current state to goal_state.
void jtag_add_sleep(uint32_t us)
enum tap_state tap_state_t
Defines JTAG Test Access Port states.
#define LOG_USER(expr ...)
#define LOG_WARNING(expr ...)
#define LOG_ERROR(expr ...)
#define LOG_DEBUG(expr ...)
size_t size
Size of the control block search area.
int ir_length
size of instruction register
bool enabled
Is this TAP currently enabled?
This holds methods shared between all instances of a given target type.
const char * name
Name of this type of target.
#define ERROR_TARGET_DATA_ABORT
#define ERROR_TARGET_FAILURE