OpenOCD
xtensa_chip.c
Go to the documentation of this file.
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 
3 /***************************************************************************
4  * Xtensa Chip-level Target Support for OpenOCD *
5  * Copyright (C) 2020-2022 Cadence Design Systems, Inc. *
6  ***************************************************************************/
7 
8 #ifdef HAVE_CONFIG_H
9 #include "config.h"
10 #endif
11 
12 #include "assert.h"
13 #include <target/target.h>
14 #include <target/target_type.h>
15 #include <target/arm_adi_v5.h>
16 #include <rtos/rtos.h>
17 #include "xtensa_chip.h"
18 #include "xtensa_fileio.h"
19 
20 int xtensa_chip_init_arch_info(struct target *target, void *arch_info,
21  struct xtensa_debug_module_config *dm_cfg)
22 {
23  struct xtensa_chip_common *xtensa_chip = (struct xtensa_chip_common *)arch_info;
24  int ret = xtensa_init_arch_info(target, &xtensa_chip->xtensa, dm_cfg);
25  if (ret != ERROR_OK)
26  return ret;
27  /* All xtensa target structures point back to original xtensa_chip */
28  xtensa_chip->xtensa.xtensa_chip = arch_info;
29  return ERROR_OK;
30 }
31 
33 {
34  int ret = xtensa_target_init(cmd_ctx, target);
35  if (ret != ERROR_OK)
36  return ret;
37  return xtensa_fileio_init(target);
38 }
39 
41 {
42  return ERROR_OK;
43 }
44 
45 static int xtensa_chip_poll(struct target *target)
46 {
47  enum target_state old_state = target->state;
48  int ret = xtensa_poll(target);
49 
50  if (old_state != TARGET_HALTED && target->state == TARGET_HALTED) {
51  /*Call any event callbacks that are applicable */
52  if (old_state == TARGET_DEBUG_RUNNING) {
54  } else {
57  }
58  }
59 
60  return ret;
61 }
62 
63 static int xtensa_chip_virt2phys(struct target *target,
64  target_addr_t virtual, target_addr_t *physical)
65 {
66  if (physical) {
67  *physical = virtual;
68  return ERROR_OK;
69  }
70  return ERROR_FAIL;
71 }
72 
73 static const struct xtensa_debug_ops xtensa_chip_dm_dbg_ops = {
75  .queue_reg_read = xtensa_dm_queue_reg_read,
76  .queue_reg_write = xtensa_dm_queue_reg_write
77 };
78 
79 static const struct xtensa_power_ops xtensa_chip_dm_pwr_ops = {
81  .queue_reg_write = xtensa_dm_queue_pwr_reg_write
82 };
83 
84 static int xtensa_chip_target_create(struct target *target, Jim_Interp *interp)
85 {
86  struct xtensa_debug_module_config xtensa_chip_dm_cfg = {
88  .pwr_ops = &xtensa_chip_dm_pwr_ops,
89  .tap = NULL,
90  .queue_tdi_idle = NULL,
91  .queue_tdi_idle_arg = NULL,
92  .dap = NULL,
93  .debug_ap = NULL,
94  .debug_apsel = DP_APSEL_INVALID,
95  .ap_offset = 0,
96  };
97 
99  if (adiv5_verify_config(pc) == ERROR_OK) {
100  xtensa_chip_dm_cfg.dap = pc->dap;
101  xtensa_chip_dm_cfg.debug_apsel = pc->ap_num;
102  xtensa_chip_dm_cfg.ap_offset = target->dbgbase;
103  LOG_DEBUG("DAP: ap_num %" PRId64 " DAP %p\n", pc->ap_num, pc->dap);
104  } else {
105  xtensa_chip_dm_cfg.tap = target->tap;
106  LOG_DEBUG("JTAG: %s:%s pos %d", target->tap->chip, target->tap->tapname,
108  }
109 
110  struct xtensa_chip_common *xtensa_chip = calloc(1, sizeof(struct xtensa_chip_common));
111  if (!xtensa_chip) {
112  LOG_ERROR("Failed to alloc chip-level memory!");
113  return ERROR_FAIL;
114  }
115 
116  int ret = xtensa_chip_init_arch_info(target, xtensa_chip, &xtensa_chip_dm_cfg);
117  if (ret != ERROR_OK) {
118  LOG_ERROR("Failed to init arch info!");
119  free(xtensa_chip);
120  return ret;
121  }
122 
123  /*Assume running target. If different, the first poll will fix this. */
126  return ERROR_OK;
127 }
128 
130 {
133  free(xtensa->xtensa_chip);
134 }
135 
136 static int xtensa_chip_examine(struct target *target)
137 {
139  int retval = xtensa_dm_examine(&xtensa->dbg_mod);
140  if (retval == ERROR_OK)
141  retval = xtensa_examine(target);
142  return retval;
143 }
144 
145 static int xtensa_chip_jim_configure(struct target *target, struct jim_getopt_info *goi)
146 {
148 }
149 
152  .name = "xtensa",
153 
154  .poll = xtensa_chip_poll,
155  .arch_state = xtensa_chip_arch_state,
156 
157  .halt = xtensa_halt,
158  .resume = xtensa_resume,
159  .step = xtensa_step,
160 
161  .assert_reset = xtensa_assert_reset,
162  .deassert_reset = xtensa_deassert_reset,
163  .soft_reset_halt = xtensa_soft_reset_halt,
164 
165  .virt2phys = xtensa_chip_virt2phys,
166  .mmu = xtensa_mmu_is_enabled,
167  .read_memory = xtensa_read_memory,
168  .write_memory = xtensa_write_memory,
169 
170  .read_buffer = xtensa_read_buffer,
171  .write_buffer = xtensa_write_buffer,
172 
173  .checksum_memory = xtensa_checksum_memory,
174 
175  .get_gdb_reg_list = xtensa_get_gdb_reg_list,
176 
177  .run_algorithm = xtensa_run_algorithm,
178  .start_algorithm = xtensa_start_algorithm,
179  .wait_algorithm = xtensa_wait_algorithm,
180 
181  .add_breakpoint = xtensa_breakpoint_add,
182  .remove_breakpoint = xtensa_breakpoint_remove,
183 
184  .add_watchpoint = xtensa_watchpoint_add,
185  .remove_watchpoint = xtensa_watchpoint_remove,
186 
187  .target_create = xtensa_chip_target_create,
188  .target_jim_configure = xtensa_chip_jim_configure,
189  .init_target = xtensa_chip_target_init,
190  .examine = xtensa_chip_examine,
191  .deinit_target = xtensa_chip_target_deinit,
192 
193  .gdb_query_custom = xtensa_gdb_query_custom,
194 
195  .commands = xtensa_command_handlers,
196 
197  .get_gdb_fileio_info = xtensa_get_gdb_fileio_info,
198  .gdb_fileio_end = xtensa_gdb_fileio_end,
199 };
int adiv5_verify_config(struct adiv5_private_config *pc)
Definition: arm_adi_v5.c:2472
int adiv5_jim_configure_ext(struct target *target, struct jim_getopt_info *goi, struct adiv5_private_config *pc, enum adiv5_configure_dap_optional optional)
Definition: arm_adi_v5.c:2427
This defines formats and data structures used to talk to ADIv5 entities.
@ ADI_CONFIGURE_DAP_OPTIONAL
Definition: arm_adi_v5.h:794
#define DP_APSEL_INVALID
Definition: arm_adi_v5.h:110
#define ERROR_FAIL
Definition: log.h:170
#define LOG_ERROR(expr ...)
Definition: log.h:132
#define LOG_DEBUG(expr ...)
Definition: log.h:109
#define ERROR_OK
Definition: log.h:164
struct adiv5_dap * dap
Definition: arm_adi_v5.h:787
A TCL -ish GetOpt like code.
Definition: jim-nvp.h:135
int abs_chain_position
Definition: jtag.h:105
char * chip
Definition: jtag.h:102
char * tapname
Definition: jtag.h:103
This holds methods shared between all instances of a given target type.
Definition: target_type.h:26
const char * name
Name of this type of target.
Definition: target_type.h:31
Definition: target.h:116
struct jtag_tap * tap
Definition: target.h:119
enum target_debug_reason debug_reason
Definition: target.h:154
enum target_state state
Definition: target.h:157
uint32_t dbgbase
Definition: target.h:175
void * private_config
Definition: target.h:165
struct xtensa xtensa
Definition: xtensa_chip.h:16
const struct xtensa_debug_ops * dbg_ops
int(* queue_enable)(struct xtensa_debug_module *dm)
enable operation
int(* queue_reg_read)(struct xtensa_debug_module *dm, enum xtensa_dm_pwr_reg reg, uint8_t *data, uint32_t clear)
register read.
Represents a generic Xtensa core.
Definition: xtensa.h:241
struct xtensa_debug_module dbg_mod
Definition: xtensa.h:245
struct xtensa_chip_common * xtensa_chip
Definition: xtensa.h:243
int target_call_event_callbacks(struct target *target, enum target_event event)
Definition: target.c:1764
@ DBG_REASON_NOTHALTED
Definition: target.h:74
@ TARGET_EVENT_HALTED
Definition: target.h:252
@ TARGET_EVENT_DEBUG_HALTED
Definition: target.h:271
target_state
Definition: target.h:53
@ TARGET_DEBUG_RUNNING
Definition: target.h:58
@ TARGET_HALTED
Definition: target.h:56
@ TARGET_RUNNING
Definition: target.h:55
uint64_t target_addr_t
Definition: types.h:335
#define NULL
Definition: usb.h:16
int xtensa_gdb_query_custom(struct target *target, const char *packet, char **response_p)
Definition: xtensa.c:3191
int xtensa_breakpoint_add(struct target *target, struct breakpoint *breakpoint)
Definition: xtensa.c:2481
void xtensa_target_deinit(struct target *target)
Definition: xtensa.c:3412
int xtensa_watchpoint_add(struct target *target, struct watchpoint *watchpoint)
Definition: xtensa.c:2563
int xtensa_poll(struct target *target)
Definition: xtensa.c:2233
int xtensa_halt(struct target *target)
Definition: xtensa.c:1501
int xtensa_breakpoint_remove(struct target *target, struct breakpoint *breakpoint)
Definition: xtensa.c:2525
int xtensa_read_buffer(struct target *target, target_addr_t address, uint32_t count, uint8_t *buffer)
Definition: xtensa.c:2016
int xtensa_get_gdb_reg_list(struct target *target, struct reg **reg_list[], int *reg_list_size, enum target_register_class reg_class)
Definition: xtensa.c:1424
int xtensa_step(struct target *target, int current, target_addr_t address, int handle_breakpoints)
Definition: xtensa.c:1869
int xtensa_target_init(struct command_context *cmd_ctx, struct target *target)
Definition: xtensa.c:3346
int xtensa_checksum_memory(struct target *target, target_addr_t address, uint32_t count, uint32_t *checksum)
Definition: xtensa.c:2227
const struct command_registration xtensa_command_handlers[]
Definition: xtensa.c:4541
int xtensa_examine(struct target *target)
Definition: xtensa.c:821
int xtensa_start_algorithm(struct target *target, int num_mem_params, struct mem_param *mem_params, int num_reg_params, struct reg_param *reg_params, target_addr_t entry_point, target_addr_t exit_point, void *arch_info)
Definition: xtensa.c:2639
int xtensa_init_arch_info(struct target *target, struct xtensa *xtensa, const struct xtensa_debug_module_config *dm_cfg)
Definition: xtensa.c:3302
int xtensa_resume(struct target *target, int current, target_addr_t address, int handle_breakpoints, int debug_execution)
Definition: xtensa.c:1608
int xtensa_watchpoint_remove(struct target *target, struct watchpoint *watchpoint)
Definition: xtensa.c:2619
int xtensa_write_buffer(struct target *target, target_addr_t address, uint32_t count, const uint8_t *buffer)
Definition: xtensa.c:2221
int xtensa_write_memory(struct target *target, target_addr_t address, uint32_t size, uint32_t count, const uint8_t *buffer)
Definition: xtensa.c:2022
int xtensa_mmu_is_enabled(struct target *target, int *enabled)
Definition: xtensa.c:1493
int xtensa_deassert_reset(struct target *target)
Definition: xtensa.c:1117
int xtensa_read_memory(struct target *target, target_addr_t address, uint32_t size, uint32_t count, uint8_t *buffer)
Definition: xtensa.c:1933
int xtensa_soft_reset_halt(struct target *target)
Definition: xtensa.c:1139
int xtensa_assert_reset(struct target *target)
Definition: xtensa.c:1096
int xtensa_run_algorithm(struct target *target, int num_mem_params, struct mem_param *mem_params, int num_reg_params, struct reg_param *reg_params, target_addr_t entry_point, target_addr_t exit_point, unsigned int timeout_ms, void *arch_info)
Definition: xtensa.c:2838
int xtensa_wait_algorithm(struct target *target, int num_mem_params, struct mem_param *mem_params, int num_reg_params, struct reg_param *reg_params, target_addr_t exit_point, unsigned int timeout_ms, void *arch_info)
Waits for an algorithm in the target.
Definition: xtensa.c:2730
static struct xtensa * target_to_xtensa(struct target *target)
Definition: xtensa.h:290
int xtensa_chip_init_arch_info(struct target *target, void *arch_info, struct xtensa_debug_module_config *dm_cfg)
Definition: xtensa_chip.c:20
static void xtensa_chip_target_deinit(struct target *target)
Definition: xtensa_chip.c:129
int xtensa_chip_target_init(struct command_context *cmd_ctx, struct target *target)
Definition: xtensa_chip.c:32
static int xtensa_chip_jim_configure(struct target *target, struct jim_getopt_info *goi)
Definition: xtensa_chip.c:145
static int xtensa_chip_examine(struct target *target)
Definition: xtensa_chip.c:136
int xtensa_chip_arch_state(struct target *target)
Definition: xtensa_chip.c:40
static int xtensa_chip_virt2phys(struct target *target, target_addr_t virtual, target_addr_t *physical)
Definition: xtensa_chip.c:63
struct target_type xtensa_chip_target
Methods for generic example of Xtensa-based chip-level targets.
Definition: xtensa_chip.c:151
static const struct xtensa_debug_ops xtensa_chip_dm_dbg_ops
Definition: xtensa_chip.c:73
static int xtensa_chip_target_create(struct target *target, Jim_Interp *interp)
Definition: xtensa_chip.c:84
static int xtensa_chip_poll(struct target *target)
Definition: xtensa_chip.c:45
static const struct xtensa_power_ops xtensa_chip_dm_pwr_ops
Definition: xtensa_chip.c:79
int xtensa_dm_queue_reg_read(struct xtensa_debug_module *dm, enum xtensa_dm_reg reg, uint8_t *value)
int xtensa_dm_queue_pwr_reg_write(struct xtensa_debug_module *dm, enum xtensa_dm_pwr_reg reg, uint32_t data)
int xtensa_dm_queue_pwr_reg_read(struct xtensa_debug_module *dm, enum xtensa_dm_pwr_reg reg, uint8_t *data, uint32_t clear)
int xtensa_dm_queue_reg_write(struct xtensa_debug_module *dm, enum xtensa_dm_reg reg, uint32_t value)
int xtensa_dm_queue_enable(struct xtensa_debug_module *dm)
int xtensa_dm_examine(struct xtensa_debug_module *dm)
int xtensa_fileio_detect_proc(struct target *target)
Checks for and processes an Xtensa File-IO request.
Definition: xtensa_fileio.c:41
int xtensa_gdb_fileio_end(struct target *target, int retcode, int fileio_errno, bool ctrl_c)
int xtensa_get_gdb_fileio_info(struct target *target, struct gdb_fileio_info *fileio_info)
Definition: xtensa_fileio.c:69
int xtensa_fileio_init(struct target *target)
Definition: xtensa_fileio.c:21