This defines formats and data structures used to talk to ADIv5 entities. More...

Include dependency graph for arm_adi_v5.h:

This graph shows which files directly or indirectly include this file:

Data Structures
struct	adiv5_ap
	This represents an ARM Debug Interface (v5) Access Port (AP). More...

struct	adiv5_dap
	This represents an ARM Debug Interface (v5) Debug Access Port (DAP). More...

struct	adiv5_mem_ap_spot

struct	adiv5_private_config

struct	dap_ops
	Transport-neutral representation of queued DAP transactions, supporting both JTAG and SWD transports. More...

Macros
#define	ADIV5_AP_REG_IDR (0xFC) /* RO: Identification Register */

#define	ADIV5_DP_SELECT_APBANK 0x000000F0

#define	ADIV5_DP_SELECT_APSEL 0xFF000000

#define	ADIV5_MEM_AP_REG_BASE (0xF8) /* RO: Debug Base Address register */

#define	ADIV5_MEM_AP_REG_BASE64 (0xF0) /* RO: Debug Base Address (LA) register */

#define	ADIV5_MEM_AP_REG_BD0 (0x10) /* RW: Banked Data register 0-3 */

#define	ADIV5_MEM_AP_REG_BD1 (0x14)

#define	ADIV5_MEM_AP_REG_BD2 (0x18)

#define	ADIV5_MEM_AP_REG_BD3 (0x1C)

#define	ADIV5_MEM_AP_REG_CFG (0xF4) /* RO: Configuration register */

#define	ADIV5_MEM_AP_REG_CSW (0x00)

#define	ADIV5_MEM_AP_REG_DRW (0x0C) /* RW: Data Read/Write register */

#define	ADIV5_MEM_AP_REG_MBT (0x20) /* --: Memory Barrier Transfer register */

#define	ADIV5_MEM_AP_REG_TAR (0x04)

#define	ADIV5_MEM_AP_REG_TAR64 (0x08) /* RW: Large Physical Address Extension */

#define	ADIV6_AP_REG_IDR (0xD00 + ADIV5_AP_REG_IDR)

#define	ADIV6_MEM_AP_REG_BASE (0xD00 + ADIV5_MEM_AP_REG_BASE)

#define	ADIV6_MEM_AP_REG_BASE64 (0xD00 + ADIV5_MEM_AP_REG_BASE64)

#define	ADIV6_MEM_AP_REG_BD0 (0xD00 + ADIV5_MEM_AP_REG_BD0)

#define	ADIV6_MEM_AP_REG_BD1 (0xD00 + ADIV5_MEM_AP_REG_BD1)

#define	ADIV6_MEM_AP_REG_BD2 (0xD00 + ADIV5_MEM_AP_REG_BD2)

#define	ADIV6_MEM_AP_REG_BD3 (0xD00 + ADIV5_MEM_AP_REG_BD3)

#define	ADIV6_MEM_AP_REG_CFG (0xD00 + ADIV5_MEM_AP_REG_CFG)

#define	ADIV6_MEM_AP_REG_CSW (0xD00 + ADIV5_MEM_AP_REG_CSW)

#define	ADIV6_MEM_AP_REG_DRW (0xD00 + ADIV5_MEM_AP_REG_DRW)

#define	ADIV6_MEM_AP_REG_MBT (0xD00 + ADIV5_MEM_AP_REG_MBT)

#define	ADIV6_MEM_AP_REG_TAR (0xD00 + ADIV5_MEM_AP_REG_TAR)

#define	ADIV6_MEM_AP_REG_TAR64 (0xD00 + ADIV5_MEM_AP_REG_TAR64)

#define	AP_REG_IDR(dap) (is_adiv6(dap) ? ADIV6_AP_REG_IDR : ADIV5_AP_REG_IDR)

#define	AP_REG_IDR_CLASS_COM (0x1)

#define	AP_REG_IDR_CLASS_MASK (0x0001E000)

#define	AP_REG_IDR_CLASS_MEM_AP (0x8)

#define	AP_REG_IDR_CLASS_NONE (0x0)

#define	AP_REG_IDR_CLASS_SHIFT (13)

#define	AP_REG_IDR_DESIGNER_MASK (0x0FFE0000)

#define	AP_REG_IDR_DESIGNER_SHIFT (17)

#define	AP_REG_IDR_REVISION_MASK (0xF0000000)

#define	AP_REG_IDR_REVISION_SHIFT (28)

#define	AP_REG_IDR_TYPE_MASK (0x0000000F)

#define	AP_REG_IDR_TYPE_SHIFT (0)

#define	AP_REG_IDR_VALUE(d, c, t)

#define	AP_REG_IDR_VARIANT_MASK (0x000000F0)

#define	AP_REG_IDR_VARIANT_SHIFT (4)

#define	AP_TYPE_MASK (AP_REG_IDR_DESIGNER_MASK \| AP_REG_IDR_CLASS_MASK \| AP_REG_IDR_TYPE_MASK)

#define	ARM_ID 0x23B

#define	BANK_REG(bank, reg) (((bank) << 4) \| (reg))

#define	CDBGPWRUPACK (1UL << 29)

#define	CDBGPWRUPREQ (1UL << 28)

#define	CDBGRSTACK (1UL << 27)

#define	CDBGRSTREQ (1UL << 26)

#define	CORUNDETECT (1UL << 0)

#define	CSW_128BIT 4

#define	CSW_16BIT 1

#define	CSW_256BIT 5

#define	CSW_32BIT 2

#define	CSW_64BIT 3

#define	CSW_8BIT 0

#define	CSW_ADDRINC_MASK (3UL << 4)

#define	CSW_ADDRINC_OFF 0UL

#define	CSW_ADDRINC_PACKED (2UL << 4)

#define	CSW_ADDRINC_SINGLE (1UL << 4)

#define	CSW_AHB_DEFAULT (CSW_AHB_HPROT1 \| CSW_AHB_MASTER_DEBUG \| CSW_DBGSWENABLE)

#define	CSW_AHB_HPROT1 (1UL << 25)

#define	CSW_AHB_MASTER_DEBUG (1UL << 29)

#define	CSW_AHB_SPROT (1UL << 30)

#define	CSW_APB_DEFAULT (CSW_DBGSWENABLE)

#define	CSW_AXI_ARPROT0_PRIV (1UL << 28)

#define	CSW_AXI_ARPROT1_NONSEC (1UL << 29)

#define	CSW_AXI_DEFAULT (CSW_AXI_ARPROT0_PRIV \| CSW_AXI_ARPROT1_NONSEC \| CSW_DBGSWENABLE)

#define	CSW_DBGSWENABLE (1UL << 31)

#define	CSW_DEVICE_EN (1UL << 6)

#define	CSW_SIZE_MASK 7

#define	CSW_SPIDEN (1UL << 23)

#define	CSW_TRIN_PROG (1UL << 7)

#define	CSYSPWRUPACK (1UL << 31)

#define	CSYSPWRUPREQ (1UL << 30)

#define	DAPABORT (1UL << 0)

#define	DLCR_TO_TRN(dlcr) ((uint32_t)(1 + ((3 & (dlcr)) >> 8))) /* 1..4 clocks */

#define	DP_ABORT BANK_REG(0x0, 0x0) /* DPv1+: SWD: wo */

#define	DP_APSEL_INVALID 0xF00 /* more than DP_APSEL_MAX and not ADIv6 aligned 4k */

#define	DP_APSEL_MAX (255) /* Strict limit for ADIv5, number of AP buffers for ADIv6 */

#define	DP_BASEPTR0 BANK_REG(0x2, 0x0) /* DPv3: ro */

#define	DP_BASEPTR0_VALID BIT(0)

#define	DP_BASEPTR1 BANK_REG(0x3, 0x0) /* DPv3: ro */

#define	DP_CTRL_STAT BANK_REG(0x0, 0x4) /* DPv0+: rw */

#define	DP_DLCR BANK_REG(0x1, 0x4) /* DPv1+: SWD: rw */

#define	DP_DLPIDR BANK_REG(0x3, 0x4) /* DPv2: ro */

#define	DP_DLPIDR_PROTVSN 1u

#define	DP_DPIDR BANK_REG(0x0, 0x0) /* DPv1+: ro */

#define	DP_DPIDR1 BANK_REG(0x1, 0x0) /* DPv3: ro */

#define	DP_DPIDR1_ASIZE_MASK (0x7F)

#define	DP_DPIDR1_ERRMODE BIT(7)

#define	DP_DPIDR_VERSION_MASK (0xFUL << DP_DPIDR_VERSION_SHIFT)

#define	DP_DPIDR_VERSION_SHIFT 12

#define	DP_EVENTSTAT BANK_REG(0x4, 0x4) /* DPv2: ro */

#define	DP_RDBUFF BANK_REG(0x0, 0xC) /* DPv0+: ro */

#define	DP_RESEND BANK_REG(0x0, 0x8) /* DPv1+: SWD: ro */

#define	DP_SELECT BANK_REG(0x0, 0x8) /* DPv0+: JTAG: rw; SWD: wo */

#define	DP_SELECT1 BANK_REG(0x5, 0x4) /* DPv3: ro */

#define	DP_SELECT_DPBANK 0x0000000F

#define	DP_TARGETID BANK_REG(0x2, 0x4) /* DPv2: ro */

#define	DP_TARGETSEL BANK_REG(0x0, 0xC) /* DPv2: SWD: wo */

#define	DP_TARGETSEL_DPID_MASK 0x0FFFFFFFU

#define	DP_TARGETSEL_INSTANCEID_MASK 0xF0000000U

#define	DP_TARGETSEL_INSTANCEID_SHIFT 28

#define	DP_TARGETSEL_INVALID 0xFFFFFFFFU

#define	DPAP_READ 1

#define	DPAP_WRITE 0

#define	MEM_AP_REG_BASE(dap) (is_adiv6(dap) ? ADIV6_MEM_AP_REG_BASE : ADIV5_MEM_AP_REG_BASE)

#define	MEM_AP_REG_BASE64(dap) (is_adiv6(dap) ? ADIV6_MEM_AP_REG_BASE64 : ADIV5_MEM_AP_REG_BASE64)

#define	MEM_AP_REG_BD0(dap) (is_adiv6(dap) ? ADIV6_MEM_AP_REG_BD0 : ADIV5_MEM_AP_REG_BD0)

#define	MEM_AP_REG_BD1(dap) (is_adiv6(dap) ? ADIV6_MEM_AP_REG_BD1 : ADIV5_MEM_AP_REG_BD1)

#define	MEM_AP_REG_BD2(dap) (is_adiv6(dap) ? ADIV6_MEM_AP_REG_BD2 : ADIV5_MEM_AP_REG_BD2)

#define	MEM_AP_REG_BD3(dap) (is_adiv6(dap) ? ADIV6_MEM_AP_REG_BD3 : ADIV5_MEM_AP_REG_BD3)

#define	MEM_AP_REG_CFG(dap) (is_adiv6(dap) ? ADIV6_MEM_AP_REG_CFG : ADIV5_MEM_AP_REG_CFG)

#define	MEM_AP_REG_CFG_BE BIT(0)

#define	MEM_AP_REG_CFG_INVALID 0xFFFFFFF8

#define	MEM_AP_REG_CFG_LA BIT(1)

#define	MEM_AP_REG_CFG_LD BIT(2)

#define	MEM_AP_REG_CSW(dap) (is_adiv6(dap) ? ADIV6_MEM_AP_REG_CSW : ADIV5_MEM_AP_REG_CSW)

#define	MEM_AP_REG_DRW(dap) (is_adiv6(dap) ? ADIV6_MEM_AP_REG_DRW : ADIV5_MEM_AP_REG_DRW)

#define	MEM_AP_REG_MBT(dap) (is_adiv6(dap) ? ADIV6_MEM_AP_REG_MBT : ADIV5_MEM_AP_REG_MBT)

#define	MEM_AP_REG_TAR(dap) (is_adiv6(dap) ? ADIV6_MEM_AP_REG_TAR : ADIV5_MEM_AP_REG_TAR)

#define	MEM_AP_REG_TAR64(dap) (is_adiv6(dap) ? ADIV6_MEM_AP_REG_TAR64 : ADIV5_MEM_AP_REG_TAR64)

#define	ORUNERRCLR (1UL << 4) /* SWD-only */

#define	READOK (1UL << 6) /* SWD-only */

#define	SELECT_AP_MASK (~(uint64_t)DP_SELECT_DPBANK)

#define	SSTICKYCMP (1UL << 4)

#define	SSTICKYERR (1UL << 5)

#define	SSTICKYORUN (1UL << 1)

#define	STKCMPCLR (1UL << 1) /* SWD-only */

#define	STKERRCLR (1UL << 2) /* SWD-only */

#define	SWD_ACK_FAULT 0x4

#define	SWD_ACK_OK 0x1

#define	SWD_ACK_WAIT 0x2

#define	WDATAERR (1UL << 7) /* SWD-only */

#define	WDERRCLR (1UL << 3) /* SWD-only */

Enumerations
enum	adiv5_configure_dap_optional { ADI_CONFIGURE_DAP_COMPULSORY = false , ADI_CONFIGURE_DAP_OPTIONAL = true }

enum	ap_type { AP_TYPE_JTAG_AP = AP_REG_IDR_VALUE(ARM_ID, AP_REG_IDR_CLASS_NONE, 0) , AP_TYPE_COM_AP = AP_REG_IDR_VALUE(ARM_ID, AP_REG_IDR_CLASS_COM, 0) , AP_TYPE_AHB3_AP = AP_REG_IDR_VALUE(ARM_ID, AP_REG_IDR_CLASS_MEM_AP, 1) , AP_TYPE_APB_AP = AP_REG_IDR_VALUE(ARM_ID, AP_REG_IDR_CLASS_MEM_AP, 2) , AP_TYPE_AXI_AP = AP_REG_IDR_VALUE(ARM_ID, AP_REG_IDR_CLASS_MEM_AP, 4) , AP_TYPE_AHB5_AP = AP_REG_IDR_VALUE(ARM_ID, AP_REG_IDR_CLASS_MEM_AP, 5) , AP_TYPE_APB4_AP = AP_REG_IDR_VALUE(ARM_ID, AP_REG_IDR_CLASS_MEM_AP, 6) , AP_TYPE_AXI5_AP = AP_REG_IDR_VALUE(ARM_ID, AP_REG_IDR_CLASS_MEM_AP, 7) , AP_TYPE_AHB5H_AP = AP_REG_IDR_VALUE(ARM_ID, AP_REG_IDR_CLASS_MEM_AP, 8) }

enum	swd_special_seq { LINE_RESET , JTAG_TO_SWD , JTAG_TO_DORMANT , SWD_TO_JTAG , SWD_TO_DORMANT , DORMANT_TO_SWD , DORMANT_TO_JTAG }

Functions
const char *	adiv5_dap_name (struct adiv5_dap *self)

const struct swd_driver *	adiv5_dap_swd_driver (struct adiv5_dap *self)

struct adiv5_dap *	adiv5_get_dap (struct arm_dap_object *obj)

int	adiv5_jim_configure (struct target target, struct jim_getopt_info goi)

int	adiv5_jim_configure_ext (struct target target, struct jim_getopt_info goi, struct adiv5_private_config *pc, enum adiv5_configure_dap_optional optional)

int	adiv5_jim_mem_ap_spot_configure (struct adiv5_mem_ap_spot cfg, struct jim_getopt_info goi)

int	adiv5_mem_ap_spot_init (struct adiv5_mem_ap_spot *p)

int	adiv5_verify_config (struct adiv5_private_config *pc)

int	adiv6_dap_read_baseptr (struct command_invocation cmd, struct adiv5_dap dap, target_addr_t *baseptr)

int	dap_cleanup_all (void)

int	dap_dp_init (struct adiv5_dap *dap)
	Initialize a DAP. More...

int	dap_dp_init_or_reconnect (struct adiv5_dap *dap)
	Initialize a DAP or do reconnect if DAP is not accessible. More...

static int	dap_dp_poll_register (struct adiv5_dap *dap, unsigned reg, uint32_t mask, uint32_t value, int timeout)

static int	dap_dp_read_atomic (struct adiv5_dap dap, unsigned reg, uint32_t value)

int	dap_find_get_ap (struct adiv5_dap dap, enum ap_type type_to_find, struct adiv5_ap *ap_out)

struct adiv5_ap *	dap_get_ap (struct adiv5_dap *dap, uint64_t ap_num)

struct adiv5_ap *	dap_get_config_ap (struct adiv5_dap *dap, uint64_t ap_num)

int	dap_info_command (struct command_invocation cmd, struct adiv5_ap ap)

struct adiv5_dap *	dap_instance_by_jim_obj (Jim_Interp interp, Jim_Obj o)

void	dap_invalidate_cache (struct adiv5_dap *dap)
	Invalidate cached DP select and cached TAR and CSW of all APs. More...

static bool	dap_is_multidrop (struct adiv5_dap *dap)
	Check if SWD multidrop configuration is valid. More...

int	dap_lookup_cs_component (struct adiv5_ap ap, uint8_t type, target_addr_t addr, int32_t idx)

int	dap_put_ap (struct adiv5_ap *ap)

static int	dap_queue_ap_abort (struct adiv5_dap dap, uint8_t ack)
	Queue an AP abort operation. More...

static int	dap_queue_ap_read (struct adiv5_ap ap, unsigned reg, uint32_t data)
	Queue an AP register read. More...

static int	dap_queue_ap_write (struct adiv5_ap *ap, unsigned reg, uint32_t data)
	Queue an AP register write. More...

static int	dap_queue_dp_read (struct adiv5_dap dap, unsigned reg, uint32_t data)
	Queue a DP register read. More...

static int	dap_queue_dp_write (struct adiv5_dap *dap, unsigned reg, uint32_t data)
	Queue a DP register write. More...

int	dap_register_commands (struct command_context *cmd_ctx)

static int	dap_run (struct adiv5_dap *dap)
	Perform all queued DAP operations, and clear any errors posted in the CTRL_STAT register when they are done. More...

static int	dap_send_sequence (struct adiv5_dap *dap, enum swd_special_seq seq)
	Send an adi-v5 sequence to the DAP. More...

static int	dap_sync (struct adiv5_dap *dap)

int	dap_to_jtag (struct adiv5_dap *dap)
	Put the debug link into JTAG mode, if the target supports it. More...

int	dap_to_swd (struct adiv5_dap *dap)
	Put the debug link into SWD mode, if the target supports it. More...

static bool	is_64bit_ap (struct adiv5_ap *ap)

static bool	is_adiv6 (const struct adiv5_dap *dap)
	Check if DAP is ADIv6. More...

bool	is_ap_num_valid (struct adiv5_dap *dap, uint64_t ap_num)

int	mem_ap_init (struct adiv5_ap *ap)
	Initialize a DAP. More...

int	mem_ap_read_atomic_u32 (struct adiv5_ap ap, target_addr_t address, uint32_t value)
	Synchronous read of a word from memory or a system register. More...

int	mem_ap_read_buf (struct adiv5_ap ap, uint8_t buffer, uint32_t size, uint32_t count, target_addr_t address)

int	mem_ap_read_buf_noincr (struct adiv5_ap ap, uint8_t buffer, uint32_t size, uint32_t count, target_addr_t address)

int	mem_ap_read_u32 (struct adiv5_ap ap, target_addr_t address, uint32_t value)
	Asynchronous (queued) read of a word from memory or a system register. More...

int	mem_ap_write_atomic_u32 (struct adiv5_ap *ap, target_addr_t address, uint32_t value)
	Synchronous write of a word to memory or a system register. More...

int	mem_ap_write_buf (struct adiv5_ap ap, const uint8_t buffer, uint32_t size, uint32_t count, target_addr_t address)

int	mem_ap_write_buf_noincr (struct adiv5_ap ap, const uint8_t buffer, uint32_t size, uint32_t count, target_addr_t address)

int	mem_ap_write_u32 (struct adiv5_ap *ap, target_addr_t address, uint32_t value)
	Asynchronous (queued) write of a word to memory or a system register. More...

Variables
const struct command_registration	dap_instance_commands []

const struct dap_ops	jtag_dp_ops

const struct dap_ops	swd_dap_ops

Detailed Description

This defines formats and data structures used to talk to ADIv5 entities.

Those include a DAP, different types of Debug Port (DP), and memory mapped resources accessed through a MEM-AP.

Definition in file arm_adi_v5.h.

Macro Definition Documentation

◆ ADIV5_AP_REG_IDR

#define ADIV5_AP_REG_IDR (0xFC) /* RO: Identification Register */

Definition at line 159 of file arm_adi_v5.h.

◆ ADIV5_DP_SELECT_APBANK

#define ADIV5_DP_SELECT_APBANK 0x000000F0

Definition at line 101 of file arm_adi_v5.h.

◆ ADIV5_DP_SELECT_APSEL

#define ADIV5_DP_SELECT_APSEL 0xFF000000

Definition at line 100 of file arm_adi_v5.h.

◆ ADIV5_MEM_AP_REG_BASE

#define ADIV5_MEM_AP_REG_BASE (0xF8) /* RO: Debug Base Address register */

Definition at line 130 of file arm_adi_v5.h.

◆ ADIV5_MEM_AP_REG_BASE64

#define ADIV5_MEM_AP_REG_BASE64 (0xF0) /* RO: Debug Base Address (LA) register */

Definition at line 128 of file arm_adi_v5.h.

◆ ADIV5_MEM_AP_REG_BD0

#define ADIV5_MEM_AP_REG_BD0 (0x10) /* RW: Banked Data register 0-3 */

Definition at line 123 of file arm_adi_v5.h.

◆ ADIV5_MEM_AP_REG_BD1

#define ADIV5_MEM_AP_REG_BD1 (0x14)

Definition at line 124 of file arm_adi_v5.h.

◆ ADIV5_MEM_AP_REG_BD2

#define ADIV5_MEM_AP_REG_BD2 (0x18)

Definition at line 125 of file arm_adi_v5.h.

◆ ADIV5_MEM_AP_REG_BD3

#define ADIV5_MEM_AP_REG_BD3 (0x1C)

Definition at line 126 of file arm_adi_v5.h.

◆ ADIV5_MEM_AP_REG_CFG

#define ADIV5_MEM_AP_REG_CFG (0xF4) /* RO: Configuration register */

Definition at line 129 of file arm_adi_v5.h.

◆ ADIV5_MEM_AP_REG_CSW

#define ADIV5_MEM_AP_REG_CSW (0x00)

Definition at line 119 of file arm_adi_v5.h.

◆ ADIV5_MEM_AP_REG_DRW

#define ADIV5_MEM_AP_REG_DRW (0x0C) /* RW: Data Read/Write register */

Definition at line 122 of file arm_adi_v5.h.

◆ ADIV5_MEM_AP_REG_MBT

#define ADIV5_MEM_AP_REG_MBT (0x20) /* --: Memory Barrier Transfer register */

Definition at line 127 of file arm_adi_v5.h.

◆ ADIV5_MEM_AP_REG_TAR

#define ADIV5_MEM_AP_REG_TAR (0x04)

Definition at line 120 of file arm_adi_v5.h.

◆ ADIV5_MEM_AP_REG_TAR64

#define ADIV5_MEM_AP_REG_TAR64 (0x08) /* RW: Large Physical Address Extension */

Definition at line 121 of file arm_adi_v5.h.

◆ ADIV6_AP_REG_IDR

#define ADIV6_AP_REG_IDR (0xD00 + ADIV5_AP_REG_IDR)

Definition at line 160 of file arm_adi_v5.h.

◆ ADIV6_MEM_AP_REG_BASE

#define ADIV6_MEM_AP_REG_BASE (0xD00 + ADIV5_MEM_AP_REG_BASE)

Definition at line 143 of file arm_adi_v5.h.

◆ ADIV6_MEM_AP_REG_BASE64

#define ADIV6_MEM_AP_REG_BASE64 (0xD00 + ADIV5_MEM_AP_REG_BASE64)

Definition at line 141 of file arm_adi_v5.h.

◆ ADIV6_MEM_AP_REG_BD0

#define ADIV6_MEM_AP_REG_BD0 (0xD00 + ADIV5_MEM_AP_REG_BD0)

Definition at line 136 of file arm_adi_v5.h.

◆ ADIV6_MEM_AP_REG_BD1

#define ADIV6_MEM_AP_REG_BD1 (0xD00 + ADIV5_MEM_AP_REG_BD1)

Definition at line 137 of file arm_adi_v5.h.

◆ ADIV6_MEM_AP_REG_BD2

#define ADIV6_MEM_AP_REG_BD2 (0xD00 + ADIV5_MEM_AP_REG_BD2)

Definition at line 138 of file arm_adi_v5.h.

◆ ADIV6_MEM_AP_REG_BD3

#define ADIV6_MEM_AP_REG_BD3 (0xD00 + ADIV5_MEM_AP_REG_BD3)

Definition at line 139 of file arm_adi_v5.h.

◆ ADIV6_MEM_AP_REG_CFG

#define ADIV6_MEM_AP_REG_CFG (0xD00 + ADIV5_MEM_AP_REG_CFG)

Definition at line 142 of file arm_adi_v5.h.

◆ ADIV6_MEM_AP_REG_CSW

#define ADIV6_MEM_AP_REG_CSW (0xD00 + ADIV5_MEM_AP_REG_CSW)

Definition at line 132 of file arm_adi_v5.h.

◆ ADIV6_MEM_AP_REG_DRW

#define ADIV6_MEM_AP_REG_DRW (0xD00 + ADIV5_MEM_AP_REG_DRW)

Definition at line 135 of file arm_adi_v5.h.

◆ ADIV6_MEM_AP_REG_MBT

#define ADIV6_MEM_AP_REG_MBT (0xD00 + ADIV5_MEM_AP_REG_MBT)

Definition at line 140 of file arm_adi_v5.h.

◆ ADIV6_MEM_AP_REG_TAR

#define ADIV6_MEM_AP_REG_TAR (0xD00 + ADIV5_MEM_AP_REG_TAR)

Definition at line 133 of file arm_adi_v5.h.

◆ ADIV6_MEM_AP_REG_TAR64

#define ADIV6_MEM_AP_REG_TAR64 (0xD00 + ADIV5_MEM_AP_REG_TAR64)

Definition at line 134 of file arm_adi_v5.h.

◆ AP_REG_IDR

#define AP_REG_IDR ( dap ) (is_adiv6(dap) ? ADIV6_AP_REG_IDR : ADIV5_AP_REG_IDR)

Definition at line 161 of file arm_adi_v5.h.

◆ AP_REG_IDR_CLASS_COM

#define AP_REG_IDR_CLASS_COM (0x1)

Definition at line 224 of file arm_adi_v5.h.

◆ AP_REG_IDR_CLASS_MASK

#define AP_REG_IDR_CLASS_MASK (0x0001E000)

Definition at line 216 of file arm_adi_v5.h.

◆ AP_REG_IDR_CLASS_MEM_AP

#define AP_REG_IDR_CLASS_MEM_AP (0x8)

Definition at line 225 of file arm_adi_v5.h.

◆ AP_REG_IDR_CLASS_NONE

#define AP_REG_IDR_CLASS_NONE (0x0)

Definition at line 223 of file arm_adi_v5.h.

◆ AP_REG_IDR_CLASS_SHIFT

#define AP_REG_IDR_CLASS_SHIFT (13)

Definition at line 217 of file arm_adi_v5.h.

◆ AP_REG_IDR_DESIGNER_MASK

#define AP_REG_IDR_DESIGNER_MASK (0x0FFE0000)

Definition at line 214 of file arm_adi_v5.h.

◆ AP_REG_IDR_DESIGNER_SHIFT

#define AP_REG_IDR_DESIGNER_SHIFT (17)

Definition at line 215 of file arm_adi_v5.h.

◆ AP_REG_IDR_REVISION_MASK

#define AP_REG_IDR_REVISION_MASK (0xF0000000)

Definition at line 212 of file arm_adi_v5.h.

◆ AP_REG_IDR_REVISION_SHIFT

#define AP_REG_IDR_REVISION_SHIFT (28)

Definition at line 213 of file arm_adi_v5.h.

◆ AP_REG_IDR_TYPE_MASK

#define AP_REG_IDR_TYPE_MASK (0x0000000F)

Definition at line 220 of file arm_adi_v5.h.

◆ AP_REG_IDR_TYPE_SHIFT

#define AP_REG_IDR_TYPE_SHIFT (0)

Definition at line 221 of file arm_adi_v5.h.

◆ AP_REG_IDR_VALUE

#define AP_REG_IDR_VALUE	(	d,
		c,
		t
	)

Value:

    (\
    (((d) << AP_REG_IDR_DESIGNER_SHIFT) & AP_REG_IDR_DESIGNER_MASK) | \
    (((c) << AP_REG_IDR_CLASS_SHIFT) & AP_REG_IDR_CLASS_MASK) | \
    (((t) << AP_REG_IDR_TYPE_SHIFT) & AP_REG_IDR_TYPE_MASK) \
)

Definition at line 227 of file arm_adi_v5.h.

◆ AP_REG_IDR_VARIANT_MASK

#define AP_REG_IDR_VARIANT_MASK (0x000000F0)

Definition at line 218 of file arm_adi_v5.h.

◆ AP_REG_IDR_VARIANT_SHIFT

#define AP_REG_IDR_VARIANT_SHIFT (4)

Definition at line 219 of file arm_adi_v5.h.

◆ AP_TYPE_MASK

#define AP_TYPE_MASK (AP_REG_IDR_DESIGNER_MASK | AP_REG_IDR_CLASS_MASK | AP_REG_IDR_TYPE_MASK)

Definition at line 233 of file arm_adi_v5.h.

◆ ARM_ID

#define ARM_ID 0x23B

Definition at line 28 of file arm_adi_v5.h.

◆ BANK_REG

#define BANK_REG	(	bank,
		reg
	)	(((bank) << 4) \| (reg))

Definition at line 38 of file arm_adi_v5.h.

◆ CDBGPWRUPACK

#define CDBGPWRUPACK (1UL << 29)

Definition at line 94 of file arm_adi_v5.h.

◆ CDBGPWRUPREQ

#define CDBGPWRUPREQ (1UL << 28)

Definition at line 93 of file arm_adi_v5.h.

◆ CDBGRSTACK

#define CDBGRSTACK (1UL << 27)

Definition at line 92 of file arm_adi_v5.h.

◆ CDBGRSTREQ

#define CDBGRSTREQ (1UL << 26)

Definition at line 91 of file arm_adi_v5.h.

◆ CORUNDETECT

#define CORUNDETECT (1UL << 0)

Definition at line 82 of file arm_adi_v5.h.

◆ CSW_128BIT

#define CSW_128BIT 4

Definition at line 169 of file arm_adi_v5.h.

◆ CSW_16BIT

#define CSW_16BIT 1

Definition at line 166 of file arm_adi_v5.h.

◆ CSW_256BIT

#define CSW_256BIT 5

Definition at line 170 of file arm_adi_v5.h.

◆ CSW_32BIT

#define CSW_32BIT 2

Definition at line 167 of file arm_adi_v5.h.

◆ CSW_64BIT

#define CSW_64BIT 3

Definition at line 168 of file arm_adi_v5.h.

◆ CSW_8BIT

#define CSW_8BIT 0

Definition at line 165 of file arm_adi_v5.h.

◆ CSW_ADDRINC_MASK

#define CSW_ADDRINC_MASK (3UL << 4)

Definition at line 171 of file arm_adi_v5.h.

◆ CSW_ADDRINC_OFF

#define CSW_ADDRINC_OFF 0UL

Definition at line 172 of file arm_adi_v5.h.

◆ CSW_ADDRINC_PACKED

#define CSW_ADDRINC_PACKED (2UL << 4)

Definition at line 174 of file arm_adi_v5.h.

◆ CSW_ADDRINC_SINGLE

#define CSW_ADDRINC_SINGLE (1UL << 4)

Definition at line 173 of file arm_adi_v5.h.

◆ CSW_AHB_DEFAULT

#define CSW_AHB_DEFAULT (CSW_AHB_HPROT1 | CSW_AHB_MASTER_DEBUG | CSW_DBGSWENABLE)

Definition at line 193 of file arm_adi_v5.h.

◆ CSW_AHB_HPROT1

#define CSW_AHB_HPROT1 (1UL << 25)

Definition at line 186 of file arm_adi_v5.h.

◆ CSW_AHB_MASTER_DEBUG

#define CSW_AHB_MASTER_DEBUG (1UL << 29)

Definition at line 188 of file arm_adi_v5.h.

◆ CSW_AHB_SPROT

#define CSW_AHB_SPROT (1UL << 30)

Definition at line 191 of file arm_adi_v5.h.

◆ CSW_APB_DEFAULT

#define CSW_APB_DEFAULT (CSW_DBGSWENABLE)

Definition at line 203 of file arm_adi_v5.h.

◆ CSW_AXI_ARPROT0_PRIV

#define CSW_AXI_ARPROT0_PRIV (1UL << 28)

Definition at line 196 of file arm_adi_v5.h.

◆ CSW_AXI_ARPROT1_NONSEC

#define CSW_AXI_ARPROT1_NONSEC (1UL << 29)

Definition at line 198 of file arm_adi_v5.h.

◆ CSW_AXI_DEFAULT

#define CSW_AXI_DEFAULT (CSW_AXI_ARPROT0_PRIV | CSW_AXI_ARPROT1_NONSEC | CSW_DBGSWENABLE)

Definition at line 200 of file arm_adi_v5.h.

◆ CSW_DBGSWENABLE

#define CSW_DBGSWENABLE (1UL << 31)

Definition at line 183 of file arm_adi_v5.h.

◆ CSW_DEVICE_EN

#define CSW_DEVICE_EN (1UL << 6)

Definition at line 175 of file arm_adi_v5.h.

◆ CSW_SIZE_MASK

#define CSW_SIZE_MASK 7

Definition at line 164 of file arm_adi_v5.h.

◆ CSW_SPIDEN

#define CSW_SPIDEN (1UL << 23)

Definition at line 182 of file arm_adi_v5.h.

◆ CSW_TRIN_PROG

#define CSW_TRIN_PROG (1UL << 7)

Definition at line 176 of file arm_adi_v5.h.

◆ CSYSPWRUPACK

#define CSYSPWRUPACK (1UL << 31)

Definition at line 96 of file arm_adi_v5.h.

◆ CSYSPWRUPREQ

#define CSYSPWRUPREQ (1UL << 30)

Definition at line 95 of file arm_adi_v5.h.

◆ DAPABORT

#define DAPABORT (1UL << 0)

Definition at line 68 of file arm_adi_v5.h.

◆ DLCR_TO_TRN

#define DLCR_TO_TRN ( dlcr ) ((uint32_t)(1 + ((3 & (dlcr)) >> 8))) /* 1..4 clocks */

Definition at line 61 of file arm_adi_v5.h.

◆ DP_ABORT

#define DP_ABORT BANK_REG(0x0, 0x0) /* DPv1+: SWD: wo */

Definition at line 46 of file arm_adi_v5.h.

◆ DP_APSEL_INVALID

#define DP_APSEL_INVALID 0xF00 /* more than DP_APSEL_MAX and not ADIv6 aligned 4k */

Definition at line 110 of file arm_adi_v5.h.

◆ DP_APSEL_MAX

#define DP_APSEL_MAX (255) /* Strict limit for ADIv5, number of AP buffers for ADIv6 */

Definition at line 109 of file arm_adi_v5.h.

◆ DP_BASEPTR0

#define DP_BASEPTR0 BANK_REG(0x2, 0x0) /* DPv3: ro */

Definition at line 48 of file arm_adi_v5.h.

◆ DP_BASEPTR0_VALID

#define DP_BASEPTR0_VALID BIT(0)

Definition at line 79 of file arm_adi_v5.h.

◆ DP_BASEPTR1

#define DP_BASEPTR1 BANK_REG(0x3, 0x0) /* DPv3: ro */

Definition at line 49 of file arm_adi_v5.h.

◆ DP_CTRL_STAT

#define DP_CTRL_STAT BANK_REG(0x0, 0x4) /* DPv0+: rw */

Definition at line 50 of file arm_adi_v5.h.

◆ DP_DLCR

#define DP_DLCR BANK_REG(0x1, 0x4) /* DPv1+: SWD: rw */

Definition at line 51 of file arm_adi_v5.h.

◆ DP_DLPIDR

#define DP_DLPIDR BANK_REG(0x3, 0x4) /* DPv2: ro */

Definition at line 53 of file arm_adi_v5.h.

◆ DP_DLPIDR_PROTVSN

#define DP_DLPIDR_PROTVSN 1u

Definition at line 98 of file arm_adi_v5.h.

◆ DP_DPIDR

#define DP_DPIDR BANK_REG(0x0, 0x0) /* DPv1+: ro */

Definition at line 45 of file arm_adi_v5.h.

◆ DP_DPIDR1

#define DP_DPIDR1 BANK_REG(0x1, 0x0) /* DPv3: ro */

Definition at line 47 of file arm_adi_v5.h.

◆ DP_DPIDR1_ASIZE_MASK

#define DP_DPIDR1_ASIZE_MASK (0x7F)

Definition at line 75 of file arm_adi_v5.h.

◆ DP_DPIDR1_ERRMODE

#define DP_DPIDR1_ERRMODE BIT(7)

Definition at line 76 of file arm_adi_v5.h.

◆ DP_DPIDR_VERSION_MASK

#define DP_DPIDR_VERSION_MASK (0xFUL << DP_DPIDR_VERSION_SHIFT)

Definition at line 65 of file arm_adi_v5.h.

◆ DP_DPIDR_VERSION_SHIFT

#define DP_DPIDR_VERSION_SHIFT 12

Definition at line 64 of file arm_adi_v5.h.

◆ DP_EVENTSTAT

#define DP_EVENTSTAT BANK_REG(0x4, 0x4) /* DPv2: ro */

Definition at line 54 of file arm_adi_v5.h.

◆ DP_RDBUFF

#define DP_RDBUFF BANK_REG(0x0, 0xC) /* DPv0+: ro */

Definition at line 58 of file arm_adi_v5.h.

◆ DP_RESEND

#define DP_RESEND BANK_REG(0x0, 0x8) /* DPv1+: SWD: ro */

Definition at line 56 of file arm_adi_v5.h.

◆ DP_SELECT

#define DP_SELECT BANK_REG(0x0, 0x8) /* DPv0+: JTAG: rw; SWD: wo */

Definition at line 57 of file arm_adi_v5.h.

◆ DP_SELECT1

#define DP_SELECT1 BANK_REG(0x5, 0x4) /* DPv3: ro */

Definition at line 55 of file arm_adi_v5.h.

◆ DP_SELECT_DPBANK

#define DP_SELECT_DPBANK 0x0000000F

Definition at line 102 of file arm_adi_v5.h.

◆ DP_TARGETID

#define DP_TARGETID BANK_REG(0x2, 0x4) /* DPv2: ro */

Definition at line 52 of file arm_adi_v5.h.

◆ DP_TARGETSEL

#define DP_TARGETSEL BANK_REG(0x0, 0xC) /* DPv2: SWD: wo */

Definition at line 59 of file arm_adi_v5.h.

◆ DP_TARGETSEL_DPID_MASK

#define DP_TARGETSEL_DPID_MASK 0x0FFFFFFFU

Definition at line 113 of file arm_adi_v5.h.

◆ DP_TARGETSEL_INSTANCEID_MASK

#define DP_TARGETSEL_INSTANCEID_MASK 0xF0000000U

Definition at line 114 of file arm_adi_v5.h.

◆ DP_TARGETSEL_INSTANCEID_SHIFT

#define DP_TARGETSEL_INSTANCEID_SHIFT 28

Definition at line 115 of file arm_adi_v5.h.

◆ DP_TARGETSEL_INVALID

#define DP_TARGETSEL_INVALID 0xFFFFFFFFU

Definition at line 112 of file arm_adi_v5.h.

◆ DPAP_READ

#define DPAP_READ 1

Definition at line 36 of file arm_adi_v5.h.

◆ DPAP_WRITE

#define DPAP_WRITE 0

Definition at line 35 of file arm_adi_v5.h.

◆ MEM_AP_REG_BASE

#define MEM_AP_REG_BASE ( dap ) (is_adiv6(dap) ? ADIV6_MEM_AP_REG_BASE : ADIV5_MEM_AP_REG_BASE)

Definition at line 156 of file arm_adi_v5.h.

◆ MEM_AP_REG_BASE64

#define MEM_AP_REG_BASE64 ( dap ) (is_adiv6(dap) ? ADIV6_MEM_AP_REG_BASE64 : ADIV5_MEM_AP_REG_BASE64)

Definition at line 154 of file arm_adi_v5.h.

◆ MEM_AP_REG_BD0

#define MEM_AP_REG_BD0 ( dap ) (is_adiv6(dap) ? ADIV6_MEM_AP_REG_BD0 : ADIV5_MEM_AP_REG_BD0)

Definition at line 149 of file arm_adi_v5.h.

◆ MEM_AP_REG_BD1

#define MEM_AP_REG_BD1 ( dap ) (is_adiv6(dap) ? ADIV6_MEM_AP_REG_BD1 : ADIV5_MEM_AP_REG_BD1)

Definition at line 150 of file arm_adi_v5.h.

◆ MEM_AP_REG_BD2

#define MEM_AP_REG_BD2 ( dap ) (is_adiv6(dap) ? ADIV6_MEM_AP_REG_BD2 : ADIV5_MEM_AP_REG_BD2)

Definition at line 151 of file arm_adi_v5.h.

◆ MEM_AP_REG_BD3

#define MEM_AP_REG_BD3 ( dap ) (is_adiv6(dap) ? ADIV6_MEM_AP_REG_BD3 : ADIV5_MEM_AP_REG_BD3)

Definition at line 152 of file arm_adi_v5.h.

◆ MEM_AP_REG_CFG

#define MEM_AP_REG_CFG ( dap ) (is_adiv6(dap) ? ADIV6_MEM_AP_REG_CFG : ADIV5_MEM_AP_REG_CFG)

Definition at line 155 of file arm_adi_v5.h.

◆ MEM_AP_REG_CFG_BE

#define MEM_AP_REG_CFG_BE BIT(0)

Definition at line 206 of file arm_adi_v5.h.

◆ MEM_AP_REG_CFG_INVALID

#define MEM_AP_REG_CFG_INVALID 0xFFFFFFF8

Definition at line 209 of file arm_adi_v5.h.

◆ MEM_AP_REG_CFG_LA

#define MEM_AP_REG_CFG_LA BIT(1)

Definition at line 207 of file arm_adi_v5.h.

◆ MEM_AP_REG_CFG_LD

#define MEM_AP_REG_CFG_LD BIT(2)

Definition at line 208 of file arm_adi_v5.h.

◆ MEM_AP_REG_CSW

#define MEM_AP_REG_CSW ( dap ) (is_adiv6(dap) ? ADIV6_MEM_AP_REG_CSW : ADIV5_MEM_AP_REG_CSW)

Definition at line 145 of file arm_adi_v5.h.

◆ MEM_AP_REG_DRW

#define MEM_AP_REG_DRW ( dap ) (is_adiv6(dap) ? ADIV6_MEM_AP_REG_DRW : ADIV5_MEM_AP_REG_DRW)

Definition at line 148 of file arm_adi_v5.h.

◆ MEM_AP_REG_MBT

#define MEM_AP_REG_MBT ( dap ) (is_adiv6(dap) ? ADIV6_MEM_AP_REG_MBT : ADIV5_MEM_AP_REG_MBT)

Definition at line 153 of file arm_adi_v5.h.

◆ MEM_AP_REG_TAR

#define MEM_AP_REG_TAR ( dap ) (is_adiv6(dap) ? ADIV6_MEM_AP_REG_TAR : ADIV5_MEM_AP_REG_TAR)

Definition at line 146 of file arm_adi_v5.h.

◆ MEM_AP_REG_TAR64

#define MEM_AP_REG_TAR64 ( dap ) (is_adiv6(dap) ? ADIV6_MEM_AP_REG_TAR64 : ADIV5_MEM_AP_REG_TAR64)

Definition at line 147 of file arm_adi_v5.h.

◆ ORUNERRCLR

#define ORUNERRCLR (1UL << 4) /* SWD-only */

Definition at line 72 of file arm_adi_v5.h.

◆ READOK

#define READOK (1UL << 6) /* SWD-only */

Definition at line 87 of file arm_adi_v5.h.

◆ SELECT_AP_MASK

#define SELECT_AP_MASK (~(uint64_t)DP_SELECT_DPBANK)

Definition at line 107 of file arm_adi_v5.h.

◆ SSTICKYCMP

#define SSTICKYCMP (1UL << 4)

Definition at line 85 of file arm_adi_v5.h.

◆ SSTICKYERR

#define SSTICKYERR (1UL << 5)

Definition at line 86 of file arm_adi_v5.h.

◆ SSTICKYORUN

#define SSTICKYORUN (1UL << 1)

Definition at line 83 of file arm_adi_v5.h.

◆ STKCMPCLR

#define STKCMPCLR (1UL << 1) /* SWD-only */

Definition at line 69 of file arm_adi_v5.h.

◆ STKERRCLR

#define STKERRCLR (1UL << 2) /* SWD-only */

Definition at line 70 of file arm_adi_v5.h.

◆ SWD_ACK_FAULT

#define SWD_ACK_FAULT 0x4

Definition at line 33 of file arm_adi_v5.h.

◆ SWD_ACK_OK

#define SWD_ACK_OK 0x1

Definition at line 31 of file arm_adi_v5.h.

◆ SWD_ACK_WAIT

#define SWD_ACK_WAIT 0x2

Definition at line 32 of file arm_adi_v5.h.

◆ WDATAERR

#define WDATAERR (1UL << 7) /* SWD-only */

Definition at line 88 of file arm_adi_v5.h.

◆ WDERRCLR

#define WDERRCLR (1UL << 3) /* SWD-only */

Definition at line 71 of file arm_adi_v5.h.

Enumeration Type Documentation

◆ adiv5_configure_dap_optional

enum adiv5_configure_dap_optional

Enumerator
ADI_CONFIGURE_DAP_COMPULSORY
ADI_CONFIGURE_DAP_OPTIONAL

Definition at line 792 of file arm_adi_v5.h.

◆ ap_type

enum ap_type

Enumerator
AP_TYPE_JTAG_AP
AP_TYPE_COM_AP
AP_TYPE_AHB3_AP
AP_TYPE_APB_AP
AP_TYPE_AXI_AP
AP_TYPE_AHB5_AP
AP_TYPE_APB4_AP
AP_TYPE_AXI5_AP
AP_TYPE_AHB5H_AP

Definition at line 487 of file arm_adi_v5.h.

◆ swd_special_seq

enum swd_special_seq

Enumerator
LINE_RESET
JTAG_TO_SWD
JTAG_TO_DORMANT
SWD_TO_JTAG
SWD_TO_DORMANT
DORMANT_TO_SWD
DORMANT_TO_JTAG

Definition at line 236 of file arm_adi_v5.h.

Function Documentation

◆ adiv5_dap_name()

const char* adiv5_dap_name ( struct adiv5_dap * self )

Definition at line 54 of file arm_dap.c.

References container_of, arm_dap_object::dap, and arm_dap_object::name.

Referenced by adiv5_jim_spot_configure(), COMMAND_HANDLER(), dap_check_config(), dap_dp_init(), dap_dp_init_or_reconnect(), swd_connect_multidrop(), and swd_multidrop_select().

◆ adiv5_dap_swd_driver()

const struct swd_driver* adiv5_dap_swd_driver ( struct adiv5_dap * self )

Definition at line 60 of file arm_dap.c.

References container_of, arm_dap_object::dap, and arm_dap_object::swd.

Referenced by swd_clear_sticky_errors(), swd_finish_read(), swd_queue_ap_abort(), swd_queue_ap_read(), swd_queue_ap_write(), swd_queue_dp_read_inner(), swd_queue_dp_write(), swd_queue_dp_write_inner(), swd_run_inner(), and swd_send_sequence().

◆ adiv5_get_dap()

struct adiv5_dap* adiv5_get_dap ( struct arm_dap_object * obj )

Definition at line 66 of file arm_dap.c.

References arm_dap_object::dap.

Referenced by COMMAND_HANDLER().

◆ adiv5_jim_configure()

int adiv5_jim_configure	(	struct target *	target,
		struct jim_getopt_info *	goi
	)

Definition at line 2467 of file arm_adi_v5.c.

References ADI_CONFIGURE_DAP_COMPULSORY, adiv5_jim_configure_ext(), and NULL.

◆ adiv5_jim_configure_ext()

int adiv5_jim_configure_ext	(	struct target *	target,
		struct jim_getopt_info *	goi,
		struct adiv5_private_config *	pc,
		enum adiv5_configure_dap_optional	optional
	)

Definition at line 2427 of file arm_adi_v5.c.

References ADI_CONFIGURE_DAP_COMPULSORY, adiv5_jim_spot_configure(), adiv5_private_config::ap_num, adiv5_private_config::dap, target::dap_configured, DP_APSEL_INVALID, target::has_dap, jim_getopt_info::interp, LOG_ERROR, NULL, target::private_config, adiv5_dap::tap, target::tap, and target::tap_configured.

Referenced by aarch64_jim_configure(), adiv5_jim_configure(), and xtensa_chip_jim_configure().

◆ adiv5_jim_mem_ap_spot_configure()

int adiv5_jim_mem_ap_spot_configure	(	struct adiv5_mem_ap_spot *	cfg,
		struct jim_getopt_info *	goi
	)

Definition at line 2483 of file arm_adi_v5.c.

References adiv5_jim_spot_configure(), adiv5_mem_ap_spot::ap_num, adiv5_mem_ap_spot::base, and adiv5_mem_ap_spot::dap.

Referenced by arm_tpiu_swo_configure(), and cti_configure().

◆ adiv5_mem_ap_spot_init()

int adiv5_mem_ap_spot_init ( struct adiv5_mem_ap_spot * p )

Definition at line 2489 of file arm_adi_v5.c.

References adiv5_mem_ap_spot::ap_num, adiv5_mem_ap_spot::base, adiv5_mem_ap_spot::dap, DP_APSEL_INVALID, ERROR_OK, and NULL.

Referenced by cti_create(), and jim_arm_tpiu_swo_create().

◆ adiv5_verify_config()

int adiv5_verify_config ( struct adiv5_private_config * pc )

Definition at line 2472 of file arm_adi_v5.c.

References adiv5_private_config::dap, ERROR_FAIL, and ERROR_OK.

Referenced by aarch64_target_create(), armv8r_target_create(), cortex_m_target_create(), cortex_r4_target_create(), and xtensa_chip_target_create().

◆ adiv6_dap_read_baseptr()

int adiv6_dap_read_baseptr	(	struct command_invocation *	cmd,
		struct adiv5_dap *	dap,
		target_addr_t *	baseptr
	)

Definition at line 1265 of file arm_adi_v5.c.

References adiv5_dap::asize, cmd, command_print(), dap_dp_read_atomic(), dap_queue_dp_read(), DP_BASEPTR0, DP_BASEPTR0_VALID, DP_BASEPTR1, ERROR_FAIL, and ERROR_OK.

Referenced by COMMAND_HANDLER().

◆ dap_cleanup_all()

int dap_cleanup_all ( void )

Definition at line 160 of file arm_dap.c.

References adiv5_dap::ap, arm_dap_object::dap, DP_APSEL_MAX, ERROR_OK, lh(), list_for_each_entry_safe, LOG_ERROR, arm_dap_object::name, adiv5_dap::ops, dap_ops::quit, and adiv5_ap::refcount.

Referenced by openocd_main().

◆ dap_dp_init()

int dap_dp_init ( struct adiv5_dap * dap )

Initialize a DAP.

This sets up the power domains, prepares the DP for further use and activates overrun checking.

Parameters

dap	The DAP being initialized.

Definition at line 779 of file arm_adi_v5.c.

References adiv5_dap_name(), CDBGPWRUPACK, CDBGPWRUPREQ, CORUNDETECT, CSYSPWRUPACK, CSYSPWRUPREQ, dap_dp_poll_register(), dap_invalidate_cache(), DAP_POWER_DOMAIN_TIMEOUT, dap_queue_dp_read(), dap_queue_dp_write(), dap_run(), adiv5_dap::do_reconnect, DP_CTRL_STAT, adiv5_dap::dp_ctrl_stat, ERROR_OK, adiv5_dap::ignore_syspwrupack, LOG_DEBUG, NULL, and SSTICKYERR.

Referenced by dap_dp_init_or_reconnect(), handle_reset_halt(), jtag_connect(), stlink_dap_op_connect(), swd_connect(), and vdebug_dap_connect().

◆ dap_dp_init_or_reconnect()

int dap_dp_init_or_reconnect ( struct adiv5_dap * dap )

Initialize a DAP or do reconnect if DAP is not accessible.

Parameters

dap	The DAP being initialized.

Definition at line 856 of file arm_adi_v5.c.

References adiv5_dap_name(), CDBGPWRUPREQ, dap_ops::connect, CSYSPWRUPREQ, dap_dp_init(), dap_dp_read_atomic(), adiv5_dap::do_reconnect, DP_CTRL_STAT, adiv5_dap::dp_ctrl_stat, LOG_DEBUG, NULL, and adiv5_dap::ops.

Referenced by cortex_m_assert_reset(), and cortex_m_deassert_reset().

◆ dap_dp_poll_register()

static int dap_dp_poll_register	(	struct adiv5_dap *	dap,
		unsigned	reg,
		uint32_t	mask,
		uint32_t	value,
		int	timeout
	)

inlinestatic

Definition at line 674 of file arm_adi_v5.h.

References alive_sleep(), dap_dp_read_atomic(), ERROR_OK, ERROR_WAIT, LOG_DEBUG, and mask.

Referenced by dap_dp_init().

◆ dap_dp_read_atomic()

static int dap_dp_read_atomic	(	struct adiv5_dap *	dap,
		unsigned	reg,
		uint32_t *	value
	)

inlinestatic

Definition at line 662 of file arm_adi_v5.h.

References dap_queue_dp_read(), dap_run(), and ERROR_OK.

Referenced by adiv6_dap_read_baseptr(), dap_dp_init_or_reconnect(), and dap_dp_poll_register().

◆ dap_find_get_ap()

int dap_find_get_ap	(	struct adiv5_dap *	dap,
		enum ap_type	type_to_find,
		struct adiv5_ap **	ap_out
	)

Definition at line 1106 of file arm_adi_v5.c.

References adiv5_ap::ap_num, AP_REG_IDR, AP_TYPE_MASK, ap_type_to_description(), adiv5_ap::dap, dap_get_ap(), dap_put_ap(), dap_queue_ap_read(), dap_run(), DP_APSEL_MAX, ERROR_FAIL, ERROR_OK, is_adiv6(), and LOG_DEBUG.

Referenced by aarch64_examine_first(), cortex_a_examine_first(), cortex_m_find_mem_ap(), and xtensa_dm_examine().

◆ dap_get_ap()

struct adiv5_ap* dap_get_ap	(	struct adiv5_dap *	dap,
		uint64_t	ap_num
	)

Definition at line 1188 of file arm_adi_v5.c.

References _dap_get_ap(), adiv5_ap::ap_num, adiv5_ap::dap, LOG_DEBUG, and adiv5_ap::refcount.

Referenced by aarch64_examine_first(), ap_read_register(), ap_write_register(), COMMAND_HANDLER(), cortex_a_examine_first(), cortex_m_examine(), cti_create(), dap_find_get_ap(), kinetis_ke_mdm_read_register(), kinetis_ke_mdm_write_register(), kinetis_mdm_read_register(), kinetis_mdm_write_register(), mem_ap_examine(), rtp_rom_loop(), and xtensa_dm_examine().

◆ dap_get_config_ap()

struct adiv5_ap* dap_get_config_ap	(	struct adiv5_dap *	dap,
		uint64_t	ap_num
	)

Definition at line 1197 of file arm_adi_v5.c.

References _dap_get_ap(), adiv5_ap::ap_num, adiv5_ap::config_ap_never_release, adiv5_ap::dap, LOG_DEBUG, and adiv5_ap::refcount.

Referenced by COMMAND_HANDLER().

◆ dap_info_command()

int dap_info_command	(	struct command_invocation *	cmd,
		struct adiv5_ap *	ap
	)

Definition at line 2221 of file arm_adi_v5.c.

References rtp_ops::ap_header, cmd, dap_info_ap_header(), dap_info_cs_component(), dap_info_mem_ap_header(), dap_info_rom_table_entry(), and rtp_ap().

Referenced by COMMAND_HANDLER().

◆ dap_instance_by_jim_obj()

struct adiv5_dap* dap_instance_by_jim_obj	(	Jim_Interp *	interp,
		Jim_Obj *	o
	)

Definition at line 70 of file arm_dap.c.

References arm_dap_object::dap, lh(), list_for_each_entry, arm_dap_object::name, name, and NULL.

Referenced by adiv5_jim_spot_configure().

◆ dap_invalidate_cache()

void dap_invalidate_cache ( struct adiv5_dap * dap )

Invalidate cached DP select and cached TAR and CSW of all APs.

Definition at line 756 of file arm_adi_v5.c.

References adiv5_dap::ap, adiv5_ap::csw_value, DP_APSEL_MAX, adiv5_dap::last_read, NULL, adiv5_dap::select, adiv5_dap::select1_valid, adiv5_dap::select_dpbanksel_valid, adiv5_dap::select_valid, and adiv5_ap::tar_valid.

Referenced by dap_dp_init(), stlink_dap_op_connect(), swd_connect_multidrop(), and swd_connect_single().

◆ dap_is_multidrop()

static bool dap_is_multidrop ( struct adiv5_dap * dap )

inlinestatic

Check if SWD multidrop configuration is valid.

Definition at line 756 of file arm_adi_v5.h.

References adiv5_ap::dap, adiv5_dap::multidrop_dp_id_valid, and adiv5_dap::multidrop_instance_id_valid.

Referenced by dap_check_config(), swd_connect(), swd_multidrop_select(), and swd_multidrop_select_inner().

◆ dap_lookup_cs_component()

int dap_lookup_cs_component	(	struct adiv5_ap *	ap,
		uint8_t	type,
		target_addr_t *	addr,
		int32_t	idx
	)

Definition at line 2275 of file arm_adi_v5.c.

References addr, rtp_ops::ap_header, dap_lookup_data::ap_num, adiv5_ap::ap_num, dap_lookup_data::component_base, CORESIGHT_COMPONENT_FOUND, dap_lookup_cs_component_cs_component(), ERROR_OK, ERROR_TARGET_RESOURCE_NOT_AVAILABLE, LOG_DEBUG, NULL, rtp_ap(), type, and dap_lookup_data::type.

Referenced by aarch64_examine_first(), and cortex_a_examine_first().

◆ dap_put_ap()

int dap_put_ap ( struct adiv5_ap * ap )

◆ dap_queue_ap_abort()

static int dap_queue_ap_abort	(	struct adiv5_dap *	dap,
		uint8_t *	ack
	)

inlinestatic

Queue an AP abort operation.

The current AP transaction is aborted, including any update of the transaction counter. The AP is left in an unknown state (so it must be re-initialized). For use only after the AP has reported WAIT status for an extended period.

Parameters

dap	The DAP used for writing.
ack	Pointer to where transaction status will be stored.

Returns: ERROR_OK for success, else a fault code.

Definition at line 632 of file arm_adi_v5.h.

References adiv5_dap::ops, and dap_ops::queue_ap_abort.

◆ dap_queue_ap_read()

static int dap_queue_ap_read	(	struct adiv5_ap *	ap,
		unsigned	reg,
		uint32_t *	data
	)

inlinestatic

Queue an AP register read.

Parameters

ap	The AP used for reading.
reg	The number of the AP register being read.
data	Pointer saying where to store the register's value (in host endianness).

Returns: ERROR_OK for success, else a fault code.

Definition at line 590 of file arm_adi_v5.h.

References adiv5_ap::ap_num, adiv5_ap::dap, LOG_ERROR, adiv5_dap::ops, dap_ops::queue_ap_read, and adiv5_ap::refcount.

Referenced by ap_read_register(), COMMAND_HANDLER(), dap_find_get_ap(), dap_get_debugbase(), dap_queue_read_reg(), kinetis_ke_mdm_read_register(), kinetis_mdm_read_register(), mem_ap_init(), mem_ap_read(), mem_ap_read_tar(), mem_ap_read_u32(), and mem_ap_setup_transfer_verify_size_packing().

◆ dap_queue_ap_write()

static int dap_queue_ap_write	(	struct adiv5_ap *	ap,
		unsigned	reg,
		uint32_t	data
	)

inlinestatic

Queue an AP register write.

Parameters

ap	The AP used for writing.
reg	The number of the AP register being written.
data	Value being written (host endianness)

Returns: ERROR_OK for success, else a fault code.

Definition at line 610 of file arm_adi_v5.h.

References adiv5_ap::ap_num, adiv5_ap::dap, LOG_ERROR, adiv5_dap::ops, dap_ops::queue_ap_write, and adiv5_ap::refcount.

Referenced by ap_write_register(), COMMAND_HANDLER(), kinetis_ke_mdm_write_register(), kinetis_mdm_write_register(), mem_ap_setup_csw(), mem_ap_setup_tar(), mem_ap_write(), and mem_ap_write_u32().

◆ dap_queue_dp_read()

static int dap_queue_dp_read	(	struct adiv5_dap *	dap,
		unsigned	reg,
		uint32_t *	data
	)

inlinestatic

Queue a DP register read.

Note that not all DP registers are readable; also, that JTAG and SWD have slight differences in DP register support.

Parameters

dap	The DAP used for reading.
reg	The two-bit number of the DP register being read.
data	Pointer saying where to store the register's value (in host endianness).

Returns: ERROR_OK for success, else a fault code.

Definition at line 555 of file arm_adi_v5.h.

References adiv5_dap::ops, and dap_ops::queue_dp_read.

Referenced by adiv6_dap_read_baseptr(), COMMAND_HANDLER(), dap_dp_init(), and dap_dp_read_atomic().

◆ dap_queue_dp_write()

static int dap_queue_dp_write	(	struct adiv5_dap *	dap,
		unsigned	reg,
		uint32_t	data
	)

inlinestatic

Queue a DP register write.

Note that not all DP registers are writable; also, that JTAG and SWD have slight differences in DP register support.

Parameters

dap	The DAP used for writing.
reg	The two-bit number of the DP register being written.
data	Value being written (host endianness)

Returns: ERROR_OK for success, else a fault code.

Definition at line 573 of file arm_adi_v5.h.

References adiv5_dap::ops, and dap_ops::queue_dp_write.

Referenced by COMMAND_HANDLER(), and dap_dp_init().

◆ dap_register_commands()

int dap_register_commands ( struct command_context * cmd_ctx )

Definition at line 539 of file arm_dap.c.

Referenced by setup_command_handler().

◆ dap_run()

static int dap_run ( struct adiv5_dap * dap )

inlinestatic

Perform all queued DAP operations, and clear any errors posted in the CTRL_STAT register when they are done.

Note that if more than one AP operation will be queued, one of the first operations in the queue should probably enable CORUNDETECT in the CTRL/STAT register.

Parameters

dap	The DAP used.

Returns: ERROR_OK for success, else a fault code.

Definition at line 648 of file arm_adi_v5.h.

References adiv5_dap::ops, and dap_ops::run.

Referenced by aarch64_examine_first(), ap_read_register(), ap_write_register(), COMMAND_HANDLER(), cortex_a_init_debug_access(), cortex_m_endreset_event(), cortex_m_examine_exception_reason(), cortex_m_fast_read_all_regs(), dap_dp_init(), dap_dp_read_atomic(), dap_find_get_ap(), dap_get_debugbase(), dap_init_all(), jtag_limit_queue_size(), kinetis_ke_mdm_read_register(), kinetis_ke_mdm_write_register(), kinetis_mdm_read_register(), kinetis_mdm_write_register(), mem_ap_init(), mem_ap_read(), mem_ap_read_atomic_u32(), mem_ap_read_tar(), mem_ap_setup_transfer_verify_size_packing(), mem_ap_write(), mem_ap_write_atomic_u32(), rtp_read_cs_regs(), and rtp_rom_loop().

◆ dap_send_sequence()

static int dap_send_sequence	(	struct adiv5_dap *	dap,
		enum swd_special_seq	seq
	)

inlinestatic

Send an adi-v5 sequence to the DAP.

Parameters

dap	The DAP used for reading.
seq	The sequence to send.

Returns: ERROR_OK for success, else a fault code.

Definition at line 536 of file arm_adi_v5.h.

References adiv5_dap::ops, and dap_ops::send_sequence.

Referenced by dap_to_jtag(), and dap_to_swd().

◆ dap_sync()

static int dap_sync ( struct adiv5_dap * dap )

inlinestatic

Definition at line 654 of file arm_adi_v5.h.

References ERROR_OK, adiv5_dap::ops, and dap_ops::sync.

◆ dap_to_jtag()

int dap_to_jtag ( struct adiv5_dap * dap )

Put the debug link into JTAG mode, if the target supports it.

The link's initial mode may be either SWD or JTAG.

Note that targets implemented with SW-DP do not support JTAG, and that some targets which could otherwise support it may have been configured to disable JTAG signaling

Parameters

dap	The DAP used

Returns: ERROR_OK or else a fault code.

Definition at line 969 of file arm_adi_v5.c.

References dap_send_sequence(), LOG_DEBUG, and SWD_TO_JTAG.

Referenced by COMMAND_HANDLER().

◆ dap_to_swd()

int dap_to_swd ( struct adiv5_dap * dap )

Put the debug link into SWD mode, if the target supports it.

The link's initial mode may be either JTAG (for example, with SWJ-DP after reset) or SWD.

Note that targets using the JTAG-DP do not support SWD, and that some targets which could otherwise support it may have been configured to disable SWD signaling

Parameters

dap	The DAP used

Returns: ERROR_OK or else a fault code.

Definition at line 951 of file arm_adi_v5.c.

References dap_send_sequence(), JTAG_TO_SWD, and LOG_DEBUG.

Referenced by COMMAND_HANDLER().

◆ is_64bit_ap()

static bool is_64bit_ap ( struct adiv5_ap * ap )

inlinestatic

Definition at line 511 of file arm_adi_v5.h.

References adiv5_ap::cfg_reg, and MEM_AP_REG_CFG_LA.

Referenced by COMMAND_HANDLER(), dap_get_debugbase(), dap_info_mem_ap_header(), mem_ap_read_tar(), mem_ap_setup_tar(), rtp_ap(), and rtp_rom_loop().

◆ is_adiv6()

static bool is_adiv6 ( const struct adiv5_dap * dap )

inlinestatic

Check if DAP is ADIv6.

Parameters

dap	The DAP to test

Returns: true for ADIv6, false for either ADIv5 or unknown version

Definition at line 523 of file arm_adi_v5.h.

References adiv5_dap::adi_version.

Referenced by _dap_get_ap(), COMMAND_HANDLER(), dap_find_get_ap(), dap_init_all(), dmem_ap_q_read(), dmem_ap_q_write(), is_ap_num_valid(), jtag_ap_q_bankselect(), jtagdp_overrun_check(), log_dap_cmd(), rshim_ap_q_read(), rshim_ap_q_write(), rtp_ap(), stlink_dap_ap_read(), stlink_dap_ap_write(), swd_queue_ap_bankselect(), swd_queue_dp_bankselect(), and vdebug_dap_bankselect().

◆ is_ap_num_valid()

bool is_ap_num_valid	(	struct adiv5_dap *	dap,
		uint64_t	ap_num
	)

Definition at line 1077 of file arm_adi_v5.c.

References adiv5_dap::asize, DP_APSEL_MAX, and is_adiv6().

Referenced by _dap_get_ap(), and COMMAND_HANDLER().

◆ mem_ap_init()

int mem_ap_init ( struct adiv5_ap * ap )

Initialize a DAP.

This sets up the power domains, prepares the DP for further use, and arranges to use AP #0 for all AP operations until dap_ap-select() changes that policy.

Parameters

ap	The MEM-AP being initialized.

Definition at line 887 of file arm_adi_v5.c.

References adiv5_dap::ap, BIT, adiv5_ap::cfg_reg, CSW_128BIT, CSW_256BIT, CSW_32BIT, CSW_64BIT, adiv5_ap::csw_size_probed_mask, adiv5_ap::csw_size_supported_mask, adiv5_ap::csw_value, adiv5_ap::dap, dap_queue_ap_read(), dap_run(), ERROR_OK, LOG_DEBUG, MEM_AP_REG_CFG, MEM_AP_REG_CFG_BE, MEM_AP_REG_CFG_LA, MEM_AP_REG_CFG_LD, adiv5_ap::packed_transfers_probed, adiv5_ap::packed_transfers_supported, adiv5_ap::tar_valid, adiv5_dap::ti_be_32_quirks, true, and adiv5_ap::unaligned_access_bad.

Referenced by aarch64_examine_first(), cortex_a_examine_first(), cortex_m_examine(), mem_ap_examine(), and xtensa_dm_examine().

◆ mem_ap_read_atomic_u32()

int mem_ap_read_atomic_u32	(	struct adiv5_ap *	ap,
		target_addr_t	address,
		uint32_t *	value
	)

Synchronous read of a word from memory or a system register.

As a side effect, this flushes any queued transactions.

Parameters

ap	The MEM-AP to access.
address	Address of the 32-bit word to read; it must be readable by the currently selected MEM-AP.
value	points to where the result will be stored.

Returns: ERROR_OK for success; *value holds the result. Otherwise a fault code.

Definition at line 266 of file arm_adi_v5.c.

References adiv5_ap::dap, dap_run(), ERROR_OK, and mem_ap_read_u32().

Referenced by aarch64_check_state_one(), aarch64_clear_reset_catch(), aarch64_debug_entry(), aarch64_enable_reset_catch(), aarch64_handle_target_request(), aarch64_init_debug_access(), aarch64_prepare_restart_one(), aarch64_read_cpu_memory(), aarch64_read_cpu_memory_fast(), aarch64_read_cpu_memory_slow(), aarch64_step(), aarch64_write_cpu_memory(), arm_cti_ack_events(), arm_cti_mod_reg_bits(), arm_cti_read_reg(), armv7a_setup_semihosting(), armv8_set_dbgreg_bits(), COMMAND_HANDLER(), cortex_a_debug_entry(), cortex_a_deinit_target(), cortex_a_examine_first(), cortex_a_handle_target_request(), cortex_a_init_debug_access(), cortex_a_internal_restart(), cortex_a_poll(), cortex_a_read_copro(), cortex_a_read_cpu_memory(), cortex_a_read_cpu_memory_fast(), cortex_a_read_cpu_memory_slow(), cortex_a_read_dcc(), cortex_a_set_dscr_bits(), cortex_a_wait_dscr_bits(), cortex_a_wait_instrcmpl(), cortex_a_write_cpu_memory(), cortex_m_assert_reset(), cortex_m_clear_halt(), cortex_m_endreset_event(), cortex_m_examine_exception_reason(), cortex_m_load_core_reg_u32(), cortex_m_read_dhcsr_atomic_sticky(), cortex_m_soft_reset_halt(), dpmv8_dpm_prepare(), dpmv8_exec_opcode(), dpmv8_read_dcc(), and dpmv8_read_dcc_64().

◆ mem_ap_read_buf()

int mem_ap_read_buf	(	struct adiv5_ap *	ap,
		uint8_t *	buffer,
		uint32_t	size,
		uint32_t	count,
		target_addr_t	address
	)

Definition at line 722 of file arm_adi_v5.c.

References adiv5_dap::ap, buffer, count, mem_ap_read(), and size.

Referenced by cortex_m_read_memory(), mem_ap_read_memory(), xtensa_dm_queue_pwr_reg_read(), and xtensa_dm_queue_reg_read().

◆ mem_ap_read_buf_noincr()

int mem_ap_read_buf_noincr	(	struct adiv5_ap *	ap,
		uint8_t *	buffer,
		uint32_t	size,
		uint32_t	count,
		target_addr_t	address
	)

Definition at line 734 of file arm_adi_v5.c.

References adiv5_dap::ap, buffer, count, mem_ap_read(), and size.

Referenced by aarch64_read_cpu_memory_fast(), cortex_a_read_cpu_memory_fast(), cortex_m_dcc_read(), and cortex_m_profiling().

◆ mem_ap_read_u32()

int mem_ap_read_u32	(	struct adiv5_ap *	ap,
		target_addr_t	address,
		uint32_t *	value
	)

Asynchronous (queued) read of a word from memory or a system register.

Parameters

ap	The MEM-AP to access.
address	Address of the 32-bit word to read; it must be readable by the currently selected MEM-AP.
value	points to where the word will be stored when the transaction queue is flushed (assuming no errors).

Returns: ERROR_OK for success. Otherwise a fault code.

Definition at line 237 of file arm_adi_v5.c.

References CSW_32BIT, CSW_ADDRINC_MASK, adiv5_ap::csw_value, adiv5_ap::dap, dap_queue_ap_read(), ERROR_OK, MEM_AP_REG_BD0, and mem_ap_setup_transfer().

Referenced by aarch64_examine_first(), COMMAND_HANDLER(), cortex_m_debug_entry(), cortex_m_examine_exception_reason(), cortex_m_fast_read_all_regs(), cortex_m_load_core_reg_u32(), cortex_m_queue_reg_read(), cortex_m_store_core_reg_u32(), dap_queue_read_reg(), dpmv8_dpm_prepare(), and mem_ap_read_atomic_u32().

◆ mem_ap_write_atomic_u32()

int mem_ap_write_atomic_u32	(	struct adiv5_ap *	ap,
		target_addr_t	address,
		uint32_t	value
	)

Synchronous write of a word to memory or a system register.

As a side effect, this flushes any queued transactions.

Parameters

ap	The MEM-AP to access.
address	Address to be written; it must be writable by the currently selected MEM-AP.
value	Word that will be written.

Returns: ERROR_OK for success; the data was written. Otherwise a fault code.

Definition at line 318 of file arm_adi_v5.c.

References adiv5_ap::dap, dap_run(), ERROR_OK, and mem_ap_write_u32().

Referenced by aarch64_assert_reset(), aarch64_clear_reset_catch(), aarch64_dap_write_memap_register_u32(), aarch64_debug_entry(), aarch64_enable_reset_catch(), aarch64_examine_first(), aarch64_init_debug_access(), aarch64_prepare_restart_one(), aarch64_read_cpu_memory(), aarch64_read_cpu_memory_fast(), aarch64_read_cpu_memory_slow(), aarch64_step(), aarch64_write_cpu_memory(), aarch64_write_cpu_memory_fast(), aarch64_write_cpu_memory_slow(), arm_cti_ack_events(), arm_cti_enable(), arm_cti_mod_reg_bits(), arm_cti_write_reg(), armv7a_setup_semihosting(), armv8_set_dbgreg_bits(), COMMAND_HANDLER(), cortex_a_dap_write_memap_register_u32(), cortex_a_deassert_reset(), cortex_a_debug_entry(), cortex_a_deinit_target(), cortex_a_examine_first(), cortex_a_halt(), cortex_a_init_debug_access(), cortex_a_internal_restart(), cortex_a_read_cpu_memory(), cortex_a_read_cpu_memory_fast(), cortex_a_set_dcc_mode(), cortex_a_set_dscr_bits(), cortex_a_write_copro(), cortex_a_write_cpu_memory(), cortex_a_write_cpu_memory_fast(), cortex_a_write_cpu_memory_slow(), cortex_m_assert_reset(), cortex_m_clear_halt(), cortex_m_fast_read_all_regs(), cortex_m_load_core_reg_u32(), cortex_m_soft_reset_halt(), cortex_m_store_core_reg_u32(), cortex_m_write_debug_halt_mask(), dpmv8_bpwp_disable(), handle_reset_halt(), and wrap_write_u32().

◆ mem_ap_write_buf()

int mem_ap_write_buf	(	struct adiv5_ap *	ap,
		const uint8_t *	buffer,
		uint32_t	size,
		uint32_t	count,
		target_addr_t	address
	)

Definition at line 728 of file arm_adi_v5.c.

References adiv5_dap::ap, buffer, count, mem_ap_write(), and size.

Referenced by COMMAND_HANDLER(), and cortex_m_write_memory().

◆ mem_ap_write_buf_noincr()

int mem_ap_write_buf_noincr	(	struct adiv5_ap *	ap,
		const uint8_t *	buffer,
		uint32_t	size,
		uint32_t	count,
		target_addr_t	address
	)

Definition at line 740 of file arm_adi_v5.c.

References adiv5_dap::ap, buffer, count, mem_ap_write(), and size.

Referenced by aarch64_write_cpu_memory_fast(), cortex_a_write_cpu_memory_fast(), and cortex_m_dcc_read().

◆ mem_ap_write_u32()

int mem_ap_write_u32	(	struct adiv5_ap *	ap,
		target_addr_t	address,
		uint32_t	value
	)

Asynchronous (queued) write of a word to memory or a system register.

Parameters

ap	The MEM-AP to access.
address	Address to be written; it must be writable by the currently selected MEM-AP.
value	Word that will be written to the address when transaction queue is flushed (assuming no errors).

Returns: ERROR_OK for success. Otherwise a fault code.

Definition at line 289 of file arm_adi_v5.c.

References CSW_32BIT, CSW_ADDRINC_MASK, adiv5_ap::csw_value, adiv5_ap::dap, dap_queue_ap_write(), ERROR_OK, MEM_AP_REG_BD0, and mem_ap_setup_transfer().

Referenced by armv8_dpm_handle_exception(), COMMAND_HANDLER(), cortex_a_exec_opcode(), cortex_a_init_debug_access(), cortex_a_write_dcc(), cortex_m_assert_reset(), cortex_m_endreset_event(), cortex_m_load_core_reg_u32(), cortex_m_queue_reg_read(), cortex_m_soft_reset_halt(), cortex_m_store_core_reg_u32(), dpmv8_exec_opcode(), dpmv8_write_dcc(), dpmv8_write_dcc_64(), mem_ap_write_atomic_u32(), xtensa_dm_queue_pwr_reg_read(), xtensa_dm_queue_pwr_reg_write(), and xtensa_dm_queue_reg_write().

Variable Documentation

◆ dap_instance_commands

const struct command_registration dap_instance_commands[]

extern

Definition at line 2884 of file arm_adi_v5.c.

Referenced by dap_create().

◆ jtag_dp_ops

const struct dap_ops jtag_dp_ops

extern

Definition at line 890 of file adi_v5_jtag.c.

Referenced by dap_init_all().

◆ swd_dap_ops

const struct dap_ops swd_dap_ops

extern

Definition at line 640 of file adi_v5_swd.c.

Referenced by dap_init_all().

Data Structures

Macros

Enumerations

Functions

Variables

Detailed Description

Macro Definition Documentation

◆ ADIV5_AP_REG_IDR

◆ ADIV5_DP_SELECT_APBANK

◆ ADIV5_DP_SELECT_APSEL

◆ ADIV5_MEM_AP_REG_BASE

◆ ADIV5_MEM_AP_REG_BASE64

◆ ADIV5_MEM_AP_REG_BD0

◆ ADIV5_MEM_AP_REG_BD1

◆ ADIV5_MEM_AP_REG_BD2

◆ ADIV5_MEM_AP_REG_BD3

◆ ADIV5_MEM_AP_REG_CFG

◆ ADIV5_MEM_AP_REG_CSW

◆ ADIV5_MEM_AP_REG_DRW

◆ ADIV5_MEM_AP_REG_MBT

◆ ADIV5_MEM_AP_REG_TAR

◆ ADIV5_MEM_AP_REG_TAR64

◆ ADIV6_AP_REG_IDR

◆ ADIV6_MEM_AP_REG_BASE

◆ ADIV6_MEM_AP_REG_BASE64

◆ ADIV6_MEM_AP_REG_BD0

◆ ADIV6_MEM_AP_REG_BD1

◆ ADIV6_MEM_AP_REG_BD2

◆ ADIV6_MEM_AP_REG_BD3

◆ ADIV6_MEM_AP_REG_CFG

◆ ADIV6_MEM_AP_REG_CSW

◆ ADIV6_MEM_AP_REG_DRW

◆ ADIV6_MEM_AP_REG_MBT

◆ ADIV6_MEM_AP_REG_TAR

◆ ADIV6_MEM_AP_REG_TAR64

◆ AP_REG_IDR

◆ AP_REG_IDR_CLASS_COM

◆ AP_REG_IDR_CLASS_MASK

◆ AP_REG_IDR_CLASS_MEM_AP

◆ AP_REG_IDR_CLASS_NONE

◆ AP_REG_IDR_CLASS_SHIFT

◆ AP_REG_IDR_DESIGNER_MASK

◆ AP_REG_IDR_DESIGNER_SHIFT

◆ AP_REG_IDR_REVISION_MASK

◆ AP_REG_IDR_REVISION_SHIFT

◆ AP_REG_IDR_TYPE_MASK

◆ AP_REG_IDR_TYPE_SHIFT

◆ AP_REG_IDR_VALUE

◆ AP_REG_IDR_VARIANT_MASK

◆ AP_REG_IDR_VARIANT_SHIFT

◆ AP_TYPE_MASK

◆ ARM_ID

◆ BANK_REG

◆ CDBGPWRUPACK

◆ CDBGPWRUPREQ

◆ CDBGRSTACK

◆ CDBGRSTREQ

◆ CORUNDETECT

◆ CSW_128BIT

◆ CSW_16BIT

◆ CSW_256BIT

◆ CSW_32BIT

◆ CSW_64BIT

◆ CSW_8BIT

◆ CSW_ADDRINC_MASK

◆ CSW_ADDRINC_OFF

◆ CSW_ADDRINC_PACKED

◆ CSW_ADDRINC_SINGLE

◆ CSW_AHB_DEFAULT

◆ CSW_AHB_HPROT1

◆ CSW_AHB_MASTER_DEBUG

◆ CSW_AHB_SPROT

◆ CSW_APB_DEFAULT

◆ CSW_AXI_ARPROT0_PRIV

◆ CSW_AXI_ARPROT1_NONSEC

◆ CSW_AXI_DEFAULT

◆ CSW_DBGSWENABLE

◆ CSW_DEVICE_EN

◆ CSW_SIZE_MASK

◆ CSW_SPIDEN