OpenOCD
arm_adi_v5.h
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1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 
3 /***************************************************************************
4  * Copyright (C) 2006 by Magnus Lundin *
5  * lundin@mlu.mine.nu *
6  * *
7  * Copyright (C) 2008 by Spencer Oliver *
8  * spen@spen-soft.co.uk *
9  * *
10  * Copyright (C) 2019-2021, Ampere Computing LLC *
11  ***************************************************************************/
12 
13 #ifndef OPENOCD_TARGET_ARM_ADI_V5_H
14 #define OPENOCD_TARGET_ARM_ADI_V5_H
15 
23 #include <helper/list.h>
24 #include "arm_jtag.h"
25 #include "helper/bits.h"
26 
27 /* JEP106 ID for ARM */
28 #define ARM_ID 0x23B
29 
30 /* three-bit ACK values for SWD access (sent LSB first) */
31 #define SWD_ACK_OK 0x1
32 #define SWD_ACK_WAIT 0x2
33 #define SWD_ACK_FAULT 0x4
34 
35 #define DPAP_WRITE 0
36 #define DPAP_READ 1
37 
38 #define BANK_REG(bank, reg) (((bank) << 4) | (reg))
39 
40 /* A[3:0] for DP registers; A[1:0] are always zero.
41  * - JTAG accesses all of these via JTAG_DP_DPACC, except for
42  * IDCODE (JTAG_DP_IDCODE) and ABORT (JTAG_DP_ABORT).
43  * - SWD accesses these directly, sometimes needing SELECT.DPBANKSEL
44  */
45 #define DP_DPIDR BANK_REG(0x0, 0x0) /* DPv1+: ro */
46 #define DP_ABORT BANK_REG(0x0, 0x0) /* DPv1+: SWD: wo */
47 #define DP_DPIDR1 BANK_REG(0x1, 0x0) /* DPv3: ro */
48 #define DP_BASEPTR0 BANK_REG(0x2, 0x0) /* DPv3: ro */
49 #define DP_BASEPTR1 BANK_REG(0x3, 0x0) /* DPv3: ro */
50 #define DP_CTRL_STAT BANK_REG(0x0, 0x4) /* DPv0+: rw */
51 #define DP_DLCR BANK_REG(0x1, 0x4) /* DPv1+: SWD: rw */
52 #define DP_TARGETID BANK_REG(0x2, 0x4) /* DPv2: ro */
53 #define DP_DLPIDR BANK_REG(0x3, 0x4) /* DPv2: ro */
54 #define DP_EVENTSTAT BANK_REG(0x4, 0x4) /* DPv2: ro */
55 #define DP_SELECT1 BANK_REG(0x5, 0x4) /* DPv3: ro */
56 #define DP_RESEND BANK_REG(0x0, 0x8) /* DPv1+: SWD: ro */
57 #define DP_SELECT BANK_REG(0x0, 0x8) /* DPv0+: JTAG: rw; SWD: wo */
58 #define DP_RDBUFF BANK_REG(0x0, 0xC) /* DPv0+: ro */
59 #define DP_TARGETSEL BANK_REG(0x0, 0xC) /* DPv2: SWD: wo */
60 
61 #define DLCR_TO_TRN(dlcr) ((uint32_t)(1 + ((3 & (dlcr)) >> 8))) /* 1..4 clocks */
62 
63 /* Fields of DP_DPIDR register */
64 #define DP_DPIDR_VERSION_SHIFT 12
65 #define DP_DPIDR_VERSION_MASK (0xFUL << DP_DPIDR_VERSION_SHIFT)
66 
67 /* Fields of the DP's AP ABORT register */
68 #define DAPABORT (1UL << 0)
69 #define STKCMPCLR (1UL << 1) /* SWD-only */
70 #define STKERRCLR (1UL << 2) /* SWD-only */
71 #define WDERRCLR (1UL << 3) /* SWD-only */
72 #define ORUNERRCLR (1UL << 4) /* SWD-only */
73 
74 /* Fields of register DP_DPIDR1 */
75 #define DP_DPIDR1_ASIZE_MASK (0x7F)
76 #define DP_DPIDR1_ERRMODE BIT(7)
77 
78 /* Fields of register DP_BASEPTR0 */
79 #define DP_BASEPTR0_VALID BIT(0)
80 
81 /* Fields of the DP's CTRL/STAT register */
82 #define CORUNDETECT (1UL << 0)
83 #define SSTICKYORUN (1UL << 1)
84 /* 3:2 - transaction mode (e.g. pushed compare) */
85 #define SSTICKYCMP (1UL << 4)
86 #define SSTICKYERR (1UL << 5)
87 #define READOK (1UL << 6) /* SWD-only */
88 #define WDATAERR (1UL << 7) /* SWD-only */
89 /* 11:8 - mask lanes for pushed compare or verify ops */
90 /* 21:12 - transaction counter */
91 #define CDBGRSTREQ (1UL << 26)
92 #define CDBGRSTACK (1UL << 27)
93 #define CDBGPWRUPREQ (1UL << 28)
94 #define CDBGPWRUPACK (1UL << 29)
95 #define CSYSPWRUPREQ (1UL << 30)
96 #define CSYSPWRUPACK (1UL << 31)
97 
98 #define DP_DLPIDR_PROTVSN 1u
99 
100 #define ADIV5_DP_SELECT_APSEL 0xFF000000
101 #define ADIV5_DP_SELECT_APBANK 0x000000F0
102 #define DP_SELECT_DPBANK 0x0000000F
103 /*
104  * Mask of AP ADDR in select cache, concatenating DP SELECT and DP_SELECT1.
105  * In case of ADIv5, the mask contains both APSEL and APBANKSEL fields.
106  */
107 #define SELECT_AP_MASK (~(uint64_t)DP_SELECT_DPBANK)
108 
109 #define DP_APSEL_MAX (255) /* Strict limit for ADIv5, number of AP buffers for ADIv6 */
110 #define DP_APSEL_INVALID 0xF00 /* more than DP_APSEL_MAX and not ADIv6 aligned 4k */
111 
112 #define DP_TARGETSEL_INVALID 0xFFFFFFFFU
113 #define DP_TARGETSEL_DPID_MASK 0x0FFFFFFFU
114 #define DP_TARGETSEL_INSTANCEID_MASK 0xF0000000U
115 #define DP_TARGETSEL_INSTANCEID_SHIFT 28
116 
117 
118 /* MEM-AP register addresses */
119 #define ADIV5_MEM_AP_REG_CSW (0x00)
120 #define ADIV5_MEM_AP_REG_TAR (0x04)
121 #define ADIV5_MEM_AP_REG_TAR64 (0x08) /* RW: Large Physical Address Extension */
122 #define ADIV5_MEM_AP_REG_DRW (0x0C) /* RW: Data Read/Write register */
123 #define ADIV5_MEM_AP_REG_BD0 (0x10) /* RW: Banked Data register 0-3 */
124 #define ADIV5_MEM_AP_REG_BD1 (0x14)
125 #define ADIV5_MEM_AP_REG_BD2 (0x18)
126 #define ADIV5_MEM_AP_REG_BD3 (0x1C)
127 #define ADIV5_MEM_AP_REG_MBT (0x20) /* --: Memory Barrier Transfer register */
128 #define ADIV5_MEM_AP_REG_BASE64 (0xF0) /* RO: Debug Base Address (LA) register */
129 #define ADIV5_MEM_AP_REG_CFG (0xF4) /* RO: Configuration register */
130 #define ADIV5_MEM_AP_REG_BASE (0xF8) /* RO: Debug Base Address register */
131 
132 #define ADIV6_MEM_AP_REG_CSW (0xD00 + ADIV5_MEM_AP_REG_CSW)
133 #define ADIV6_MEM_AP_REG_TAR (0xD00 + ADIV5_MEM_AP_REG_TAR)
134 #define ADIV6_MEM_AP_REG_TAR64 (0xD00 + ADIV5_MEM_AP_REG_TAR64)
135 #define ADIV6_MEM_AP_REG_DRW (0xD00 + ADIV5_MEM_AP_REG_DRW)
136 #define ADIV6_MEM_AP_REG_BD0 (0xD00 + ADIV5_MEM_AP_REG_BD0)
137 #define ADIV6_MEM_AP_REG_BD1 (0xD00 + ADIV5_MEM_AP_REG_BD1)
138 #define ADIV6_MEM_AP_REG_BD2 (0xD00 + ADIV5_MEM_AP_REG_BD2)
139 #define ADIV6_MEM_AP_REG_BD3 (0xD00 + ADIV5_MEM_AP_REG_BD3)
140 #define ADIV6_MEM_AP_REG_MBT (0xD00 + ADIV5_MEM_AP_REG_MBT)
141 #define ADIV6_MEM_AP_REG_BASE64 (0xD00 + ADIV5_MEM_AP_REG_BASE64)
142 #define ADIV6_MEM_AP_REG_CFG (0xD00 + ADIV5_MEM_AP_REG_CFG)
143 #define ADIV6_MEM_AP_REG_BASE (0xD00 + ADIV5_MEM_AP_REG_BASE)
144 
145 #define MEM_AP_REG_CSW(dap) (is_adiv6(dap) ? ADIV6_MEM_AP_REG_CSW : ADIV5_MEM_AP_REG_CSW)
146 #define MEM_AP_REG_TAR(dap) (is_adiv6(dap) ? ADIV6_MEM_AP_REG_TAR : ADIV5_MEM_AP_REG_TAR)
147 #define MEM_AP_REG_TAR64(dap) (is_adiv6(dap) ? ADIV6_MEM_AP_REG_TAR64 : ADIV5_MEM_AP_REG_TAR64)
148 #define MEM_AP_REG_DRW(dap) (is_adiv6(dap) ? ADIV6_MEM_AP_REG_DRW : ADIV5_MEM_AP_REG_DRW)
149 #define MEM_AP_REG_BD0(dap) (is_adiv6(dap) ? ADIV6_MEM_AP_REG_BD0 : ADIV5_MEM_AP_REG_BD0)
150 #define MEM_AP_REG_BD1(dap) (is_adiv6(dap) ? ADIV6_MEM_AP_REG_BD1 : ADIV5_MEM_AP_REG_BD1)
151 #define MEM_AP_REG_BD2(dap) (is_adiv6(dap) ? ADIV6_MEM_AP_REG_BD2 : ADIV5_MEM_AP_REG_BD2)
152 #define MEM_AP_REG_BD3(dap) (is_adiv6(dap) ? ADIV6_MEM_AP_REG_BD3 : ADIV5_MEM_AP_REG_BD3)
153 #define MEM_AP_REG_MBT(dap) (is_adiv6(dap) ? ADIV6_MEM_AP_REG_MBT : ADIV5_MEM_AP_REG_MBT)
154 #define MEM_AP_REG_BASE64(dap) (is_adiv6(dap) ? ADIV6_MEM_AP_REG_BASE64 : ADIV5_MEM_AP_REG_BASE64)
155 #define MEM_AP_REG_CFG(dap) (is_adiv6(dap) ? ADIV6_MEM_AP_REG_CFG : ADIV5_MEM_AP_REG_CFG)
156 #define MEM_AP_REG_BASE(dap) (is_adiv6(dap) ? ADIV6_MEM_AP_REG_BASE : ADIV5_MEM_AP_REG_BASE)
157 
158 /* Generic AP register address */
159 #define ADIV5_AP_REG_IDR (0xFC) /* RO: Identification Register */
160 #define ADIV6_AP_REG_IDR (0xD00 + ADIV5_AP_REG_IDR)
161 #define AP_REG_IDR(dap) (is_adiv6(dap) ? ADIV6_AP_REG_IDR : ADIV5_AP_REG_IDR)
162 
163 /* Fields of the MEM-AP's CSW register */
164 #define CSW_SIZE_MASK 7
165 #define CSW_8BIT 0
166 #define CSW_16BIT 1
167 #define CSW_32BIT 2
168 #define CSW_64BIT 3
169 #define CSW_128BIT 4
170 #define CSW_256BIT 5
171 #define CSW_ADDRINC_MASK (3UL << 4)
172 #define CSW_ADDRINC_OFF 0UL
173 #define CSW_ADDRINC_SINGLE (1UL << 4)
174 #define CSW_ADDRINC_PACKED (2UL << 4)
175 #define CSW_DEVICE_EN (1UL << 6)
176 #define CSW_TRIN_PROG (1UL << 7)
177 
178 /* All fields in bits 12 and above are implementation-defined
179  * Defaults for AHB/AXI in "Standard Memory Access Port Definitions" from ADI
180  * Some bits are shared between buses
181  */
182 #define CSW_SPIDEN (1UL << 23)
183 #define CSW_DBGSWENABLE (1UL << 31)
184 
185 /* AHB: Privileged */
186 #define CSW_AHB_HPROT1 (1UL << 25)
187 /* AHB: set HMASTER signals to AHB-AP ID */
188 #define CSW_AHB_MASTER_DEBUG (1UL << 29)
189 /* AHB5: non-secure access via HNONSEC
190  * AHB3: SBO, UNPREDICTABLE if zero */
191 #define CSW_AHB_SPROT (1UL << 30)
192 /* AHB: initial value of csw_default */
193 #define CSW_AHB_DEFAULT (CSW_AHB_HPROT1 | CSW_AHB_MASTER_DEBUG | CSW_DBGSWENABLE)
194 
195 /* AXI: Privileged */
196 #define CSW_AXI_ARPROT0_PRIV (1UL << 28)
197 /* AXI: Non-secure */
198 #define CSW_AXI_ARPROT1_NONSEC (1UL << 29)
199 /* AXI: initial value of csw_default */
200 #define CSW_AXI_DEFAULT (CSW_AXI_ARPROT0_PRIV | CSW_AXI_ARPROT1_NONSEC | CSW_DBGSWENABLE)
201 
202 /* APB: initial value of csw_default */
203 #define CSW_APB_DEFAULT (CSW_DBGSWENABLE)
204 
205 /* Fields of the MEM-AP's CFG register */
206 #define MEM_AP_REG_CFG_BE BIT(0)
207 #define MEM_AP_REG_CFG_LA BIT(1)
208 #define MEM_AP_REG_CFG_LD BIT(2)
209 #define MEM_AP_REG_CFG_INVALID 0xFFFFFFF8
210 
211 /* Fields of the MEM-AP's IDR register */
212 #define AP_REG_IDR_REVISION_MASK (0xF0000000)
213 #define AP_REG_IDR_REVISION_SHIFT (28)
214 #define AP_REG_IDR_DESIGNER_MASK (0x0FFE0000)
215 #define AP_REG_IDR_DESIGNER_SHIFT (17)
216 #define AP_REG_IDR_CLASS_MASK (0x0001E000)
217 #define AP_REG_IDR_CLASS_SHIFT (13)
218 #define AP_REG_IDR_VARIANT_MASK (0x000000F0)
219 #define AP_REG_IDR_VARIANT_SHIFT (4)
220 #define AP_REG_IDR_TYPE_MASK (0x0000000F)
221 #define AP_REG_IDR_TYPE_SHIFT (0)
222 
223 #define AP_REG_IDR_CLASS_NONE (0x0)
224 #define AP_REG_IDR_CLASS_COM (0x1)
225 #define AP_REG_IDR_CLASS_MEM_AP (0x8)
226 
227 #define AP_REG_IDR_VALUE(d, c, t) (\
228  (((d) << AP_REG_IDR_DESIGNER_SHIFT) & AP_REG_IDR_DESIGNER_MASK) | \
229  (((c) << AP_REG_IDR_CLASS_SHIFT) & AP_REG_IDR_CLASS_MASK) | \
230  (((t) << AP_REG_IDR_TYPE_SHIFT) & AP_REG_IDR_TYPE_MASK) \
231 )
232 
233 #define AP_TYPE_MASK (AP_REG_IDR_DESIGNER_MASK | AP_REG_IDR_CLASS_MASK | AP_REG_IDR_TYPE_MASK)
234 
235 /* FIXME: not SWD specific; should be renamed, e.g. adiv5_special_seq */
244 };
245 
250 struct adiv5_ap {
254  struct adiv5_dap *dap;
255 
261  uint64_t ap_num;
262 
266  uint32_t csw_default;
267 
273  uint32_t csw_value;
274 
294 
301 
306  uint32_t memaccess_tck;
307 
308  /* Size of TAR autoincrement block, ARM ADI Specification requires at least 10 bits */
310 
311  /* true if packed transfers are supported by the MEM-AP */
314 
315  /* true if unaligned memory access is not supported by the MEM-AP */
317 
318  /* true if tar_value is in sync with TAR register */
319  bool tar_valid;
320 
321  /* MEM AP configuration register indicating LPAE support */
322  uint32_t cfg_reg;
323 
324  /* references counter */
325  unsigned int refcount;
326 
327  /* AP referenced during config. Never put it, even when refcount reaches zero */
329 };
330 
331 
348 struct adiv5_dap {
349  const struct dap_ops *ops;
350 
351  /* dap transaction list for WAIT support */
352  struct list_head cmd_journal;
353 
354  /* pool for dap_cmd objects */
355  struct list_head cmd_pool;
356 
357  /* number of dap_cmd objects in the pool */
359 
360  struct jtag_tap *tap;
361  /* Control config */
362  uint32_t dp_ctrl_stat;
363 
364  struct adiv5_ap ap[DP_APSEL_MAX + 1];
365 
366  /* The current manually selected AP by the "dap apsel" command */
367  uint64_t apsel;
368 
370  uint64_t select;
373  bool select1_valid; /* ADIv6 only */
384 
385  /* information about current pending SWjDP-AHBAP transaction */
386  uint8_t ack;
387 
392  uint32_t *last_read;
393 
394  /* The TI TMS470 and TMS570 series processors use a BE-32 memory ordering
395  * despite lack of support in the ARMv7 architecture. Memory access through
396  * the AHB-AP has strange byte ordering these processors, and we need to
397  * swizzle appropriately. */
399 
400  /* The Nuvoton NPCX M4 has an issue with writing to non-4-byte-aligned mmios.
401  * The work around is to repeat the data in all 4 bytes of DRW */
403 
409 
415 
419 
426 
431 
433  unsigned int adi_version;
434 
435  /* ADIv6 only field indicating ROM Table address size */
436  unsigned int asize;
437 };
438 
446 struct dap_ops {
448  int (*pre_connect_init)(struct adiv5_dap *dap);
449 
451  int (*connect)(struct adiv5_dap *dap);
452 
454  int (*send_sequence)(struct adiv5_dap *dap, enum swd_special_seq seq);
455 
457  int (*queue_dp_read)(struct adiv5_dap *dap, unsigned reg,
458  uint32_t *data);
460  int (*queue_dp_write)(struct adiv5_dap *dap, unsigned reg,
461  uint32_t data);
462 
464  int (*queue_ap_read)(struct adiv5_ap *ap, unsigned reg,
465  uint32_t *data);
467  int (*queue_ap_write)(struct adiv5_ap *ap, unsigned reg,
468  uint32_t data);
469 
471  int (*queue_ap_abort)(struct adiv5_dap *dap, uint8_t *ack);
472 
474  int (*run)(struct adiv5_dap *dap);
475 
478  int (*sync)(struct adiv5_dap *dap);
479 
481  void (*quit)(struct adiv5_dap *dap);
482 };
483 
484 /*
485  * Access Port types
486  */
487 enum ap_type {
491  AP_TYPE_APB_AP = AP_REG_IDR_VALUE(ARM_ID, AP_REG_IDR_CLASS_MEM_AP, 2), /* APB2 or APB3 Memory-AP */
492  AP_TYPE_AXI_AP = AP_REG_IDR_VALUE(ARM_ID, AP_REG_IDR_CLASS_MEM_AP, 4), /* AXI3 or AXI4 Memory-AP */
496  AP_TYPE_AHB5H_AP = AP_REG_IDR_VALUE(ARM_ID, AP_REG_IDR_CLASS_MEM_AP, 8), /* AHB5 with enhanced HPROT Memory-AP */
497 };
498 
499 extern const struct dap_ops jtag_dp_ops;
500 extern const struct dap_ops swd_dap_ops;
501 
502 /* Check the ap->cfg_reg Long Address field (bit 1)
503  *
504  * 0b0: The AP only supports physical addresses 32 bits or smaller
505  * 0b1: The AP supports physical addresses larger than 32 bits
506  *
507  * @param ap The AP used for reading.
508  *
509  * @return true for 64 bit, false for 32 bit
510  */
511 static inline bool is_64bit_ap(struct adiv5_ap *ap)
512 {
513  return (ap->cfg_reg & MEM_AP_REG_CFG_LA) != 0;
514 }
515 
523 static inline bool is_adiv6(const struct adiv5_dap *dap)
524 {
525  return dap->adi_version == 6;
526 }
527 
536 static inline int dap_send_sequence(struct adiv5_dap *dap,
537  enum swd_special_seq seq)
538 {
539  assert(dap->ops);
540  return dap->ops->send_sequence(dap, seq);
541 }
542 
555 static inline int dap_queue_dp_read(struct adiv5_dap *dap,
556  unsigned reg, uint32_t *data)
557 {
558  assert(dap->ops);
559  return dap->ops->queue_dp_read(dap, reg, data);
560 }
561 
573 static inline int dap_queue_dp_write(struct adiv5_dap *dap,
574  unsigned reg, uint32_t data)
575 {
576  assert(dap->ops);
577  return dap->ops->queue_dp_write(dap, reg, data);
578 }
579 
590 static inline int dap_queue_ap_read(struct adiv5_ap *ap,
591  unsigned reg, uint32_t *data)
592 {
593  assert(ap->dap->ops);
594  if (ap->refcount == 0) {
595  ap->refcount = 1;
596  LOG_ERROR("BUG: refcount AP#0x%" PRIx64 " used without get", ap->ap_num);
597  }
598  return ap->dap->ops->queue_ap_read(ap, reg, data);
599 }
600 
610 static inline int dap_queue_ap_write(struct adiv5_ap *ap,
611  unsigned reg, uint32_t data)
612 {
613  assert(ap->dap->ops);
614  if (ap->refcount == 0) {
615  ap->refcount = 1;
616  LOG_ERROR("BUG: refcount AP#0x%" PRIx64 " used without get", ap->ap_num);
617  }
618  return ap->dap->ops->queue_ap_write(ap, reg, data);
619 }
620 
632 static inline int dap_queue_ap_abort(struct adiv5_dap *dap, uint8_t *ack)
633 {
634  assert(dap->ops);
635  return dap->ops->queue_ap_abort(dap, ack);
636 }
637 
648 static inline int dap_run(struct adiv5_dap *dap)
649 {
650  assert(dap->ops);
651  return dap->ops->run(dap);
652 }
653 
654 static inline int dap_sync(struct adiv5_dap *dap)
655 {
656  assert(dap->ops);
657  if (dap->ops->sync)
658  return dap->ops->sync(dap);
659  return ERROR_OK;
660 }
661 
662 static inline int dap_dp_read_atomic(struct adiv5_dap *dap, unsigned reg,
663  uint32_t *value)
664 {
665  int retval;
666 
667  retval = dap_queue_dp_read(dap, reg, value);
668  if (retval != ERROR_OK)
669  return retval;
670 
671  return dap_run(dap);
672 }
673 
674 static inline int dap_dp_poll_register(struct adiv5_dap *dap, unsigned reg,
675  uint32_t mask, uint32_t value, int timeout)
676 {
677  assert(timeout > 0);
678  assert((value & mask) == value);
679 
680  int ret;
681  uint32_t regval;
682  LOG_DEBUG("DAP: poll %x, mask 0x%08" PRIx32 ", value 0x%08" PRIx32,
683  reg, mask, value);
684  do {
685  ret = dap_dp_read_atomic(dap, reg, &regval);
686  if (ret != ERROR_OK)
687  return ret;
688 
689  if ((regval & mask) == value)
690  break;
691 
692  alive_sleep(10);
693  } while (--timeout);
694 
695  if (!timeout) {
696  LOG_DEBUG("DAP: poll %x timeout", reg);
697  return ERROR_WAIT;
698  } else {
699  return ERROR_OK;
700  }
701 }
702 
703 /* Queued MEM-AP memory mapped single word transfers. */
704 int mem_ap_read_u32(struct adiv5_ap *ap,
705  target_addr_t address, uint32_t *value);
706 int mem_ap_write_u32(struct adiv5_ap *ap,
707  target_addr_t address, uint32_t value);
708 
709 /* Synchronous MEM-AP memory mapped single word transfers. */
710 int mem_ap_read_atomic_u32(struct adiv5_ap *ap,
711  target_addr_t address, uint32_t *value);
712 int mem_ap_write_atomic_u32(struct adiv5_ap *ap,
713  target_addr_t address, uint32_t value);
714 
715 /* Synchronous MEM-AP memory mapped bus block transfers. */
716 int mem_ap_read_buf(struct adiv5_ap *ap,
717  uint8_t *buffer, uint32_t size, uint32_t count, target_addr_t address);
718 int mem_ap_write_buf(struct adiv5_ap *ap,
719  const uint8_t *buffer, uint32_t size, uint32_t count, target_addr_t address);
720 
721 /* Synchronous, non-incrementing buffer functions for accessing fifos. */
722 int mem_ap_read_buf_noincr(struct adiv5_ap *ap,
723  uint8_t *buffer, uint32_t size, uint32_t count, target_addr_t address);
724 int mem_ap_write_buf_noincr(struct adiv5_ap *ap,
725  const uint8_t *buffer, uint32_t size, uint32_t count, target_addr_t address);
726 
727 /* Initialisation of the debug system, power domains and registers */
728 int dap_dp_init(struct adiv5_dap *dap);
729 int dap_dp_init_or_reconnect(struct adiv5_dap *dap);
730 int mem_ap_init(struct adiv5_ap *ap);
731 
732 /* Invalidate cached DP select and cached TAR and CSW of all APs */
733 void dap_invalidate_cache(struct adiv5_dap *dap);
734 
735 /* read ADIv6 baseptr register */
736 int adiv6_dap_read_baseptr(struct command_invocation *cmd, struct adiv5_dap *dap, target_addr_t *baseptr);
737 
738 /* test if ap_num is valid, based on current knowledge of dap */
739 bool is_ap_num_valid(struct adiv5_dap *dap, uint64_t ap_num);
740 
741 /* Probe Access Ports to find a particular type. Increment AP refcount */
742 int dap_find_get_ap(struct adiv5_dap *dap,
743  enum ap_type type_to_find,
744  struct adiv5_ap **ap_out);
745 
746 /* Return AP with specified ap_num. Increment AP refcount */
747 struct adiv5_ap *dap_get_ap(struct adiv5_dap *dap, uint64_t ap_num);
748 
749 /* Return AP with specified ap_num. Increment AP refcount and keep it non-zero */
750 struct adiv5_ap *dap_get_config_ap(struct adiv5_dap *dap, uint64_t ap_num);
751 
752 /* Decrement AP refcount and release the AP when refcount reaches zero */
753 int dap_put_ap(struct adiv5_ap *ap);
754 
756 static inline bool dap_is_multidrop(struct adiv5_dap *dap)
757 {
759 }
760 
761 /* Lookup CoreSight component */
762 int dap_lookup_cs_component(struct adiv5_ap *ap,
763  uint8_t type, target_addr_t *addr, int32_t idx);
764 
765 struct target;
766 
767 /* Put debug link into SWD mode */
768 int dap_to_swd(struct adiv5_dap *dap);
769 
770 /* Put debug link into JTAG mode */
771 int dap_to_jtag(struct adiv5_dap *dap);
772 
773 extern const struct command_registration dap_instance_commands[];
774 
775 struct arm_dap_object;
776 extern struct adiv5_dap *dap_instance_by_jim_obj(Jim_Interp *interp, Jim_Obj *o);
777 extern struct adiv5_dap *adiv5_get_dap(struct arm_dap_object *obj);
778 extern int dap_info_command(struct command_invocation *cmd,
779  struct adiv5_ap *ap);
780 extern int dap_register_commands(struct command_context *cmd_ctx);
781 extern const char *adiv5_dap_name(struct adiv5_dap *self);
782 extern const struct swd_driver *adiv5_dap_swd_driver(struct adiv5_dap *self);
783 extern int dap_cleanup_all(void);
784 
786  uint64_t ap_num;
787  struct adiv5_dap *dap;
788 };
789 
790 extern int adiv5_verify_config(struct adiv5_private_config *pc);
791 
795 };
796 
797 extern int adiv5_jim_configure_ext(struct target *target, struct jim_getopt_info *goi,
798  struct adiv5_private_config *pc,
799  enum adiv5_configure_dap_optional optional);
800 extern int adiv5_jim_configure(struct target *target, struct jim_getopt_info *goi);
801 
803  struct adiv5_dap *dap;
804  uint64_t ap_num;
805  uint32_t base;
806 };
807 
808 extern int adiv5_mem_ap_spot_init(struct adiv5_mem_ap_spot *p);
810  struct jim_getopt_info *goi);
811 
812 #endif /* OPENOCD_TARGET_ARM_ADI_V5_H */
const struct dap_ops jtag_dp_ops
Definition: adi_v5_jtag.c:898
struct adiv5_ap * dap_get_config_ap(struct adiv5_dap *dap, uint64_t ap_num)
Definition: arm_adi_v5.c:1197
const struct dap_ops swd_dap_ops
Definition: adi_v5_swd.c:677
int dap_cleanup_all(void)
Definition: arm_dap.c:160
static int dap_queue_ap_write(struct adiv5_ap *ap, unsigned reg, uint32_t data)
Queue an AP register write.
Definition: arm_adi_v5.h:610
int mem_ap_read_buf(struct adiv5_ap *ap, uint8_t *buffer, uint32_t size, uint32_t count, target_addr_t address)
Definition: arm_adi_v5.c:722
static bool is_64bit_ap(struct adiv5_ap *ap)
Definition: arm_adi_v5.h:511
int mem_ap_read_buf_noincr(struct adiv5_ap *ap, uint8_t *buffer, uint32_t size, uint32_t count, target_addr_t address)
Definition: arm_adi_v5.c:734
ap_type
Definition: arm_adi_v5.h:487
@ AP_TYPE_APB_AP
Definition: arm_adi_v5.h:491
@ AP_TYPE_AXI_AP
Definition: arm_adi_v5.h:492
@ AP_TYPE_APB4_AP
Definition: arm_adi_v5.h:494
@ AP_TYPE_AHB3_AP
Definition: arm_adi_v5.h:490
@ AP_TYPE_COM_AP
Definition: arm_adi_v5.h:489
@ AP_TYPE_AHB5H_AP
Definition: arm_adi_v5.h:496
@ AP_TYPE_JTAG_AP
Definition: arm_adi_v5.h:488
@ AP_TYPE_AXI5_AP
Definition: arm_adi_v5.h:495
@ AP_TYPE_AHB5_AP
Definition: arm_adi_v5.h:493
int adiv5_verify_config(struct adiv5_private_config *pc)
Definition: arm_adi_v5.c:2472
static int dap_queue_dp_write(struct adiv5_dap *dap, unsigned reg, uint32_t data)
Queue a DP register write.
Definition: arm_adi_v5.h:573
int dap_info_command(struct command_invocation *cmd, struct adiv5_ap *ap)
Definition: arm_adi_v5.c:2221
#define AP_REG_IDR_CLASS_COM
Definition: arm_adi_v5.h:224
static int dap_queue_dp_read(struct adiv5_dap *dap, unsigned reg, uint32_t *data)
Queue a DP register read.
Definition: arm_adi_v5.h:555
int mem_ap_read_u32(struct adiv5_ap *ap, target_addr_t address, uint32_t *value)
Asynchronous (queued) read of a word from memory or a system register.
Definition: arm_adi_v5.c:237
int adiv5_mem_ap_spot_init(struct adiv5_mem_ap_spot *p)
Definition: arm_adi_v5.c:2489
#define ARM_ID
Definition: arm_adi_v5.h:28
int mem_ap_write_u32(struct adiv5_ap *ap, target_addr_t address, uint32_t value)
Asynchronous (queued) write of a word to memory or a system register.
Definition: arm_adi_v5.c:289
struct adiv5_dap * dap_instance_by_jim_obj(Jim_Interp *interp, Jim_Obj *o)
Definition: arm_dap.c:70
bool is_ap_num_valid(struct adiv5_dap *dap, uint64_t ap_num)
Definition: arm_adi_v5.c:1077
static int dap_queue_ap_abort(struct adiv5_dap *dap, uint8_t *ack)
Queue an AP abort operation.
Definition: arm_adi_v5.h:632
static int dap_send_sequence(struct adiv5_dap *dap, enum swd_special_seq seq)
Send an adi-v5 sequence to the DAP.
Definition: arm_adi_v5.h:536
int adiv6_dap_read_baseptr(struct command_invocation *cmd, struct adiv5_dap *dap, target_addr_t *baseptr)
Definition: arm_adi_v5.c:1265
adiv5_configure_dap_optional
Definition: arm_adi_v5.h:792
@ ADI_CONFIGURE_DAP_OPTIONAL
Definition: arm_adi_v5.h:794
@ ADI_CONFIGURE_DAP_COMPULSORY
Definition: arm_adi_v5.h:793
#define AP_REG_IDR_CLASS_MEM_AP
Definition: arm_adi_v5.h:225
static int dap_dp_read_atomic(struct adiv5_dap *dap, unsigned reg, uint32_t *value)
Definition: arm_adi_v5.h:662
const struct swd_driver * adiv5_dap_swd_driver(struct adiv5_dap *self)
Definition: arm_dap.c:60
int adiv5_jim_configure(struct target *target, struct jim_getopt_info *goi)
Definition: arm_adi_v5.c:2467
int dap_find_get_ap(struct adiv5_dap *dap, enum ap_type type_to_find, struct adiv5_ap **ap_out)
Definition: arm_adi_v5.c:1106
int mem_ap_write_buf_noincr(struct adiv5_ap *ap, const uint8_t *buffer, uint32_t size, uint32_t count, target_addr_t address)
Definition: arm_adi_v5.c:740
int dap_to_jtag(struct adiv5_dap *dap)
Put the debug link into JTAG mode, if the target supports it.
Definition: arm_adi_v5.c:969
int adiv5_jim_configure_ext(struct target *target, struct jim_getopt_info *goi, struct adiv5_private_config *pc, enum adiv5_configure_dap_optional optional)
Definition: arm_adi_v5.c:2427
int dap_register_commands(struct command_context *cmd_ctx)
Definition: arm_dap.c:539
int dap_dp_init_or_reconnect(struct adiv5_dap *dap)
Initialize a DAP or do reconnect if DAP is not accessible.
Definition: arm_adi_v5.c:856
int dap_lookup_cs_component(struct adiv5_ap *ap, uint8_t type, target_addr_t *addr, int32_t idx)
Definition: arm_adi_v5.c:2275
#define DP_APSEL_MAX
Definition: arm_adi_v5.h:109
int dap_dp_init(struct adiv5_dap *dap)
Initialize a DAP.
Definition: arm_adi_v5.c:779
static int dap_sync(struct adiv5_dap *dap)
Definition: arm_adi_v5.h:654
struct adiv5_dap * adiv5_get_dap(struct arm_dap_object *obj)
Definition: arm_dap.c:66
int mem_ap_read_atomic_u32(struct adiv5_ap *ap, target_addr_t address, uint32_t *value)
Synchronous read of a word from memory or a system register.
Definition: arm_adi_v5.c:266
int dap_to_swd(struct adiv5_dap *dap)
Put the debug link into SWD mode, if the target supports it.
Definition: arm_adi_v5.c:951
struct adiv5_ap * dap_get_ap(struct adiv5_dap *dap, uint64_t ap_num)
Definition: arm_adi_v5.c:1188
int dap_put_ap(struct adiv5_ap *ap)
Definition: arm_adi_v5.c:1208
#define MEM_AP_REG_CFG_LA
Definition: arm_adi_v5.h:207
int mem_ap_init(struct adiv5_ap *ap)
Initialize a DAP.
Definition: arm_adi_v5.c:887
int mem_ap_write_buf(struct adiv5_ap *ap, const uint8_t *buffer, uint32_t size, uint32_t count, target_addr_t address)
Definition: arm_adi_v5.c:728
swd_special_seq
Definition: arm_adi_v5.h:236
@ DORMANT_TO_JTAG
Definition: arm_adi_v5.h:243
@ JTAG_TO_SWD
Definition: arm_adi_v5.h:238
@ DORMANT_TO_SWD
Definition: arm_adi_v5.h:242
@ LINE_RESET
Definition: arm_adi_v5.h:237
@ JTAG_TO_DORMANT
Definition: arm_adi_v5.h:239
@ SWD_TO_DORMANT
Definition: arm_adi_v5.h:241
@ SWD_TO_JTAG
Definition: arm_adi_v5.h:240
static int dap_queue_ap_read(struct adiv5_ap *ap, unsigned reg, uint32_t *data)
Queue an AP register read.
Definition: arm_adi_v5.h:590
const char * adiv5_dap_name(struct adiv5_dap *self)
Definition: arm_dap.c:54
void dap_invalidate_cache(struct adiv5_dap *dap)
Invalidate cached DP select and cached TAR and CSW of all APs.
Definition: arm_adi_v5.c:756
const struct command_registration dap_instance_commands[]
Definition: arm_adi_v5.c:2891
static bool is_adiv6(const struct adiv5_dap *dap)
Check if DAP is ADIv6.
Definition: arm_adi_v5.h:523
#define AP_REG_IDR_VALUE(d, c, t)
Definition: arm_adi_v5.h:227
static int dap_dp_poll_register(struct adiv5_dap *dap, unsigned reg, uint32_t mask, uint32_t value, int timeout)
Definition: arm_adi_v5.h:674
static int dap_run(struct adiv5_dap *dap)
Perform all queued DAP operations, and clear any errors posted in the CTRL_STAT register when they ar...
Definition: arm_adi_v5.h:648
static bool dap_is_multidrop(struct adiv5_dap *dap)
Check if SWD multidrop configuration is valid.
Definition: arm_adi_v5.h:756
#define AP_REG_IDR_CLASS_NONE
Definition: arm_adi_v5.h:223
int adiv5_jim_mem_ap_spot_configure(struct adiv5_mem_ap_spot *cfg, struct jim_getopt_info *goi)
Definition: arm_adi_v5.c:2483
int mem_ap_write_atomic_u32(struct adiv5_ap *ap, target_addr_t address, uint32_t value)
Synchronous write of a word to memory or a system register.
Definition: arm_adi_v5.c:318
int mask
Definition: esirisc.c:1741
uint8_t type
Definition: esp_usb_jtag.c:0
void alive_sleep(uint64_t ms)
Definition: log.c:456
#define ERROR_WAIT
Definition: log.h:171
#define LOG_ERROR(expr ...)
Definition: log.h:132
#define LOG_DEBUG(expr ...)
Definition: log.h:109
#define ERROR_OK
Definition: log.h:164
target_addr_t addr
Start address to search for the control block.
Definition: rtt/rtt.c:28
size_t size
Size of the control block search area.
Definition: rtt/rtt.c:30
This represents an ARM Debug Interface (v5) Access Port (AP).
Definition: arm_adi_v5.h:250
uint32_t csw_size_supported_mask
Save the supported CSW.Size data types for the MEM-AP.
Definition: arm_adi_v5.h:286
bool unaligned_access_bad
Definition: arm_adi_v5.h:316
bool config_ap_never_release
Definition: arm_adi_v5.h:328
bool packed_transfers_probed
Definition: arm_adi_v5.h:313
bool tar_valid
Definition: arm_adi_v5.h:319
bool packed_transfers_supported
Definition: arm_adi_v5.h:312
uint32_t tar_autoincr_block
Definition: arm_adi_v5.h:309
unsigned int refcount
Definition: arm_adi_v5.h:325
uint32_t csw_size_probed_mask
Probed CSW.Size data types for the MEM-AP.
Definition: arm_adi_v5.h:293
uint64_t ap_num
ADIv5: Number of this AP (0~255) ADIv6: Base address of this AP (4k aligned) TODO: to be more coheren...
Definition: arm_adi_v5.h:261
struct adiv5_dap * dap
DAP this AP belongs to.
Definition: arm_adi_v5.h:254
uint32_t memaccess_tck
Configures how many extra tck clocks are added after starting a MEM-AP access before we try to read i...
Definition: arm_adi_v5.h:306
uint32_t cfg_reg
Definition: arm_adi_v5.h:322
uint32_t csw_default
Default value for (MEM-AP) AP_REG_CSW register.
Definition: arm_adi_v5.h:266
target_addr_t tar_value
Cache for (MEM-AP) AP_REG_TAR register value This is written to configure the address being read or w...
Definition: arm_adi_v5.h:300
uint32_t csw_value
Cache for (MEM-AP) AP_REG_CSW register value.
Definition: arm_adi_v5.h:273
This represents an ARM Debug Interface (v5) Debug Access Port (DAP).
Definition: arm_adi_v5.h:348
uint8_t ack
Definition: arm_adi_v5.h:386
bool ti_be_32_quirks
Definition: arm_adi_v5.h:398
unsigned int adi_version
Indicates ADI version (5, 6 or 0 for unknown) being used.
Definition: arm_adi_v5.h:433
struct list_head cmd_journal
Definition: arm_adi_v5.h:352
bool select_valid
Validity of DP SELECT cache.
Definition: arm_adi_v5.h:372
bool select1_valid
Definition: arm_adi_v5.h:373
struct adiv5_ap ap[DP_APSEL_MAX+1]
Definition: arm_adi_v5.h:364
size_t cmd_pool_size
Definition: arm_adi_v5.h:358
bool select_dpbanksel_valid
Partial DPBANKSEL validity for SWD only.
Definition: arm_adi_v5.h:383
bool stlink_flush_ap_write
STLINK adapter need to know if last AP operation was read or write, and in case of write has to flush...
Definition: arm_adi_v5.h:408
uint32_t dp_ctrl_stat
Definition: arm_adi_v5.h:362
bool multidrop_instance_id_valid
TINSTANCE field of multidrop_targetsel has been configured.
Definition: arm_adi_v5.h:425
bool do_reconnect
Signals that an attempt to reestablish communication afresh should be performed before the next acces...
Definition: arm_adi_v5.h:414
const struct dap_ops * ops
Definition: arm_adi_v5.h:349
uint32_t * last_read
Holds the pointer to the destination word for the last queued read, for use with posted AP read seque...
Definition: arm_adi_v5.h:392
uint64_t apsel
Definition: arm_adi_v5.h:367
struct jtag_tap * tap
Definition: arm_adi_v5.h:360
bool switch_through_dormant
Record if enter in SWD required passing through DORMANT.
Definition: arm_adi_v5.h:430
uint32_t multidrop_targetsel
Value to select DP in SWD multidrop mode or DP_TARGETSEL_INVALID.
Definition: arm_adi_v5.h:421
uint64_t select
Cache for DP SELECT and SELECT1 (ADIv6) register.
Definition: arm_adi_v5.h:370
bool multidrop_dp_id_valid
TPARTNO and TDESIGNER fields of multidrop_targetsel have been configured.
Definition: arm_adi_v5.h:423
struct list_head cmd_pool
Definition: arm_adi_v5.h:355
unsigned int asize
Definition: arm_adi_v5.h:436
bool ignore_syspwrupack
Flag saying whether to ignore the syspwrupack flag in DAP.
Definition: arm_adi_v5.h:418
bool nu_npcx_quirks
Definition: arm_adi_v5.h:402
struct adiv5_dap * dap
Definition: arm_adi_v5.h:803
struct adiv5_dap * dap
Definition: arm_adi_v5.h:787
When run_command is called, a new instance will be created on the stack, filled with the proper value...
Definition: command.h:76
Transport-neutral representation of queued DAP transactions, supporting both JTAG and SWD transports.
Definition: arm_adi_v5.h:446
int(* connect)(struct adiv5_dap *dap)
connect operation for SWD
Definition: arm_adi_v5.h:451
int(* queue_ap_abort)(struct adiv5_dap *dap, uint8_t *ack)
AP operation abort.
Definition: arm_adi_v5.h:471
int(* sync)(struct adiv5_dap *dap)
Executes all queued DAP operations but doesn't check sticky error conditions.
Definition: arm_adi_v5.h:478
void(* quit)(struct adiv5_dap *dap)
Optional; called at OpenOCD exit.
Definition: arm_adi_v5.h:481
int(* queue_dp_read)(struct adiv5_dap *dap, unsigned reg, uint32_t *data)
DP register read.
Definition: arm_adi_v5.h:457
int(* send_sequence)(struct adiv5_dap *dap, enum swd_special_seq seq)
send a sequence to the DAP
Definition: arm_adi_v5.h:454
int(* queue_dp_write)(struct adiv5_dap *dap, unsigned reg, uint32_t data)
DP register write.
Definition: arm_adi_v5.h:460
int(* run)(struct adiv5_dap *dap)
Executes all queued DAP operations.
Definition: arm_adi_v5.h:474
int(* queue_ap_write)(struct adiv5_ap *ap, unsigned reg, uint32_t data)
AP register write.
Definition: arm_adi_v5.h:467
int(* pre_connect_init)(struct adiv5_dap *dap)
Optional; called once on the first enabled dap before connecting.
Definition: arm_adi_v5.h:448
int(* queue_ap_read)(struct adiv5_ap *ap, unsigned reg, uint32_t *data)
AP register read.
Definition: arm_adi_v5.h:464
A TCL -ish GetOpt like code.
Definition: jim-nvp.h:135
Definition: jtag.h:101
Definition: list.h:40
Definition: register.h:111
Definition: target.h:116
Definition: psoc6.c:84
uint64_t target_addr_t
Definition: types.h:335
uint8_t cmd
Definition: vdebug.c:1
uint8_t count[4]
Definition: vdebug.c:22