Data Fields | |
| const char * | name |
| struct reg_cache * | next |
| unsigned | num_regs |
| struct reg * | reg_list |
Detailed Description
Definition at line 144 of file register.h.
Field Documentation
◆ name
| const char* reg_cache::name |
Definition at line 145 of file register.h.
Referenced by arc_build_bcr_reg_cache(), arc_build_reg_cache(), arm_build_reg_cache(), armv7m_build_reg_cache(), armv8_build_reg_cache(), avr32_build_reg_cache(), COMMAND_HANDLER(), cortex_m_dwt_setup(), dsp563xx_build_reg_cache(), embeddedice_build_reg_cache(), esirisc_build_reg_cache(), etb_build_reg_cache(), etm_build_reg_cache(), lakemont_build_reg_cache(), mips32_build_reg_cache(), mips64_build_reg_cache(), or1k_build_reg_cache(), riscv_init_registers(), stm8_build_reg_cache(), xscale_build_reg_cache(), and xtensa_build_reg_cache().
◆ next
| struct reg_cache* reg_cache::next |
Definition at line 146 of file register.h.
Referenced by aarch64_assert_reset(), aarch64_restore_context(), arc_build_bcr_reg_cache(), arc_build_reg_cache(), arc_get_gdb_reg_list(), arc_reg_get_by_name(), arm7_9_examine(), arm_build_reg_cache(), armv7m_build_reg_cache(), armv8_build_reg_cache(), armv8_get_gdb_reg_list(), avr32_build_reg_cache(), COMMAND_HANDLER(), dsp563xx_build_reg_cache(), embeddedice_build_reg_cache(), esirisc_build_reg_cache(), etb_build_reg_cache(), etm_build_reg_cache(), lakemont_build_reg_cache(), mips32_build_reg_cache(), or1k_build_reg_cache(), register_get_by_name(), register_get_by_number(), register_unlink_cache(), stm8_build_reg_cache(), xscale_build_reg_cache(), and xtensa_build_reg_cache().
◆ num_regs
| unsigned reg_cache::num_regs |
Definition at line 148 of file register.h.
Referenced by adapter_load_context(), arc_build_bcr_reg_cache(), arc_build_reg_cache(), arc_get_gdb_reg_list(), arc_reg_get_by_name(), arm_build_reg_cache(), arm_dpm_full_context(), arm_dpm_write_dirty_registers(), arm_free_reg_cache(), arm_full_context(), armv7m_build_reg_cache(), armv7m_free_reg_cache(), armv7m_get_gdb_reg_list(), armv7m_read_core_reg(), armv7m_restore_context(), armv7m_start_algorithm(), armv7m_wait_algorithm(), armv7m_write_core_reg(), armv8_build_reg_cache(), armv8_dpm_full_context(), armv8_dpm_read_core_reg(), armv8_dpm_write_core_reg(), armv8_dpm_write_dirty_registers(), armv8_free_cache(), armv8_get_gdb_reg_list(), avr32_build_reg_cache(), COMMAND_HANDLER(), cortex_m_dwt_free(), cortex_m_dwt_setup(), cortex_m_fast_read_all_regs(), cortex_m_slow_read_all_regs(), dsp563xx_build_reg_cache(), embeddedice_build_reg_cache(), embeddedice_free_reg_cache(), esirisc_build_reg_cache(), esirisc_restore_context(), esirisc_save_context(), etb_build_reg_cache(), etm_build_reg_cache(), etm_reg_add(), etm_reg_lookup(), get_num_user_regs(), lakemont_build_reg_cache(), mips32_build_reg_cache(), mips64_build_reg_cache(), mips64_invalidate_core_regs(), or1k_build_reg_cache(), read_all_core_hw_regs(), register_cache_invalidate(), register_get_by_name(), register_get_by_number(), restore_context(), riscv_free_registers(), riscv_get_gdb_reg_list_internal(), riscv_init_registers(), riscv_invalidate_register_cache(), stm8_build_reg_cache(), stm8_free_reg_cache(), write_all_core_hw_regs(), x86_32_get_gdb_reg_list(), xscale_debug_entry(), xtensa_build_reg_cache(), xtensa_fetch_all_regs(), xtensa_free_reg_cache(), xtensa_get_gdb_reg_list(), xtensa_start_algorithm(), xtensa_wait_algorithm(), and xtensa_write_dirty_registers().
◆ reg_list
| struct reg* reg_cache::reg_list |
Definition at line 147 of file register.h.
Referenced by access_register_command(), adapter_debug_entry(), adapter_load_context(), arc_build_bcr_reg_cache(), arc_build_reg_cache(), arc_free_reg_cache(), arc_get_gdb_reg_list(), arc_reg_get_by_name(), arc_restore_context(), arc_resume(), arc_save_context(), arc_step(), arm11_read_memory_inner(), arm11_write_memory_inner(), arm720t_soft_reset_halt(), arm7_9_assert_reset(), arm7_9_clear_halt(), arm7_9_clear_watchpoints(), arm7_9_dcc_completion(), arm7_9_debug_entry(), arm7_9_disable_eice_step(), arm7_9_enable_eice_step(), arm7_9_execute_fast_sys_speed(), arm7_9_execute_sys_speed(), arm7_9_halt(), arm7_9_handle_target_request(), arm7_9_poll(), arm7_9_resume(), arm7_9_set_breakpoint(), arm7_9_set_software_breakpoints(), arm7_9_set_watchpoint(), arm7_9_setup_semihosting(), arm7_9_soft_reset_halt(), arm7_9_unset_breakpoint(), arm7_9_unset_watchpoint(), arm7_9_write_memory(), arm7tdmi_branch_resume_thumb(), arm920t_read_cp15_interpreted(), arm920t_soft_reset_halt(), arm920t_write_cp15_interpreted(), arm926ejs_examine_debug_reason(), arm926ejs_soft_reset_halt(), arm9tdmi_branch_resume_thumb(), arm9tdmi_disable_single_step(), arm9tdmi_enable_single_step(), arm_build_reg_cache(), arm_dpm_full_context(), arm_dpm_read_current_registers(), arm_dpm_write_dirty_registers(), arm_free_reg_cache(), arm_full_context(), arm_get_gdb_reg_list(), arm_reg_current(), arm_semihosting(), arm_set_cpsr(), armv4_5_get_reg(), armv4_5_set_reg(), armv7m_arch_state(), armv7m_build_reg_cache(), armv7m_free_reg_cache(), armv7m_get_gdb_reg_list(), armv7m_read_core_reg(), armv7m_restore_context(), armv7m_start_algorithm(), armv7m_wait_algorithm(), armv7m_write_core_reg(), armv8_build_reg_cache(), armv8_dpm_full_context(), armv8_dpm_handle_exception(), armv8_dpm_read_current_registers(), armv8_dpm_write_dirty_registers(), armv8_free_cache(), armv8_get_core_reg32(), armv8_get_gdb_reg_list(), armv8_read_reg_simdfp_aarch32(), armv8_reg_current(), armv8_write_reg_simdfp_aarch32(), avr32_ap7k_restore_context(), avr32_ap7k_resume(), avr32_ap7k_save_context(), avr32_build_reg_cache(), avr32_read_core_reg(), avr32_write_core_reg(), calcaddr_physfromlin(), COMMAND_HANDLER(), cortex_m_debug_entry(), cortex_m_dwt_free(), cortex_m_dwt_setup(), cortex_m_examine(), cortex_m_fast_read_all_regs(), cortex_m_restore_one(), cortex_m_slow_read_all_regs(), dsp563xx_build_reg_cache(), dsp563xx_debug_init(), dsp563xx_get_gdb_reg_list(), dsp563xx_invalidate_x_context(), dsp563xx_read_core_reg(), dsp563xx_read_memory_core(), dsp563xx_read_register(), dsp563xx_reg_pc_read(), dsp563xx_reg_read_high_io(), dsp563xx_reg_ssh_read(), dsp563xx_reg_ssh_write(), dsp563xx_reg_ssl_read(), dsp563xx_reg_write_high_io(), dsp563xx_resume(), dsp563xx_step_ex(), dsp563xx_write_core_reg(), dsp563xx_write_memory_core(), dsp563xx_write_register(), embeddedice_build_reg_cache(), embeddedice_free_reg_cache(), embeddedice_setup(), esirisc_build_reg_cache(), esirisc_free_reg_cache(), esirisc_get_gdb_reg_list(), esirisc_restore_context(), esirisc_save_context(), etb_build_reg_cache(), etb_init(), etb_read_trace(), etb_start_capture(), etb_status(), etm_build_reg_cache(), etm_reg_add(), etm_reg_lookup(), execute_resume(), feroceon_branch_resume_thumb(), feroceon_bulk_write_memory(), feroceon_disable_single_step(), feroceon_enable_single_step(), feroceon_set_dbgrq(), get_register(), halt_prep(), lakemont_arch_state(), lakemont_build_reg_cache(), lakemont_poll(), lakemont_resume(), lakemont_step(), mips32_arch_state(), mips32_build_reg_cache(), mips32_cp0_set_reg_by_name(), mips32_cp0_set_reg_by_number(), mips32_get_gdb_reg_list(), mips32_read_core_reg(), mips32_restore_context(), mips32_run_algorithm(), mips32_run_and_wait(), mips32_save_context(), mips32_set_all_fpr_width(), mips32_write_core_reg(), mips64_arch_state(), mips64_build_reg_cache(), mips64_get_gdb_reg_list(), mips64_invalidate_core_regs(), mips64_read_core_reg(), mips64_restore_context(), mips64_write_core_reg(), mips_m4k_debug_entry(), mips_m4k_internal_restore(), mips_m4k_step(), mips_mips64_debug_entry(), mips_mips64_resume(), mips_mips64_step(), or1k_build_reg_cache(), or1k_debug_entry(), or1k_get_gdb_reg_list(), or1k_read_core_reg(), or1k_restore_context(), or1k_resume_or_step(), or1k_save_context(), or1k_write_core_reg(), post_result(), read_all_core_hw_regs(), read_hw_reg(), read_hw_reg_to_cache(), read_mem(), reg_cache_get(), reg_cache_set(), register_cache_invalidate(), register_get_by_name(), register_get_by_number(), register_read(), register_size(), register_write_direct(), restore_context(), riscv_free_registers(), riscv_get_gdb_reg_list_internal(), riscv_get_register(), riscv_init_registers(), riscv_invalidate_register_cache(), riscv_set_register(), set_debug_regs(), stm8_arch_state(), stm8_build_reg_cache(), stm8_debug_entry(), stm8_free_reg_cache(), stm8_get_gdb_reg_list(), stm8_read_core_reg(), stm8_restore_context(), stm8_resume(), stm8_run_algorithm(), stm8_run_and_wait(), stm8_save_context(), stm8_step(), stm8_write_core_reg(), unset_debug_regs(), update_mstatus_actual(), write_all_core_hw_regs(), write_hw_reg(), write_hw_reg_from_cache(), write_mem(), x86_32_common_read_io(), x86_32_common_virt2phys(), x86_32_common_write_io(), x86_32_get_gdb_reg_list(), xscale_assert_reset(), xscale_deassert_reset(), xscale_debug_entry(), xscale_disable_mmu_caches(), xscale_disable_single_step(), xscale_enable_mmu_caches(), xscale_enable_single_step(), xscale_free_reg_cache(), xscale_get_reg(), xscale_get_ttb(), xscale_read_dcsr(), xscale_read_memory(), xscale_read_tx(), xscale_resume(), xscale_send_u32(), xscale_set_breakpoint(), xscale_set_reg(), xscale_set_watchpoint(), xscale_step_inner(), xscale_unset_breakpoint(), xscale_unset_watchpoint(), xscale_write_dcsr(), xscale_write_dcsr_sw(), xscale_write_memory(), xscale_write_rx(), xtensa_build_reg_cache(), xtensa_cause_clear(), xtensa_do_step(), xtensa_fetch_all_regs(), xtensa_free_reg_cache(), xtensa_get_gdb_reg_list(), xtensa_imprecise_exception_clear(), xtensa_imprecise_exception_occurred(), xtensa_mark_register_dirty(), xtensa_reg_get(), xtensa_reg_set(), xtensa_start_algorithm(), xtensa_wait_algorithm(), and xtensa_write_dirty_registers().
The documentation for this struct was generated from the following file:
