OpenOCD
lakemont.c
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1 /*
2  * Copyright(c) 2013-2016 Intel Corporation.
3  *
4  * Adrian Burns (adrian.burns@intel.com)
5  * Thomas Faust (thomas.faust@intel.com)
6  * Ivan De Cesaris (ivan.de.cesaris@intel.com)
7  * Julien Carreno (julien.carreno@intel.com)
8  * Jeffrey Maxwell (jeffrey.r.maxwell@intel.com)
9  * Jessica Gomez (jessica.gomez.hernandez@intel.com)
10  *
11  * This program is free software; you can redistribute it and/or modify
12  * it under the terms of the GNU General Public License as published by
13  * the Free Software Foundation; either version 2 of the License, or
14  * (at your option) any later version.
15  *
16  * This program is distributed in the hope that it will be useful, but
17  * WITHOUT ANY WARRANTY; without even the implied warranty of
18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19  * General Public License for more details.
20  *
21  * You should have received a copy of the GNU General Public License
22  * along with this program. If not, see <http://www.gnu.org/licenses/>.
23  *
24  * Contact Information:
25  * Intel Corporation
26  */
27 
28 /*
29  * @file
30  * This implements the probemode operations for Lakemont 1 (LMT1).
31  */
32 
33 #ifdef HAVE_CONFIG_H
34 #include "config.h"
35 #endif
36 
37 #include <helper/log.h>
38 
39 #include "target.h"
40 #include "target_type.h"
41 #include "lakemont.h"
42 #include "register.h"
43 #include "breakpoints.h"
44 #include "x86_32_common.h"
45 
46 static int irscan(struct target *t, uint8_t *out,
47  uint8_t *in, uint8_t ir_len);
48 static int drscan(struct target *t, uint8_t *out, uint8_t *in, uint8_t len);
49 static int save_context(struct target *target);
50 static int restore_context(struct target *target);
51 static uint32_t get_tapstatus(struct target *t);
52 static int enter_probemode(struct target *t);
53 static int exit_probemode(struct target *t);
54 static int halt_prep(struct target *t);
55 static int do_halt(struct target *t);
56 static int do_resume(struct target *t);
57 static int read_all_core_hw_regs(struct target *t);
58 static int write_all_core_hw_regs(struct target *t);
59 static int read_hw_reg(struct target *t,
60  int reg, uint32_t *regval, uint8_t cache);
61 static int write_hw_reg(struct target *t,
62  int reg, uint32_t regval, uint8_t cache);
64  (struct target *target);
65 static int submit_reg_pir(struct target *t, int num);
66 static int submit_instruction_pir(struct target *t, int num);
67 static int submit_pir(struct target *t, uint64_t op);
68 static int lakemont_get_core_reg(struct reg *reg);
69 static int lakemont_set_core_reg(struct reg *reg, uint8_t *buf);
70 
71 static struct scan_blk scan;
72 
73 /* registers and opcodes for register access, pm_idx is used to identify the
74  * registers that are modified for lakemont probemode specific operations
75  */
76 static const struct {
77  uint8_t id;
78  const char *name;
79  uint64_t op;
80  uint8_t pm_idx;
81  unsigned bits;
82  enum reg_type type;
83  const char *group;
84  const char *feature;
85 } regs[] = {
86  /* general purpose registers */
87  { EAX, "eax", 0x000000D01D660000, 0, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.core" },
88  { ECX, "ecx", 0x000000501D660000, 1, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.core" },
89  { EDX, "edx", 0x000000901D660000, 2, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.core" },
90  { EBX, "ebx", 0x000000101D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.core" },
91  { ESP, "esp", 0x000000E01D660000, NOT_PMREG, 32, REG_TYPE_DATA_PTR, "general", "org.gnu.gdb.i386.core" },
92  { EBP, "ebp", 0x000000601D660000, NOT_PMREG, 32, REG_TYPE_DATA_PTR, "general", "org.gnu.gdb.i386.core" },
93  { ESI, "esi", 0x000000A01D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.core" },
94  { EDI, "edi", 0x000000201D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.core" },
95 
96  /* instruction pointer & flags */
97  { EIP, "eip", 0x000000C01D660000, 3, 32, REG_TYPE_CODE_PTR, "general", "org.gnu.gdb.i386.core" },
98  { EFLAGS, "eflags", 0x000000401D660000, 4, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.core" },
99 
100  /* segment registers */
101  { CS, "cs", 0x000000281D660000, 5, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.core" },
102  { SS, "ss", 0x000000C81D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.core" },
103  { DS, "ds", 0x000000481D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.core" },
104  { ES, "es", 0x000000A81D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.core" },
105  { FS, "fs", 0x000000881D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.core" },
106  { GS, "gs", 0x000000081D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.core" },
107 
108  /* floating point unit registers - not accessible via JTAG - here to satisfy GDB */
109  { ST0, "st0", 0x0, NOT_AVAIL_REG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.core" },
110  { ST1, "st1", 0x0, NOT_AVAIL_REG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.core" },
111  { ST2, "st2", 0x0, NOT_AVAIL_REG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.core" },
112  { ST3, "st3", 0x0, NOT_AVAIL_REG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.core" },
113  { ST4, "st4", 0x0, NOT_AVAIL_REG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.core" },
114  { ST5, "st5", 0x0, NOT_AVAIL_REG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.core" },
115  { ST6, "st6", 0x0, NOT_AVAIL_REG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.core" },
116  { ST7, "st7", 0x0, NOT_AVAIL_REG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.core" },
117  { FCTRL, "fctrl", 0x0, NOT_AVAIL_REG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.core" },
118  { FSTAT, "fstat", 0x0, NOT_AVAIL_REG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.core" },
119  { FTAG, "ftag", 0x0, NOT_AVAIL_REG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.core" },
120  { FISEG, "fiseg", 0x0, NOT_AVAIL_REG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.core" },
121  { FIOFF, "fioff", 0x0, NOT_AVAIL_REG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.core" },
122  { FOSEG, "foseg", 0x0, NOT_AVAIL_REG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.core" },
123  { FOOFF, "fooff", 0x0, NOT_AVAIL_REG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.core" },
124  { FOP, "fop", 0x0, NOT_AVAIL_REG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.core" },
125 
126  /* control registers */
127  { CR0, "cr0", 0x000000001D660000, 6, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" },
128  { CR2, "cr2", 0x000000BC1D660000, 7, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" },
129  { CR3, "cr3", 0x000000801D660000, 8, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" },
130  { CR4, "cr4", 0x0000002C1D660000, 9, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" },
131 
132  /* debug registers */
133  { DR0, "dr0", 0x0000007C1D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" },
134  { DR1, "dr1", 0x000000FC1D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" },
135  { DR2, "dr2", 0x000000021D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" },
136  { DR3, "dr3", 0x000000821D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" },
137  { DR6, "dr6", 0x000000301D660000, 10, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" },
138  { DR7, "dr7", 0x000000B01D660000, 11, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" },
139 
140  /* descriptor tables */
141  { IDTB, "idtbase", 0x000000581D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" },
142  { IDTL, "idtlimit", 0x000000D81D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" },
143  { IDTAR, "idtar", 0x000000981D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" },
144  { GDTB, "gdtbase", 0x000000B81D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" },
145  { GDTL, "gdtlimit", 0x000000781D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" },
146  { GDTAR, "gdtar", 0x000000381D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" },
147  { TR, "tr", 0x000000701D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" },
148  { LDTR, "ldtr", 0x000000F01D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" },
149  { LDTB, "ldbase", 0x000000041D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" },
150  { LDTL, "ldlimit", 0x000000841D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" },
151  { LDTAR, "ldtar", 0x000000F81D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" },
152 
153  /* segment registers */
154  { CSB, "csbase", 0x000000F41D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" },
155  { CSL, "cslimit", 0x0000000C1D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" },
156  { CSAR, "csar", 0x000000741D660000, 12, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" },
157  { DSB, "dsbase", 0x000000941D660000, 13, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" },
158  { DSL, "dslimit", 0x000000541D660000, 14, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" },
159  { DSAR, "dsar", 0x000000141D660000, 15, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" },
160  { ESB, "esbase", 0x0000004C1D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" },
161  { ESL, "eslimit", 0x000000CC1D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" },
162  { ESAR, "esar", 0x0000008C1D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" },
163  { FSB, "fsbase", 0x000000641D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" },
164  { FSL, "fslimit", 0x000000E41D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" },
165  { FSAR, "fsar", 0x000000A41D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" },
166  { GSB, "gsbase", 0x000000C41D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" },
167  { GSL, "gslimit", 0x000000241D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" },
168  { GSAR, "gsar", 0x000000441D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" },
169  { SSB, "ssbase", 0x000000341D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" },
170  { SSL, "sslimit", 0x000000B41D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" },
171  { SSAR, "ssar", 0x000000D41D660000, 16, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" },
172  { TSSB, "tssbase", 0x000000E81D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" },
173  { TSSL, "tsslimit", 0x000000181D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" },
174  { TSSAR, "tssar", 0x000000681D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" },
175  /* probemode control register */
176  { PMCR, "pmcr", 0x000000421D660000, 17, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" },
177 };
178 
179 static const struct {
180  uint8_t id;
181  const char *name;
182  uint64_t op;
183 } instructions[] = {
184  /* memory read/write */
185  { MEMRDB32, "MEMRDB32", 0x0909090909090851 },
186  { MEMRDB16, "MEMRDB16", 0x09090909090851E6 },
187  { MEMRDH32, "MEMRDH32", 0x090909090908D166 },
188  { MEMRDH16, "MEMRDH16", 0x090909090908D1E6 },
189  { MEMRDW32, "MEMRDW32", 0x09090909090908D1 },
190  { MEMRDW16, "MEMRDW16", 0x0909090908D1E666 },
191  { MEMWRB32, "MEMWRB32", 0x0909090909090811 },
192  { MEMWRB16, "MEMWRB16", 0x09090909090811E6 },
193  { MEMWRH32, "MEMWRH32", 0x0909090909089166 },
194  { MEMWRH16, "MEMWRH16", 0x09090909090891E6 },
195  { MEMWRW32, "MEMWRW32", 0x0909090909090891 },
196  { MEMWRW16, "MEMWRW16", 0x090909090891E666 },
197  /* IO read/write */
198  { IORDB32, "IORDB32", 0x0909090909090937 },
199  { IORDB16, "IORDB16", 0x09090909090937E6 },
200  { IORDH32, "IORDH32", 0x090909090909B766 },
201  { IORDH16, "IORDH16", 0x090909090909B7E6 },
202  { IORDW32, "IORDW32", 0x09090909090909B7 },
203  { IORDW16, "IORDW16", 0x0909090909B7E666 },
204  { IOWRB32, "IOWRB32", 0x0909090909090977 },
205  { IOWRB16, "IOWRB16", 0x09090909090977E6 },
206  { IOWRH32, "IOWRH32", 0x090909090909F766 },
207  { IOWRH16, "IOWRH16", 0x090909090909F7E6 },
208  { IOWRW32, "IOWRW32", 0x09090909090909F7 },
209  { IOWRW16, "IOWRW16", 0x0909090909F7E666 },
210  /* lakemont1 core shadow ram access opcodes */
211  { SRAMACCESS, "SRAMACCESS", 0x0000000E9D660000 },
212  { SRAM2PDR, "SRAM2PDR", 0x4CF0000000000000 },
213  { PDR2SRAM, "PDR2SRAM", 0x0CF0000000000000 },
214  { WBINVD, "WBINVD", 0x09090909090990F0 },
215 };
216 
217 bool check_not_halted(const struct target *t)
218 {
219  bool halted = t->state == TARGET_HALTED;
220  if (!halted)
221  LOG_ERROR("target running, halt it first");
222  return !halted;
223 }
224 
225 static int irscan(struct target *t, uint8_t *out,
226  uint8_t *in, uint8_t ir_len)
227 {
228  int retval = ERROR_OK;
229  struct x86_32_common *x86_32 = target_to_x86_32(t);
230  if (NULL == t->tap) {
231  retval = ERROR_FAIL;
232  LOG_ERROR("%s invalid target tap", __func__);
233  return retval;
234  }
235  if (ir_len != t->tap->ir_length) {
236  retval = ERROR_FAIL;
237  if (t->tap->enabled)
238  LOG_ERROR("%s tap enabled but tap irlen=%d",
239  __func__, t->tap->ir_length);
240  else
241  LOG_ERROR("%s tap not enabled and irlen=%d",
242  __func__, t->tap->ir_length);
243  return retval;
244  }
245  struct scan_field *fields = &scan.field;
246  fields->num_bits = ir_len;
247  fields->out_value = out;
248  fields->in_value = in;
249  jtag_add_ir_scan(x86_32->curr_tap, fields, TAP_IDLE);
250  if (x86_32->flush) {
251  retval = jtag_execute_queue();
252  if (retval != ERROR_OK)
253  LOG_ERROR("%s failed to execute queue", __func__);
254  }
255  return retval;
256 }
257 
258 static int drscan(struct target *t, uint8_t *out, uint8_t *in, uint8_t len)
259 {
260  int retval = ERROR_OK;
261  uint64_t data = 0;
262  struct x86_32_common *x86_32 = target_to_x86_32(t);
263  if (NULL == t->tap) {
264  retval = ERROR_FAIL;
265  LOG_ERROR("%s invalid target tap", __func__);
266  return retval;
267  }
268  if (len > MAX_SCAN_SIZE || 0 == len) {
269  retval = ERROR_FAIL;
270  LOG_ERROR("%s data len is %d bits, max is %d bits",
271  __func__, len, MAX_SCAN_SIZE);
272  return retval;
273  }
274  struct scan_field *fields = &scan.field;
275  fields->out_value = out;
276  fields->in_value = in;
277  fields->num_bits = len;
278  jtag_add_dr_scan(x86_32->curr_tap, 1, fields, TAP_IDLE);
279  if (x86_32->flush) {
280  retval = jtag_execute_queue();
281  if (retval != ERROR_OK) {
282  LOG_ERROR("%s drscan failed to execute queue", __func__);
283  return retval;
284  }
285  }
286  if (in != NULL) {
287  if (len >= 8) {
288  for (int n = (len / 8) - 1 ; n >= 0; n--)
289  data = (data << 8) + *(in+n);
290  } else
291  LOG_DEBUG("dr in 0x%02" PRIx8, *in);
292  } else {
293  LOG_ERROR("%s no drscan data", __func__);
294  retval = ERROR_FAIL;
295  }
296  return retval;
297 }
298 
299 static int save_context(struct target *t)
300 {
301  int err;
302  /* read core registers from lakemont sram */
303  err = read_all_core_hw_regs(t);
304  if (err != ERROR_OK) {
305  LOG_ERROR("%s error reading regs", __func__);
306  return err;
307  }
308  return ERROR_OK;
309 }
310 
311 static int restore_context(struct target *t)
312 {
313  int err = ERROR_OK;
314  uint32_t i;
315  struct x86_32_common *x86_32 = target_to_x86_32(t);
316 
317  /* write core regs into the core PM SRAM from the reg_cache */
318  err = write_all_core_hw_regs(t);
319  if (err != ERROR_OK) {
320  LOG_ERROR("%s error writing regs", __func__);
321  return err;
322  }
323 
324  for (i = 0; i < (x86_32->cache->num_regs); i++) {
325  x86_32->cache->reg_list[i].dirty = 0;
326  x86_32->cache->reg_list[i].valid = 0;
327  }
328  return err;
329 }
330 
331 /*
332  * we keep reg_cache in sync with hardware at halt/resume time, we avoid
333  * writing to real hardware here bacause pm_regs reflects the hardware
334  * while we are halted then reg_cache syncs with hw on resume
335  * TODO - in order for "reg eip force" to work it assume get/set reads
336  * and writes from hardware, may be other reasons also because generally
337  * other openocd targets read/write from hardware in get/set - watch this!
338  */
339 static int lakemont_get_core_reg(struct reg *reg)
340 {
341  int retval = ERROR_OK;
342  struct lakemont_core_reg *lakemont_reg = reg->arch_info;
343  struct target *t = lakemont_reg->target;
344  if (check_not_halted(t))
346  LOG_DEBUG("reg=%s, value=0x%08" PRIx32, reg->name,
347  buf_get_u32(reg->value, 0, 32));
348  return retval;
349 }
350 
351 static int lakemont_set_core_reg(struct reg *reg, uint8_t *buf)
352 {
353  struct lakemont_core_reg *lakemont_reg = reg->arch_info;
354  struct target *t = lakemont_reg->target;
355  uint32_t value = buf_get_u32(buf, 0, 32);
356  LOG_DEBUG("reg=%s, newval=0x%08" PRIx32, reg->name, value);
357  if (check_not_halted(t))
359  buf_set_u32(reg->value, 0, 32, value);
360  reg->dirty = 1;
361  reg->valid = 1;
362  return ERROR_OK;
363 }
364 
365 static const struct reg_arch_type lakemont_reg_type = {
366  /* these get called if reg_cache doesnt have a "valid" value
367  * of an individual reg eg "reg eip" but not for "reg" block
368  */
370  .set = lakemont_set_core_reg,
371 };
372 
374 {
375  struct x86_32_common *x86_32 = target_to_x86_32(t);
376  int num_regs = ARRAY_SIZE(regs);
377  struct reg_cache **cache_p = register_get_last_cache_p(&t->reg_cache);
378  struct reg_cache *cache = malloc(sizeof(struct reg_cache));
379  struct reg *reg_list = calloc(num_regs, sizeof(struct reg));
380  struct lakemont_core_reg *arch_info = malloc(sizeof(struct lakemont_core_reg) * num_regs);
381  struct reg_feature *feature;
382  int i;
383 
384  if (cache == NULL || reg_list == NULL || arch_info == NULL) {
385  free(cache);
386  free(reg_list);
387  free(arch_info);
388  LOG_ERROR("%s out of memory", __func__);
389  return NULL;
390  }
391 
392  /* Build the process context cache */
393  cache->name = "lakemont registers";
394  cache->next = NULL;
395  cache->reg_list = reg_list;
396  cache->num_regs = num_regs;
397  (*cache_p) = cache;
398  x86_32->cache = cache;
399 
400  for (i = 0; i < num_regs; i++) {
401  arch_info[i].target = t;
402  arch_info[i].x86_32_common = x86_32;
403  arch_info[i].op = regs[i].op;
404  arch_info[i].pm_idx = regs[i].pm_idx;
405  reg_list[i].name = regs[i].name;
406  reg_list[i].size = 32;
407  reg_list[i].value = calloc(1, 4);
408  reg_list[i].dirty = 0;
409  reg_list[i].valid = 0;
410  reg_list[i].type = &lakemont_reg_type;
411  reg_list[i].arch_info = &arch_info[i];
412 
413  reg_list[i].group = regs[i].group;
414  reg_list[i].number = i;
415  reg_list[i].exist = true;
416  reg_list[i].caller_save = true; /* gdb defaults to true */
417 
418  feature = calloc(1, sizeof(struct reg_feature));
419  if (feature) {
420  feature->name = regs[i].feature;
421  reg_list[i].feature = feature;
422  } else
423  LOG_ERROR("%s unable to allocate feature list", __func__);
424 
425  reg_list[i].reg_data_type = calloc(1, sizeof(struct reg_data_type));
426  if (reg_list[i].reg_data_type)
427  reg_list[i].reg_data_type->type = regs[i].type;
428  else
429  LOG_ERROR("%s unable to allocate reg type list", __func__);
430  }
431  return cache;
432 }
433 
434 static uint32_t get_tapstatus(struct target *t)
435 {
436  scan.out[0] = TAPSTATUS;
437  if (irscan(t, scan.out, NULL, LMT_IRLEN) != ERROR_OK)
438  return 0;
439  if (drscan(t, NULL, scan.out, TS_SIZE) != ERROR_OK)
440  return 0;
441  return buf_get_u32(scan.out, 0, 32);
442 }
443 
444 static int enter_probemode(struct target *t)
445 {
446  uint32_t tapstatus = 0;
447  tapstatus = get_tapstatus(t);
448  LOG_DEBUG("TS before PM enter = 0x%08" PRIx32, tapstatus);
449  if (tapstatus & TS_PM_BIT) {
450  LOG_DEBUG("core already in probemode");
451  return ERROR_OK;
452  }
453  scan.out[0] = PROBEMODE;
454  if (irscan(t, scan.out, NULL, LMT_IRLEN) != ERROR_OK)
455  return ERROR_FAIL;
456  scan.out[0] = 1;
457  if (drscan(t, scan.out, scan.in, 1) != ERROR_OK)
458  return ERROR_FAIL;
459  tapstatus = get_tapstatus(t);
460  LOG_DEBUG("TS after PM enter = 0x%08" PRIx32, tapstatus);
461  if ((tapstatus & TS_PM_BIT) && (!(tapstatus & TS_EN_PM_BIT)))
462  return ERROR_OK;
463  else {
464  LOG_ERROR("%s PM enter error, tapstatus = 0x%08" PRIx32
465  , __func__, tapstatus);
466  return ERROR_FAIL;
467  }
468 }
469 
470 static int exit_probemode(struct target *t)
471 {
472  uint32_t tapstatus = get_tapstatus(t);
473  LOG_DEBUG("TS before PM exit = 0x%08" PRIx32, tapstatus);
474 
475  if (!(tapstatus & TS_PM_BIT)) {
476  LOG_USER("core not in PM");
477  return ERROR_OK;
478  }
479  scan.out[0] = PROBEMODE;
480  if (irscan(t, scan.out, NULL, LMT_IRLEN) != ERROR_OK)
481  return ERROR_FAIL;
482  scan.out[0] = 0;
483  if (drscan(t, scan.out, scan.in, 1) != ERROR_OK)
484  return ERROR_FAIL;
485  return ERROR_OK;
486 }
487 
488 /* do whats needed to properly enter probemode for debug on lakemont */
489 static int halt_prep(struct target *t)
490 {
491  struct x86_32_common *x86_32 = target_to_x86_32(t);
492  if (write_hw_reg(t, DSB, PM_DSB, 0) != ERROR_OK)
493  return ERROR_FAIL;
494  LOG_DEBUG("write %s 0x%08" PRIx32, regs[DSB].name, PM_DSB);
495  if (write_hw_reg(t, DSL, PM_DSL, 0) != ERROR_OK)
496  return ERROR_FAIL;
497  LOG_DEBUG("write %s 0x%08" PRIx32, regs[DSL].name, PM_DSL);
498  if (write_hw_reg(t, DSAR, PM_DSAR, 0) != ERROR_OK)
499  return ERROR_FAIL;
500  LOG_DEBUG("write DSAR 0x%08" PRIx32, PM_DSAR);
501  if (write_hw_reg(t, CSB, PM_DSB, 0) != ERROR_OK)
502  return ERROR_FAIL;
503  LOG_DEBUG("write %s 0x%08" PRIx32, regs[CSB].name, PM_DSB);
504  if (write_hw_reg(t, CSL, PM_DSL, 0) != ERROR_OK)
505  return ERROR_FAIL;
506  LOG_DEBUG("write %s 0x%08" PRIx32, regs[CSL].name, PM_DSL);
507  if (write_hw_reg(t, DR7, PM_DR7, 0) != ERROR_OK)
508  return ERROR_FAIL;
509  LOG_DEBUG("write DR7 0x%08" PRIx32, PM_DR7);
510 
511  uint32_t eflags = buf_get_u32(x86_32->cache->reg_list[EFLAGS].value, 0, 32);
512  uint32_t csar = buf_get_u32(x86_32->cache->reg_list[CSAR].value, 0, 32);
513  uint32_t ssar = buf_get_u32(x86_32->cache->reg_list[SSAR].value, 0, 32);
514  uint32_t cr0 = buf_get_u32(x86_32->cache->reg_list[CR0].value, 0, 32);
515 
516  /* clear VM86 and IF bits if they are set */
517  LOG_DEBUG("EFLAGS = 0x%08" PRIx32 ", VM86 = %d, IF = %d", eflags,
518  eflags & EFLAGS_VM86 ? 1 : 0,
519  eflags & EFLAGS_IF ? 1 : 0);
520  if ((eflags & EFLAGS_VM86) || (eflags & EFLAGS_IF)) {
521  x86_32->pm_regs[I(EFLAGS)] = eflags & ~(EFLAGS_VM86 | EFLAGS_IF);
522  if (write_hw_reg(t, EFLAGS, x86_32->pm_regs[I(EFLAGS)], 0) != ERROR_OK)
523  return ERROR_FAIL;
524  LOG_DEBUG("EFLAGS now = 0x%08" PRIx32 ", VM86 = %d, IF = %d",
525  x86_32->pm_regs[I(EFLAGS)],
526  x86_32->pm_regs[I(EFLAGS)] & EFLAGS_VM86 ? 1 : 0,
527  x86_32->pm_regs[I(EFLAGS)] & EFLAGS_IF ? 1 : 0);
528  }
529 
530  /* set CPL to 0 for memory access */
531  if (csar & CSAR_DPL) {
532  x86_32->pm_regs[I(CSAR)] = csar & ~CSAR_DPL;
533  if (write_hw_reg(t, CSAR, x86_32->pm_regs[I(CSAR)], 0) != ERROR_OK)
534  return ERROR_FAIL;
535  LOG_DEBUG("write CSAR_CPL to 0 0x%08" PRIx32, x86_32->pm_regs[I(CSAR)]);
536  }
537  if (ssar & SSAR_DPL) {
538  x86_32->pm_regs[I(SSAR)] = ssar & ~SSAR_DPL;
539  if (write_hw_reg(t, SSAR, x86_32->pm_regs[I(SSAR)], 0) != ERROR_OK)
540  return ERROR_FAIL;
541  LOG_DEBUG("write SSAR_CPL to 0 0x%08" PRIx32, x86_32->pm_regs[I(SSAR)]);
542  }
543 
544  /* if cache's are enabled, disable and flush, depending on the core version */
545  if (!(x86_32->core_type == LMT3_5) && !(cr0 & CR0_CD)) {
546  LOG_DEBUG("caching enabled CR0 = 0x%08" PRIx32, cr0);
547  if (cr0 & CR0_PG) {
548  x86_32->pm_regs[I(CR0)] = cr0 & ~CR0_PG;
549  if (write_hw_reg(t, CR0, x86_32->pm_regs[I(CR0)], 0) != ERROR_OK)
550  return ERROR_FAIL;
551  LOG_DEBUG("cleared paging CR0_PG = 0x%08" PRIx32, x86_32->pm_regs[I(CR0)]);
552  /* submit wbinvd to flush cache */
553  if (submit_reg_pir(t, WBINVD) != ERROR_OK)
554  return ERROR_FAIL;
555  x86_32->pm_regs[I(CR0)] =
556  x86_32->pm_regs[I(CR0)] | (CR0_CD | CR0_NW | CR0_PG);
557  if (write_hw_reg(t, CR0, x86_32->pm_regs[I(CR0)], 0) != ERROR_OK)
558  return ERROR_FAIL;
559  LOG_DEBUG("set CD, NW and PG, CR0 = 0x%08" PRIx32, x86_32->pm_regs[I(CR0)]);
560  }
561  }
562  return ERROR_OK;
563 }
564 
565 static int do_halt(struct target *t)
566 {
567  /* needs proper handling later if doing a halt errors out */
569  if (enter_probemode(t) != ERROR_OK)
570  return ERROR_FAIL;
571 
573 }
574 
575 /* we need to expose the update to be able to complete the reset at SoC level */
577 {
578  if (save_context(t) != ERROR_OK)
579  return ERROR_FAIL;
580  if (halt_prep(t) != ERROR_OK)
581  return ERROR_FAIL;
582  t->state = TARGET_HALTED;
583 
585 }
586 
587 static int do_resume(struct target *t)
588 {
589  /* needs proper handling later */
591  if (restore_context(t) != ERROR_OK)
592  return ERROR_FAIL;
593  if (exit_probemode(t) != ERROR_OK)
594  return ERROR_FAIL;
595  t->state = TARGET_RUNNING;
596 
598  LOG_USER("target running");
599 
601 }
602 
603 static int read_all_core_hw_regs(struct target *t)
604 {
605  int err;
606  uint32_t regval;
607  unsigned i;
608  struct x86_32_common *x86_32 = target_to_x86_32(t);
609  for (i = 0; i < (x86_32->cache->num_regs); i++) {
610  if (NOT_AVAIL_REG == regs[i].pm_idx)
611  continue;
612  err = read_hw_reg(t, regs[i].id, &regval, 1);
613  if (err != ERROR_OK) {
614  LOG_ERROR("%s error saving reg %s",
615  __func__, x86_32->cache->reg_list[i].name);
616  return err;
617  }
618  }
619  LOG_DEBUG("read_all_core_hw_regs read %u registers ok", i);
620  return ERROR_OK;
621 }
622 
623 static int write_all_core_hw_regs(struct target *t)
624 {
625  int err;
626  unsigned i;
627  struct x86_32_common *x86_32 = target_to_x86_32(t);
628  for (i = 0; i < (x86_32->cache->num_regs); i++) {
629  if (NOT_AVAIL_REG == regs[i].pm_idx)
630  continue;
631  err = write_hw_reg(t, i, 0, 1);
632  if (err != ERROR_OK) {
633  LOG_ERROR("%s error restoring reg %s",
634  __func__, x86_32->cache->reg_list[i].name);
635  return err;
636  }
637  }
638  LOG_DEBUG("write_all_core_hw_regs wrote %u registers ok", i);
639  return ERROR_OK;
640 }
641 
642 /* read reg from lakemont core shadow ram, update reg cache if needed */
643 static int read_hw_reg(struct target *t, int reg, uint32_t *regval, uint8_t cache)
644 {
645  struct x86_32_common *x86_32 = target_to_x86_32(t);
646  struct lakemont_core_reg *arch_info;
647  arch_info = x86_32->cache->reg_list[reg].arch_info;
648  x86_32->flush = 0; /* dont flush scans till we have a batch */
649  if (submit_reg_pir(t, reg) != ERROR_OK)
650  return ERROR_FAIL;
652  return ERROR_FAIL;
654  return ERROR_FAIL;
655  x86_32->flush = 1;
656  scan.out[0] = RDWRPDR;
657  if (irscan(t, scan.out, NULL, LMT_IRLEN) != ERROR_OK)
658  return ERROR_FAIL;
659  if (drscan(t, NULL, scan.out, PDR_SIZE) != ERROR_OK)
660  return ERROR_FAIL;
661 
663  *regval = buf_get_u32(scan.out, 0, 32);
664  if (cache) {
665  buf_set_u32(x86_32->cache->reg_list[reg].value, 0, 32, *regval);
666  x86_32->cache->reg_list[reg].valid = 1;
667  x86_32->cache->reg_list[reg].dirty = 0;
668  }
669  LOG_DEBUG("reg=%s, op=0x%016" PRIx64 ", val=0x%08" PRIx32,
670  x86_32->cache->reg_list[reg].name,
671  arch_info->op,
672  *regval);
673  return ERROR_OK;
674 }
675 
676 /* write lakemont core shadow ram reg, update reg cache if needed */
677 static int write_hw_reg(struct target *t, int reg, uint32_t regval, uint8_t cache)
678 {
679  struct x86_32_common *x86_32 = target_to_x86_32(t);
680  struct lakemont_core_reg *arch_info;
681  arch_info = x86_32->cache->reg_list[reg].arch_info;
682 
683  uint8_t reg_buf[4];
684  if (cache)
685  regval = buf_get_u32(x86_32->cache->reg_list[reg].value, 0, 32);
686  buf_set_u32(reg_buf, 0, 32, regval);
687  LOG_DEBUG("reg=%s, op=0x%016" PRIx64 ", val=0x%08" PRIx32,
688  x86_32->cache->reg_list[reg].name,
689  arch_info->op,
690  regval);
691 
692  x86_32->flush = 0; /* dont flush scans till we have a batch */
693  if (submit_reg_pir(t, reg) != ERROR_OK)
694  return ERROR_FAIL;
696  return ERROR_FAIL;
697  scan.out[0] = RDWRPDR;
698  if (irscan(t, scan.out, NULL, LMT_IRLEN) != ERROR_OK)
699  return ERROR_FAIL;
700  if (drscan(t, reg_buf, scan.out, PDR_SIZE) != ERROR_OK)
701  return ERROR_FAIL;
702  x86_32->flush = 1;
704  return ERROR_FAIL;
705 
706  /* we are writing from the cache so ensure we reset flags */
707  if (cache) {
708  x86_32->cache->reg_list[reg].dirty = 0;
709  x86_32->cache->reg_list[reg].valid = 0;
710  }
711  return ERROR_OK;
712 }
713 
714 static bool is_paging_enabled(struct target *t)
715 {
716  struct x86_32_common *x86_32 = target_to_x86_32(t);
717  if (x86_32->pm_regs[I(CR0)] & CR0_PG)
718  return true;
719  else
720  return false;
721 }
722 
723 static uint8_t get_num_user_regs(struct target *t)
724 {
725  struct x86_32_common *x86_32 = target_to_x86_32(t);
726  return x86_32->cache->num_regs;
727 }
728 /* value of the CR0.PG (paging enabled) bit influences memory reads/writes */
729 static int disable_paging(struct target *t)
730 {
731  struct x86_32_common *x86_32 = target_to_x86_32(t);
732  x86_32->pm_regs[I(CR0)] = x86_32->pm_regs[I(CR0)] & ~CR0_PG;
733  int err = x86_32->write_hw_reg(t, CR0, x86_32->pm_regs[I(CR0)], 0);
734  if (err != ERROR_OK) {
735  LOG_ERROR("%s error disabling paging", __func__);
736  return err;
737  }
738  return err;
739 }
740 
741 static int enable_paging(struct target *t)
742 {
743  struct x86_32_common *x86_32 = target_to_x86_32(t);
744  x86_32->pm_regs[I(CR0)] = (x86_32->pm_regs[I(CR0)] | CR0_PG);
745  int err = x86_32->write_hw_reg(t, CR0, x86_32->pm_regs[I(CR0)], 0);
746  if (err != ERROR_OK) {
747  LOG_ERROR("%s error enabling paging", __func__);
748  return err;
749  }
750  return err;
751 }
752 
753 static bool sw_bpts_supported(struct target *t)
754 {
755  uint32_t tapstatus = get_tapstatus(t);
756  if (tapstatus & TS_SBP_BIT)
757  return true;
758  else
759  return false;
760 }
761 
762 static int transaction_status(struct target *t)
763 {
764  uint32_t tapstatus = get_tapstatus(t);
765  if ((TS_EN_PM_BIT | TS_PRDY_BIT) & tapstatus) {
766  LOG_ERROR("%s transaction error tapstatus = 0x%08" PRIx32
767  , __func__, tapstatus);
768  return ERROR_FAIL;
769  } else {
770  return ERROR_OK;
771  }
772 }
773 
774 static int submit_instruction(struct target *t, int num)
775 {
776  int err = submit_instruction_pir(t, num);
777  if (err != ERROR_OK) {
778  LOG_ERROR("%s error submitting pir", __func__);
779  return err;
780  }
781  return err;
782 }
783 
784 static int submit_reg_pir(struct target *t, int num)
785 {
786  LOG_DEBUG("reg %s op=0x%016" PRIx64, regs[num].name, regs[num].op);
787  int err = submit_pir(t, regs[num].op);
788  if (err != ERROR_OK) {
789  LOG_ERROR("%s error submitting pir", __func__);
790  return err;
791  }
792  return err;
793 }
794 
795 static int submit_instruction_pir(struct target *t, int num)
796 {
797  LOG_DEBUG("%s op=0x%016" PRIx64, instructions[num].name,
798  instructions[num].op);
799  int err = submit_pir(t, instructions[num].op);
800  if (err != ERROR_OK) {
801  LOG_ERROR("%s error submitting pir", __func__);
802  return err;
803  }
804  return err;
805 }
806 
807 /*
808  * PIR (Probe Mode Instruction Register), SUBMITPIR is an "IR only" TAP
809  * command; there is no corresponding data register
810  */
811 static int submit_pir(struct target *t, uint64_t op)
812 {
813  struct x86_32_common *x86_32 = target_to_x86_32(t);
814 
815  uint8_t op_buf[8];
816  buf_set_u64(op_buf, 0, 64, op);
817  int flush = x86_32->flush;
818  x86_32->flush = 0;
819  scan.out[0] = WRPIR;
820  if (irscan(t, scan.out, NULL, LMT_IRLEN) != ERROR_OK)
821  return ERROR_FAIL;
822  if (drscan(t, op_buf, scan.out, PIR_SIZE) != ERROR_OK)
823  return ERROR_FAIL;
824  scan.out[0] = SUBMITPIR;
825  x86_32->flush = flush;
826  if (irscan(t, scan.out, NULL, LMT_IRLEN) != ERROR_OK)
827  return ERROR_FAIL;
829  return ERROR_OK;
830 }
831 
832 int lakemont_init_target(struct command_context *cmd_ctx, struct target *t)
833 {
835  t->state = TARGET_RUNNING;
837  return ERROR_OK;
838 }
839 
840 int lakemont_init_arch_info(struct target *t, struct x86_32_common *x86_32)
841 {
844  x86_32->read_hw_reg = read_hw_reg;
845  x86_32->write_hw_reg = write_hw_reg;
849  x86_32->disable_paging = disable_paging;
850  x86_32->enable_paging = enable_paging;
851  return ERROR_OK;
852 }
853 
854 int lakemont_poll(struct target *t)
855 {
856  /* LMT1 PMCR register currently allows code breakpoints, data breakpoints,
857  * single stepping and shutdowns to be redirected to PM but does not allow
858  * redirecting into PM as a result of SMM enter and SMM exit
859  */
860  uint32_t ts = get_tapstatus(t);
861 
862  if (ts == 0xFFFFFFFF && t->state != TARGET_DEBUG_RUNNING) {
863  /* something is wrong here */
864  LOG_ERROR("tapstatus invalid - scan_chain serialization or locked JTAG access issues");
865  /* TODO: Give a hint that unlocking is wrong or maybe a
866  * 'jtag arp_init' helps
867  */
869  return ERROR_OK;
870  }
871 
872  if (t->state == TARGET_HALTED && (!(ts & TS_PM_BIT))) {
873  LOG_INFO("target running for unknown reason");
874  t->state = TARGET_RUNNING;
875  }
876 
877  if (t->state == TARGET_RUNNING &&
878  t->state != TARGET_DEBUG_RUNNING) {
879 
880  if ((ts & TS_PM_BIT) && (ts & TS_PMCR_BIT)) {
881 
882  LOG_DEBUG("redirect to PM, tapstatus=0x%08" PRIx32, get_tapstatus(t));
883 
885  if (save_context(t) != ERROR_OK)
886  return ERROR_FAIL;
887  if (halt_prep(t) != ERROR_OK)
888  return ERROR_FAIL;
889  t->state = TARGET_HALTED;
891 
892  struct x86_32_common *x86_32 = target_to_x86_32(t);
893  uint32_t eip = buf_get_u32(x86_32->cache->reg_list[EIP].value, 0, 32);
894  uint32_t dr6 = buf_get_u32(x86_32->cache->reg_list[DR6].value, 0, 32);
895  uint32_t hwbreakpoint = (uint32_t)-1;
896 
897  if (dr6 & DR6_BRKDETECT_0)
898  hwbreakpoint = 0;
899  if (dr6 & DR6_BRKDETECT_1)
900  hwbreakpoint = 1;
901  if (dr6 & DR6_BRKDETECT_2)
902  hwbreakpoint = 2;
903  if (dr6 & DR6_BRKDETECT_3)
904  hwbreakpoint = 3;
905 
906  if (hwbreakpoint != (uint32_t)-1) {
907  uint32_t dr7 = buf_get_u32(x86_32->cache->reg_list[DR7].value, 0, 32);
908  uint32_t type = dr7 & (0x03 << (DR7_RW_SHIFT + hwbreakpoint*DR7_RW_LEN_SIZE));
909  if (type == DR7_BP_EXECUTE) {
910  LOG_USER("hit hardware breakpoint (hwreg=%" PRIu32 ") at 0x%08" PRIx32, hwbreakpoint, eip);
911  } else {
912  uint32_t address = 0;
913  switch (hwbreakpoint) {
914  default:
915  case 0:
916  address = buf_get_u32(x86_32->cache->reg_list[DR0].value, 0, 32);
917  break;
918  case 1:
919  address = buf_get_u32(x86_32->cache->reg_list[DR1].value, 0, 32);
920  break;
921  case 2:
922  address = buf_get_u32(x86_32->cache->reg_list[DR2].value, 0, 32);
923  break;
924  case 3:
925  address = buf_get_u32(x86_32->cache->reg_list[DR3].value, 0, 32);
926  break;
927  }
928  LOG_USER("hit '%s' watchpoint for 0x%08" PRIx32 " (hwreg=%" PRIu32 ") at 0x%08" PRIx32,
929  type == DR7_BP_WRITE ? "write" : "access", address,
930  hwbreakpoint, eip);
931  }
933  } else {
934  /* Check if the target hit a software breakpoint.
935  * ! Watch out: EIP is currently pointing after the breakpoint opcode
936  */
937  struct breakpoint *bp = NULL;
938  bp = breakpoint_find(t, eip-1);
939  if (bp != NULL) {
941  if (bp->type == BKPT_SOFT) {
942  /* The EIP is now pointing the the next byte after the
943  * breakpoint instruction. This needs to be corrected.
944  */
945  buf_set_u32(x86_32->cache->reg_list[EIP].value, 0, 32, eip-1);
946  x86_32->cache->reg_list[EIP].dirty = 1;
947  x86_32->cache->reg_list[EIP].valid = 1;
948  LOG_USER("hit software breakpoint at 0x%08" PRIx32, eip-1);
949  } else {
950  /* it's not a hardware breakpoint (checked already in DR6 state)
951  * and it's also not a software breakpoint ...
952  */
953  LOG_USER("hit unknown breakpoint at 0x%08" PRIx32, eip);
954  }
955  } else {
956 
957  /* There is also the case that we hit an breakpoint instruction,
958  * which was not set by us. This needs to be handled be the
959  * application that introduced the breakpoint.
960  */
961 
962  LOG_USER("unknown break reason at 0x%08" PRIx32, eip);
963  }
964  }
965 
967  }
968  }
969  return ERROR_OK;
970 }
971 
973 {
974  struct x86_32_common *x86_32 = target_to_x86_32(t);
975 
976  LOG_USER("target halted due to %s at 0x%08" PRIx32 " in %s mode",
978  buf_get_u32(x86_32->cache->reg_list[EIP].value, 0, 32),
979  (buf_get_u32(x86_32->cache->reg_list[CR0].value, 0, 32) & CR0_PE) ? "protected" : "real");
980 
981  return ERROR_OK;
982 }
983 
984 int lakemont_halt(struct target *t)
985 {
986  if (t->state == TARGET_RUNNING) {
988  if (do_halt(t) != ERROR_OK)
989  return ERROR_FAIL;
990  return ERROR_OK;
991  } else {
992  LOG_ERROR("%s target not running", __func__);
993  return ERROR_FAIL;
994  }
995 }
996 
997 int lakemont_resume(struct target *t, int current, target_addr_t address,
998  int handle_breakpoints, int debug_execution)
999 {
1000  struct breakpoint *bp = NULL;
1001  struct x86_32_common *x86_32 = target_to_x86_32(t);
1002 
1003  if (check_not_halted(t))
1004  return ERROR_TARGET_NOT_HALTED;
1005  /* TODO lakemont_enable_breakpoints(t); */
1006  if (t->state == TARGET_HALTED) {
1007 
1008  /* running away for a software breakpoint needs some special handling */
1009  uint32_t eip = buf_get_u32(x86_32->cache->reg_list[EIP].value, 0, 32);
1010  bp = breakpoint_find(t, eip);
1011  if (bp != NULL /*&& bp->type == BKPT_SOFT*/) {
1012  /* the step will step over the breakpoint */
1013  if (lakemont_step(t, 0, 0, 1) != ERROR_OK) {
1014  LOG_ERROR("%s stepping over a software breakpoint at 0x%08" PRIx32 " "
1015  "failed to resume the target", __func__, eip);
1016  return ERROR_FAIL;
1017  }
1018  }
1019 
1020  /* if breakpoints are enabled, we need to redirect these into probe mode */
1021  struct breakpoint *activeswbp = t->breakpoints;
1022  while (activeswbp != NULL && activeswbp->set == 0)
1023  activeswbp = activeswbp->next;
1024  struct watchpoint *activehwbp = t->watchpoints;
1025  while (activehwbp != NULL && activehwbp->set == 0)
1026  activehwbp = activehwbp->next;
1027  if (activeswbp != NULL || activehwbp != NULL)
1028  buf_set_u32(x86_32->cache->reg_list[PMCR].value, 0, 32, 1);
1029  if (do_resume(t) != ERROR_OK)
1030  return ERROR_FAIL;
1031  } else {
1032  LOG_USER("target not halted");
1033  return ERROR_FAIL;
1034  }
1035  return ERROR_OK;
1036 }
1037 
1038 int lakemont_step(struct target *t, int current,
1039  target_addr_t address, int handle_breakpoints)
1040 {
1041  struct x86_32_common *x86_32 = target_to_x86_32(t);
1042  uint32_t eflags = buf_get_u32(x86_32->cache->reg_list[EFLAGS].value, 0, 32);
1043  uint32_t eip = buf_get_u32(x86_32->cache->reg_list[EIP].value, 0, 32);
1044  uint32_t pmcr = buf_get_u32(x86_32->cache->reg_list[PMCR].value, 0, 32);
1045  struct breakpoint *bp = NULL;
1046  int retval = ERROR_OK;
1047  uint32_t tapstatus = 0;
1048 
1049  if (check_not_halted(t))
1050  return ERROR_TARGET_NOT_HALTED;
1051  bp = breakpoint_find(t, eip);
1052  if (retval == ERROR_OK && bp != NULL/*&& bp->type == BKPT_SOFT*/) {
1053  /* TODO: This should only be done for software breakpoints.
1054  * Stepping from hardware breakpoints should be possible with the resume flag
1055  * Needs testing.
1056  */
1057  retval = x86_32_common_remove_breakpoint(t, bp);
1058  }
1059 
1060  /* Set EFLAGS[TF] and PMCR[IR], exit pm and wait for PRDY# */
1061  LOG_DEBUG("modifying PMCR = 0x%08" PRIx32 " and EFLAGS = 0x%08" PRIx32, pmcr, eflags);
1062  eflags = eflags | (EFLAGS_TF | EFLAGS_RF);
1063  buf_set_u32(x86_32->cache->reg_list[EFLAGS].value, 0, 32, eflags);
1064  buf_set_u32(x86_32->cache->reg_list[PMCR].value, 0, 32, 1);
1065  LOG_DEBUG("EFLAGS [TF] [RF] bits set=0x%08" PRIx32 ", PMCR=0x%08" PRIx32 ", EIP=0x%08" PRIx32,
1066  eflags, pmcr, eip);
1067 
1068  tapstatus = get_tapstatus(t);
1069 
1072  if (restore_context(t) != ERROR_OK)
1073  return ERROR_FAIL;
1074  if (exit_probemode(t) != ERROR_OK)
1075  return ERROR_FAIL;
1076 
1078 
1079  tapstatus = get_tapstatus(t);
1080  if (tapstatus & (TS_PM_BIT | TS_EN_PM_BIT | TS_PRDY_BIT | TS_PMCR_BIT)) {
1081  /* target has stopped */
1082  if (save_context(t) != ERROR_OK)
1083  return ERROR_FAIL;
1084  if (halt_prep(t) != ERROR_OK)
1085  return ERROR_FAIL;
1086  t->state = TARGET_HALTED;
1087 
1088  LOG_USER("step done from EIP 0x%08" PRIx32 " to 0x%08" PRIx32, eip,
1089  buf_get_u32(x86_32->cache->reg_list[EIP].value, 0, 32));
1091  } else {
1092  /* target didn't stop
1093  * I hope the poll() will catch it, but the deleted breakpoint is gone
1094  */
1095  LOG_ERROR("%s target didn't stop after executing a single step", __func__);
1096  t->state = TARGET_RUNNING;
1097  return ERROR_FAIL;
1098  }
1099 
1100  /* try to re-apply the breakpoint, even of step failed
1101  * TODO: When a bp was set, we should try to stop the target - fix the return above
1102  */
1103  if (bp != NULL/*&& bp->type == BKPT_SOFT*/) {
1104  /* TODO: This should only be done for software breakpoints.
1105  * Stepping from hardware breakpoints should be possible with the resume flag
1106  * Needs testing.
1107  */
1108  retval = x86_32_common_add_breakpoint(t, bp);
1109  }
1110 
1111  return retval;
1112 }
1113 
1114 /* TODO - implement resetbreak fully through CLTAP registers */
1116 {
1117  LOG_DEBUG("-");
1118  return ERROR_OK;
1119 }
1120 
1122 {
1123  LOG_DEBUG("-");
1124  return ERROR_OK;
1125 }
static const struct reg_arch_type lakemont_reg_type
Definition: lakemont.c:365
static int submit_instruction_pir(struct target *t, int num)
Definition: lakemont.c:795
Definition: nds32_reg.h:117
static struct reg_cache * lakemont_build_reg_cache(struct target *target)
Definition: lakemont.c:373
static int submit_instruction(struct target *t, int num)
Definition: lakemont.c:774
struct reg_cache * next
Definition: register.h:149
bool(* is_paging_enabled)(struct target *t)
uint32_t target_addr_t
Definition: types.h:356
Definition: nds32_reg.h:68
static int drscan(struct target *t, uint8_t *out, uint8_t *in, uint8_t len)
Definition: lakemont.c:258
#define LOG_DEBUG(expr...)
Definition: log.h:115
const struct reg_arch_type * type
Definition: register.h:144
#define PDR_SIZE
Definition: lakemont.h:56
const char * name
Definition: register.h:118
static int enter_probemode(struct target *t)
Definition: lakemont.c:444
const char * name
Definition: register.h:148
#define SSAR_DPL
Definition: x86_32_common.h:53
int lakemont_reset_assert(struct target *t)
Definition: lakemont.c:1115
#define CSAR_DPL
Definition: x86_32_common.h:51
int(* get)(struct reg *reg)
Definition: register.h:155
bool exist
Definition: register.h:133
Definition: nds32_reg.h:118
static int save_context(struct target *target)
Definition: lakemont.c:299
void jtag_add_dr_scan(struct jtag_tap *active, int in_num_fields, const struct scan_field *in_fields, tap_state_t state)
Generate a DR SCAN using the fields passed to the function.
Definition: jtag/core.c:451
struct reg_feature * feature
Definition: register.h:122
#define CR0_NW
Definition: x86_32_common.h:56
#define LOG_INFO(expr...)
Definition: log.h:123
static int halt_prep(struct target *t)
Definition: lakemont.c:489
#define ERROR_TARGET_NOT_HALTED
Definition: target.h:689
const uint8_t * out_value
A pointer to value to be scanned into the device.
Definition: jtag.h:111
static bool is_paging_enabled(struct target *t)
Definition: lakemont.c:714
#define TS_EN_PM_BIT
Definition: lakemont.h:72
static int write_all_core_hw_regs(struct target *t)
Definition: lakemont.c:623
#define CR0_PE
Definition: x86_32_common.h:55
#define DR7_BP_WRITE
int lakemont_halt(struct target *t)
Definition: lakemont.c:984
#define TS_PRDY_BIT
Definition: lakemont.h:71
static int halted(struct target *target, const char *label)
Definition: davinci.c:69
static int lakemont_set_core_reg(struct reg *reg, uint8_t *buf)
Definition: lakemont.c:351
int ir_length
size of instruction register
Definition: jtag.h:130
#define DR6_BRKDETECT_1
Definition: x86_32_common.h:64
#define ERROR_FAIL
Definition: log.h:150
static struct scan_blk scan
Definition: lakemont.c:71
Definition: nds32_reg.h:65
#define LMT_IRLEN
Definition: lakemont.h:40
#define DR6_BRKDETECT_3
Definition: x86_32_common.h:66
#define EFLAGS_RF
Definition: x86_32_common.h:48
int(* enable_paging)(struct target *t)
uint32_t size
Definition: register.h:135
struct target * target
Definition: lakemont.h:79
enum target_debug_reason debug_reason
Definition: target.h:165
uint32_t number
Definition: register.h:120
This structure defines a single scan field in the scan.
Definition: jtag.h:107
int x86_32_common_remove_breakpoint(struct target *t, struct breakpoint *bp)
int(* submit_instruction)(struct target *t, int num)
static int enable_paging(struct target *t)
Definition: lakemont.c:741
#define EFLAGS_VM86
Definition: x86_32_common.h:49
static int read_hw_reg(struct target *t, int reg, uint32_t *regval, uint8_t cache)
Definition: lakemont.c:643
unsigned num_regs
Definition: register.h:151
#define WRPIR
Definition: lakemont.h:46
Definition: jtag.h:79
static int write_hw_reg(struct target *t, int reg, uint32_t regval, uint8_t cache)
Definition: lakemont.c:677
static int restore_context(struct target *target)
Definition: lakemont.c:311
static int irscan(struct target *t, uint8_t *out, uint8_t *in, uint8_t ir_len)
Definition: lakemont.c:225
Definition: nds32_reg.h:122
#define NOT_PMREG
Definition: lakemont.h:62
static void buf_set_u32(uint8_t *_buffer, unsigned first, unsigned num, uint32_t value)
Sets num bits in _buffer, starting at the first bit, using the bits in value.
Definition: binarybuffer.h:40
struct reg * reg_list
Definition: register.h:150
Definition: nds32_reg.h:67
struct jtag_tap * curr_tap
int(* read_hw_reg)(struct target *t, int reg, uint32_t *regval, uint8_t cache)
enum reg_type type
Definition: lakemont.c:82
#define PROBEMODE
Definition: lakemont.h:45
const char * name
Definition: lakemont.c:78
struct breakpoint * breakpoints
Definition: target.h:170
int num_bits
The number of bits this field specifies.
Definition: jtag.h:109
static uint32_t get_tapstatus(struct target *t)
Definition: lakemont.c:434
static int disable_paging(struct target *t)
Definition: lakemont.c:729
bool caller_save
Definition: register.h:124
#define PM_DSL
Definition: lakemont.h:65
static bool sw_bpts_supported(struct target *t)
Definition: lakemont.c:753
int lakemont_step(struct target *t, int current, target_addr_t address, int handle_breakpoints)
Definition: lakemont.c:1038
#define I(name)
Definition: lakemont.h:91
struct reg_cache ** register_get_last_cache_p(struct reg_cache **first)
Definition: register.c:60
#define MAX_SCAN_SIZE
Definition: lakemont.h:59
static int do_resume(struct target *t)
Definition: lakemont.c:587
#define DR7_RW_SHIFT
#define NOT_AVAIL_REG
Definition: lakemont.h:63
Definition: nds32_reg.h:116
#define EFLAGS_TF
Definition: x86_32_common.h:46
struct reg_cache * reg_cache
Definition: target.h:169
#define LOG_ERROR(expr...)
Definition: log.h:129
struct reg_cache * cache
int lakemont_poll(struct target *t)
Definition: lakemont.c:854
struct reg_data_type * reg_data_type
Definition: register.h:138
uint64_t op
Definition: lakemont.c:79
struct x86_32_common * x86_32_common
Definition: lakemont.h:80
#define TS_SBP_BIT
Definition: lakemont.h:75
enum target_state state
Definition: target.h:168
const char * name
Definition: register.h:48
struct watchpoint * next
Definition: breakpoints.h:54
#define EFLAGS_IF
Definition: x86_32_common.h:47
#define LOG_USER(expr...)
Definition: log.h:132
#define DR6_BRKDETECT_2
Definition: x86_32_common.h:65
#define PIR_SIZE
Definition: lakemont.h:55
int(* write_hw_reg)(struct target *t, int reg, uint32_t regval, uint8_t cache)
Definition: register.h:116
int lakemont_init_target(struct command_context *cmd_ctx, struct target *t)
Definition: lakemont.c:832
static int exit_probemode(struct target *t)
Definition: lakemont.c:470
uint8_t pm_idx
Definition: lakemont.c:80
static int lakemont_get_core_reg(struct reg *reg)
Definition: lakemont.c:339
#define DR7_RW_LEN_SIZE
static const struct @62 instructions[]
bool enabled
Is this TAP currently enabled?
Definition: jtag.h:129
bool valid
Definition: register.h:131
target_addr_t address
Definition: breakpoints.h:48
#define PM_DSB
Definition: lakemont.h:64
int lakemont_reset_deassert(struct target *t)
Definition: lakemont.c:1121
static uint8_t get_num_user_regs(struct target *t)
Definition: lakemont.c:723
uint8_t out[MAX_SCAN_SIZE]
Definition: lakemont.h:86
void jtag_add_ir_scan(struct jtag_tap *active, struct scan_field *in_fields, tap_state_t state)
Generate an IR SCAN with a list of scan fields with one entry for each enabled TAP.
Definition: jtag/core.c:373
uint8_t id
Definition: lakemont.c:77
#define CR0_PG
Definition: x86_32_common.h:58
int x86_32_common_add_breakpoint(struct target *t, struct breakpoint *bp)
int lakemont_init_arch_info(struct target *t, struct x86_32_common *x86_32)
Definition: lakemont.c:840
reg_type
Definition: register.h:27
void jtag_add_sleep(uint32_t us)
Definition: jtag/core.c:768
enum breakpoint_type type
Definition: breakpoints.h:39
#define RDWRPDR
Definition: lakemont.h:47
static uint32_t buf_get_u32(const uint8_t *_buffer, unsigned first, unsigned num)
Retrieves num bits from _buffer, starting at the first bit, returning the bits in a 32-bit word...
Definition: binarybuffer.h:107
enum reg_type type
Definition: register.h:105
static const struct @61 regs[]
#define DELAY_SUBMITPIR
Definition: lakemont.h:68
uint64_t op
Definition: lakemont.h:81
void * arch_info
Definition: register.h:143
static int read_all_core_hw_regs(struct target *t)
Definition: lakemont.c:603
uint8_t in[MAX_SCAN_SIZE]
Definition: lakemont.h:87
Definition: nds32_reg.h:115
#define PM_DR7
Definition: lakemont.h:67
uint8_t pm_idx
Definition: lakemont.h:82
const char * group
Definition: register.h:141
int jtag_execute_queue(void)
For software FIFO implementations, the queued commands can be executed during this call or earlier...
Definition: jtag/core.c:861
void * value
Definition: register.h:127
#define TAPSTATUS
Definition: lakemont.h:48
bool check_not_halted(const struct target *t)
Definition: lakemont.c:217
struct breakpoint * breakpoint_find(struct target *target, target_addr_t address)
Definition: breakpoints.c:378
static int transaction_status(struct target *t)
Definition: lakemont.c:762
enum x86_core_type core_type
#define ARRAY_SIZE(x)
Compute the number of elements of a variable length array.
Definition: types.h:69
static int do_halt(struct target *t)
Definition: lakemont.c:565
#define ERROR_OK
Definition: log.h:144
Definition: nds32_reg.h:69
int(* disable_paging)(struct target *t)
int lakemont_resume(struct target *t, int current, target_addr_t address, int handle_breakpoints, int debug_execution)
Definition: lakemont.c:997
struct jtag_tap * tap
Definition: target.h:130
bool(* sw_bpts_supported)(struct target *t)
#define TS_PM_BIT
Definition: lakemont.h:73
#define PM_DSAR
Definition: lakemont.h:66
static int submit_pir(struct target *t, uint64_t op)
Definition: lakemont.c:811
const char * debug_reason_name(struct target *t)
struct watchpoint * watchpoints
Definition: target.h:171
uint8_t * in_value
A pointer to a 32-bit memory location for data scanned out.
Definition: jtag.h:113
#define DR7_BP_EXECUTE
uint8_t(* get_num_user_regs)(struct target *t)
static struct x86_32_common * target_to_x86_32(struct target *target)
int target_call_event_callbacks(struct target *target, enum target_event event)
#define CR0_CD
Definition: x86_32_common.h:57
#define NULL
Definition: usb.h:27
#define TS_PMCR_BIT
Definition: lakemont.h:74
static int submit_reg_pir(struct target *t, int num)
Definition: lakemont.c:784
#define SUBMITPIR
Definition: lakemont.h:44
int(* transaction_status)(struct target *t)
Definition: nds32_reg.h:121
uint32_t pm_regs[NUM_PM_REGS]
int lakemont_arch_state(struct target *t)
Definition: lakemont.c:972
const char * group
Definition: lakemont.c:83
unsigned bits
Definition: lakemont.c:81
static void buf_set_u64(uint8_t *_buffer, unsigned first, unsigned num, uint64_t value)
Sets num bits in _buffer, starting at the first bit, using the bits in value.
Definition: binarybuffer.h:69
#define TS_SIZE
Definition: lakemont.h:57
Definition: target.h:126
struct scan_field field
Definition: lakemont.h:88
int lakemont_update_after_probemode_entry(struct target *t)
Definition: lakemont.c:576
const char * feature
Definition: lakemont.c:84
bool dirty
Definition: register.h:129
#define DR6_BRKDETECT_0
Definition: x86_32_common.h:63
struct breakpoint * next
Definition: breakpoints.h:42