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hla_target.c
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1 // SPDX-License-Identifier: GPL-2.0-or-later
2 
3 /***************************************************************************
4  * Copyright (C) 2011 by Mathias Kuester *
5  * Mathias Kuester <kesmtp@freenet.de> *
6  * *
7  * Copyright (C) 2011 by Spencer Oliver *
8  * spen@spen-soft.co.uk *
9  * *
10  * revised: 4/25/13 by brent@mbari.org [DCC target request support] *
11  ***************************************************************************/
12 
13 #ifdef HAVE_CONFIG_H
14 #include "config.h"
15 #endif
16 
17 #include "jtag/interface.h"
18 #include "jtag/jtag.h"
19 #include "jtag/hla/hla_transport.h"
20 #include "jtag/hla/hla_interface.h"
21 #include "jtag/hla/hla_layout.h"
22 #include "register.h"
23 #include "algorithm.h"
24 #include "target.h"
25 #include "breakpoints.h"
26 #include "target_type.h"
27 #include "armv7m.h"
28 #include "cortex_m.h"
29 #include "arm_adi_v5.h"
30 #include "arm_semihosting.h"
31 #include "target_request.h"
32 #include <rtt/rtt.h>
33 
34 #define SAVED_DCRDR dbgbase /* FIXME: using target->dbgbase to preserve DCRDR */
35 
36 #define ARMV7M_SCS_DCRSR DCB_DCRSR
37 #define ARMV7M_SCS_DCRDR DCB_DCRDR
38 
39 static inline struct hl_interface_s *target_to_adapter(struct target *target)
40 {
41  return target->tap->priv;
42 }
43 
45  uint32_t regsel, uint32_t *value)
46 {
48  return adapter->layout->api->read_reg(adapter->handle, regsel, value);
49 }
50 
52  uint32_t regsel, uint32_t value)
53 {
55  return adapter->layout->api->write_reg(adapter->handle, regsel, value);
56 }
57 
59 {
63  }
64 
65  return ERROR_OK;
66 }
67 
68 static int hl_dcc_read(struct hl_interface_s *hl_if, uint8_t *value, uint8_t *ctrl)
69 {
70  uint16_t dcrdr;
71  int retval = hl_if->layout->api->read_mem(hl_if->handle,
72  DCB_DCRDR, 1, sizeof(dcrdr), (uint8_t *)&dcrdr);
73  if (retval == ERROR_OK) {
74  *ctrl = (uint8_t)dcrdr;
75  *value = (uint8_t)(dcrdr >> 8);
76 
77  LOG_DEBUG("data 0x%x ctrl 0x%x", *value, *ctrl);
78 
79  if (dcrdr & 1) {
80  /* write ack back to software dcc register
81  * to signify we have read data */
82  /* atomically clear just the byte containing the busy bit */
83  static const uint8_t zero;
84  retval = hl_if->layout->api->write_mem(hl_if->handle, DCB_DCRDR, 1, 1, &zero);
85  }
86  }
87  return retval;
88 }
89 
91  uint32_t size, uint8_t *buffer)
92 {
94  uint8_t data;
95  uint8_t ctrl;
96  uint32_t i;
97 
98  for (i = 0; i < (size * 4); i++) {
99  int err = hl_dcc_read(hl_if, &data, &ctrl);
100  if (err != ERROR_OK)
101  return err;
102 
103  buffer[i] = data;
104  }
105 
106  return ERROR_OK;
107 }
108 
110 {
111  struct target *target = priv;
112  int err;
113 
115  return ERROR_OK;
117 
118  if (!target->dbg_msg_enabled)
119  return ERROR_OK;
120 
121  if (target->state == TARGET_RUNNING) {
122  uint8_t data;
123  uint8_t ctrl;
124 
125  err = hl_dcc_read(hl_if, &data, &ctrl);
126  if (err != ERROR_OK)
127  return err;
128 
129  /* check if we have data */
130  if (ctrl & (1 << 0)) {
131  uint32_t request;
132 
133  /* we assume target is quick enough */
134  request = data;
135  err = hl_dcc_read(hl_if, &data, &ctrl);
136  if (err != ERROR_OK)
137  return err;
138 
139  request |= (data << 8);
140  err = hl_dcc_read(hl_if, &data, &ctrl);
141  if (err != ERROR_OK)
142  return err;
143 
144  request |= (data << 16);
145  err = hl_dcc_read(hl_if, &data, &ctrl);
146  if (err != ERROR_OK)
147  return err;
148 
149  request |= (data << 24);
150  target_request(target, request);
151  }
152  }
153 
154  return ERROR_OK;
155 }
156 
158  struct cortex_m_common *cortex_m,
159  struct jtag_tap *tap)
160 {
161  struct armv7m_common *armv7m;
162 
163  LOG_DEBUG("%s", __func__);
164 
165  armv7m = &cortex_m->armv7m;
166  armv7m_init_arch_info(target, armv7m);
167 
170 
172  armv7m->is_hla_target = true;
173 
176 
177  return ERROR_OK;
178 }
179 
180 static int adapter_init_target(struct command_context *cmd_ctx,
181  struct target *target)
182 {
183  LOG_DEBUG("%s", __func__);
184 
187  return ERROR_OK;
188 }
189 
191  Jim_Interp *interp)
192 {
193  LOG_DEBUG("%s", __func__);
195  if (pc && pc->ap_num != DP_APSEL_INVALID && pc->ap_num != 0) {
196  LOG_ERROR("hla_target: invalid parameter -ap-num (> 0)");
198  }
199 
200  struct cortex_m_common *cortex_m = calloc(1, sizeof(struct cortex_m_common));
201  if (!cortex_m) {
202  LOG_ERROR("No memory creating target");
203  return ERROR_FAIL;
204  }
205 
207 
209 
210  return ERROR_OK;
211 }
212 
213 static int adapter_load_context(struct target *target)
214 {
215  struct armv7m_common *armv7m = target_to_armv7m(target);
216  int num_regs = armv7m->arm.core_cache->num_regs;
217 
218  for (int i = 0; i < num_regs; i++) {
219 
220  struct reg *r = &armv7m->arm.core_cache->reg_list[i];
221  if (r->exist && !r->valid)
222  armv7m->arm.read_core_reg(target, r, i, ARM_MODE_ANY);
223  }
224 
225  return ERROR_OK;
226 }
227 
228 static int adapter_debug_entry(struct target *target)
229 {
231  struct armv7m_common *armv7m = target_to_armv7m(target);
232  struct arm *arm = &armv7m->arm;
233  struct reg *r;
234  uint32_t xpsr;
235  int retval;
236 
237  /* preserve the DCRDR across halts */
238  retval = target_read_u32(target, DCB_DCRDR, &target->SAVED_DCRDR);
239  if (retval != ERROR_OK)
240  return retval;
241 
242  retval = armv7m->examine_debug_reason(target);
243  if (retval != ERROR_OK)
244  return retval;
245 
247 
248  /* make sure we clear the vector catch bit */
249  adapter->layout->api->write_debug_reg(adapter->handle, DCB_DEMCR, TRCENA);
250 
251  r = arm->cpsr;
252  xpsr = buf_get_u32(r->value, 0, 32);
253 
254  /* Are we in an exception handler */
255  if (xpsr & 0x1FF) {
256  armv7m->exception_number = (xpsr & 0x1FF);
257 
260  } else {
261  unsigned control = buf_get_u32(arm->core_cache
262  ->reg_list[ARMV7M_CONTROL].value, 0, 3);
263 
264  /* is this thread privileged? */
265  arm->core_mode = control & 1
267  : ARM_MODE_THREAD;
268 
269  /* which stack is it using? */
270  if (control & 2)
272  else
274 
275  armv7m->exception_number = 0;
276  }
277 
278  LOG_DEBUG("entered debug state in core mode: %s at PC 0x%08" PRIx32 ", target->state: %s",
280  buf_get_u32(arm->pc->value, 0, 32),
282 
283  return retval;
284 }
285 
286 static int adapter_poll(struct target *target)
287 {
288  enum target_state state;
290  struct armv7m_common *armv7m = target_to_armv7m(target);
291  enum target_state prev_target_state = target->state;
292 
293  state = adapter->layout->api->state(adapter->handle);
294 
295  if (state == TARGET_UNKNOWN) {
296  LOG_ERROR("jtag status contains invalid mode value - communication failure");
297  return ERROR_TARGET_FAILURE;
298  }
299 
300  if (prev_target_state == state)
301  return ERROR_OK;
302 
303  if (prev_target_state == TARGET_DEBUG_RUNNING && state == TARGET_RUNNING)
304  return ERROR_OK;
305 
306  target->state = state;
307 
308  if (state == TARGET_HALTED) {
309 
310  int retval = adapter_debug_entry(target);
311  if (retval != ERROR_OK)
312  return retval;
313 
314  if (prev_target_state == TARGET_DEBUG_RUNNING) {
316  } else {
317  if (arm_semihosting(target, &retval) != 0)
318  return retval;
319 
321  }
322 
323  LOG_DEBUG("halted: PC: 0x%08" PRIx32, buf_get_u32(armv7m->arm.pc->value, 0, 32));
324  }
325 
326  return ERROR_OK;
327 }
328 
329 static int hl_assert_reset(struct target *target)
330 {
331  int res = ERROR_OK;
333  struct armv7m_common *armv7m = target_to_armv7m(target);
334  bool use_srst_fallback = true;
335 
336  LOG_DEBUG("%s", __func__);
337 
339 
340  bool srst_asserted = false;
341 
344  res = adapter_assert_reset();
345  srst_asserted = true;
346  }
347 
348  adapter->layout->api->write_debug_reg(adapter->handle, DCB_DHCSR, DBGKEY|C_DEBUGEN);
349 
351  && srst_asserted && res == ERROR_OK) {
352  /* If the target is not examined, now under reset it is good time to retry examination */
353  LOG_TARGET_DEBUG(target, "Trying to re-examine under reset");
355  }
356 
357  /* only set vector catch if halt is requested */
358  if (target->reset_halt)
359  adapter->layout->api->write_debug_reg(adapter->handle, DCB_DEMCR, TRCENA|VC_CORERESET);
360  else
361  adapter->layout->api->write_debug_reg(adapter->handle, DCB_DEMCR, TRCENA);
362 
364  if (!srst_asserted) {
365  res = adapter_assert_reset();
366  }
367  if (res == ERROR_COMMAND_NOTFOUND)
368  LOG_ERROR("Hardware srst not supported, falling back to software reset");
369  else if (res == ERROR_OK) {
370  /* hardware srst supported */
371  use_srst_fallback = false;
372  }
373  }
374 
375  if (use_srst_fallback) {
376  /* stlink v1 api does not support hardware srst, so we use a software reset fallback */
377  adapter->layout->api->write_debug_reg(adapter->handle, NVIC_AIRCR, AIRCR_VECTKEY | AIRCR_SYSRESETREQ);
378  }
379 
380  res = adapter->layout->api->reset(adapter->handle);
381 
382  if (res != ERROR_OK)
383  return res;
384 
385  /* registers are now invalid */
387 
388  if (target->reset_halt) {
391  } else {
393  }
394 
395  return ERROR_OK;
396 }
397 
398 static int hl_deassert_reset(struct target *target)
399 {
401 
402  LOG_DEBUG("%s", __func__);
403 
406 
407  target->SAVED_DCRDR = 0; /* clear both DCC busy bits on initial resume */
408 
409  return target->reset_halt ? ERROR_OK : target_resume(target, 1, 0, 0, 0);
410 }
411 
412 static int adapter_halt(struct target *target)
413 {
414  int res;
416 
417  LOG_DEBUG("%s", __func__);
418 
419  if (target->state == TARGET_HALTED) {
420  LOG_DEBUG("target was already halted");
421  return ERROR_OK;
422  }
423 
424  if (target->state == TARGET_UNKNOWN)
425  LOG_WARNING("target was in unknown state when halt was requested");
426 
427  res = adapter->layout->api->halt(adapter->handle);
428 
429  if (res != ERROR_OK)
430  return res;
431 
433 
434  return ERROR_OK;
435 }
436 
437 static int adapter_resume(struct target *target, int current,
438  target_addr_t address, int handle_breakpoints,
439  int debug_execution)
440 {
441  int res;
443  struct armv7m_common *armv7m = target_to_armv7m(target);
444  uint32_t resume_pc;
445  struct breakpoint *breakpoint = NULL;
446  struct reg *pc;
447 
448  LOG_DEBUG("%s %d " TARGET_ADDR_FMT " %d %d", __func__, current,
449  address, handle_breakpoints, debug_execution);
450 
451  if (target->state != TARGET_HALTED) {
452  LOG_TARGET_ERROR(target, "not halted");
454  }
455 
456  if (!debug_execution) {
460  }
461 
462  pc = armv7m->arm.pc;
463  if (!current) {
464  buf_set_u32(pc->value, 0, 32, address);
465  pc->dirty = true;
466  pc->valid = true;
467  }
468 
469  if (!breakpoint_find(target, buf_get_u32(pc->value, 0, 32))
470  && !debug_execution) {
472  }
473 
474  resume_pc = buf_get_u32(pc->value, 0, 32);
475 
476  /* write any user vector flags */
477  res = target_write_u32(target, DCB_DEMCR, TRCENA | armv7m->demcr);
478  if (res != ERROR_OK)
479  return res;
480 
482 
483  /* restore SAVED_DCRDR */
484  res = target_write_u32(target, DCB_DCRDR, target->SAVED_DCRDR);
485  if (res != ERROR_OK)
486  return res;
487 
488  /* registers are now invalid */
490 
491  /* the front-end may request us not to handle breakpoints */
492  if (handle_breakpoints) {
493  /* Single step past breakpoint at current address */
494  breakpoint = breakpoint_find(target, resume_pc);
495  if (breakpoint) {
496  LOG_DEBUG("unset breakpoint at " TARGET_ADDR_FMT " (ID: %" PRIu32 ")",
500 
501  res = adapter->layout->api->step(adapter->handle);
502 
503  if (res != ERROR_OK)
504  return res;
505 
507  }
508  }
509 
510  res = adapter->layout->api->run(adapter->handle);
511 
512  if (res != ERROR_OK)
513  return res;
514 
516 
517  if (!debug_execution) {
520  } else {
523  }
524 
525  return ERROR_OK;
526 }
527 
528 static int adapter_step(struct target *target, int current,
529  target_addr_t address, int handle_breakpoints)
530 {
531  int res;
533  struct armv7m_common *armv7m = target_to_armv7m(target);
534  struct breakpoint *breakpoint = NULL;
535  struct reg *pc = armv7m->arm.pc;
536  bool bkpt_inst_found = false;
537 
538  LOG_DEBUG("%s", __func__);
539 
540  if (target->state != TARGET_HALTED) {
541  LOG_TARGET_ERROR(target, "not halted");
543  }
544 
545  if (!current) {
546  buf_set_u32(pc->value, 0, 32, address);
547  pc->dirty = true;
548  pc->valid = true;
549  }
550 
551  uint32_t pc_value = buf_get_u32(pc->value, 0, 32);
552 
553  /* the front-end may request us not to handle breakpoints */
554  if (handle_breakpoints) {
555  breakpoint = breakpoint_find(target, pc_value);
556  if (breakpoint)
558  }
559 
560  armv7m_maybe_skip_bkpt_inst(target, &bkpt_inst_found);
561 
563 
565 
566  /* restore SAVED_DCRDR */
567  res = target_write_u32(target, DCB_DCRDR, target->SAVED_DCRDR);
568  if (res != ERROR_OK)
569  return res;
570 
572 
573  res = adapter->layout->api->step(adapter->handle);
574 
575  if (res != ERROR_OK)
576  return res;
577 
578  /* registers are now invalid */
580 
581  if (breakpoint)
583 
586 
587  LOG_INFO("halted: PC: 0x%08" PRIx32, buf_get_u32(armv7m->arm.pc->value, 0, 32));
588 
589  return ERROR_OK;
590 }
591 
592 static int adapter_read_memory(struct target *target, target_addr_t address,
593  uint32_t size, uint32_t count,
594  uint8_t *buffer)
595 {
597 
598  if (!count || !buffer)
600 
601  LOG_DEBUG("%s " TARGET_ADDR_FMT " %" PRIu32 " %" PRIu32,
602  __func__, address, size, count);
603 
604  return adapter->layout->api->read_mem(adapter->handle, address, size, count, buffer);
605 }
606 
607 static int adapter_write_memory(struct target *target, target_addr_t address,
608  uint32_t size, uint32_t count,
609  const uint8_t *buffer)
610 {
612 
613  if (!count || !buffer)
615 
616  LOG_DEBUG("%s " TARGET_ADDR_FMT " %" PRIu32 " %" PRIu32,
617  __func__, address, size, count);
618 
619  return adapter->layout->api->write_mem(adapter->handle, address, size, count, buffer);
620 }
621 
622 static const struct command_registration hla_command_handlers[] = {
623  {
625  },
626  {
628  },
629  {
631  },
632  /* START_DEPRECATED_TPIU */
633  {
635  },
636  /* END_DEPRECATED_TPIU */
638 };
639 
640 struct target_type hla_target = {
641  .name = "hla_target",
642 
643  .init_target = adapter_init_target,
644  .deinit_target = cortex_m_deinit_target,
645  .target_create = adapter_target_create,
646  .target_jim_configure = adiv5_jim_configure,
647  .examine = cortex_m_examine,
648  .commands = hla_command_handlers,
649 
650  .poll = adapter_poll,
651  .arch_state = armv7m_arch_state,
652 
653  .target_request_data = hl_target_request_data,
654  .assert_reset = hl_assert_reset,
655  .deassert_reset = hl_deassert_reset,
656 
657  .halt = adapter_halt,
658  .resume = adapter_resume,
659  .step = adapter_step,
660 
661  .get_gdb_arch = arm_get_gdb_arch,
662  .get_gdb_reg_list = armv7m_get_gdb_reg_list,
663 
664  .read_memory = adapter_read_memory,
665  .write_memory = adapter_write_memory,
666  .checksum_memory = armv7m_checksum_memory,
667  .blank_check_memory = armv7m_blank_check_memory,
668 
669  .run_algorithm = armv7m_run_algorithm,
670  .start_algorithm = armv7m_start_algorithm,
671  .wait_algorithm = armv7m_wait_algorithm,
672 
673  .add_breakpoint = cortex_m_add_breakpoint,
674  .remove_breakpoint = cortex_m_remove_breakpoint,
675  .add_watchpoint = cortex_m_add_watchpoint,
676  .remove_watchpoint = cortex_m_remove_watchpoint,
677  .profiling = cortex_m_profiling,
678 };
const char * arm_get_gdb_arch(const struct target *target)
Definition: armv4_5.c:1267
@ ARM_MODE_HANDLER
Definition: arm.h:95
@ ARM_MODE_ANY
Definition: arm.h:105
@ ARM_MODE_USER_THREAD
Definition: arm.h:94
@ ARM_MODE_THREAD
Definition: arm.h:93
const struct command_registration arm_command_handlers[]
Definition: armv4_5.c:1247
const char * arm_mode_name(unsigned psr_mode)
Map PSR mode bits to the name of an ARM processor operating mode.
Definition: armv4_5.c:171
int adiv5_jim_configure(struct target *target, struct jim_getopt_info *goi)
Definition: arm_adi_v5.c:2467
This defines formats and data structures used to talk to ADIv5 entities.
#define DP_APSEL_INVALID
Definition: arm_adi_v5.h:110
int arm_semihosting(struct target *target, int *retval)
Checks for and processes an ARM semihosting request.
int arm_semihosting_init(struct target *target)
Initialize ARM semihosting support.
const struct command_registration arm_tpiu_deprecated_command_handlers[]
int armv7m_get_gdb_reg_list(struct target *target, struct reg **reg_list[], int *reg_list_size, enum target_register_class reg_class)
Returns generic ARM userspace registers to GDB.
Definition: armv7m.c:459
int armv7m_maybe_skip_bkpt_inst(struct target *target, bool *inst_found)
Definition: armv7m.c:1065
const int armv7m_psp_reg_map[ARMV7M_NUM_CORE_REGS]
Definition: armv7m.c:51
struct reg_cache * armv7m_build_reg_cache(struct target *target)
Builds cache of architecturally defined registers.
Definition: armv7m.c:763
const int armv7m_msp_reg_map[ARMV7M_NUM_CORE_REGS]
Definition: armv7m.c:60
int armv7m_run_algorithm(struct target *target, int num_mem_params, struct mem_param *mem_params, int num_reg_params, struct reg_param *reg_params, target_addr_t entry_point, target_addr_t exit_point, unsigned int timeout_ms, void *arch_info)
Runs a Thumb algorithm in the target.
Definition: armv7m.c:483
int armv7m_checksum_memory(struct target *target, target_addr_t address, uint32_t count, uint32_t *checksum)
Generates a CRC32 checksum of a memory region.
Definition: armv7m.c:882
int armv7m_wait_algorithm(struct target *target, int num_mem_params, struct mem_param *mem_params, int num_reg_params, struct reg_param *reg_params, target_addr_t exit_point, unsigned int timeout_ms, void *arch_info)
Waits for an algorithm in the target.
Definition: armv7m.c:622
int armv7m_blank_check_memory(struct target *target, struct target_memory_check_block *blocks, int num_blocks, uint8_t erased_value)
Checks an array of memory regions whether they are erased.
Definition: armv7m.c:933
int armv7m_arch_state(struct target *target)
Logs summary of ARMv7-M state for a halted target.
Definition: armv7m.c:728
int armv7m_restore_context(struct target *target)
Restores target context using the cache of core registers set up by armv7m_build_reg_cache(),...
Definition: armv7m.c:168
int armv7m_start_algorithm(struct target *target, int num_mem_params, struct mem_param *mem_params, int num_reg_params, struct reg_param *reg_params, target_addr_t entry_point, target_addr_t exit_point, void *arch_info)
Starts a Thumb algorithm in the target.
Definition: armv7m.c:508
int armv7m_init_arch_info(struct target *target, struct armv7m_common *armv7m)
Sets up target as a generic ARMv7-M core.
Definition: armv7m.c:860
@ ARMV7M_CONTROL
Definition: armv7m.h:147
static struct armv7m_common * target_to_armv7m(struct target *target)
Definition: armv7m.h:262
const struct command_registration armv7m_trace_command_handlers[]
Definition: armv7m_trace.c:140
static uint32_t buf_get_u32(const uint8_t *_buffer, unsigned first, unsigned num)
Retrieves num bits from _buffer, starting at the first bit, returning the bits in a 32-bit word.
Definition: binarybuffer.h:99
static void buf_set_u32(uint8_t *_buffer, unsigned first, unsigned num, uint32_t value)
Sets num bits in _buffer, starting at the first bit, using the bits in value.
Definition: binarybuffer.h:31
struct breakpoint * breakpoint_find(struct target *target, target_addr_t address)
Definition: breakpoints.c:489
#define ERROR_COMMAND_SYNTAX_ERROR
Definition: command.h:402
#define ERROR_COMMAND_NOTFOUND
Definition: command.h:403
#define COMMAND_REGISTRATION_DONE
Use this as the last entry in an array of command_registration records.
Definition: command.h:253
void cortex_m_enable_watchpoints(struct target *target)
Definition: cortex_m.c:2131
int cortex_m_add_watchpoint(struct target *target, struct watchpoint *watchpoint)
Definition: cortex_m.c:2040
void cortex_m_enable_breakpoints(struct target *target)
Definition: cortex_m.c:1205
int cortex_m_remove_breakpoint(struct target *target, struct breakpoint *breakpoint)
Definition: cortex_m.c:1915
int cortex_m_examine(struct target *target)
Definition: cortex_m.c:2487
int cortex_m_remove_watchpoint(struct target *target, struct watchpoint *watchpoint)
Definition: cortex_m.c:2083
int cortex_m_add_breakpoint(struct target *target, struct breakpoint *breakpoint)
Definition: cortex_m.c:1900
int cortex_m_set_breakpoint(struct target *target, struct breakpoint *breakpoint)
Definition: cortex_m.c:1774
void cortex_m_deinit_target(struct target *target)
Definition: cortex_m.c:2179
int cortex_m_unset_breakpoint(struct target *target, struct breakpoint *breakpoint)
Definition: cortex_m.c:1859
int cortex_m_profiling(struct target *target, uint32_t *samples, uint32_t max_num_samples, uint32_t *num_samples, uint32_t seconds)
Definition: cortex_m.c:2196
#define DBGKEY
Definition: cortex_m.h:128
#define AIRCR_VECTKEY
Definition: cortex_m.h:172
#define CORTEX_M_COMMON_MAGIC
Definition: cortex_m.h:20
#define AIRCR_SYSRESETREQ
Definition: cortex_m.h:173
#define VC_CORERESET
Definition: cortex_m.h:149
#define DCB_DEMCR
Definition: cortex_m.h:81
#define C_DEBUGEN
Definition: cortex_m.h:129
#define DCB_DCRDR
Definition: cortex_m.h:80
#define NVIC_AIRCR
Definition: cortex_m.h:158
#define DCB_DHCSR
Definition: cortex_m.h:78
#define TRCENA
Definition: cortex_m.h:141
static struct esp_usb_jtag * priv
Definition: esp_usb_jtag.c:219
static struct libusb_device_handle * adapter
Definition: ft232r.c:63
static struct hl_interface_s hl_if
Definition: hla_interface.c:26
static int hl_target_request_data(struct target *target, uint32_t size, uint8_t *buffer)
Definition: hla_target.c:90
static struct hl_interface_s * target_to_adapter(struct target *target)
Definition: hla_target.c:39
static int adapter_poll(struct target *target)
Definition: hla_target.c:286
static int adapter_init_target(struct command_context *cmd_ctx, struct target *target)
Definition: hla_target.c:180
static int adapter_write_memory(struct target *target, target_addr_t address, uint32_t size, uint32_t count, const uint8_t *buffer)
Definition: hla_target.c:607
static int adapter_examine_debug_reason(struct target *target)
Definition: hla_target.c:58
static int adapter_init_arch_info(struct target *target, struct cortex_m_common *cortex_m, struct jtag_tap *tap)
Definition: hla_target.c:157
static int adapter_halt(struct target *target)
Definition: hla_target.c:412
static int adapter_store_core_reg_u32(struct target *target, uint32_t regsel, uint32_t value)
Definition: hla_target.c:51
static int hl_assert_reset(struct target *target)
Definition: hla_target.c:329
static const struct command_registration hla_command_handlers[]
Definition: hla_target.c:622
static int hl_dcc_read(struct hl_interface_s *hl_if, uint8_t *value, uint8_t *ctrl)
Definition: hla_target.c:68
static int hl_deassert_reset(struct target *target)
Definition: hla_target.c:398
static int adapter_read_memory(struct target *target, target_addr_t address, uint32_t size, uint32_t count, uint8_t *buffer)
Definition: hla_target.c:592
static int adapter_step(struct target *target, int current, target_addr_t address, int handle_breakpoints)
Definition: hla_target.c:528
static int adapter_resume(struct target *target, int current, target_addr_t address, int handle_breakpoints, int debug_execution)
Definition: hla_target.c:437
static int adapter_target_create(struct target *target, Jim_Interp *interp)
Definition: hla_target.c:190
static int adapter_load_core_reg_u32(struct target *target, uint32_t regsel, uint32_t *value)
Definition: hla_target.c:44
struct target_type hla_target
Definition: hla_target.c:640
static int hl_handle_target_request(void *priv)
Definition: hla_target.c:109
static int adapter_load_context(struct target *target)
Definition: hla_target.c:213
static int adapter_debug_entry(struct target *target)
Definition: hla_target.c:228
static enum reset_types jtag_reset_config
Definition: jtag/core.c:87
int adapter_deassert_reset(void)
Definition: jtag/core.c:1900
enum reset_types jtag_get_reset_config(void)
Definition: jtag/core.c:1734
int adapter_assert_reset(void)
Definition: jtag/core.c:1880
The JTAG interface can be implemented with a software or hardware fifo.
reset_types
Definition: jtag.h:216
@ RESET_SRST_NO_GATING
Definition: jtag.h:225
@ RESET_HAS_SRST
Definition: jtag.h:219
#define LOG_WARNING(expr ...)
Definition: log.h:129
#define ERROR_FAIL
Definition: log.h:170
#define LOG_TARGET_ERROR(target, fmt_str,...)
Definition: log.h:158
#define LOG_TARGET_DEBUG(target, fmt_str,...)
Definition: log.h:149
#define LOG_ERROR(expr ...)
Definition: log.h:132
#define LOG_INFO(expr ...)
Definition: log.h:126
#define LOG_DEBUG(expr ...)
Definition: log.h:109
#define ERROR_OK
Definition: log.h:164
#define zero
Definition: mips32.c:165
void register_cache_invalidate(struct reg_cache *cache)
Marks the contents of the register cache as invalid (and clean).
Definition: register.c:94
struct rtt_control ctrl
Control block.
Definition: rtt/rtt.c:25
size_t size
Size of the control block search area.
Definition: rtt/rtt.c:30
const struct command_registration rtt_target_command_handlers[]
Definition: rtt/tcl.c:261
Represents a generic ARM core, with standard application registers.
Definition: arm.h:174
enum arm_mode core_mode
Record the current core mode: SVC, USR, or some other mode.
Definition: arm.h:195
struct reg * cpsr
Handle to the CPSR/xPSR; valid in all core modes.
Definition: arm.h:183
struct reg * pc
Handle to the PC; valid in all core modes.
Definition: arm.h:180
const int * map
Support for arm_reg_current()
Definition: arm.h:189
int(* read_core_reg)(struct target *target, struct reg *reg, int num, enum arm_mode mode)
Retrieve a single core register.
Definition: arm.h:223
struct reg_cache * core_cache
Definition: arm.h:177
bool is_hla_target
Definition: armv7m.h:236
int exception_number
Definition: armv7m.h:227
struct arm arm
Definition: armv7m.h:225
int(* store_core_reg_u32)(struct target *target, uint32_t regsel, uint32_t value)
Definition: armv7m.h:242
int(* load_core_reg_u32)(struct target *target, uint32_t regsel, uint32_t *value)
Definition: armv7m.h:241
uint32_t demcr
Definition: armv7m.h:233
int(* examine_debug_reason)(struct target *target)
Definition: armv7m.h:244
uint32_t unique_id
Definition: breakpoints.h:35
target_addr_t address
Definition: breakpoints.h:27
const struct command_registration * chain
If non-NULL, the commands in chain will be registered in the same context and scope of this registrat...
Definition: command.h:249
struct armv7m_common armv7m
Definition: cortex_m.h:222
unsigned int common_magic
Definition: cortex_m.h:220
const struct hl_layout * layout
Definition: hla_interface.h:46
int(* read_mem)(void *handle, uint32_t addr, uint32_t size, uint32_t count, uint8_t *buffer)
Definition: hla_layout.h:64
int(* write_mem)(void *handle, uint32_t addr, uint32_t size, uint32_t count, const uint8_t *buffer)
Definition: hla_layout.h:67
struct hl_layout_api_s * api
Definition: hla_layout.h:128
Definition: jtag.h:101
void * priv
Definition: jtag.h:143
unsigned num_regs
Definition: register.h:148
struct reg * reg_list
Definition: register.h:147
Definition: register.h:111
bool valid
Definition: register.h:126
bool exist
Definition: register.h:128
uint8_t * value
Definition: register.h:122
bool dirty
Definition: register.h:124
This holds methods shared between all instances of a given target type.
Definition: target_type.h:26
const char * name
Name of this type of target.
Definition: target_type.h:31
Definition: target.h:116
struct jtag_tap * tap
Definition: target.h:119
enum target_debug_reason debug_reason
Definition: target.h:154
enum target_state state
Definition: target.h:157
void * private_config
Definition: target.h:165
uint32_t dbg_msg_enabled
Definition: target.h:163
bool reset_halt
Definition: target.h:144
bool defer_examine
Should we defer examine to later.
Definition: target.h:123
int target_call_event_callbacks(struct target *target, enum target_event event)
Definition: target.c:1764
void target_free_all_working_areas(struct target *target)
Definition: target.c:2150
int target_write_u32(struct target *target, target_addr_t address, uint32_t value)
Definition: target.c:2641
int target_examine_one(struct target *target)
Examine the specified target, letting it perform any Initialisation that requires JTAG access.
Definition: target.c:672
const char * target_state_name(const struct target *t)
Return the name of this targets current state.
Definition: target.c:260
static int srst_asserted
Definition: target.c:2849
int target_register_timer_callback(int(*callback)(void *priv), unsigned int time_ms, enum target_timer_type type, void *priv)
The period is very approximate, the callback can happen much more often or much more rarely than spec...
Definition: target.c:1658
int target_read_u32(struct target *target, target_addr_t address, uint32_t *value)
Definition: target.c:2550
int target_resume(struct target *target, int current, target_addr_t address, int handle_breakpoints, int debug_execution)
Make the target (re)start executing using its saved execution context (possibly with some modificatio...
Definition: target.c:556
@ DBG_REASON_NOTHALTED
Definition: target.h:74
@ DBG_REASON_DBGRQ
Definition: target.h:69
@ DBG_REASON_SINGLESTEP
Definition: target.h:73
@ DBG_REASON_BREAKPOINT
Definition: target.h:70
#define ERROR_TARGET_NOT_HALTED
Definition: target.h:790
static bool target_was_examined(const struct target *target)
Definition: target.h:436
@ TARGET_TIMER_TYPE_PERIODIC
Definition: target.h:327
@ TARGET_EVENT_DEBUG_RESUMED
Definition: target.h:272
@ TARGET_EVENT_HALTED
Definition: target.h:252
@ TARGET_EVENT_RESUMED
Definition: target.h:253
@ TARGET_EVENT_DEBUG_HALTED
Definition: target.h:271
target_state
Definition: target.h:53
@ TARGET_RESET
Definition: target.h:57
@ TARGET_DEBUG_RUNNING
Definition: target.h:58
@ TARGET_UNKNOWN
Definition: target.h:54
@ TARGET_HALTED
Definition: target.h:56
@ TARGET_RUNNING
Definition: target.h:55
#define ERROR_TARGET_FAILURE
Definition: target.h:791
int target_request(struct target *target, uint32_t request)
#define TARGET_ADDR_FMT
Definition: types.h:342
uint64_t target_addr_t
Definition: types.h:335
#define NULL
Definition: usb.h:16
uint8_t state[4]
Definition: vdebug.c:21
uint8_t count[4]
Definition: vdebug.c:22