OpenOCD
armv4_5.c File Reference
Include dependency graph for armv4_5.c:

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Macros

#define ARMV4_5_CORE_REG_MODENUM(cache, mode, num)   (cache->reg_list[armv4_5_core_reg_map[mode][num]])
 

Enumerations

enum  {
  ARMV4_5_SPSR_FIQ = 32, ARMV4_5_SPSR_IRQ = 33, ARMV4_5_SPSR_SVC = 34, ARMV4_5_SPSR_ABT = 35,
  ARMV4_5_SPSR_UND = 36, ARM_SPSR_MON = 41
}
 

Functions

int arm_arch_state (struct target *target)
 
int arm_blank_check_memory (struct target *target, target_addr_t address, uint32_t count, uint32_t *blank, uint8_t erased_value)
 Runs ARM code in the target to check whether a memory block holds all ones. More...
 
struct reg_cachearm_build_reg_cache (struct target *target, struct arm *arm)
 
int arm_checksum_memory (struct target *target, target_addr_t address, uint32_t count, uint32_t *checksum)
 Runs ARM code in the target to calculate a CRC32 checksum. More...
 
static int arm_default_mcr (struct target *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t value)
 
static int arm_default_mrc (struct target *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t *value)
 
static int arm_full_context (struct target *target)
 
static void arm_gdb_dummy_init (void)
 
int arm_get_gdb_reg_list (struct target *target, struct reg **reg_list[], int *reg_list_size, enum target_register_class reg_class)
 
int arm_init_arch_info (struct target *target, struct arm *arm)
 
const char * arm_mode_name (unsigned psr_mode)
 Map PSR mode bits to the name of an ARM processor operating mode. More...
 
int arm_mode_to_number (enum arm_mode mode)
 Map PSR mode bits to linear number indexing armv4_5_core_reg_map. More...
 
struct regarm_reg_current (struct arm *arm, unsigned regnum)
 Returns handle to the register currently mapped to a given number. More...
 
void arm_set_cpsr (struct arm *arm, uint32_t cpsr)
 Configures host-side ARM records to reflect the specified CPSR. More...
 
static int armv4_5_get_core_reg (struct reg *reg)
 
enum arm_mode armv4_5_number_to_mode (int number)
 Map linear number indexing armv4_5_core_reg_map to PSR mode bits. More...
 
int armv4_5_run_algorithm (struct target *target, int num_mem_params, struct mem_param *mem_params, int num_reg_params, struct reg_param *reg_params, target_addr_t entry_point, target_addr_t exit_point, int timeout_ms, void *arch_info)
 
static int armv4_5_run_algorithm_completion (struct target *target, uint32_t exit_point, int timeout_ms, void *arch_info)
 
int armv4_5_run_algorithm_inner (struct target *target, int num_mem_params, struct mem_param *mem_params, int num_reg_params, struct reg_param *reg_params, uint32_t entry_point, uint32_t exit_point, int timeout_ms, void *arch_info, int(*run_it)(struct target *target, uint32_t exit_point, int timeout_ms, void *arch_info))
 
static int armv4_5_set_core_reg (struct reg *reg, uint8_t *buf)
 
 COMMAND_HANDLER (handle_armv4_5_reg_command)
 
 COMMAND_HANDLER (handle_armv4_5_core_state_command)
 
 COMMAND_HANDLER (handle_arm_disassemble_command)
 
 COMMAND_HANDLER (handle_arm_semihosting_command)
 
 COMMAND_HANDLER (handle_arm_semihosting_fileio_command)
 
 COMMAND_HANDLER (handle_arm_semihosting_cmdline)
 
bool is_arm_mode (unsigned psr_mode)
 Return true iff the parameter denotes a valid ARM processor mode. More...
 
static int jim_mcrmrc (Jim_Interp *interp, int argc, Jim_Obj *const *argv)
 

Variables

static const uint8_t arm_abt_indices [3]
 
const struct command_registration arm_command_handlers []
 
struct {
   unsigned   cookie
 
   unsigned   gdb_index
 
   enum arm_mode   mode
 
   const char *   name
 
arm_core_regs []
 
static const struct
command_registration 
arm_exec_command_handlers []
 
static const uint8_t arm_fiq_indices [8]
 
static struct reg_feature arm_gdb_dummy_fp_features
 
struct reg arm_gdb_dummy_fp_reg
 Dummy FPA registers are required to support GDB on ARM. More...
 
static const uint8_t arm_gdb_dummy_fp_value [12]
 
struct reg arm_gdb_dummy_fps_reg
 Dummy FPA status registers are required to support GDB on ARM. More...
 
static const uint8_t arm_gdb_dummy_fps_value [4]
 
static const uint8_t arm_irq_indices [3]
 
struct {
   const uint8_t *   indices
 
   unsigned short   n_indices
 
   const char *   name
 
   unsigned short   psr
 
arm_mode_data []
 
static const uint8_t arm_mon_indices [3]
 
static const struct reg_arch_type arm_reg_type
 
static const char * arm_state_strings []
 
static const uint8_t arm_svc_indices [3]
 
static const uint8_t arm_und_indices [3]
 
static const uint8_t arm_usr_indices [17]
 
const int armv4_5_core_reg_map [8][17]
 

Macro Definition Documentation

#define ARMV4_5_CORE_REG_MODENUM (   cache,
  mode,
  num 
)    (cache->reg_list[armv4_5_core_reg_map[mode][num]])

Definition at line 686 of file armv4_5.c.

Enumeration Type Documentation

anonymous enum
Enumerator
ARMV4_5_SPSR_FIQ 
ARMV4_5_SPSR_IRQ 
ARMV4_5_SPSR_SVC 
ARMV4_5_SPSR_ABT 
ARMV4_5_SPSR_UND 
ARM_SPSR_MON 

Definition at line 39 of file armv4_5.c.

Function Documentation

int arm_blank_check_memory ( struct target target,
target_addr_t  address,
uint32_t  count,
uint32_t *  blank,
uint8_t  erased_value 
)
static int arm_default_mcr ( struct target target,
int  cpnum,
uint32_t  op1,
uint32_t  op2,
uint32_t  CRn,
uint32_t  CRm,
uint32_t  value 
)
static

Definition at line 1672 of file armv4_5.c.

References ERROR_FAIL, LOG_ERROR, and target_type_name().

Referenced by arm_init_arch_info().

static int arm_default_mrc ( struct target target,
int  cpnum,
uint32_t  op1,
uint32_t  op2,
uint32_t  CRn,
uint32_t  CRm,
uint32_t *  value 
)
static

Definition at line 1663 of file armv4_5.c.

References ERROR_FAIL, LOG_ERROR, and target_type_name().

Referenced by arm_init_arch_info().

static int arm_full_context ( struct target target)
static
static void arm_gdb_dummy_init ( void  )
static

Definition at line 506 of file armv4_5.c.

References register_init_dummy().

const char* arm_mode_name ( unsigned  psr_mode)

Map PSR mode bits to the name of an ARM processor operating mode.

Definition at line 165 of file armv4_5.c.

References arm_mode_data, ARRAY_SIZE, LOG_ERROR, and psr.

Referenced by adapter_debug_entry(), arm7_9_debug_entry(), arm7_9_restore_context(), arm_arch_state(), arm_set_cpsr(), armv4_5_set_core_reg(), armv7m_arch_state(), cortex_m_debug_entry(), and xscale_debug_entry().

int arm_mode_to_number ( enum arm_mode  mode)

Map PSR mode bits to linear number indexing armv4_5_core_reg_map.

Definition at line 186 of file armv4_5.c.

References ARM_MODE_1176_MON, ARM_MODE_ABT, ARM_MODE_ANY, ARM_MODE_FIQ, ARM_MODE_IRQ, ARM_MODE_MON, ARM_MODE_SVC, ARM_MODE_SYS, ARM_MODE_UND, ARM_MODE_USR, and LOG_ERROR.

Referenced by arm_set_cpsr().

struct reg* arm_reg_current ( struct arm arm,
unsigned  regnum 
)

Returns handle to the register currently mapped to a given number.

Someone must have called arm_set_cpsr() before.

Parameters
armThis core's state and registers are used.
regnumFrom 0..15 corresponding to R0..R14 and PC. Note that R0..R7 don't require mapping; you may access those as the first eight entries in the register cache. Likewise R15 (PC) doesn't need mapping; you may also access it directly. However, R8..R14, and SPSR (arm->spsr) must be mapped. CPSR (arm->cpsr) is also not mapped.

Definition at line 442 of file armv4_5.c.

References arm::core_cache, LOG_ERROR, arm::map, NULL, and reg_cache::reg_list.

Referenced by arm7_9_debug_entry(), arm7_9_read_memory(), arm7_9_soft_reset_halt(), arm7_9_write_memory(), arm_dpm_read_current_registers(), arm_get_gdb_reg_list(), arm_semihosting(), COMMAND_HANDLER(), cortex_a_debug_entry(), cortex_a_read_cpu_memory(), cortex_a_read_cpu_memory_slow(), cortex_a_write_cpu_memory(), cortex_a_write_cpu_memory_slow(), post_result(), and xscale_debug_entry().

static int armv4_5_get_core_reg ( struct reg reg)
static
enum arm_mode armv4_5_number_to_mode ( int  number)

Map linear number indexing armv4_5_core_reg_map to PSR mode bits.

Definition at line 215 of file armv4_5.c.

References ARM_MODE_ABT, ARM_MODE_ANY, ARM_MODE_FIQ, ARM_MODE_IRQ, ARM_MODE_MON, ARM_MODE_SVC, ARM_MODE_SYS, ARM_MODE_UND, ARM_MODE_USR, and LOG_ERROR.

Referenced by arm7_9_full_context(), arm7_9_restore_context(), xscale_full_context(), and xscale_restore_banked().

int armv4_5_run_algorithm ( struct target target,
int  num_mem_params,
struct mem_param mem_params,
int  num_reg_params,
struct reg_param reg_params,
target_addr_t  entry_point,
target_addr_t  exit_point,
int  timeout_ms,
void *  arch_info 
)
static int armv4_5_run_algorithm_completion ( struct target target,
uint32_t  exit_point,
int  timeout_ms,
void *  arch_info 
)
static
COMMAND_HANDLER ( handle_arm_semihosting_fileio_command  )
COMMAND_HANDLER ( handle_arm_semihosting_cmdline  )
static int jim_mcrmrc ( Jim_Interp *  interp,
int  argc,
Jim_Obj *const *  argv 
)
static

Variable Documentation

const uint8_t arm_abt_indices[3]
static
Initial value:

Definition at line 65 of file armv4_5.c.

const struct command_registration arm_command_handlers[]
Initial value:
= {
{
.name = "arm",
.mode = COMMAND_ANY,
.help = "ARM command group",
.usage = "",
},
}
static const struct command_registration arm_exec_command_handlers[]
Definition: armv4_5.c:1130
#define COMMAND_REGISTRATION_DONE
Use this as the last entry in an array of command_registration records.
Definition: command.h:222

Definition at line 1189 of file armv4_5.c.

const { ... } arm_core_regs[]
const struct command_registration arm_exec_command_handlers[]
static

Definition at line 1130 of file armv4_5.c.

const uint8_t arm_fiq_indices[8]
static
Initial value:
= {
16, 17, 18, 19, 20, 21, 22, ARMV4_5_SPSR_FIQ,
}

Definition at line 53 of file armv4_5.c.

struct reg_feature arm_gdb_dummy_fp_features
static
Initial value:
= {
.name = "net.sourceforge.openocd.fake_fpa"
}

Definition at line 468 of file armv4_5.c.

struct reg arm_gdb_dummy_fp_reg
Initial value:
= {
.name = "GDB dummy FPA register",
.value = (uint8_t *) arm_gdb_dummy_fp_value,
.valid = 1,
.size = 96,
.exist = false,
.number = 16,
.group = "fake_fpa",
}
const char * feature
Definition: armv7m.c:84
static struct reg_feature arm_gdb_dummy_fp_features
Definition: armv4_5.c:468
const char * group
Definition: armv7m.c:83
static const uint8_t arm_gdb_dummy_fp_value[12]
Definition: armv4_5.c:466

Dummy FPA registers are required to support GDB on ARM.

Register packets require eight obsolete FPA register values. Modern ARM cores use Vector Floating Point (VFP), if they have any floating point support. VFP is not FPA-compatible.

Definition at line 478 of file armv4_5.c.

Referenced by arm_get_gdb_reg_list().

const uint8_t arm_gdb_dummy_fp_value[12]
static

Definition at line 466 of file armv4_5.c.

struct reg arm_gdb_dummy_fps_reg
Initial value:
= {
.name = "GDB dummy FPA status register",
.value = (uint8_t *) arm_gdb_dummy_fps_value,
.valid = 1,
.size = 32,
.exist = false,
.number = 24,
.group = "fake_fpa",
}
const char * feature
Definition: armv7m.c:84
static const uint8_t arm_gdb_dummy_fps_value[4]
Definition: armv4_5.c:489
static struct reg_feature arm_gdb_dummy_fp_features
Definition: armv4_5.c:468
const char * group
Definition: armv7m.c:83

Dummy FPA status registers are required to support GDB on ARM.

Register packets require an obsolete FPA status register.

Definition at line 495 of file armv4_5.c.

Referenced by arm_get_gdb_reg_list().

const uint8_t arm_gdb_dummy_fps_value[4]
static

Definition at line 489 of file armv4_5.c.

const uint8_t arm_irq_indices[3]
static
Initial value:

Definition at line 57 of file armv4_5.c.

const { ... } arm_mode_data[]
const uint8_t arm_mon_indices[3]
static
Initial value:
= {
39, 40, ARM_SPSR_MON,
}

Definition at line 73 of file armv4_5.c.

const struct reg_arch_type arm_reg_type
static
Initial value:
= {
}
static int armv4_5_get_core_reg(struct reg *reg)
Definition: armv4_5.c:514
static int armv4_5_set_core_reg(struct reg *reg, uint8_t *buf)
Definition: armv4_5.c:535

Definition at line 577 of file armv4_5.c.

Referenced by arm_build_reg_cache().

const char* arm_state_strings[]
static
Initial value:
= {
"ARM", "Thumb", "Jazelle", "ThumbEE",
}

Definition at line 240 of file armv4_5.c.

Referenced by arm_arch_state(), arm_set_cpsr(), and COMMAND_HANDLER().

const uint8_t arm_svc_indices[3]
static
Initial value:

Definition at line 61 of file armv4_5.c.

const uint8_t arm_und_indices[3]
static
Initial value:

Definition at line 69 of file armv4_5.c.

const uint8_t arm_usr_indices[17]
static
Initial value:
= {
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, ARMV4_5_CPSR,
}

Definition at line 49 of file armv4_5.c.

const int armv4_5_core_reg_map[8][17]
Initial value:
= {
{
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 31
},
{
0, 1, 2, 3, 4, 5, 6, 7, 16, 17, 18, 19, 20, 21, 22, 15, 32
},
{
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 23, 24, 15, 33
},
{
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 25, 26, 15, 34
},
{
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 27, 28, 15, 35
},
{
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 29, 30, 15, 36
},
{
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 31
},
{
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 37, 38, 15, 39,
}
}

Definition at line 346 of file armv4_5.c.

Referenced by arm_set_cpsr().

unsigned cookie

Definition at line 265 of file armv4_5.c.

Referenced by arm_build_reg_cache().

unsigned gdb_index

Definition at line 266 of file armv4_5.c.

const uint8_t* indices

Definition at line 84 of file armv4_5.c.

unsigned short n_indices

Definition at line 83 of file armv4_5.c.

Referenced by COMMAND_HANDLER().

unsigned short psr

Definition at line 79 of file armv4_5.c.

Referenced by arm_mode_name(), COMMAND_HANDLER(), and is_arm_mode().